1 /* Blackfin Pin Interrupt (PINT) model
3 Copyright (C) 2010-2015 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc. and Mike Frysinger.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "dv-bfin_pint.h"
31 /* Only accessed indirectly via the associated set/clear MMRs. */
32 bu32 mask
, edge
, invert
;
34 /* Order after here is important -- matches hardware MMR layout. */
46 #define mmr_base() offsetof(struct bfin_pint, mask_set)
47 #define mmr_offset(mmr) (offsetof(struct bfin_pint, mmr) - mmr_base())
49 static const char * const mmr_names
[] =
51 "PINT_MASK_SET", "PINT_MASK_CLEAR", "PINT_REQUEST", "PINT_ASSIGN",
52 "PINT_EDGE_SET", "PINT_EDGE_CLEAR", "PINT_INVERT_SET",
53 "PINT_INVERT_CLEAR", "PINT_PINSTATE", "PINT_LATCH",
55 #define mmr_name(off) mmr_names[(off) / 4]
58 bfin_pint_io_write_buffer (struct hw
*me
, const void *source
, int space
,
59 address_word addr
, unsigned nr_bytes
)
61 struct bfin_pint
*pint
= hw_data (me
);
67 value
= dv_load_4 (source
);
69 value
= dv_load_2 (source
);
70 mmr_off
= addr
- pint
->base
;
71 valuep
= (void *)((unsigned long)pint
+ mmr_base() + mmr_off
);
75 /* XXX: The hardware allows 16 or 32 bit accesses ... */
76 dv_bfin_mmr_require_32 (me
, addr
, nr_bytes
, true);
80 case mmr_offset(request
):
81 case mmr_offset(assign
):
82 case mmr_offset(pinstate
):
83 case mmr_offset(latch
):
86 case mmr_offset(mask_set
):
87 dv_w1c_4 (&pint
->mask
, value
, -1);
89 case mmr_offset(mask_clear
):
92 case mmr_offset(edge_set
):
93 dv_w1c_4 (&pint
->edge
, value
, -1);
95 case mmr_offset(edge_clear
):
98 case mmr_offset(invert_set
):
99 dv_w1c_4 (&pint
->invert
, value
, -1);
101 case mmr_offset(invert_clear
):
102 pint
->invert
|= value
;
105 dv_bfin_mmr_invalid (me
, addr
, nr_bytes
, true);
110 /* If updating masks, make sure we send updated port info. */
113 case mmr_offset(dir
):
114 case mmr_offset(data
) ... mmr_offset(toggle
):
115 bfin_pint_forward_ouput (me
, pint
, data
);
117 case mmr_offset(maska
) ... mmr_offset(maska_toggle
):
118 bfin_pint_forward_int (me
, pint
, pint
->maska
, 0);
120 case mmr_offset(maskb
) ... mmr_offset(maskb_toggle
):
121 bfin_pint_forward_int (me
, pint
, pint
->maskb
, 1);
130 bfin_pint_io_read_buffer (struct hw
*me
, void *dest
, int space
,
131 address_word addr
, unsigned nr_bytes
)
133 struct bfin_pint
*pint
= hw_data (me
);
137 mmr_off
= addr
- pint
->base
;
138 valuep
= (void *)((unsigned long)pint
+ mmr_base() + mmr_off
);
142 /* XXX: The hardware allows 16 or 32 bit accesses ... */
143 dv_bfin_mmr_require_32 (me
, addr
, nr_bytes
, false);
147 case mmr_offset(request
):
148 case mmr_offset(assign
):
149 case mmr_offset(pinstate
):
150 case mmr_offset(latch
):
151 dv_store_4 (dest
, *valuep
);
153 case mmr_offset(mask_set
):
154 case mmr_offset(mask_clear
):
155 dv_store_4 (dest
, pint
->mask
);
157 case mmr_offset(edge_set
):
158 case mmr_offset(edge_clear
):
159 dv_store_4 (dest
, pint
->edge
);
161 case mmr_offset(invert_set
):
162 case mmr_offset(invert_clear
):
163 dv_store_4 (dest
, pint
->invert
);
166 dv_bfin_mmr_invalid (me
, addr
, nr_bytes
, false);
173 #define ENC(bmap, piq) (((bmap) << 8) + (piq))
175 #define PIQ_PORTS(n) \
176 { "piq0@"#n, ENC(n, 0), 0, input_port, }, \
177 { "piq1@"#n, ENC(n, 1), 0, input_port, }, \
178 { "piq2@"#n, ENC(n, 2), 0, input_port, }, \
179 { "piq3@"#n, ENC(n, 3), 0, input_port, }, \
180 { "piq4@"#n, ENC(n, 4), 0, input_port, }, \
181 { "piq5@"#n, ENC(n, 5), 0, input_port, }, \
182 { "piq6@"#n, ENC(n, 6), 0, input_port, }, \
183 { "piq7@"#n, ENC(n, 7), 0, input_port, }, \
184 { "piq8@"#n, ENC(n, 8), 0, input_port, }, \
185 { "piq9@"#n, ENC(n, 9), 0, input_port, }, \
186 { "piq10@"#n, ENC(n, 10), 0, input_port, }, \
187 { "piq11@"#n, ENC(n, 11), 0, input_port, }, \
188 { "piq12@"#n, ENC(n, 12), 0, input_port, }, \
189 { "piq13@"#n, ENC(n, 13), 0, input_port, }, \
190 { "piq14@"#n, ENC(n, 14), 0, input_port, }, \
191 { "piq15@"#n, ENC(n, 15), 0, input_port, }, \
192 { "piq16@"#n, ENC(n, 16), 0, input_port, }, \
193 { "piq17@"#n, ENC(n, 17), 0, input_port, }, \
194 { "piq18@"#n, ENC(n, 18), 0, input_port, }, \
195 { "piq19@"#n, ENC(n, 19), 0, input_port, }, \
196 { "piq20@"#n, ENC(n, 20), 0, input_port, }, \
197 { "piq21@"#n, ENC(n, 21), 0, input_port, }, \
198 { "piq22@"#n, ENC(n, 22), 0, input_port, }, \
199 { "piq23@"#n, ENC(n, 23), 0, input_port, }, \
200 { "piq24@"#n, ENC(n, 24), 0, input_port, }, \
201 { "piq25@"#n, ENC(n, 25), 0, input_port, }, \
202 { "piq26@"#n, ENC(n, 26), 0, input_port, }, \
203 { "piq27@"#n, ENC(n, 27), 0, input_port, }, \
204 { "piq28@"#n, ENC(n, 28), 0, input_port, }, \
205 { "piq29@"#n, ENC(n, 29), 0, input_port, }, \
206 { "piq30@"#n, ENC(n, 30), 0, input_port, }, \
207 { "piq31@"#n, ENC(n, 31), 0, input_port, },
209 static const struct hw_port_descriptor bfin_pint_ports
[] =
211 { "stat", 0, 0, output_port
, },
224 bfin_pint_port_event (struct hw
*me
, int my_port
, struct hw
*source
,
225 int source_port
, int level
)
231 attach_bfin_pint_regs (struct hw
*me
, struct bfin_pint
*pint
)
233 address_word attach_address
;
235 unsigned attach_size
;
236 reg_property_spec reg
;
238 if (hw_find_property (me
, "reg") == NULL
)
239 hw_abort (me
, "Missing \"reg\" property");
241 if (!hw_find_reg_array_property (me
, "reg", 0, ®
))
242 hw_abort (me
, "\"reg\" property must contain three addr/size entries");
244 hw_unit_address_to_attach_address (hw_parent (me
),
246 &attach_space
, &attach_address
, me
);
247 hw_unit_size_to_attach_size (hw_parent (me
), ®
.size
, &attach_size
, me
);
249 if (attach_size
!= BFIN_MMR_PINT_SIZE
)
250 hw_abort (me
, "\"reg\" size must be %#x", BFIN_MMR_PINT_SIZE
);
252 hw_attach_address (hw_parent (me
),
253 0, attach_space
, attach_address
, attach_size
, me
);
255 pint
->base
= attach_address
;
259 bfin_pint_finish (struct hw
*me
)
261 struct bfin_pint
*pint
;
263 pint
= HW_ZALLOC (me
, struct bfin_pint
);
265 set_hw_data (me
, pint
);
266 set_hw_io_read_buffer (me
, bfin_pint_io_read_buffer
);
267 set_hw_io_write_buffer (me
, bfin_pint_io_write_buffer
);
268 set_hw_ports (me
, bfin_pint_ports
);
269 set_hw_port_event (me
, bfin_pint_port_event
);
271 /* Initialize the PINT. */
272 switch (dv_get_bus_num (me
))
275 pint
->assign
= 0x00000101;
278 pint
->assign
= 0x01010000;
281 pint
->assign
= 0x00000101;
284 pint
->assign
= 0x02020303;
287 /* XXX: Should move this default into device tree. */
288 hw_abort (me
, "no support for PINT at this address yet");
291 attach_bfin_pint_regs (me
, pint
);
294 const struct hw_descriptor dv_bfin_pint_descriptor
[] =
296 {"bfin_pint", bfin_pint_finish
,},