sim/bfin/dv-bfin_ppi.c

   1 /* Blackfin Parallel Port Interface (PPI) model
   2    For "old style" PPIs on BF53x/etc... parts.
   3
   4    Copyright (C) 2010-2011 Free Software Foundation, Inc.
   5    Contributed by Analog Devices, Inc.
   6
   7    This file is part of simulators.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  21
  22 #include "config.h"
  23
  24 #include "sim-main.h"
  25 #include "devices.h"
  26 #include "dv-bfin_ppi.h"
  27 #include "gui.h"
  28
  29 /* XXX: TX is merely a stub.  */
  30
  31 struct bfin_ppi
  32 {
  33   /* This top portion matches common dv_bfin struct.  */
  34   bu32 base;
  35   struct hw *dma_master;
  36   bool acked;
  37
  38   struct hw_event *handler;
  39   char saved_byte;
  40   int saved_count;
  41
  42   /* GUI state.  */
  43   void *gui_state;
  44   int color;
  45
  46   /* Order after here is important -- matches hardware MMR layout.  */
  47   bu16 BFIN_MMR_16(control);
  48   bu16 BFIN_MMR_16(status);
  49   bu16 BFIN_MMR_16(count);
  50   bu16 BFIN_MMR_16(delay);
  51   bu16 BFIN_MMR_16(frame);
  52 };
  53 #define mmr_base()      offsetof(struct bfin_ppi, control)
  54 #define mmr_offset(mmr) (offsetof(struct bfin_ppi, mmr) - mmr_base())
  55
  56 static const char * const mmr_names[] = {
  57   "PPI_CONTROL", "PPI_STATUS", "PPI_COUNT", "PPI_DELAY", "PPI_FRAME",
  58 };
  59 #define mmr_name(off) mmr_names[(off) / 4]
  60
  61 static void
  62 bfin_ppi_gui_setup (struct bfin_ppi *ppi)
  63 {
  64   int bpp;
  65
  66   /* If we are in RX mode, nothing to do.  */
  67   if (!(ppi->control & PORT_DIR))
  68     return;
  69
  70   bpp = bfin_gui_color_depth (ppi->color);
  71   ppi->gui_state = bfin_gui_setup (ppi->gui_state,
  72                                    ppi->control & PORT_EN,
  73                                    (ppi->count + 1) / (bpp / 8),
  74                                    ppi->frame,
  75                                    ppi->color);
  76 }
  77
  78 static unsigned
  79 bfin_ppi_io_write_buffer (struct hw *me, const void *source, int space,
  80                           address_word addr, unsigned nr_bytes)
  81 {
  82   struct bfin_ppi *ppi = hw_data (me);
  83   bu32 mmr_off;
  84   bu32 value;
  85   bu16 *valuep;
  86
  87   value = dv_load_2 (source);
  88   mmr_off = addr - ppi->base;
  89   valuep = (void *)((unsigned long)ppi + mmr_base() + mmr_off);
  90
  91   HW_TRACE_WRITE ();
  92
  93   dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
  94
  95   switch (mmr_off)
  96     {
  97     case mmr_offset(control):
  98       *valuep = value;
  99       bfin_ppi_gui_setup (ppi);
 100       break;
 101     case mmr_offset(count):
 102     case mmr_offset(delay):
 103     case mmr_offset(frame):
 104       *valuep = value;
 105       break;
 106     case mmr_offset(status):
 107       dv_w1c_2 (valuep, value, (1 << 10));
 108       break;
 109     default:
 110       dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
 111       break;
 112     }
 113
 114   return nr_bytes;
 115 }
 116
 117 static unsigned
 118 bfin_ppi_io_read_buffer (struct hw *me, void *dest, int space,
 119                          address_word addr, unsigned nr_bytes)
 120 {
 121   struct bfin_ppi *ppi = hw_data (me);
 122   bu32 mmr_off;
 123   bu16 *valuep;
 124
 125   mmr_off = addr - ppi->base;
 126   valuep = (void *)((unsigned long)ppi + mmr_base() + mmr_off);
 127
 128   HW_TRACE_READ ();
 129
 130   dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
 131
 132   switch (mmr_off)
 133     {
 134     case mmr_offset(control):
 135     case mmr_offset(count):
 136     case mmr_offset(delay):
 137     case mmr_offset(frame):
 138     case mmr_offset(status):
 139       dv_store_2 (dest, *valuep);
 140       break;
 141     default:
 142       dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
 143       break;
 144     }
 145
 146   return nr_bytes;
 147 }
 148
 149 static unsigned
 150 bfin_ppi_dma_read_buffer (struct hw *me, void *dest, int space,
 151                           unsigned_word addr, unsigned nr_bytes)
 152 {
 153   HW_TRACE_DMA_READ ();
 154   return 0;
 155 }
 156
 157 static unsigned
 158 bfin_ppi_dma_write_buffer (struct hw *me, const void *source,
 159                            int space, unsigned_word addr,
 160                            unsigned nr_bytes,
 161                            int violate_read_only_section)
 162 {
 163   struct bfin_ppi *ppi = hw_data (me);
 164
 165   HW_TRACE_DMA_WRITE ();
 166
 167   return bfin_gui_update (ppi->gui_state, source, nr_bytes);
 168 }
 169
 170 static const struct hw_port_descriptor bfin_ppi_ports[] = {
 171   { "stat", 0, 0, output_port, },
 172   { NULL, 0, 0, 0, },
 173 };
 174
 175 static void
 176 attach_bfin_ppi_regs (struct hw *me, struct bfin_ppi *ppi)
 177 {
 178   address_word attach_address;
 179   int attach_space;
 180   unsigned attach_size;
 181   reg_property_spec reg;
 182
 183   if (hw_find_property (me, "reg") == NULL)
 184     hw_abort (me, "Missing \"reg\" property");
 185
 186   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 187     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 188
 189   hw_unit_address_to_attach_address (hw_parent (me),
 190                                      &reg.address,
 191                                      &attach_space, &attach_address, me);
 192   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 193
 194   if (attach_size != BFIN_MMR_PPI_SIZE)
 195     hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_PPI_SIZE);
 196
 197   hw_attach_address (hw_parent (me),
 198                      0, attach_space, attach_address, attach_size, me);
 199
 200   ppi->base = attach_address;
 201 }
 202
 203 static void
 204 bfin_ppi_finish (struct hw *me)
 205 {
 206   struct bfin_ppi *ppi;
 207   const char *color;
 208
 209   ppi = HW_ZALLOC (me, struct bfin_ppi);
 210
 211   set_hw_data (me, ppi);
 212   set_hw_io_read_buffer (me, bfin_ppi_io_read_buffer);
 213   set_hw_io_write_buffer (me, bfin_ppi_io_write_buffer);
 214   set_hw_dma_read_buffer (me, bfin_ppi_dma_read_buffer);
 215   set_hw_dma_write_buffer (me, bfin_ppi_dma_write_buffer);
 216   set_hw_ports (me, bfin_ppi_ports);
 217
 218   attach_bfin_ppi_regs (me, ppi);
 219
 220   /* Initialize the PPI.  */
 221   if (hw_find_property (me, "color"))
 222     color = hw_find_string_property (me, "color");
 223   else
 224     color = NULL;
 225   ppi->color = bfin_gui_color (color);
 226 }
 227
 228 const struct hw_descriptor dv_bfin_ppi_descriptor[] = {
 229   {"bfin_ppi", bfin_ppi_finish,},
 230   {NULL, NULL},
 231 };