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sim: bfin: new port
[deliverable/binutils-gdb.git] / sim / bfin / dv-bfin_sic.c
1 /* Blackfin System Interrupt Controller (SIC) model.
2
3 Copyright (C) 2010-2011 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22
23 #include "sim-main.h"
24 #include "devices.h"
25 #include "dv-bfin_sic.h"
26 #include "dv-bfin_cec.h"
27
28 struct bfin_sic
29 {
30 /* We assume first element is the base. */
31 bu32 base;
32
33 /* Order after here is important -- matches hardware MMR layout. */
34 bu16 BFIN_MMR_16(swrst);
35 bu16 BFIN_MMR_16(syscr);
36 bu16 BFIN_MMR_16(rvect); /* XXX: BF59x has a 32bit AUX_REVID here. */
37 union {
38 struct {
39 bu32 imask0;
40 bu32 iar0, iar1, iar2, iar3;
41 bu32 isr0, iwr0;
42 bu32 _pad0[9];
43 bu32 imask1;
44 bu32 iar4, iar5, iar6, iar7;
45 bu32 isr1, iwr1;
46 } bf52x;
47 struct {
48 bu32 imask;
49 bu32 iar0, iar1, iar2, iar3;
50 bu32 isr, iwr;
51 } bf537;
52 struct {
53 bu32 imask0, imask1, imask2;
54 bu32 isr0, isr1, isr2;
55 bu32 iwr0, iwr1, iwr2;
56 bu32 iar0, iar1, iar2, iar3;
57 bu32 iar4, iar5, iar6, iar7;
58 bu32 iar8, iar9, iar10, iar11;
59 } bf54x;
60 struct {
61 bu32 imask0, imask1;
62 bu32 iar0, iar1, iar2, iar3;
63 bu32 iar4, iar5, iar6, iar7;
64 bu32 isr0, isr1;
65 bu32 iwr0, iwr1;
66 } bf561;
67 };
68 };
69 #define mmr_base() offsetof(struct bfin_sic, swrst)
70 #define mmr_offset(mmr) (offsetof(struct bfin_sic, mmr) - mmr_base())
71 #define mmr_idx(mmr) (mmr_offset (mmr) / 4)
72
73 static const char * const bf52x_mmr_names[] = {
74 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IAR0", "SIC_IAR1",
75 "SIC_IAR2", "SIC_IAR3", "SIC_ISR0", "SIC_IWR0",
76 [mmr_idx (bf52x.imask1)] = "SIC_IMASK1", "SIC_IAR4", "SIC_IAR5",
77 "SIC_IAR6", "SIC_IAR7", "SIC_ISR1", "SIC_IWR1",
78 };
79 static const char * const bf537_mmr_names[] = {
80 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK", "SIC_IAR0", "SIC_IAR1",
81 "SIC_IAR2", "SIC_IAR3", "SIC_ISR", "SIC_IWR",
82 };
83 static const char * const bf54x_mmr_names[] = {
84 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IMASK1", "SIC_IMASK2",
85 "SIC_ISR0", "SIC_ISR1", "SIC_ISR2", "SIC_IWR0", "SIC_IWR1", "SIC_IWR2",
86 "SIC_IAR0", "SIC_IAR1", "SIC_IAR2", "SIC_IAR3",
87 "SIC_IAR4", "SIC_IAR5", "SIC_IAR6", "SIC_IAR7",
88 "SIC_IAR8", "SIC_IAR9", "SIC_IAR10", "SIC_IAR11",
89 };
90 static const char * const bf561_mmr_names[] = {
91 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IMASK1",
92 "SIC_IAR0", "SIC_IAR1", "SIC_IAR2", "SIC_IAR3",
93 "SIC_IAR4", "SIC_IAR5", "SIC_IAR6", "SIC_IAR7",
94 "SIC_ISR0", "SIC_ISR1", "SIC_IWR0", "SIC_IWR1",
95 };
96 static const char * const *mmr_names;
97 #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
98
99 static void
100 bfin_sic_forward_interrupts (struct hw *me, bu32 *isr, bu32 *imask, bu32 *iar)
101 {
102 int my_port;
103 bu32 ipend;
104
105 /* Process pending and unmasked interrupts. */
106 ipend = *isr & *imask;
107
108 /* Usually none are pending unmasked, so avoid bit twiddling. */
109 if (!ipend)
110 return;
111
112 for (my_port = 0; my_port < 32; ++my_port)
113 {
114 bu32 iar_idx, iar_off, iar_val;
115 bu32 bit = (1 << my_port);
116
117 /* This bit isn't pending, so check next one. */
118 if (!(ipend & bit))
119 continue;
120
121 /* The IAR registers map the System input to the Core output.
122 Every 4 bits in the IAR are used to map to IVG{7..15}. */
123 iar_idx = my_port / 8;
124 iar_off = (my_port % 8) * 4;
125 iar_val = (iar[iar_idx] & (0xf << iar_off)) >> iar_off;
126 hw_port_event (me, IVG7 + iar_val, 1);
127 }
128 }
129
130 static void
131 bfin_sic_52x_forward_interrupts (struct hw *me, struct bfin_sic *sic)
132 {
133 bfin_sic_forward_interrupts (me, &sic->bf52x.isr0, &sic->bf52x.imask0, &sic->bf52x.iar0);
134 bfin_sic_forward_interrupts (me, &sic->bf52x.isr1, &sic->bf52x.imask1, &sic->bf52x.iar4);
135 }
136
137 static unsigned
138 bfin_sic_52x_io_write_buffer (struct hw *me, const void *source, int space,
139 address_word addr, unsigned nr_bytes)
140 {
141 struct bfin_sic *sic = hw_data (me);
142 bu32 mmr_off;
143 bu32 value;
144 bu16 *value16p;
145 bu32 *value32p;
146 void *valuep;
147
148 if (nr_bytes == 4)
149 value = dv_load_4 (source);
150 else
151 value = dv_load_2 (source);
152
153 mmr_off = addr - sic->base;
154 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
155 value16p = valuep;
156 value32p = valuep;
157
158 HW_TRACE_WRITE ();
159
160 /* XXX: Discard all SIC writes for now. */
161 switch (mmr_off)
162 {
163 case mmr_offset(swrst):
164 /* XXX: This should trigger a software reset ... */
165 break;
166 case mmr_offset(syscr):
167 /* XXX: what to do ... */
168 break;
169 case mmr_offset(bf52x.imask0):
170 case mmr_offset(bf52x.imask1):
171 bfin_sic_52x_forward_interrupts (me, sic);
172 *value32p = value;
173 break;
174 case mmr_offset(bf52x.iar0) ... mmr_offset(bf52x.iar3):
175 case mmr_offset(bf52x.iar4) ... mmr_offset(bf52x.iar7):
176 case mmr_offset(bf52x.iwr0):
177 case mmr_offset(bf52x.iwr1):
178 *value32p = value;
179 break;
180 case mmr_offset(bf52x.isr0):
181 case mmr_offset(bf52x.isr1):
182 /* ISR is read-only. */
183 break;
184 default:
185 /* XXX: Should discard other writes. */
186 ;
187 }
188
189 return nr_bytes;
190 }
191
192 static unsigned
193 bfin_sic_52x_io_read_buffer (struct hw *me, void *dest, int space,
194 address_word addr, unsigned nr_bytes)
195 {
196 struct bfin_sic *sic = hw_data (me);
197 bu32 mmr_off;
198 bu16 *value16p;
199 bu32 *value32p;
200 void *valuep;
201
202 mmr_off = addr - sic->base;
203 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
204 value16p = valuep;
205 value32p = valuep;
206
207 HW_TRACE_READ ();
208
209 switch (mmr_off)
210 {
211 case mmr_offset(swrst):
212 case mmr_offset(syscr):
213 case mmr_offset(rvect):
214 dv_store_2 (dest, *value16p);
215 break;
216 case mmr_offset(bf52x.imask0):
217 case mmr_offset(bf52x.imask1):
218 case mmr_offset(bf52x.iar0) ... mmr_offset(bf52x.iar3):
219 case mmr_offset(bf52x.iar4) ... mmr_offset(bf52x.iar7):
220 case mmr_offset(bf52x.iwr0):
221 case mmr_offset(bf52x.iwr1):
222 case mmr_offset(bf52x.isr0):
223 case mmr_offset(bf52x.isr1):
224 dv_store_4 (dest, *value32p);
225 break;
226 default:
227 if (nr_bytes == 2)
228 dv_store_2 (dest, 0);
229 else
230 dv_store_4 (dest, 0);
231 break;
232 }
233
234 return nr_bytes;
235 }
236
237 static void
238 bfin_sic_537_forward_interrupts (struct hw *me, struct bfin_sic *sic)
239 {
240 bfin_sic_forward_interrupts (me, &sic->bf537.isr, &sic->bf537.imask, &sic->bf537.iar0);
241 }
242
243 static unsigned
244 bfin_sic_537_io_write_buffer (struct hw *me, const void *source, int space,
245 address_word addr, unsigned nr_bytes)
246 {
247 struct bfin_sic *sic = hw_data (me);
248 bu32 mmr_off;
249 bu32 value;
250 bu16 *value16p;
251 bu32 *value32p;
252 void *valuep;
253
254 if (nr_bytes == 4)
255 value = dv_load_4 (source);
256 else
257 value = dv_load_2 (source);
258
259 mmr_off = addr - sic->base;
260 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
261 value16p = valuep;
262 value32p = valuep;
263
264 HW_TRACE_WRITE ();
265
266 /* XXX: Discard all SIC writes for now. */
267 switch (mmr_off)
268 {
269 case mmr_offset(swrst):
270 /* XXX: This should trigger a software reset ... */
271 break;
272 case mmr_offset(syscr):
273 /* XXX: what to do ... */
274 break;
275 case mmr_offset(bf537.imask):
276 bfin_sic_537_forward_interrupts (me, sic);
277 *value32p = value;
278 break;
279 case mmr_offset(bf537.iar0):
280 case mmr_offset(bf537.iar1):
281 case mmr_offset(bf537.iar2):
282 case mmr_offset(bf537.iar3):
283 case mmr_offset(bf537.iwr):
284 *value32p = value;
285 break;
286 case mmr_offset(bf537.isr):
287 /* ISR is read-only. */
288 break;
289 default:
290 /* XXX: Should discard other writes. */
291 ;
292 }
293
294 return nr_bytes;
295 }
296
297 static unsigned
298 bfin_sic_537_io_read_buffer (struct hw *me, void *dest, int space,
299 address_word addr, unsigned nr_bytes)
300 {
301 struct bfin_sic *sic = hw_data (me);
302 bu32 mmr_off;
303 bu16 *value16p;
304 bu32 *value32p;
305 void *valuep;
306
307 mmr_off = addr - sic->base;
308 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
309 value16p = valuep;
310 value32p = valuep;
311
312 HW_TRACE_READ ();
313
314 switch (mmr_off)
315 {
316 case mmr_offset(swrst):
317 case mmr_offset(syscr):
318 case mmr_offset(rvect):
319 dv_store_2 (dest, *value16p);
320 break;
321 case mmr_offset(bf537.imask):
322 case mmr_offset(bf537.iar0):
323 case mmr_offset(bf537.iar1):
324 case mmr_offset(bf537.iar2):
325 case mmr_offset(bf537.iar3):
326 case mmr_offset(bf537.isr):
327 case mmr_offset(bf537.iwr):
328 dv_store_4 (dest, *value32p);
329 break;
330 default:
331 if (nr_bytes == 2)
332 dv_store_2 (dest, 0);
333 else
334 dv_store_4 (dest, 0);
335 break;
336 }
337
338 return nr_bytes;
339 }
340
341 static void
342 bfin_sic_54x_forward_interrupts (struct hw *me, struct bfin_sic *sic)
343 {
344 bfin_sic_forward_interrupts (me, &sic->bf54x.isr0, &sic->bf54x.imask0, &sic->bf54x.iar0);
345 bfin_sic_forward_interrupts (me, &sic->bf54x.isr1, &sic->bf54x.imask1, &sic->bf54x.iar4);
346 bfin_sic_forward_interrupts (me, &sic->bf54x.isr2, &sic->bf54x.imask2, &sic->bf54x.iar8);
347 }
348
349 static unsigned
350 bfin_sic_54x_io_write_buffer (struct hw *me, const void *source, int space,
351 address_word addr, unsigned nr_bytes)
352 {
353 struct bfin_sic *sic = hw_data (me);
354 bu32 mmr_off;
355 bu32 value;
356 bu16 *value16p;
357 bu32 *value32p;
358 void *valuep;
359
360 if (nr_bytes == 4)
361 value = dv_load_4 (source);
362 else
363 value = dv_load_2 (source);
364
365 mmr_off = addr - sic->base;
366 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
367 value16p = valuep;
368 value32p = valuep;
369
370 HW_TRACE_WRITE ();
371
372 /* XXX: Discard all SIC writes for now. */
373 switch (mmr_off)
374 {
375 case mmr_offset(swrst):
376 /* XXX: This should trigger a software reset ... */
377 break;
378 case mmr_offset(syscr):
379 /* XXX: what to do ... */
380 break;
381 case mmr_offset(bf54x.imask0) ... mmr_offset(bf54x.imask2):
382 bfin_sic_54x_forward_interrupts (me, sic);
383 *value32p = value;
384 break;
385 case mmr_offset(bf54x.iar0) ... mmr_offset(bf54x.iar11):
386 case mmr_offset(bf54x.iwr0) ... mmr_offset(bf54x.iwr2):
387 *value32p = value;
388 break;
389 case mmr_offset(bf54x.isr0) ... mmr_offset(bf54x.isr2):
390 /* ISR is read-only. */
391 break;
392 default:
393 /* XXX: Should discard other writes. */
394 ;
395 }
396
397 return nr_bytes;
398 }
399
400 static unsigned
401 bfin_sic_54x_io_read_buffer (struct hw *me, void *dest, int space,
402 address_word addr, unsigned nr_bytes)
403 {
404 struct bfin_sic *sic = hw_data (me);
405 bu32 mmr_off;
406 bu16 *value16p;
407 bu32 *value32p;
408 void *valuep;
409
410 mmr_off = addr - sic->base;
411 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
412 value16p = valuep;
413 value32p = valuep;
414
415 HW_TRACE_READ ();
416
417 switch (mmr_off)
418 {
419 case mmr_offset(swrst):
420 case mmr_offset(syscr):
421 case mmr_offset(rvect):
422 dv_store_2 (dest, *value16p);
423 break;
424 case mmr_offset(bf54x.imask0) ... mmr_offset(bf54x.imask2):
425 case mmr_offset(bf54x.iar0) ... mmr_offset(bf54x.iar11):
426 case mmr_offset(bf54x.iwr0) ... mmr_offset(bf54x.iwr2):
427 case mmr_offset(bf54x.isr0) ... mmr_offset(bf54x.isr2):
428 dv_store_4 (dest, *value32p);
429 break;
430 default:
431 if (nr_bytes == 2)
432 dv_store_2 (dest, 0);
433 else
434 dv_store_4 (dest, 0);
435 break;
436 }
437
438 return nr_bytes;
439 }
440
441 static void
442 bfin_sic_561_forward_interrupts (struct hw *me, struct bfin_sic *sic)
443 {
444 bfin_sic_forward_interrupts (me, &sic->bf561.isr0, &sic->bf561.imask0, &sic->bf561.iar0);
445 bfin_sic_forward_interrupts (me, &sic->bf561.isr1, &sic->bf561.imask1, &sic->bf561.iar4);
446 }
447
448 static unsigned
449 bfin_sic_561_io_write_buffer (struct hw *me, const void *source, int space,
450 address_word addr, unsigned nr_bytes)
451 {
452 struct bfin_sic *sic = hw_data (me);
453 bu32 mmr_off;
454 bu32 value;
455 bu16 *value16p;
456 bu32 *value32p;
457 void *valuep;
458
459 if (nr_bytes == 4)
460 value = dv_load_4 (source);
461 else
462 value = dv_load_2 (source);
463
464 mmr_off = addr - sic->base;
465 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
466 value16p = valuep;
467 value32p = valuep;
468
469 HW_TRACE_WRITE ();
470
471 /* XXX: Discard all SIC writes for now. */
472 switch (mmr_off)
473 {
474 case mmr_offset(swrst):
475 /* XXX: This should trigger a software reset ... */
476 break;
477 case mmr_offset(syscr):
478 /* XXX: what to do ... */
479 break;
480 case mmr_offset(bf561.imask0):
481 case mmr_offset(bf561.imask1):
482 bfin_sic_561_forward_interrupts (me, sic);
483 *value32p = value;
484 break;
485 case mmr_offset(bf561.iar0) ... mmr_offset(bf561.iar3):
486 case mmr_offset(bf561.iar4) ... mmr_offset(bf561.iar7):
487 case mmr_offset(bf561.iwr0):
488 case mmr_offset(bf561.iwr1):
489 *value32p = value;
490 break;
491 case mmr_offset(bf561.isr0):
492 case mmr_offset(bf561.isr1):
493 /* ISR is read-only. */
494 break;
495 default:
496 /* XXX: Should discard other writes. */
497 ;
498 }
499
500 return nr_bytes;
501 }
502
503 static unsigned
504 bfin_sic_561_io_read_buffer (struct hw *me, void *dest, int space,
505 address_word addr, unsigned nr_bytes)
506 {
507 struct bfin_sic *sic = hw_data (me);
508 bu32 mmr_off;
509 bu16 *value16p;
510 bu32 *value32p;
511 void *valuep;
512
513 mmr_off = addr - sic->base;
514 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
515 value16p = valuep;
516 value32p = valuep;
517
518 HW_TRACE_READ ();
519
520 switch (mmr_off)
521 {
522 case mmr_offset(swrst):
523 case mmr_offset(syscr):
524 case mmr_offset(rvect):
525 dv_store_2 (dest, *value16p);
526 break;
527 case mmr_offset(bf561.imask0):
528 case mmr_offset(bf561.imask1):
529 case mmr_offset(bf561.iar0) ... mmr_offset(bf561.iar3):
530 case mmr_offset(bf561.iar4) ... mmr_offset(bf561.iar7):
531 case mmr_offset(bf561.iwr0):
532 case mmr_offset(bf561.iwr1):
533 case mmr_offset(bf561.isr0):
534 case mmr_offset(bf561.isr1):
535 dv_store_4 (dest, *value32p);
536 break;
537 default:
538 if (nr_bytes == 2)
539 dv_store_2 (dest, 0);
540 else
541 dv_store_4 (dest, 0);
542 break;
543 }
544
545 return nr_bytes;
546 }
547
548 /* XXX: This doesn't handle DMA<->peripheral mappings. */
549 #define BFIN_SIC_TO_CEC_PORTS \
550 { "ivg7", IVG7, 0, output_port, }, \
551 { "ivg8", IVG8, 0, output_port, }, \
552 { "ivg9", IVG9, 0, output_port, }, \
553 { "ivg10", IVG10, 0, output_port, }, \
554 { "ivg11", IVG11, 0, output_port, }, \
555 { "ivg12", IVG12, 0, output_port, }, \
556 { "ivg13", IVG13, 0, output_port, }, \
557 { "ivg14", IVG14, 0, output_port, }, \
558 { "ivg15", IVG15, 0, output_port, },
559
560 static const struct hw_port_descriptor bfin_sic_50x_ports[] = {
561 BFIN_SIC_TO_CEC_PORTS
562 /* SIC0 */
563 { "pll", 0, 0, input_port, },
564 { "dma_stat", 1, 0, input_port, },
565 { "ppi@0", 2, 0, input_port, },
566 { "sport@0_stat", 3, 0, input_port, },
567 { "sport@1_stat", 4, 0, input_port, },
568 { "uart2@0_stat", 5, 0, input_port, },
569 { "uart2@1_stat", 6, 0, input_port, },
570 { "spi@0", 7, 0, input_port, },
571 { "spi@1", 8, 0, input_port, },
572 { "can_stat", 9, 0, input_port, },
573 { "rsi_int0", 10, 0, input_port, },
574 /*{ "reserved", 11, 0, input_port, },*/
575 { "counter@0", 12, 0, input_port, },
576 { "counter@1", 13, 0, input_port, },
577 { "dma@0", 14, 0, input_port, },
578 { "dma@1", 15, 0, input_port, },
579 { "dma@2", 16, 0, input_port, },
580 { "dma@3", 17, 0, input_port, },
581 { "dma@4", 18, 0, input_port, },
582 { "dma@5", 19, 0, input_port, },
583 { "dma@6", 20, 0, input_port, },
584 { "dma@7", 21, 0, input_port, },
585 { "dma@8", 22, 0, input_port, },
586 { "dma@9", 23, 0, input_port, },
587 { "dma@10", 24, 0, input_port, },
588 { "dma@11", 25, 0, input_port, },
589 { "can_rx", 26, 0, input_port, },
590 { "can_tx", 27, 0, input_port, },
591 { "twi@0", 28, 0, input_port, },
592 { "portf_irq_a", 29, 0, input_port, },
593 { "portf_irq_b", 30, 0, input_port, },
594 /*{ "reserved", 31, 0, input_port, },*/
595 /* SIC1 */
596 { "gptimer@0", 100, 0, input_port, },
597 { "gptimer@1", 101, 0, input_port, },
598 { "gptimer@2", 102, 0, input_port, },
599 { "gptimer@3", 103, 0, input_port, },
600 { "gptimer@4", 104, 0, input_port, },
601 { "gptimer@5", 105, 0, input_port, },
602 { "gptimer@6", 106, 0, input_port, },
603 { "gptimer@7", 107, 0, input_port, },
604 { "portg_irq_a", 108, 0, input_port, },
605 { "portg_irq_b", 109, 0, input_port, },
606 { "mdma@0", 110, 0, input_port, },
607 { "mdma@1", 111, 0, input_port, },
608 { "wdog", 112, 0, input_port, },
609 { "porth_irq_a", 113, 0, input_port, },
610 { "porth_irq_b", 114, 0, input_port, },
611 { "acm_stat", 115, 0, input_port, },
612 { "acm_int", 116, 0, input_port, },
613 /*{ "reserved", 117, 0, input_port, },*/
614 /*{ "reserved", 118, 0, input_port, },*/
615 { "pwm@0_trip", 119, 0, input_port, },
616 { "pwm@0_sync", 120, 0, input_port, },
617 { "pwm@1_trip", 121, 0, input_port, },
618 { "pwm@1_sync", 122, 0, input_port, },
619 { "rsi_int1", 123, 0, input_port, },
620 { NULL, 0, 0, 0, },
621 };
622
623 static const struct hw_port_descriptor bfin_sic_51x_ports[] = {
624 BFIN_SIC_TO_CEC_PORTS
625 /* SIC0 */
626 { "pll", 0, 0, input_port, },
627 { "dma_stat", 1, 0, input_port, },
628 { "dmar0_block", 2, 0, input_port, },
629 { "dmar1_block", 3, 0, input_port, },
630 { "dmar0_over", 4, 0, input_port, },
631 { "dmar1_over", 5, 0, input_port, },
632 { "ppi@0", 6, 0, input_port, },
633 { "emac_stat", 7, 0, input_port, },
634 { "sport@0_stat", 8, 0, input_port, },
635 { "sport@1_stat", 9, 0, input_port, },
636 { "ptp_err", 10, 0, input_port, },
637 /*{ "reserved", 11, 0, input_port, },*/
638 { "uart@0_stat", 12, 0, input_port, },
639 { "uart@1_stat", 13, 0, input_port, },
640 { "rtc", 14, 0, input_port, },
641 { "dma@0", 15, 0, input_port, },
642 { "dma@3", 16, 0, input_port, },
643 { "dma@4", 17, 0, input_port, },
644 { "dma@5", 18, 0, input_port, },
645 { "dma@6", 19, 0, input_port, },
646 { "twi@0", 20, 0, input_port, },
647 { "dma@7", 21, 0, input_port, },
648 { "dma@8", 22, 0, input_port, },
649 { "dma@9", 23, 0, input_port, },
650 { "dma@10", 24, 0, input_port, },
651 { "dma@11", 25, 0, input_port, },
652 { "otp", 26, 0, input_port, },
653 { "counter", 27, 0, input_port, },
654 { "dma@1", 28, 0, input_port, },
655 { "porth_irq_a", 29, 0, input_port, },
656 { "dma@2", 30, 0, input_port, },
657 { "porth_irq_b", 31, 0, input_port, },
658 /* SIC1 */
659 { "gptimer@0", 100, 0, input_port, },
660 { "gptimer@1", 101, 0, input_port, },
661 { "gptimer@2", 102, 0, input_port, },
662 { "gptimer@3", 103, 0, input_port, },
663 { "gptimer@4", 104, 0, input_port, },
664 { "gptimer@5", 105, 0, input_port, },
665 { "gptimer@6", 106, 0, input_port, },
666 { "gptimer@7", 107, 0, input_port, },
667 { "portg_irq_a", 108, 0, input_port, },
668 { "portg_irq_b", 109, 0, input_port, },
669 { "mdma@0", 110, 0, input_port, },
670 { "mdma@1", 111, 0, input_port, },
671 { "wdog", 112, 0, input_port, },
672 { "portf_irq_a", 113, 0, input_port, },
673 { "portf_irq_b", 114, 0, input_port, },
674 { "spi@0", 115, 0, input_port, },
675 { "spi@1", 116, 0, input_port, },
676 /*{ "reserved", 117, 0, input_port, },*/
677 /*{ "reserved", 118, 0, input_port, },*/
678 { "rsi_int0", 119, 0, input_port, },
679 { "rsi_int1", 120, 0, input_port, },
680 { "pwm_trip", 121, 0, input_port, },
681 { "pwm_sync", 122, 0, input_port, },
682 { "ptp_stat", 123, 0, input_port, },
683 { NULL, 0, 0, 0, },
684 };
685
686 static const struct hw_port_descriptor bfin_sic_52x_ports[] = {
687 BFIN_SIC_TO_CEC_PORTS
688 /* SIC0 */
689 { "pll", 0, 0, input_port, },
690 { "dma_stat", 1, 0, input_port, },
691 { "dmar0_block", 2, 0, input_port, },
692 { "dmar1_block", 3, 0, input_port, },
693 { "dmar0_over", 4, 0, input_port, },
694 { "dmar1_over", 5, 0, input_port, },
695 { "ppi@0", 6, 0, input_port, },
696 { "emac_stat", 7, 0, input_port, },
697 { "sport@0_stat", 8, 0, input_port, },
698 { "sport@1_stat", 9, 0, input_port, },
699 /*{ "reserved", 10, 0, input_port, },*/
700 /*{ "reserved", 11, 0, input_port, },*/
701 { "uart@0_stat", 12, 0, input_port, },
702 { "uart@1_stat", 13, 0, input_port, },
703 { "rtc", 14, 0, input_port, },
704 { "dma@0", 15, 0, input_port, },
705 { "dma@3", 16, 0, input_port, },
706 { "dma@4", 17, 0, input_port, },
707 { "dma@5", 18, 0, input_port, },
708 { "dma@6", 19, 0, input_port, },
709 { "twi@0", 20, 0, input_port, },
710 { "dma@7", 21, 0, input_port, },
711 { "dma@8", 22, 0, input_port, },
712 { "dma@9", 23, 0, input_port, },
713 { "dma@10", 24, 0, input_port, },
714 { "dma@11", 25, 0, input_port, },
715 { "otp", 26, 0, input_port, },
716 { "counter", 27, 0, input_port, },
717 { "dma@1", 28, 0, input_port, },
718 { "porth_irq_a", 29, 0, input_port, },
719 { "dma@2", 30, 0, input_port, },
720 { "porth_irq_b", 31, 0, input_port, },
721 /* SIC1 */
722 { "gptimer@0", 100, 0, input_port, },
723 { "gptimer@1", 101, 0, input_port, },
724 { "gptimer@2", 102, 0, input_port, },
725 { "gptimer@3", 103, 0, input_port, },
726 { "gptimer@4", 104, 0, input_port, },
727 { "gptimer@5", 105, 0, input_port, },
728 { "gptimer@6", 106, 0, input_port, },
729 { "gptimer@7", 107, 0, input_port, },
730 { "portg_irq_a", 108, 0, input_port, },
731 { "portg_irq_b", 109, 0, input_port, },
732 { "mdma@0", 110, 0, input_port, },
733 { "mdma@1", 111, 0, input_port, },
734 { "wdog", 112, 0, input_port, },
735 { "portf_irq_a", 113, 0, input_port, },
736 { "portf_irq_b", 114, 0, input_port, },
737 { "spi@0", 115, 0, input_port, },
738 { "nfc_stat", 116, 0, input_port, },
739 { "hostdp_stat", 117, 0, input_port, },
740 { "hostdp_done", 118, 0, input_port, },
741 { "usb_int0", 120, 0, input_port, },
742 { "usb_int1", 121, 0, input_port, },
743 { "usb_int2", 122, 0, input_port, },
744 { NULL, 0, 0, 0, },
745 };
746
747 static void
748 bfin_sic_52x_port_event (struct hw *me, int my_port, struct hw *source,
749 int source_port, int level)
750 {
751 struct bfin_sic *sic = hw_data (me);
752 bu32 idx = my_port / 100;
753 bu32 bit = (1 << (my_port & 0x1f));
754
755 /* SIC only exists to forward interrupts from the system to the CEC. */
756 switch (idx)
757 {
758 case 0: sic->bf52x.isr0 |= bit; break;
759 case 1: sic->bf52x.isr1 |= bit; break;
760 }
761
762 /* XXX: Handle SIC wakeup source ?
763 if (sic->bf52x.iwr0 & bit)
764 What to do ?;
765 if (sic->bf52x.iwr1 & bit)
766 What to do ?;
767 */
768
769 bfin_sic_52x_forward_interrupts (me, sic);
770 }
771
772 static const struct hw_port_descriptor bfin_sic_533_ports[] = {
773 BFIN_SIC_TO_CEC_PORTS
774 { "pll", 0, 0, input_port, },
775 { "dma_stat", 1, 0, input_port, },
776 { "ppi@0", 2, 0, input_port, },
777 { "sport@0_stat", 3, 0, input_port, },
778 { "sport@1_stat", 4, 0, input_port, },
779 { "spi@0", 5, 0, input_port, },
780 { "uart@0_stat", 6, 0, input_port, },
781 { "rtc", 7, 0, input_port, },
782 { "dma@0", 8, 0, input_port, },
783 { "dma@1", 9, 0, input_port, },
784 { "dma@2", 10, 0, input_port, },
785 { "dma@3", 11, 0, input_port, },
786 { "dma@4", 12, 0, input_port, },
787 { "dma@5", 13, 0, input_port, },
788 { "dma@6", 14, 0, input_port, },
789 { "dma@7", 15, 0, input_port, },
790 { "gptimer@0", 16, 0, input_port, },
791 { "gptimer@1", 17, 0, input_port, },
792 { "gptimer@2", 18, 0, input_port, },
793 { "portf_irq_a", 19, 0, input_port, },
794 { "portf_irq_b", 20, 0, input_port, },
795 { "mdma@0", 21, 0, input_port, },
796 { "mdma@1", 22, 0, input_port, },
797 { "wdog", 23, 0, input_port, },
798 { NULL, 0, 0, 0, },
799 };
800
801 static void
802 bfin_sic_533_port_event (struct hw *me, int my_port, struct hw *source,
803 int source_port, int level)
804 {
805 struct bfin_sic *sic = hw_data (me);
806 bu32 bit = (1 << my_port);
807
808 /* SIC only exists to forward interrupts from the system to the CEC. */
809 sic->bf537.isr |= bit;
810
811 /* XXX: Handle SIC wakeup source ?
812 if (sic->bf537.iwr & bit)
813 What to do ?;
814 */
815
816 bfin_sic_537_forward_interrupts (me, sic);
817 }
818
819 static const struct hw_port_descriptor bfin_sic_537_ports[] = {
820 BFIN_SIC_TO_CEC_PORTS
821 { "pll", 0, 0, input_port, },
822 { "dma_stat", 10, 0, input_port, },
823 { "dmar0_block", 11, 0, input_port, },
824 { "dmar1_block", 12, 0, input_port, },
825 { "dmar0_over", 13, 0, input_port, },
826 { "dmar1_over", 14, 0, input_port, },
827 { "can_stat", 20, 0, input_port, },
828 { "emac_stat", 21, 0, input_port, },
829 { "sport@0_stat", 22, 0, input_port, },
830 { "sport@1_stat", 23, 0, input_port, },
831 { "ppi@0", 24, 0, input_port, },
832 { "spi@0", 25, 0, input_port, },
833 { "uart@0_stat", 26, 0, input_port, },
834 { "uart@1_stat", 27, 0, input_port, },
835 { "rtc", 30, 0, input_port, },
836 { "dma@0", 40, 0, input_port, },
837 { "dma@3", 50, 0, input_port, },
838 { "dma@4", 60, 0, input_port, },
839 { "dma@5", 70, 0, input_port, },
840 { "dma@6", 80, 0, input_port, },
841 { "twi@0", 90, 0, input_port, },
842 { "dma@7", 100, 0, input_port, },
843 { "dma@8", 110, 0, input_port, },
844 { "dma@9", 120, 0, input_port, },
845 { "dma@10", 130, 0, input_port, },
846 { "dma@11", 140, 0, input_port, },
847 { "can_rx", 150, 0, input_port, },
848 { "can_tx", 160, 0, input_port, },
849 { "dma@1", 170, 0, input_port, },
850 { "porth_irq_a", 171, 0, input_port, },
851 { "dma@2", 180, 0, input_port, },
852 { "porth_irq_b", 181, 0, input_port, },
853 { "gptimer@0", 190, 0, input_port, },
854 { "gptimer@1", 200, 0, input_port, },
855 { "gptimer@2", 210, 0, input_port, },
856 { "gptimer@3", 220, 0, input_port, },
857 { "gptimer@4", 230, 0, input_port, },
858 { "gptimer@5", 240, 0, input_port, },
859 { "gptimer@6", 250, 0, input_port, },
860 { "gptimer@7", 260, 0, input_port, },
861 { "portf_irq_a", 270, 0, input_port, },
862 { "portg_irq_a", 271, 0, input_port, },
863 { "portg_irq_b", 280, 0, input_port, },
864 { "mdma@0", 290, 0, input_port, },
865 { "mdma@1", 300, 0, input_port, },
866 { "wdog", 310, 0, input_port, },
867 { "portf_irq_b", 311, 0, input_port, },
868 { NULL, 0, 0, 0, },
869 };
870
871 static void
872 bfin_sic_537_port_event (struct hw *me, int my_port, struct hw *source,
873 int source_port, int level)
874 {
875 struct bfin_sic *sic = hw_data (me);
876 bu32 bit = (1 << (my_port / 10));
877
878 /* SIC only exists to forward interrupts from the system to the CEC. */
879 sic->bf537.isr |= bit;
880
881 /* XXX: Handle SIC wakeup source ?
882 if (sic->bf537.iwr & bit)
883 What to do ?;
884 */
885
886 bfin_sic_537_forward_interrupts (me, sic);
887 }
888
889 static const struct hw_port_descriptor bfin_sic_538_ports[] = {
890 BFIN_SIC_TO_CEC_PORTS
891 /* SIC0 */
892 { "pll", 0, 0, input_port, },
893 { "dmac@0_stat", 1, 0, input_port, },
894 { "ppi@0", 2, 0, input_port, },
895 { "sport@0_stat", 3, 0, input_port, },
896 { "sport@1_stat", 4, 0, input_port, },
897 { "spi@0", 5, 0, input_port, },
898 { "uart@0_stat", 6, 0, input_port, },
899 { "rtc", 7, 0, input_port, },
900 { "dma@0", 8, 0, input_port, },
901 { "dma@1", 9, 0, input_port, },
902 { "dma@2", 10, 0, input_port, },
903 { "dma@3", 11, 0, input_port, },
904 { "dma@4", 12, 0, input_port, },
905 { "dma@5", 13, 0, input_port, },
906 { "dma@6", 14, 0, input_port, },
907 { "dma@7", 15, 0, input_port, },
908 { "gptimer@0", 16, 0, input_port, },
909 { "gptimer@1", 17, 0, input_port, },
910 { "gptimer@2", 18, 0, input_port, },
911 { "portf_irq_a", 19, 0, input_port, },
912 { "portf_irq_b", 20, 0, input_port, },
913 { "mdma@0", 21, 0, input_port, },
914 { "mdma@1", 22, 0, input_port, },
915 { "wdog", 23, 0, input_port, },
916 { "dmac@1_stat", 24, 0, input_port, },
917 { "sport@2_stat", 25, 0, input_port, },
918 { "sport@3_stat", 26, 0, input_port, },
919 /*{ "reserved", 27, 0, input_port, },*/
920 { "spi@1", 28, 0, input_port, },
921 { "spi@2", 29, 0, input_port, },
922 { "uart@1_stat", 30, 0, input_port, },
923 { "uart@2_stat", 31, 0, input_port, },
924 /* SIC1 */
925 { "can_stat", 100, 0, input_port, },
926 { "dma@8", 101, 0, input_port, },
927 { "dma@9", 102, 0, input_port, },
928 { "dma@10", 103, 0, input_port, },
929 { "dma@11", 104, 0, input_port, },
930 { "dma@12", 105, 0, input_port, },
931 { "dma@13", 106, 0, input_port, },
932 { "dma@14", 107, 0, input_port, },
933 { "dma@15", 108, 0, input_port, },
934 { "dma@16", 109, 0, input_port, },
935 { "dma@17", 110, 0, input_port, },
936 { "dma@18", 111, 0, input_port, },
937 { "dma@19", 112, 0, input_port, },
938 { "twi@0", 113, 0, input_port, },
939 { "twi@1", 114, 0, input_port, },
940 { "can_rx", 115, 0, input_port, },
941 { "can_tx", 116, 0, input_port, },
942 { "mdma@2", 117, 0, input_port, },
943 { "mdma@3", 118, 0, input_port, },
944 { NULL, 0, 0, 0, },
945 };
946
947 static const struct hw_port_descriptor bfin_sic_54x_ports[] = {
948 BFIN_SIC_TO_CEC_PORTS
949 /* SIC0 */
950 { "pll", 0, 0, input_port, },
951 { "dmac@0_stat", 1, 0, input_port, },
952 { "eppi@0", 2, 0, input_port, },
953 { "sport@0_stat", 3, 0, input_port, },
954 { "sport@1_stat", 4, 0, input_port, },
955 { "spi@0", 5, 0, input_port, },
956 { "uart2@0_stat", 6, 0, input_port, },
957 { "rtc", 7, 0, input_port, },
958 { "dma@12", 8, 0, input_port, },
959 { "dma@0", 9, 0, input_port, },
960 { "dma@1", 10, 0, input_port, },
961 { "dma@2", 11, 0, input_port, },
962 { "dma@3", 12, 0, input_port, },
963 { "dma@4", 13, 0, input_port, },
964 { "dma@6", 14, 0, input_port, },
965 { "dma@7", 15, 0, input_port, },
966 { "gptimer@8", 16, 0, input_port, },
967 { "gptimer@9", 17, 0, input_port, },
968 { "gptimer@10", 18, 0, input_port, },
969 { "pint@0", 19, 0, input_port, },
970 { "pint@1", 20, 0, input_port, },
971 { "mdma@0", 21, 0, input_port, },
972 { "mdma@1", 22, 0, input_port, },
973 { "wdog", 23, 0, input_port, },
974 { "dmac@1_stat", 24, 0, input_port, },
975 { "sport@2_stat", 25, 0, input_port, },
976 { "sport@3_stat", 26, 0, input_port, },
977 { "mxvr", 27, 0, input_port, },
978 { "spi@1", 28, 0, input_port, },
979 { "spi@2", 29, 0, input_port, },
980 { "uart2@1_stat", 30, 0, input_port, },
981 { "uart2@2_stat", 31, 0, input_port, },
982 /* SIC1 */
983 { "can@0_stat", 32, 0, input_port, },
984 { "dma@18", 33, 0, input_port, },
985 { "dma@19", 34, 0, input_port, },
986 { "dma@20", 35, 0, input_port, },
987 { "dma@21", 36, 0, input_port, },
988 { "dma@13", 37, 0, input_port, },
989 { "dma@14", 38, 0, input_port, },
990 { "dma@5", 39, 0, input_port, },
991 { "dma@23", 40, 0, input_port, },
992 { "dma@8", 41, 0, input_port, },
993 { "dma@9", 42, 0, input_port, },
994 { "dma@10", 43, 0, input_port, },
995 { "dma@11", 44, 0, input_port, },
996 { "twi@0", 45, 0, input_port, },
997 { "twi@1", 46, 0, input_port, },
998 { "can@0_rx", 47, 0, input_port, },
999 { "can@0_tx", 48, 0, input_port, },
1000 { "mdma@2", 49, 0, input_port, },
1001 { "mdma@3", 50, 0, input_port, },
1002 { "mxvr_stat", 51, 0, input_port, },
1003 { "mxvr_message", 52, 0, input_port, },
1004 { "mxvr_packet", 53, 0, input_port, },
1005 { "eppi@1", 54, 0, input_port, },
1006 { "eppi@2", 55, 0, input_port, },
1007 { "uart2@3_stat", 56, 0, input_port, },
1008 { "hostdp", 57, 0, input_port, },
1009 /*{ "reserved", 58, 0, input_port, },*/
1010 { "pixc_stat", 59, 0, input_port, },
1011 { "nfc", 60, 0, input_port, },
1012 { "atapi", 61, 0, input_port, },
1013 { "can@1_stat", 62, 0, input_port, },
1014 { "dmar", 63, 0, input_port, },
1015 /* SIC2 */
1016 { "dma@15", 64, 0, input_port, },
1017 { "dma@16", 65, 0, input_port, },
1018 { "dma@17", 66, 0, input_port, },
1019 { "dma@22", 67, 0, input_port, },
1020 { "counter", 68, 0, input_port, },
1021 { "key", 69, 0, input_port, },
1022 { "can@1_rx", 70, 0, input_port, },
1023 { "can@1_tx", 71, 0, input_port, },
1024 { "sdh_mask0", 72, 0, input_port, },
1025 { "sdh_mask1", 73, 0, input_port, },
1026 /*{ "reserved", 74, 0, input_port, },*/
1027 { "usb_int0", 75, 0, input_port, },
1028 { "usb_int1", 76, 0, input_port, },
1029 { "usb_int2", 77, 0, input_port, },
1030 { "usb_dma", 78, 0, input_port, },
1031 { "otpsec", 79, 0, input_port, },
1032 /*{ "reserved", 80, 0, input_port, },*/
1033 /*{ "reserved", 81, 0, input_port, },*/
1034 /*{ "reserved", 82, 0, input_port, },*/
1035 /*{ "reserved", 83, 0, input_port, },*/
1036 /*{ "reserved", 84, 0, input_port, },*/
1037 /*{ "reserved", 85, 0, input_port, },*/
1038 { "gptimer@0", 86, 0, input_port, },
1039 { "gptimer@1", 87, 0, input_port, },
1040 { "gptimer@2", 88, 0, input_port, },
1041 { "gptimer@3", 89, 0, input_port, },
1042 { "gptimer@4", 90, 0, input_port, },
1043 { "gptimer@5", 91, 0, input_port, },
1044 { "gptimer@6", 92, 0, input_port, },
1045 { "gptimer@7", 93, 0, input_port, },
1046 { "pint2", 94, 0, input_port, },
1047 { "pint3", 95, 0, input_port, },
1048 { NULL, 0, 0, 0, },
1049 };
1050
1051 static void
1052 bfin_sic_54x_port_event (struct hw *me, int my_port, struct hw *source,
1053 int source_port, int level)
1054 {
1055 struct bfin_sic *sic = hw_data (me);
1056 bu32 idx = my_port / 100;
1057 bu32 bit = (1 << (my_port & 0x1f));
1058
1059 /* SIC only exists to forward interrupts from the system to the CEC. */
1060 switch (idx)
1061 {
1062 case 0: sic->bf54x.isr0 |= bit; break;
1063 case 1: sic->bf54x.isr1 |= bit; break;
1064 case 2: sic->bf54x.isr2 |= bit; break;
1065 }
1066
1067 /* XXX: Handle SIC wakeup source ?
1068 if (sic->bf54x.iwr0 & bit)
1069 What to do ?;
1070 if (sic->bf54x.iwr1 & bit)
1071 What to do ?;
1072 if (sic->bf54x.iwr2 & bit)
1073 What to do ?;
1074 */
1075
1076 bfin_sic_54x_forward_interrupts (me, sic);
1077 }
1078
1079 static const struct hw_port_descriptor bfin_sic_561_ports[] = {
1080 BFIN_SIC_TO_CEC_PORTS
1081 /* SIC0 */
1082 { "pll", 0, 0, input_port, },
1083 { "dmac@0_stat", 1, 0, input_port, },
1084 { "dmac@1_stat", 2, 0, input_port, },
1085 { "imdma_stat", 3, 0, input_port, },
1086 { "ppi@0", 4, 0, input_port, },
1087 { "ppi@1", 5, 0, input_port, },
1088 { "sport@0_stat", 6, 0, input_port, },
1089 { "sport@1_stat", 7, 0, input_port, },
1090 { "spi@0", 8, 0, input_port, },
1091 { "uart@0_stat", 9, 0, input_port, },
1092 /*{ "reserved", 10, 0, input_port, },*/
1093 { "dma@12", 11, 0, input_port, },
1094 { "dma@13", 12, 0, input_port, },
1095 { "dma@14", 13, 0, input_port, },
1096 { "dma@15", 14, 0, input_port, },
1097 { "dma@16", 15, 0, input_port, },
1098 { "dma@17", 16, 0, input_port, },
1099 { "dma@18", 17, 0, input_port, },
1100 { "dma@19", 18, 0, input_port, },
1101 { "dma@20", 19, 0, input_port, },
1102 { "dma@21", 20, 0, input_port, },
1103 { "dma@22", 21, 0, input_port, },
1104 { "dma@23", 22, 0, input_port, },
1105 { "dma@0", 23, 0, input_port, },
1106 { "dma@1", 24, 0, input_port, },
1107 { "dma@2", 25, 0, input_port, },
1108 { "dma@3", 26, 0, input_port, },
1109 { "dma@4", 27, 0, input_port, },
1110 { "dma@5", 28, 0, input_port, },
1111 { "dma@6", 29, 0, input_port, },
1112 { "dma@7", 30, 0, input_port, },
1113 { "dma@8", 31, 0, input_port, },
1114 /* SIC1 */
1115 { "dma@9", 100, 0, input_port, },
1116 { "dma@10", 101, 0, input_port, },
1117 { "dma@11", 102, 0, input_port, },
1118 { "gptimer@0", 103, 0, input_port, },
1119 { "gptimer@1", 104, 0, input_port, },
1120 { "gptimer@2", 105, 0, input_port, },
1121 { "gptimer@3", 106, 0, input_port, },
1122 { "gptimer@4", 107, 0, input_port, },
1123 { "gptimer@5", 108, 0, input_port, },
1124 { "gptimer@6", 109, 0, input_port, },
1125 { "gptimer@7", 110, 0, input_port, },
1126 { "gptimer@8", 111, 0, input_port, },
1127 { "gptimer@9", 112, 0, input_port, },
1128 { "gptimer@10", 113, 0, input_port, },
1129 { "gptimer@11", 114, 0, input_port, },
1130 { "portf_irq_a", 115, 0, input_port, },
1131 { "portf_irq_b", 116, 0, input_port, },
1132 { "portg_irq_a", 117, 0, input_port, },
1133 { "portg_irq_b", 118, 0, input_port, },
1134 { "porth_irq_a", 119, 0, input_port, },
1135 { "porth_irq_b", 120, 0, input_port, },
1136 { "mdma@0", 121, 0, input_port, },
1137 { "mdma@1", 122, 0, input_port, },
1138 { "mdma@2", 123, 0, input_port, },
1139 { "mdma@3", 124, 0, input_port, },
1140 { "imdma@0", 125, 0, input_port, },
1141 { "imdma@1", 126, 0, input_port, },
1142 { "wdog", 127, 0, input_port, },
1143 /*{ "reserved", 128, 0, input_port, },*/
1144 /*{ "reserved", 129, 0, input_port, },*/
1145 { "sup_irq_0", 130, 0, input_port, },
1146 { "sup_irq_1", 131, 0, input_port, },
1147 { NULL, 0, 0, 0, },
1148 };
1149
1150 static void
1151 bfin_sic_561_port_event (struct hw *me, int my_port, struct hw *source,
1152 int source_port, int level)
1153 {
1154 struct bfin_sic *sic = hw_data (me);
1155 bu32 idx = my_port / 100;
1156 bu32 bit = (1 << (my_port & 0x1f));
1157
1158 /* SIC only exists to forward interrupts from the system to the CEC. */
1159 switch (idx)
1160 {
1161 case 0: sic->bf561.isr0 |= bit; break;
1162 case 1: sic->bf561.isr1 |= bit; break;
1163 }
1164
1165 /* XXX: Handle SIC wakeup source ?
1166 if (sic->bf561.iwr0 & bit)
1167 What to do ?;
1168 if (sic->bf561.iwr1 & bit)
1169 What to do ?;
1170 */
1171
1172 bfin_sic_561_forward_interrupts (me, sic);
1173 }
1174
1175 static const struct hw_port_descriptor bfin_sic_59x_ports[] = {
1176 BFIN_SIC_TO_CEC_PORTS
1177 { "pll", 0, 0, input_port, },
1178 { "dma_stat", 1, 0, input_port, },
1179 { "ppi@0", 2, 0, input_port, },
1180 { "sport@0_stat", 3, 0, input_port, },
1181 { "sport@1_stat", 4, 0, input_port, },
1182 { "spi@0", 5, 0, input_port, },
1183 { "spi@1", 6, 0, input_port, },
1184 { "uart@0_stat", 7, 0, input_port, },
1185 { "dma@0", 8, 0, input_port, },
1186 { "dma@1", 9, 0, input_port, },
1187 { "dma@2", 10, 0, input_port, },
1188 { "dma@3", 11, 0, input_port, },
1189 { "dma@4", 12, 0, input_port, },
1190 { "dma@5", 13, 0, input_port, },
1191 { "dma@6", 14, 0, input_port, },
1192 { "dma@7", 15, 0, input_port, },
1193 { "dma@8", 16, 0, input_port, },
1194 { "portf_irq_a", 17, 0, input_port, },
1195 { "portf_irq_b", 18, 0, input_port, },
1196 { "gptimer@0", 19, 0, input_port, },
1197 { "gptimer@1", 20, 0, input_port, },
1198 { "gptimer@2", 21, 0, input_port, },
1199 { "portg_irq_a", 22, 0, input_port, },
1200 { "portg_irq_b", 23, 0, input_port, },
1201 { "twi@0", 24, 0, input_port, },
1202 /* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */
1203 { "dma@9", 25, 0, input_port, },
1204 { "dma@10", 26, 0, input_port, },
1205 { "dma@11", 27, 0, input_port, },
1206 { "dma@12", 28, 0, input_port, },
1207 /*{ "reserved", 25, 0, input_port, },*/
1208 /*{ "reserved", 26, 0, input_port, },*/
1209 /*{ "reserved", 27, 0, input_port, },*/
1210 /*{ "reserved", 28, 0, input_port, },*/
1211 { "mdma@0", 29, 0, input_port, },
1212 { "mdma@1", 30, 0, input_port, },
1213 { "wdog", 31, 0, input_port, },
1214 { NULL, 0, 0, 0, },
1215 };
1216
1217 static void
1218 attach_bfin_sic_regs (struct hw *me, struct bfin_sic *sic)
1219 {
1220 address_word attach_address;
1221 int attach_space;
1222 unsigned attach_size;
1223 reg_property_spec reg;
1224
1225 if (hw_find_property (me, "reg") == NULL)
1226 hw_abort (me, "Missing \"reg\" property");
1227
1228 if (!hw_find_reg_array_property (me, "reg", 0, &reg))
1229 hw_abort (me, "\"reg\" property must contain three addr/size entries");
1230
1231 hw_unit_address_to_attach_address (hw_parent (me),
1232 &reg.address,
1233 &attach_space, &attach_address, me);
1234 hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
1235
1236 if (attach_size != BFIN_MMR_SIC_SIZE)
1237 hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_SIC_SIZE);
1238
1239 hw_attach_address (hw_parent (me),
1240 0, attach_space, attach_address, attach_size, me);
1241
1242 sic->base = attach_address;
1243 }
1244
1245 static void
1246 bfin_sic_finish (struct hw *me)
1247 {
1248 struct bfin_sic *sic;
1249
1250 sic = HW_ZALLOC (me, struct bfin_sic);
1251
1252 set_hw_data (me, sic);
1253 attach_bfin_sic_regs (me, sic);
1254
1255 switch (hw_find_integer_property (me, "type"))
1256 {
1257 case 500 ... 509:
1258 set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
1259 set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
1260 set_hw_ports (me, bfin_sic_50x_ports);
1261 set_hw_port_event (me, bfin_sic_52x_port_event);
1262 mmr_names = bf52x_mmr_names;
1263
1264 /* Initialize the SIC. */
1265 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
1266 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
1267 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
1268 sic->bf52x.iar0 = 0x00000000;
1269 sic->bf52x.iar1 = 0x22111000;
1270 sic->bf52x.iar2 = 0x33332222;
1271 sic->bf52x.iar3 = 0x44444433;
1272 sic->bf52x.iar4 = 0x55555555;
1273 sic->bf52x.iar5 = 0x06666655;
1274 sic->bf52x.iar6 = 0x33333003;
1275 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
1276 break;
1277 case 510 ... 519:
1278 set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
1279 set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
1280 set_hw_ports (me, bfin_sic_51x_ports);
1281 set_hw_port_event (me, bfin_sic_52x_port_event);
1282 mmr_names = bf52x_mmr_names;
1283
1284 /* Initialize the SIC. */
1285 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
1286 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
1287 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
1288 sic->bf52x.iar0 = 0x00000000;
1289 sic->bf52x.iar1 = 0x11000000;
1290 sic->bf52x.iar2 = 0x33332222;
1291 sic->bf52x.iar3 = 0x44444433;
1292 sic->bf52x.iar4 = 0x55555555;
1293 sic->bf52x.iar5 = 0x06666655;
1294 sic->bf52x.iar6 = 0x33333000;
1295 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
1296 break;
1297 case 522 ... 527:
1298 set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
1299 set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
1300 set_hw_ports (me, bfin_sic_52x_ports);
1301 set_hw_port_event (me, bfin_sic_52x_port_event);
1302 mmr_names = bf52x_mmr_names;
1303
1304 /* Initialize the SIC. */
1305 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
1306 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
1307 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
1308 sic->bf52x.iar0 = 0x00000000;
1309 sic->bf52x.iar1 = 0x11000000;
1310 sic->bf52x.iar2 = 0x33332222;
1311 sic->bf52x.iar3 = 0x44444433;
1312 sic->bf52x.iar4 = 0x55555555;
1313 sic->bf52x.iar5 = 0x06666655;
1314 sic->bf52x.iar6 = 0x33333000;
1315 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
1316 break;
1317 case 531 ... 533:
1318 set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
1319 set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
1320 set_hw_ports (me, bfin_sic_533_ports);
1321 set_hw_port_event (me, bfin_sic_533_port_event);
1322 mmr_names = bf537_mmr_names;
1323
1324 /* Initialize the SIC. */
1325 sic->bf537.imask = 0;
1326 sic->bf537.isr = 0;
1327 sic->bf537.iwr = 0xFFFFFFFF;
1328 sic->bf537.iar0 = 0x10000000;
1329 sic->bf537.iar1 = 0x33322221;
1330 sic->bf537.iar2 = 0x66655444;
1331 sic->bf537.iar3 = 0; /* XXX: fix this */
1332 break;
1333 case 534:
1334 case 536:
1335 case 537:
1336 set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
1337 set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
1338 set_hw_ports (me, bfin_sic_537_ports);
1339 set_hw_port_event (me, bfin_sic_537_port_event);
1340 mmr_names = bf537_mmr_names;
1341
1342 /* Initialize the SIC. */
1343 sic->bf537.imask = 0;
1344 sic->bf537.isr = 0;
1345 sic->bf537.iwr = 0xFFFFFFFF;
1346 sic->bf537.iar0 = 0x22211000;
1347 sic->bf537.iar1 = 0x43333332;
1348 sic->bf537.iar2 = 0x55555444;
1349 sic->bf537.iar3 = 0x66655555;
1350 break;
1351 case 538 ... 539:
1352 set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
1353 set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
1354 set_hw_ports (me, bfin_sic_538_ports);
1355 set_hw_port_event (me, bfin_sic_52x_port_event);
1356 mmr_names = bf52x_mmr_names;
1357
1358 /* Initialize the SIC. */
1359 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
1360 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
1361 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
1362 sic->bf52x.iar0 = 0x10000000;
1363 sic->bf52x.iar1 = 0x33322221;
1364 sic->bf52x.iar2 = 0x66655444;
1365 sic->bf52x.iar3 = 0x00000000;
1366 sic->bf52x.iar4 = 0x32222220;
1367 sic->bf52x.iar5 = 0x44433333;
1368 sic->bf52x.iar6 = 0x00444664;
1369 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
1370 break;
1371 case 540 ... 549:
1372 set_hw_io_read_buffer (me, bfin_sic_54x_io_read_buffer);
1373 set_hw_io_write_buffer (me, bfin_sic_54x_io_write_buffer);
1374 set_hw_ports (me, bfin_sic_54x_ports);
1375 set_hw_port_event (me, bfin_sic_54x_port_event);
1376 mmr_names = bf54x_mmr_names;
1377
1378 /* Initialize the SIC. */
1379 sic->bf54x.imask0 = sic->bf54x.imask1 = sic->bf54x.imask2 = 0;
1380 sic->bf54x.isr0 = sic->bf54x.isr1 = sic->bf54x.isr2 = 0;
1381 sic->bf54x.iwr0 = sic->bf54x.iwr1 = sic->bf54x.iwr1 = 0xFFFFFFFF;
1382 sic->bf54x.iar0 = 0x10000000;
1383 sic->bf54x.iar1 = 0x33322221;
1384 sic->bf54x.iar2 = 0x66655444;
1385 sic->bf54x.iar3 = 0x00000000;
1386 sic->bf54x.iar4 = 0x32222220;
1387 sic->bf54x.iar5 = 0x44433333;
1388 sic->bf54x.iar6 = 0x00444664;
1389 sic->bf54x.iar7 = 0x00000000;
1390 sic->bf54x.iar8 = 0x44111111;
1391 sic->bf54x.iar9 = 0x44444444;
1392 sic->bf54x.iar10 = 0x44444444;
1393 sic->bf54x.iar11 = 0x55444444;
1394 break;
1395 case 561:
1396 set_hw_io_read_buffer (me, bfin_sic_561_io_read_buffer);
1397 set_hw_io_write_buffer (me, bfin_sic_561_io_write_buffer);
1398 set_hw_ports (me, bfin_sic_561_ports);
1399 set_hw_port_event (me, bfin_sic_561_port_event);
1400 mmr_names = bf561_mmr_names;
1401
1402 /* Initialize the SIC. */
1403 sic->bf561.imask0 = sic->bf561.imask1 = 0;
1404 sic->bf561.isr0 = sic->bf561.isr1 = 0;
1405 sic->bf561.iwr0 = sic->bf561.iwr1 = 0xFFFFFFFF;
1406 sic->bf561.iar0 = 0x00000000;
1407 sic->bf561.iar1 = 0x11111000;
1408 sic->bf561.iar2 = 0x21111111;
1409 sic->bf561.iar3 = 0x22222222;
1410 sic->bf561.iar4 = 0x33333222;
1411 sic->bf561.iar5 = 0x43333333;
1412 sic->bf561.iar6 = 0x21144444;
1413 sic->bf561.iar7 = 0x00006552;
1414 break;
1415 case 590 ... 599:
1416 set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
1417 set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
1418 set_hw_ports (me, bfin_sic_59x_ports);
1419 set_hw_port_event (me, bfin_sic_533_port_event);
1420 mmr_names = bf537_mmr_names;
1421
1422 /* Initialize the SIC. */
1423 sic->bf537.imask = 0;
1424 sic->bf537.isr = 0;
1425 sic->bf537.iwr = 0xFFFFFFFF;
1426 sic->bf537.iar0 = 0x00000000;
1427 sic->bf537.iar1 = 0x33322221;
1428 sic->bf537.iar2 = 0x55444443;
1429 sic->bf537.iar3 = 0x66600005;
1430 break;
1431 default:
1432 hw_abort (me, "no support for SIC on this Blackfin model yet");
1433 }
1434 }
1435
1436 const struct hw_descriptor dv_bfin_sic_descriptor[] = {
1437 {"bfin_sic", bfin_sic_finish,},
1438 {NULL, NULL},
1439 };
GDB Binutils - Deliverables
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