1 /* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model.
2 For "old style" UARTs on BF53x/etc... parts.
4 Copyright (C) 2010-2012 Free Software Foundation, Inc.
5 Contributed by Analog Devices, Inc.
7 This file is part of simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "dv-sockser.h"
27 #include "dv-bfin_uart.h"
29 /* XXX: Should we bother emulating the TX/RX FIFOs ? */
31 /* Internal state needs to be the same as bfin_uart2. */
34 /* This top portion matches common dv_bfin struct. */
36 struct hw
*dma_master
;
39 struct hw_event
*handler
;
43 /* This is aliased to DLH. */
45 /* These are aliased to DLL. */
48 /* Order after here is important -- matches hardware MMR layout. */
49 bu16
BFIN_MMR_16(dll
);
50 bu16
BFIN_MMR_16(dlh
);
51 bu16
BFIN_MMR_16(iir
);
52 bu16
BFIN_MMR_16(lcr
);
53 bu16
BFIN_MMR_16(mcr
);
54 bu16
BFIN_MMR_16(lsr
);
55 bu16
BFIN_MMR_16(msr
);
56 bu16
BFIN_MMR_16(scr
);
58 bu16
BFIN_MMR_16(gctl
);
60 #define mmr_base() offsetof(struct bfin_uart, dll)
61 #define mmr_offset(mmr) (offsetof(struct bfin_uart, mmr) - mmr_base())
63 static const char * const mmr_names
[] =
65 "UART_RBR/UART_THR", "UART_IER", "UART_IIR", "UART_LCR", "UART_MCR",
66 "UART_LSR", "UART_MSR", "UART_SCR", "<INV>", "UART_GCTL",
68 static const char *mmr_name (struct bfin_uart
*uart
, bu32 idx
)
72 return idx
== 0 ? "UART_DLL" : "UART_DLH";
73 return mmr_names
[idx
];
75 #define mmr_name(off) mmr_name (uart, (off) / 4)
77 #ifndef HAVE_DV_SOCKSER
78 # define dv_sockser_status(sd) -1
79 # define dv_sockser_write(sd, byte) do { ; } while (0)
80 # define dv_sockser_read(sd) 0xff
84 bfin_uart_poll (struct hw
*me
, void *data
)
86 struct bfin_uart
*uart
= data
;
91 lsr
= bfin_uart_get_status (me
);
93 hw_port_event (me
, DV_PORT_RX
, 1);
95 bfin_uart_reschedule (me
);
99 bfin_uart_reschedule (struct hw
*me
)
101 struct bfin_uart
*uart
= hw_data (me
);
103 if (uart
->ier
& ERBFI
)
106 uart
->handler
= hw_event_queue_schedule (me
, 10000,
107 bfin_uart_poll
, uart
);
113 hw_event_queue_deschedule (me
, uart
->handler
);
114 uart
->handler
= NULL
;
120 bfin_uart_write_byte (struct hw
*me
, bu16 thr
, bu16 mcr
)
122 struct bfin_uart
*uart
= hw_data (me
);
123 unsigned char ch
= thr
;
127 /* XXX: This probably doesn't work exactly right with
128 external FIFOs ... */
129 uart
->saved_byte
= thr
;
130 uart
->saved_count
= 1;
133 bfin_uart_write_buffer (me
, &ch
, 1);
139 bfin_uart_io_write_buffer (struct hw
*me
, const void *source
,
140 int space
, address_word addr
, unsigned nr_bytes
)
142 struct bfin_uart
*uart
= hw_data (me
);
147 value
= dv_load_2 (source
);
148 mmr_off
= addr
- uart
->base
;
149 valuep
= (void *)((unsigned long)uart
+ mmr_base() + mmr_off
);
153 dv_bfin_mmr_require_16 (me
, addr
, nr_bytes
, true);
155 /* XXX: All MMRs are "8bit" ... what happens to high 8bits ? */
158 case mmr_offset(dll
):
159 if (uart
->lcr
& DLAB
)
163 uart
->thr
= bfin_uart_write_byte (me
, value
, uart
->mcr
);
165 if (uart
->ier
& ETBEI
)
166 hw_port_event (me
, DV_PORT_TX
, 1);
169 case mmr_offset(dlh
):
170 if (uart
->lcr
& DLAB
)
175 bfin_uart_reschedule (me
);
178 case mmr_offset(iir
):
179 case mmr_offset(lsr
):
180 /* XXX: Writes are ignored ? */
182 case mmr_offset(lcr
):
183 case mmr_offset(mcr
):
184 case mmr_offset(scr
):
185 case mmr_offset(gctl
):
189 dv_bfin_mmr_invalid (me
, addr
, nr_bytes
, true);
196 /* Switch between socket and stdin on the fly. */
198 bfin_uart_get_next_byte (struct hw
*me
, bu16 rbr
, bu16 mcr
, bool *fresh
)
200 SIM_DESC sd
= hw_system (me
);
201 struct bfin_uart
*uart
= hw_data (me
);
202 int status
= dv_sockser_status (sd
);
205 /* NB: The "uart" here may only use interal state. */
212 if (uart
->saved_count
> 0)
215 rbr
= uart
->saved_byte
;
218 else if (mcr
& LOOP_ENA
)
220 /* RX is disconnected, so only return local data. */
222 else if (status
& DV_SOCKSER_DISCONNECTED
)
225 int ret
= sim_io_poll_read (sd
, 0/*STDIN*/, &byte
, 1);
234 rbr
= dv_sockser_read (sd
);
240 bfin_uart_get_status (struct hw
*me
)
242 SIM_DESC sd
= hw_system (me
);
243 struct bfin_uart
*uart
= hw_data (me
);
244 int status
= dv_sockser_status (sd
);
247 if (status
& DV_SOCKSER_DISCONNECTED
)
249 if (uart
->saved_count
<= 0)
250 uart
->saved_count
= sim_io_poll_read (sd
, 0/*STDIN*/,
251 &uart
->saved_byte
, 1);
252 lsr
|= TEMT
| THRE
| (uart
->saved_count
> 0 ? DR
: 0);
255 lsr
|= (status
& DV_SOCKSER_INPUT_EMPTY
? 0 : DR
) |
256 (status
& DV_SOCKSER_OUTPUT_EMPTY
? TEMT
| THRE
: 0);
262 bfin_uart_io_read_buffer (struct hw
*me
, void *dest
,
263 int space
, address_word addr
, unsigned nr_bytes
)
265 struct bfin_uart
*uart
= hw_data (me
);
269 mmr_off
= addr
- uart
->base
;
270 valuep
= (void *)((unsigned long)uart
+ mmr_base() + mmr_off
);
274 dv_bfin_mmr_require_16 (me
, addr
, nr_bytes
, false);
278 case mmr_offset(dll
):
279 if (uart
->lcr
& DLAB
)
280 dv_store_2 (dest
, uart
->dll
);
283 uart
->rbr
= bfin_uart_get_next_byte (me
, uart
->rbr
, uart
->mcr
, NULL
);
284 dv_store_2 (dest
, uart
->rbr
);
287 case mmr_offset(dlh
):
288 if (uart
->lcr
& DLAB
)
289 dv_store_2 (dest
, uart
->dlh
);
291 dv_store_2 (dest
, uart
->ier
);
293 case mmr_offset(lsr
):
294 /* XXX: Reads are destructive on most parts, but not all ... */
295 uart
->lsr
|= bfin_uart_get_status (me
);
296 dv_store_2 (dest
, *valuep
);
299 case mmr_offset(iir
):
300 /* XXX: Reads are destructive ... */
301 case mmr_offset(lcr
):
302 case mmr_offset(mcr
):
303 case mmr_offset(scr
):
304 case mmr_offset(gctl
):
305 dv_store_2 (dest
, *valuep
);
308 dv_bfin_mmr_invalid (me
, addr
, nr_bytes
, false);
316 bfin_uart_read_buffer (struct hw
*me
, unsigned char *buffer
, unsigned nr_bytes
)
318 SIM_DESC sd
= hw_system (me
);
319 struct bfin_uart
*uart
= hw_data (me
);
320 int status
= dv_sockser_status (sd
);
323 if (status
& DV_SOCKSER_DISCONNECTED
)
327 while (uart
->saved_count
> 0 && i
< nr_bytes
)
329 buffer
[i
++] = uart
->saved_byte
;
333 ret
= sim_io_poll_read (sd
, 0/*STDIN*/, (char *) buffer
, nr_bytes
- i
);
338 buffer
[i
++] = dv_sockser_read (sd
);
344 bfin_uart_dma_read_buffer (struct hw
*me
, void *dest
, int space
,
345 unsigned_word addr
, unsigned nr_bytes
)
347 HW_TRACE_DMA_READ ();
348 return bfin_uart_read_buffer (me
, dest
, nr_bytes
);
352 bfin_uart_write_buffer (struct hw
*me
, const unsigned char *buffer
,
355 SIM_DESC sd
= hw_system (me
);
356 int status
= dv_sockser_status (sd
);
358 if (status
& DV_SOCKSER_DISCONNECTED
)
360 sim_io_write_stdout (sd
, (const char *) buffer
, nr_bytes
);
361 sim_io_flush_stdout (sd
);
365 /* Normalize errors to a value of 0. */
366 int ret
= dv_sockser_write_buffer (sd
, buffer
, nr_bytes
);
367 nr_bytes
= CLAMP (ret
, 0, nr_bytes
);
374 bfin_uart_dma_write_buffer (struct hw
*me
, const void *source
,
375 int space
, unsigned_word addr
,
377 int violate_read_only_section
)
379 struct bfin_uart
*uart
= hw_data (me
);
382 HW_TRACE_DMA_WRITE ();
384 ret
= bfin_uart_write_buffer (me
, source
, nr_bytes
);
386 if (ret
== nr_bytes
&& (uart
->ier
& ETBEI
))
387 hw_port_event (me
, DV_PORT_TX
, 1);
392 static const struct hw_port_descriptor bfin_uart_ports
[] =
394 { "tx", DV_PORT_TX
, 0, output_port
, },
395 { "rx", DV_PORT_RX
, 0, output_port
, },
396 { "stat", DV_PORT_STAT
, 0, output_port
, },
401 attach_bfin_uart_regs (struct hw
*me
, struct bfin_uart
*uart
)
403 address_word attach_address
;
405 unsigned attach_size
;
406 reg_property_spec reg
;
408 if (hw_find_property (me
, "reg") == NULL
)
409 hw_abort (me
, "Missing \"reg\" property");
411 if (!hw_find_reg_array_property (me
, "reg", 0, ®
))
412 hw_abort (me
, "\"reg\" property must contain three addr/size entries");
414 hw_unit_address_to_attach_address (hw_parent (me
),
416 &attach_space
, &attach_address
, me
);
417 hw_unit_size_to_attach_size (hw_parent (me
), ®
.size
, &attach_size
, me
);
419 if (attach_size
!= BFIN_MMR_UART_SIZE
)
420 hw_abort (me
, "\"reg\" size must be %#x", BFIN_MMR_UART_SIZE
);
422 hw_attach_address (hw_parent (me
),
423 0, attach_space
, attach_address
, attach_size
, me
);
425 uart
->base
= attach_address
;
429 bfin_uart_finish (struct hw
*me
)
431 struct bfin_uart
*uart
;
433 uart
= HW_ZALLOC (me
, struct bfin_uart
);
435 set_hw_data (me
, uart
);
436 set_hw_io_read_buffer (me
, bfin_uart_io_read_buffer
);
437 set_hw_io_write_buffer (me
, bfin_uart_io_write_buffer
);
438 set_hw_dma_read_buffer (me
, bfin_uart_dma_read_buffer
);
439 set_hw_dma_write_buffer (me
, bfin_uart_dma_write_buffer
);
440 set_hw_ports (me
, bfin_uart_ports
);
442 attach_bfin_uart_regs (me
, uart
);
444 /* Initialize the UART. */
450 const struct hw_descriptor dv_bfin_uart_descriptor
[] =
452 {"bfin_uart", bfin_uart_finish
,},