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b14fe08a6345d9623cb24fee32fc71383fb3d3eb
[deliverable/binutils-gdb.git] / sim / bfin / machs.c
1 /* Simulator for Analog Devices Blackfin processors.
2
3 Copyright (C) 2005-2011 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22
23 #include "sim-main.h"
24 #include "gdb/sim-bfin.h"
25 #include "bfd.h"
26
27 #include "sim-hw.h"
28 #include "devices.h"
29 #include "dv-bfin_cec.h"
30 #include "dv-bfin_dmac.h"
31
32 static const MACH bfin_mach;
33
34 struct bfin_memory_layout {
35 address_word addr, len;
36 unsigned mask; /* see mapmask in sim_core_attach() */
37 };
38 struct bfin_dev_layout {
39 address_word base, len;
40 unsigned int dmac;
41 const char *dev;
42 };
43 struct bfin_dmac_layout {
44 address_word base;
45 unsigned int dma_count;
46 };
47 struct bfin_port_layout {
48 /* Which device this routes to (name/port). */
49 const char *dst, *dst_port;
50 /* Which device this routes from (name/port). */
51 const char *src, *src_port;
52 };
53 struct bfin_model_data {
54 bu32 chipid;
55 int model_num;
56 const struct bfin_memory_layout *mem;
57 size_t mem_count;
58 const struct bfin_dev_layout *dev;
59 size_t dev_count;
60 const struct bfin_dmac_layout *dmac;
61 size_t dmac_count;
62 const struct bfin_port_layout *port;
63 size_t port_count;
64 };
65
66 #define LAYOUT(_addr, _len, _mask) { .addr = _addr, .len = _len, .mask = access_##_mask, }
67 #define _DEVICE(_base, _len, _dev, _dmac) { .base = _base, .len = _len, .dev = _dev, .dmac = _dmac, }
68 #define DEVICE(_base, _len, _dev) _DEVICE(_base, _len, _dev, 0)
69 #define PORT(_dst, _dst_port, _src, _src_port) \
70 { \
71 .dst = _dst, \
72 .dst_port = _dst_port, \
73 .src = _src, \
74 .src_port = _src_port, \
75 }
76 #define SIC(_s, _ip, _d, _op) PORT("bfin_sic", "int"#_ip"@"#_s, _d, _op)
77
78 /* [1] Common sim code can't model exec-only memory.
79 http://sourceware.org/ml/gdb/2010-02/msg00047.html */
80
81 #define bf000_chipid 0
82 static const struct bfin_memory_layout bf000_mem[] = {};
83 static const struct bfin_dev_layout bf000_dev[] = {};
84 static const struct bfin_dmac_layout bf000_dmac[] = {};
85 static const struct bfin_port_layout bf000_port[] = {};
86
87 #define bf50x_chipid 0x2800
88 #define bf504_chipid bf50x_chipid
89 #define bf506_chipid bf50x_chipid
90 static const struct bfin_memory_layout bf50x_mem[] =
91 {
92 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
93 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
94 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
95 LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */
96 LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */
97 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
98 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
99 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
100 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst Cache [1] */
101 };
102 #define bf504_mem bf50x_mem
103 #define bf506_mem bf50x_mem
104 static const struct bfin_dev_layout bf50x_dev[] =
105 {
106 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
107 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
108 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
109 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
110 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
111 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
112 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
113 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
114 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
115 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
116 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
117 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
118 DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
119 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
120 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
121 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
122 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
123 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
124 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
125 };
126 #define bf504_dev bf50x_dev
127 #define bf506_dev bf50x_dev
128 static const struct bfin_dmac_layout bf50x_dmac[] =
129 {
130 { BFIN_MMR_DMAC0_BASE, 12, },
131 };
132 #define bf504_dmac bf50x_dmac
133 #define bf506_dmac bf50x_dmac
134 static const struct bfin_port_layout bf50x_port[] =
135 {
136 SIC (0, 0, "bfin_pll", "pll"),
137 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
138 SIC (0, 2, "bfin_ppi@0", "stat"),
139 SIC (0, 3, "bfin_sport@0", "stat"),
140 SIC (0, 4, "bfin_sport@1", "stat"),
141 SIC (0, 5, "bfin_uart2@0", "stat"),
142 SIC (0, 6, "bfin_uart2@1", "stat"),
143 SIC (0, 7, "bfin_spi@0", "stat"),
144 SIC (0, 8, "bfin_spi@1", "stat"),
145 SIC (0, 9, "bfin_can@0", "stat"),
146 SIC (0, 10, "bfin_rsi@0", "int0"),
147 /*SIC (0, 11, reserved),*/
148 SIC (0, 12, "bfin_counter@0", "stat"),
149 SIC (0, 13, "bfin_counter@1", "stat"),
150 SIC (0, 14, "bfin_dma@0", "di"),
151 SIC (0, 15, "bfin_dma@1", "di"),
152 SIC (0, 16, "bfin_dma@2", "di"),
153 SIC (0, 17, "bfin_dma@3", "di"),
154 SIC (0, 18, "bfin_dma@4", "di"),
155 SIC (0, 19, "bfin_dma@5", "di"),
156 SIC (0, 20, "bfin_dma@6", "di"),
157 SIC (0, 21, "bfin_dma@7", "di"),
158 SIC (0, 22, "bfin_dma@8", "di"),
159 SIC (0, 23, "bfin_dma@9", "di"),
160 SIC (0, 24, "bfin_dma@10", "di"),
161 SIC (0, 25, "bfin_dma@11", "di"),
162 SIC (0, 26, "bfin_can@0", "rx"),
163 SIC (0, 27, "bfin_can@0", "tx"),
164 SIC (0, 28, "bfin_twi@0", "stat"),
165 SIC (0, 29, "bfin_gpio@5", "mask_a"),
166 SIC (0, 30, "bfin_gpio@5", "mask_b"),
167 /*SIC (0, 31, reserved),*/
168 SIC (1, 0, "bfin_gptimer@0", "stat"),
169 SIC (1, 1, "bfin_gptimer@1", "stat"),
170 SIC (1, 2, "bfin_gptimer@2", "stat"),
171 SIC (1, 3, "bfin_gptimer@3", "stat"),
172 SIC (1, 4, "bfin_gptimer@4", "stat"),
173 SIC (1, 5, "bfin_gptimer@5", "stat"),
174 SIC (1, 6, "bfin_gptimer@6", "stat"),
175 SIC (1, 7, "bfin_gptimer@7", "stat"),
176 SIC (1, 8, "bfin_gpio@6", "mask_a"),
177 SIC (1, 9, "bfin_gpio@6", "mask_b"),
178 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
179 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
180 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
181 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
182 SIC (1, 12, "bfin_wdog@0", "gpi"),
183 SIC (1, 13, "bfin_gpio@7", "mask_a"),
184 SIC (1, 14, "bfin_gpio@7", "mask_b"),
185 SIC (1, 15, "bfin_acm@0", "stat"),
186 SIC (1, 16, "bfin_acm@1", "int"),
187 /*SIC (1, 17, reserved),*/
188 /*SIC (1, 18, reserved),*/
189 SIC (1, 19, "bfin_pwm@0", "trip"),
190 SIC (1, 20, "bfin_pwm@0", "sync"),
191 SIC (1, 21, "bfin_pwm@1", "trip"),
192 SIC (1, 22, "bfin_pwm@1", "sync"),
193 SIC (1, 23, "bfin_rsi@0", "int1"),
194 };
195 #define bf504_port bf50x_port
196 #define bf506_port bf50x_port
197
198 #define bf51x_chipid 0x27e8
199 #define bf512_chipid bf51x_chipid
200 #define bf514_chipid bf51x_chipid
201 #define bf516_chipid bf51x_chipid
202 #define bf518_chipid bf51x_chipid
203 static const struct bfin_memory_layout bf51x_mem[] =
204 {
205 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
206 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
207 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
208 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
209 LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */
210 LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */
211 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
212 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
213 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
214 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
215 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
216 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
217 };
218 #define bf512_mem bf51x_mem
219 #define bf514_mem bf51x_mem
220 #define bf516_mem bf51x_mem
221 #define bf518_mem bf51x_mem
222 static const struct bfin_dev_layout bf512_dev[] =
223 {
224 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
225 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
226 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
227 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
228 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
229 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
230 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
231 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
232 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
233 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
234 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
235 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
236 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
237 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
238 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
239 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
240 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
241 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
242 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
243 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
244 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
245 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
246 };
247 #define bf514_dev bf512_dev
248 static const struct bfin_dev_layout bf516_dev[] =
249 {
250 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
251 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
252 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
253 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
254 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
255 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
256 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
257 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
258 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
259 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
260 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
261 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
262 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
263 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
264 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
265 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
266 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
267 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
268 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
269 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
270 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
271 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
272 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
273 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
274 };
275 #define bf518_dev bf516_dev
276 #define bf512_dmac bf50x_dmac
277 #define bf514_dmac bf50x_dmac
278 #define bf516_dmac bf50x_dmac
279 #define bf518_dmac bf50x_dmac
280 static const struct bfin_port_layout bf51x_port[] =
281 {
282 SIC (0, 0, "bfin_pll", "pll"),
283 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
284 SIC (0, 2, "bfin_dmar@0", "block"),
285 SIC (0, 3, "bfin_dmar@1", "block"),
286 SIC (0, 4, "bfin_dmar@0", "overflow"),
287 SIC (0, 5, "bfin_dmar@1", "overflow"),
288 SIC (0, 6, "bfin_ppi@0", "stat"),
289 SIC (0, 7, "bfin_emac", "stat"),
290 SIC (0, 8, "bfin_sport@0", "stat"),
291 SIC (0, 9, "bfin_sport@1", "stat"),
292 SIC (0, 10, "bfin_ptp", "stat"),
293 /*SIC (0, 11, reserved),*/
294 SIC (0, 12, "bfin_uart@0", "stat"),
295 SIC (0, 13, "bfin_uart@1", "stat"),
296 SIC (0, 14, "bfin_rtc", "rtc"),
297 SIC (0, 15, "bfin_dma@0", "di"),
298 SIC (0, 16, "bfin_dma@3", "di"),
299 SIC (0, 17, "bfin_dma@4", "di"),
300 SIC (0, 18, "bfin_dma@5", "di"),
301 SIC (0, 19, "bfin_dma@6", "di"),
302 SIC (0, 20, "bfin_twi@0", "stat"),
303 SIC (0, 21, "bfin_dma@7", "di"),
304 SIC (0, 22, "bfin_dma@8", "di"),
305 SIC (0, 23, "bfin_dma@9", "di"),
306 SIC (0, 24, "bfin_dma@10", "di"),
307 SIC (0, 25, "bfin_dma@11", "di"),
308 SIC (0, 26, "bfin_otp", "stat"),
309 SIC (0, 27, "bfin_counter@0", "stat"),
310 SIC (0, 28, "bfin_dma@1", "di"),
311 SIC (0, 29, "bfin_gpio@7", "mask_a"),
312 SIC (0, 30, "bfin_dma@2", "di"),
313 SIC (0, 31, "bfin_gpio@7", "mask_b"),
314 SIC (1, 0, "bfin_gptimer@0", "stat"),
315 SIC (1, 1, "bfin_gptimer@1", "stat"),
316 SIC (1, 2, "bfin_gptimer@2", "stat"),
317 SIC (1, 3, "bfin_gptimer@3", "stat"),
318 SIC (1, 4, "bfin_gptimer@4", "stat"),
319 SIC (1, 5, "bfin_gptimer@5", "stat"),
320 SIC (1, 6, "bfin_gptimer@6", "stat"),
321 SIC (1, 7, "bfin_gptimer@7", "stat"),
322 SIC (1, 8, "bfin_gpio@6", "mask_a"),
323 SIC (1, 9, "bfin_gpio@6", "mask_b"),
324 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
325 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
326 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
327 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
328 SIC (1, 12, "bfin_wdog@0", "gpi"),
329 SIC (1, 13, "bfin_gpio@5", "mask_a"),
330 SIC (1, 14, "bfin_gpio@5", "mask_b"),
331 SIC (1, 15, "bfin_spi@0", "stat"),
332 SIC (1, 16, "bfin_spi@1", "stat"),
333 /*SIC (1, 17, reserved),*/
334 /*SIC (1, 18, reserved),*/
335 SIC (1, 19, "bfin_rsi@0", "int0"),
336 SIC (1, 20, "bfin_rsi@0", "int1"),
337 SIC (1, 21, "bfin_pwm@0", "trip"),
338 SIC (1, 22, "bfin_pwm@0", "sync"),
339 SIC (1, 23, "bfin_ptp", "stat"),
340 };
341 #define bf512_port bf51x_port
342 #define bf514_port bf51x_port
343 #define bf516_port bf51x_port
344 #define bf518_port bf51x_port
345
346 #define bf522_chipid 0x27e4
347 #define bf523_chipid 0x27e0
348 #define bf524_chipid bf522_chipid
349 #define bf525_chipid bf523_chipid
350 #define bf526_chipid bf522_chipid
351 #define bf527_chipid bf523_chipid
352 static const struct bfin_memory_layout bf52x_mem[] =
353 {
354 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
355 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
356 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
357 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
358 LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */
359 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
360 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
361 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
362 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
363 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
364 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
365 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
366 };
367 #define bf522_mem bf52x_mem
368 #define bf523_mem bf52x_mem
369 #define bf524_mem bf52x_mem
370 #define bf525_mem bf52x_mem
371 #define bf526_mem bf52x_mem
372 #define bf527_mem bf52x_mem
373 static const struct bfin_dev_layout bf522_dev[] =
374 {
375 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
376 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
377 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
378 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
379 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
380 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
381 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
382 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
383 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
384 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
385 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
386 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
387 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
388 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
389 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
390 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
391 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
392 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
393 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
394 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
395 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
396 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
397 };
398 #define bf523_dev bf522_dev
399 #define bf524_dev bf522_dev
400 #define bf525_dev bf522_dev
401 static const struct bfin_dev_layout bf526_dev[] =
402 {
403 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
404 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
405 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
406 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
407 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
408 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
409 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
410 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
411 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
412 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
413 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
414 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
415 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
416 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
417 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
418 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
419 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
420 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
421 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
422 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
423 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
424 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
425 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
426 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
427 };
428 #define bf527_dev bf526_dev
429 #define bf522_dmac bf50x_dmac
430 #define bf523_dmac bf50x_dmac
431 #define bf524_dmac bf50x_dmac
432 #define bf525_dmac bf50x_dmac
433 #define bf526_dmac bf50x_dmac
434 #define bf527_dmac bf50x_dmac
435 static const struct bfin_port_layout bf52x_port[] =
436 {
437 SIC (0, 0, "bfin_pll", "pll"),
438 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
439 SIC (0, 2, "bfin_dmar@0", "block"),
440 SIC (0, 3, "bfin_dmar@1", "block"),
441 SIC (0, 4, "bfin_dmar@0", "overflow"),
442 SIC (0, 5, "bfin_dmar@1", "overflow"),
443 SIC (0, 6, "bfin_ppi@0", "stat"),
444 SIC (0, 7, "bfin_emac", "stat"),
445 SIC (0, 8, "bfin_sport@0", "stat"),
446 SIC (0, 9, "bfin_sport@1", "stat"),
447 /*SIC (0, 10, reserved),*/
448 /*SIC (0, 11, reserved),*/
449 SIC (0, 12, "bfin_uart@0", "stat"),
450 SIC (0, 13, "bfin_uart@1", "stat"),
451 SIC (0, 14, "bfin_rtc", "rtc"),
452 SIC (0, 15, "bfin_dma@0", "di"),
453 SIC (0, 16, "bfin_dma@3", "di"),
454 SIC (0, 17, "bfin_dma@4", "di"),
455 SIC (0, 18, "bfin_dma@5", "di"),
456 SIC (0, 19, "bfin_dma@6", "di"),
457 SIC (0, 20, "bfin_twi@0", "stat"),
458 SIC (0, 21, "bfin_dma@7", "di"),
459 SIC (0, 22, "bfin_dma@8", "di"),
460 SIC (0, 23, "bfin_dma@9", "di"),
461 SIC (0, 24, "bfin_dma@10", "di"),
462 SIC (0, 25, "bfin_dma@11", "di"),
463 SIC (0, 26, "bfin_otp", "stat"),
464 SIC (0, 27, "bfin_counter@0", "stat"),
465 SIC (0, 28, "bfin_dma@1", "di"),
466 SIC (0, 29, "bfin_gpio@7", "mask_a"),
467 SIC (0, 30, "bfin_dma@2", "di"),
468 SIC (0, 31, "bfin_gpio@7", "mask_b"),
469 SIC (1, 0, "bfin_gptimer@0", "stat"),
470 SIC (1, 1, "bfin_gptimer@1", "stat"),
471 SIC (1, 2, "bfin_gptimer@2", "stat"),
472 SIC (1, 3, "bfin_gptimer@3", "stat"),
473 SIC (1, 4, "bfin_gptimer@4", "stat"),
474 SIC (1, 5, "bfin_gptimer@5", "stat"),
475 SIC (1, 6, "bfin_gptimer@6", "stat"),
476 SIC (1, 7, "bfin_gptimer@7", "stat"),
477 SIC (1, 8, "bfin_gpio@6", "mask_a"),
478 SIC (1, 9, "bfin_gpio@6", "mask_b"),
479 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
480 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
481 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
482 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
483 SIC (1, 12, "bfin_wdog@0", "gpi"),
484 SIC (1, 13, "bfin_gpio@5", "mask_a"),
485 SIC (1, 14, "bfin_gpio@5", "mask_b"),
486 SIC (1, 15, "bfin_spi@0", "stat"),
487 SIC (1, 16, "bfin_nfc", "stat"),
488 SIC (1, 17, "bfin_hostdp", "stat"),
489 SIC (1, 18, "bfin_hostdp", "done"),
490 SIC (1, 20, "bfin_usb", "int0"),
491 SIC (1, 21, "bfin_usb", "int1"),
492 SIC (1, 22, "bfin_usb", "int2"),
493 };
494 #define bf522_port bf51x_port
495 #define bf523_port bf51x_port
496 #define bf524_port bf51x_port
497 #define bf525_port bf51x_port
498 #define bf526_port bf51x_port
499 #define bf527_port bf51x_port
500
501 #define bf531_chipid 0x27a5
502 #define bf532_chipid bf531_chipid
503 #define bf533_chipid bf531_chipid
504 static const struct bfin_memory_layout bf531_mem[] =
505 {
506 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
507 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
508 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
509 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
510 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
511 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
512 };
513 static const struct bfin_memory_layout bf532_mem[] =
514 {
515 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
516 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
517 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
518 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
519 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
520 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
521 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
522 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
523 };
524 static const struct bfin_memory_layout bf533_mem[] =
525 {
526 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
527 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
528 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
529 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
530 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
531 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
532 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
533 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
534 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
535 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
536 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
537 };
538 static const struct bfin_dev_layout bf533_dev[] =
539 {
540 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
541 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
542 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
543 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
544 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
545 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
546 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
547 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
548 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
549 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
550 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
551 };
552 #define bf531_dev bf533_dev
553 #define bf532_dev bf533_dev
554 static const struct bfin_dmac_layout bf533_dmac[] =
555 {
556 { BFIN_MMR_DMAC0_BASE, 8, },
557 };
558 #define bf531_dmac bf533_dmac
559 #define bf532_dmac bf533_dmac
560 static const struct bfin_port_layout bf533_port[] =
561 {
562 SIC (0, 0, "bfin_pll", "pll"),
563 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
564 SIC (0, 2, "bfin_ppi@0", "stat"),
565 SIC (0, 3, "bfin_sport@0", "stat"),
566 SIC (0, 4, "bfin_sport@1", "stat"),
567 SIC (0, 5, "bfin_spi@0", "stat"),
568 SIC (0, 6, "bfin_uart@0", "stat"),
569 SIC (0, 7, "bfin_rtc", "rtc"),
570 SIC (0, 8, "bfin_dma@0", "di"),
571 SIC (0, 9, "bfin_dma@1", "di"),
572 SIC (0, 10, "bfin_dma@2", "di"),
573 SIC (0, 11, "bfin_dma@3", "di"),
574 SIC (0, 12, "bfin_dma@4", "di"),
575 SIC (0, 13, "bfin_dma@5", "di"),
576 SIC (0, 14, "bfin_dma@6", "di"),
577 SIC (0, 15, "bfin_dma@7", "di"),
578 SIC (0, 16, "bfin_gptimer@0", "stat"),
579 SIC (0, 17, "bfin_gptimer@1", "stat"),
580 SIC (0, 18, "bfin_gptimer@2", "stat"),
581 SIC (0, 19, "bfin_gpio@5", "mask_a"),
582 SIC (0, 20, "bfin_gpio@5", "mask_b"),
583 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
584 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
585 SIC (0, 22, "bfin_dma@258", "di"), /* mdma */
586 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
587 SIC (0, 23, "bfin_wdog@0", "gpi"),
588 };
589 #define bf531_port bf533_port
590 #define bf532_port bf533_port
591
592 #define bf534_chipid 0x27c6
593 #define bf536_chipid 0x27c8
594 #define bf537_chipid bf536_chipid
595 static const struct bfin_memory_layout bf534_mem[] =
596 {
597 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
598 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
599 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
600 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
601 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
602 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
603 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
604 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
605 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
606 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
607 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
608 };
609 static const struct bfin_memory_layout bf536_mem[] =
610 {
611 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
612 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
613 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
614 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
615 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
616 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
617 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
618 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
619 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
620 };
621 static const struct bfin_memory_layout bf537_mem[] =
622 {
623 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
624 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
625 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
626 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
627 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
628 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
629 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
630 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
631 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
632 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
633 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
634 };
635 static const struct bfin_dev_layout bf534_dev[] =
636 {
637 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
638 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
639 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
640 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
641 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
642 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
643 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
644 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
645 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
646 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
647 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
648 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
649 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
650 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
651 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
652 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
653 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
654 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
655 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
656 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
657 };
658 static const struct bfin_dev_layout bf537_dev[] =
659 {
660 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
661 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
662 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
663 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
664 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
665 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
666 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
667 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
668 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
669 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
670 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
671 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
672 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
673 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
674 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
675 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
676 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
677 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
678 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
679 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
680 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
681 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
682 };
683 #define bf536_dev bf537_dev
684 #define bf534_dmac bf50x_dmac
685 #define bf536_dmac bf50x_dmac
686 #define bf537_dmac bf50x_dmac
687 static const struct bfin_port_layout bf537_port[] =
688 {
689 SIC (0, 0, "bfin_pll", "pll"),
690 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
691 SIC (0, 1, "bfin_dmar@0", "block"),
692 SIC (0, 1, "bfin_dmar@1", "block"),
693 SIC (0, 1, "bfin_dmar@0", "overflow"),
694 SIC (0, 1, "bfin_dmar@1", "overflow"),
695 SIC (0, 2, "bfin_can@0", "stat"),
696 SIC (0, 2, "bfin_emac", "stat"),
697 SIC (0, 2, "bfin_sport@0", "stat"),
698 SIC (0, 2, "bfin_sport@1", "stat"),
699 SIC (0, 2, "bfin_ppi@0", "stat"),
700 SIC (0, 2, "bfin_spi@0", "stat"),
701 SIC (0, 2, "bfin_uart@0", "stat"),
702 SIC (0, 2, "bfin_uart@1", "stat"),
703 SIC (0, 3, "bfin_rtc", "rtc"),
704 SIC (0, 4, "bfin_dma@0", "di"),
705 SIC (0, 5, "bfin_dma@3", "di"),
706 SIC (0, 6, "bfin_dma@4", "di"),
707 SIC (0, 7, "bfin_dma@5", "di"),
708 SIC (0, 8, "bfin_dma@6", "di"),
709 SIC (0, 9, "bfin_twi@0", "stat"),
710 SIC (0, 10, "bfin_dma@7", "di"),
711 SIC (0, 11, "bfin_dma@8", "di"),
712 SIC (0, 12, "bfin_dma@9", "di"),
713 SIC (0, 13, "bfin_dma@10", "di"),
714 SIC (0, 14, "bfin_dma@11", "di"),
715 SIC (0, 15, "bfin_can@0", "rx"),
716 SIC (0, 16, "bfin_can@0", "tx"),
717 SIC (0, 17, "bfin_dma@1", "di"),
718 SIC (0, 17, "bfin_gpio@7", "mask_a"),
719 SIC (0, 18, "bfin_dma@2", "di"),
720 SIC (0, 18, "bfin_gpio@7", "mask_b"),
721 SIC (0, 19, "bfin_gptimer@0", "stat"),
722 SIC (0, 20, "bfin_gptimer@1", "stat"),
723 SIC (0, 21, "bfin_gptimer@2", "stat"),
724 SIC (0, 22, "bfin_gptimer@3", "stat"),
725 SIC (0, 23, "bfin_gptimer@4", "stat"),
726 SIC (0, 24, "bfin_gptimer@5", "stat"),
727 SIC (0, 25, "bfin_gptimer@6", "stat"),
728 SIC (0, 26, "bfin_gptimer@7", "stat"),
729 SIC (0, 27, "bfin_gpio@5", "mask_a"),
730 SIC (0, 27, "bfin_gpio@6", "mask_a"),
731 SIC (0, 28, "bfin_gpio@6", "mask_b"),
732 SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */
733 SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */
734 SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */
735 SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */
736 SIC (0, 31, "bfin_wdog@0", "gpi"),
737 SIC (0, 31, "bfin_gpio@5", "mask_b"),
738 };
739 #define bf534_port bf537_port
740 #define bf536_port bf537_port
741
742 #define bf538_chipid 0x27c4
743 #define bf539_chipid bf538_chipid
744 static const struct bfin_memory_layout bf538_mem[] =
745 {
746 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
747 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
748 LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */
749 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
750 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
751 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
752 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
753 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
754 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
755 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
756 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
757 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
758 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
759 };
760 #define bf539_mem bf538_mem
761 static const struct bfin_dev_layout bf538_dev[] =
762 {
763 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
764 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
765 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
766 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
767 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
768 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
769 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
770 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
771 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
772 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
773 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
774 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
775 _DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1),
776 _DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1),
777 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
778 _DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1", 1),
779 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
780 };
781 #define bf539_dev bf538_dev
782 static const struct bfin_dmac_layout bf538_dmac[] =
783 {
784 { BFIN_MMR_DMAC0_BASE, 8, },
785 { BFIN_MMR_DMAC1_BASE, 12, },
786 };
787 #define bf539_dmac bf538_dmac
788 static const struct bfin_port_layout bf538_port[] =
789 {
790 SIC (0, 0, "bfin_pll", "pll"),
791 SIC (0, 1, "bfin_dmac@0", "stat"),
792 SIC (0, 2, "bfin_ppi@0", "stat"),
793 SIC (0, 3, "bfin_sport@0", "stat"),
794 SIC (0, 4, "bfin_sport@1", "stat"),
795 SIC (0, 5, "bfin_spi@0", "stat"),
796 SIC (0, 6, "bfin_uart@0", "stat"),
797 SIC (0, 7, "bfin_rtc", "rtc"),
798 SIC (0, 8, "bfin_dma@0", "di"),
799 SIC (0, 9, "bfin_dma@1", "di"),
800 SIC (0, 10, "bfin_dma@2", "di"),
801 SIC (0, 11, "bfin_dma@3", "di"),
802 SIC (0, 12, "bfin_dma@4", "di"),
803 SIC (0, 13, "bfin_dma@5", "di"),
804 SIC (0, 14, "bfin_dma@6", "di"),
805 SIC (0, 15, "bfin_dma@7", "di"),
806 SIC (0, 16, "bfin_gptimer@0", "stat"),
807 SIC (0, 17, "bfin_gptimer@1", "stat"),
808 SIC (0, 18, "bfin_gptimer@2", "stat"),
809 SIC (0, 19, "bfin_gpio@5", "mask_a"),
810 SIC (0, 20, "bfin_gpio@5", "mask_b"),
811 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
812 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
813 SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */
814 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
815 SIC (0, 23, "bfin_wdog@0", "gpi"),
816 SIC (0, 24, "bfin_dmac@1", "stat"),
817 SIC (0, 25, "bfin_sport@2", "stat"),
818 SIC (0, 26, "bfin_sport@3", "stat"),
819 /*SIC (0, 27, reserved),*/
820 SIC (0, 28, "bfin_spi@1", "stat"),
821 SIC (0, 29, "bfin_spi@2", "stat"),
822 SIC (0, 30, "bfin_uart@1", "stat"),
823 SIC (0, 31, "bfin_uart@2", "stat"),
824 SIC (1, 0, "bfin_can@0", "stat"),
825 SIC (1, 1, "bfin_dma@8", "di"),
826 SIC (1, 2, "bfin_dma@9", "di"),
827 SIC (1, 3, "bfin_dma@10", "di"),
828 SIC (1, 4, "bfin_dma@11", "di"),
829 SIC (1, 5, "bfin_dma@12", "di"),
830 SIC (1, 6, "bfin_dma@13", "di"),
831 SIC (1, 7, "bfin_dma@14", "di"),
832 SIC (1, 8, "bfin_dma@15", "di"),
833 SIC (1, 9, "bfin_dma@16", "di"),
834 SIC (1, 10, "bfin_dma@17", "di"),
835 SIC (1, 11, "bfin_dma@18", "di"),
836 SIC (1, 12, "bfin_dma@19", "di"),
837 SIC (1, 13, "bfin_twi@0", "stat"),
838 SIC (1, 14, "bfin_twi@1", "stat"),
839 SIC (1, 15, "bfin_can@0", "rx"),
840 SIC (1, 16, "bfin_can@0", "tx"),
841 SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */
842 SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */
843 SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */
844 SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */
845 };
846 #define bf539_port bf538_port
847
848 #define bf54x_chipid 0x27de
849 #define bf542_chipid bf54x_chipid
850 #define bf544_chipid bf54x_chipid
851 #define bf547_chipid bf54x_chipid
852 #define bf548_chipid bf54x_chipid
853 #define bf549_chipid bf54x_chipid
854 static const struct bfin_memory_layout bf54x_mem[] =
855 {
856 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */
857 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
858 LAYOUT (0xFFC01400, 0x200, read_write), /* PORT/GPIO stub */
859 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
860 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
861 LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */
862 LAYOUT (0xFFC03900, 0x100, read_write), /* RSI stub */
863 LAYOUT (0xFFC03C00, 0x500, read_write), /* MUSB stub */
864 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
865 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
866 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
867 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
868 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
869 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
870 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
871 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
872 };
873 #define bf542_mem bf54x_mem
874 #define bf544_mem bf54x_mem
875 #define bf547_mem bf54x_mem
876 #define bf548_mem bf54x_mem
877 #define bf549_mem bf54x_mem
878 static const struct bfin_dev_layout bf542_dev[] =
879 {
880 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
881 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
882 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
883 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
884 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
885 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
886 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
887 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
888 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
889 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
890 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
891 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
892 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
893 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
894 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
895 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
896 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
897 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
898 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
899 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
900 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
901 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
902 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
903 };
904 static const struct bfin_dev_layout bf544_dev[] =
905 {
906 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
907 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
908 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
909 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
910 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
911 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
912 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
913 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
914 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
915 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
916 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
917 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
918 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
919 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
920 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
921 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
922 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
923 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
924 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
925 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
926 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
927 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
928 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
929 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
930 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
931 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
932 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
933 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
934 };
935 static const struct bfin_dev_layout bf547_dev[] =
936 {
937 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
938 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
939 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
940 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
941 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
942 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
943 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
944 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
945 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
946 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
947 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
948 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
949 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
950 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
951 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
952 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
953 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
954 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
955 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
956 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
957 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
958 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
959 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
960 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
961 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
962 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
963 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
964 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
965 };
966 #define bf548_dev bf547_dev
967 #define bf549_dev bf547_dev
968 static const struct bfin_dmac_layout bf54x_dmac[] =
969 {
970 { BFIN_MMR_DMAC0_BASE, 12, },
971 { BFIN_MMR_DMAC1_BASE, 12, },
972 };
973 #define bf542_dmac bf54x_dmac
974 #define bf544_dmac bf54x_dmac
975 #define bf547_dmac bf54x_dmac
976 #define bf548_dmac bf54x_dmac
977 #define bf549_dmac bf54x_dmac
978 static const struct bfin_port_layout bf54x_port[] =
979 {
980 SIC (0, 0, "bfin_pll", "pll"),
981 SIC (0, 1, "bfin_dmac@0", "stat"),
982 SIC (0, 2, "bfin_eppi@0", "stat"),
983 SIC (0, 3, "bfin_sport@0", "stat"),
984 SIC (0, 4, "bfin_sport@1", "stat"),
985 SIC (0, 5, "bfin_spi@0", "stat"),
986 SIC (0, 6, "bfin_uart2@0", "stat"),
987 SIC (0, 7, "bfin_rtc", "rtc"),
988 SIC (0, 8, "bfin_dma@12", "di"),
989 SIC (0, 9, "bfin_dma@0", "di"),
990 SIC (0, 10, "bfin_dma@1", "di"),
991 SIC (0, 11, "bfin_dma@2", "di"),
992 SIC (0, 12, "bfin_dma@3", "di"),
993 SIC (0, 13, "bfin_dma@4", "di"),
994 SIC (0, 14, "bfin_dma@6", "di"),
995 SIC (0, 15, "bfin_dma@7", "di"),
996 SIC (0, 16, "bfin_gptimer@8", "stat"),
997 SIC (0, 17, "bfin_gptimer@9", "stat"),
998 SIC (0, 18, "bfin_gptimer@10", "stat"),
999 SIC (0, 19, "bfin_pint@0", "stat"),
1000 SIC (0, 20, "bfin_pint@1", "stat"),
1001 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
1002 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
1003 SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */
1004 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
1005 SIC (0, 23, "bfin_wdog@0", "gpi"),
1006 SIC (0, 24, "bfin_dmac@1", "stat"),
1007 SIC (0, 25, "bfin_sport@2", "stat"),
1008 SIC (0, 26, "bfin_sport@3", "stat"),
1009 SIC (0, 27, "bfin_mxvr", "data"),
1010 SIC (0, 28, "bfin_spi@1", "stat"),
1011 SIC (0, 29, "bfin_spi@2", "stat"),
1012 SIC (0, 30, "bfin_uart2@1", "stat"),
1013 SIC (0, 31, "bfin_uart2@2", "stat"),
1014 SIC (1, 0, "bfin_can@0", "stat"),
1015 SIC (1, 1, "bfin_dma@18", "di"),
1016 SIC (1, 2, "bfin_dma@19", "di"),
1017 SIC (1, 3, "bfin_dma@20", "di"),
1018 SIC (1, 4, "bfin_dma@21", "di"),
1019 SIC (1, 5, "bfin_dma@13", "di"),
1020 SIC (1, 6, "bfin_dma@14", "di"),
1021 SIC (1, 7, "bfin_dma@5", "di"),
1022 SIC (1, 8, "bfin_dma@23", "di"),
1023 SIC (1, 9, "bfin_dma@8", "di"),
1024 SIC (1, 10, "bfin_dma@9", "di"),
1025 SIC (1, 11, "bfin_dma@10", "di"),
1026 SIC (1, 12, "bfin_dma@11", "di"),
1027 SIC (1, 13, "bfin_twi@0", "stat"),
1028 SIC (1, 14, "bfin_twi@1", "stat"),
1029 SIC (1, 15, "bfin_can@0", "rx"),
1030 SIC (1, 16, "bfin_can@0", "tx"),
1031 SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */
1032 SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */
1033 SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */
1034 SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */
1035 SIC (1, 19, "bfin_mxvr", "stat"),
1036 SIC (1, 20, "bfin_mxvr", "message"),
1037 SIC (1, 21, "bfin_mxvr", "packet"),
1038 SIC (1, 22, "bfin_eppi@1", "stat"),
1039 SIC (1, 23, "bfin_eppi@2", "stat"),
1040 SIC (1, 24, "bfin_uart2@3", "stat"),
1041 SIC (1, 25, "bfin_hostdp", "stat"),
1042 /*SIC (1, 26, reserved),*/
1043 SIC (1, 27, "bfin_pixc", "stat"),
1044 SIC (1, 28, "bfin_nfc", "stat"),
1045 SIC (1, 29, "bfin_atapi", "stat"),
1046 SIC (1, 30, "bfin_can@1", "stat"),
1047 SIC (1, 31, "bfin_dmar@0", "block"),
1048 SIC (1, 31, "bfin_dmar@1", "block"),
1049 SIC (1, 31, "bfin_dmar@0", "overflow"),
1050 SIC (1, 31, "bfin_dmar@1", "overflow"),
1051 SIC (2, 0, "bfin_dma@15", "di"),
1052 SIC (2, 1, "bfin_dma@16", "di"),
1053 SIC (2, 2, "bfin_dma@17", "di"),
1054 SIC (2, 3, "bfin_dma@22", "di"),
1055 SIC (2, 4, "bfin_counter@0", "stat"),
1056 SIC (2, 5, "bfin_kpad@0", "stat"),
1057 SIC (2, 6, "bfin_can@1", "rx"),
1058 SIC (2, 7, "bfin_can@1", "tx"),
1059 SIC (2, 8, "bfin_sdh", "mask0"),
1060 SIC (2, 9, "bfin_sdh", "mask1"),
1061 /*SIC (2, 10, reserved),*/
1062 SIC (2, 11, "bfin_usb", "int0"),
1063 SIC (2, 12, "bfin_usb", "int1"),
1064 SIC (2, 13, "bfin_usb", "int2"),
1065 SIC (2, 14, "bfin_usb", "dma"),
1066 SIC (2, 15, "bfin_otp", "stat"),
1067 /*SIC (2, 16, reserved),*/
1068 /*SIC (2, 17, reserved),*/
1069 /*SIC (2, 18, reserved),*/
1070 /*SIC (2, 19, reserved),*/
1071 /*SIC (2, 20, reserved),*/
1072 /*SIC (2, 21, reserved),*/
1073 SIC (2, 22, "bfin_gptimer@0", "stat"),
1074 SIC (2, 23, "bfin_gptimer@1", "stat"),
1075 SIC (2, 24, "bfin_gptimer@2", "stat"),
1076 SIC (2, 25, "bfin_gptimer@3", "stat"),
1077 SIC (2, 26, "bfin_gptimer@4", "stat"),
1078 SIC (2, 27, "bfin_gptimer@5", "stat"),
1079 SIC (2, 28, "bfin_gptimer@6", "stat"),
1080 SIC (2, 29, "bfin_gptimer@7", "stat"),
1081 SIC (2, 30, "bfin_pint@2", "stat"),
1082 SIC (2, 31, "bfin_pint@3", "stat"),
1083 };
1084 #define bf542_port bf54x_port
1085 #define bf544_port bf54x_port
1086 #define bf547_port bf54x_port
1087 #define bf548_port bf54x_port
1088 #define bf549_port bf54x_port
1089
1090 /* This is only Core A of course ... */
1091 #define bf561_chipid 0x27bb
1092 static const struct bfin_memory_layout bf561_mem[] =
1093 {
1094 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
1095 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
1096 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
1097 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
1098 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
1099 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
1100 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
1101 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
1102 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
1103 };
1104 static const struct bfin_dev_layout bf561_dev[] =
1105 {
1106 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
1107 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
1108 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
1109 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
1110 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
1111 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
1112 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
1113 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
1114 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
1115 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
1116 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
1117 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
1118 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
1119 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
1120 _DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1),
1121 DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"),
1122 _DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1),
1123 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
1124 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
1125 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
1126 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
1127 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"),
1128 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
1129 };
1130 static const struct bfin_dmac_layout bf561_dmac[] =
1131 {
1132 { BFIN_MMR_DMAC0_BASE, 12, },
1133 { BFIN_MMR_DMAC1_BASE, 12, },
1134 /* XXX: IMDMA: { 0xFFC01800, 4, }, */
1135 };
1136 static const struct bfin_port_layout bf561_port[] =
1137 {
1138 /* SIC0 */
1139 SIC (0, 0, "bfin_pll", "pll"),
1140 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
1141 /*SIC (0, 2, "bfin_dmac@1", "stat"),*/
1142 /*SIC (0, 3, "bfin_imdmac", "stat"),*/
1143 SIC (0, 4, "bfin_ppi@0", "stat"),
1144 SIC (0, 5, "bfin_ppi@1", "stat"),
1145 SIC (0, 6, "bfin_sport@0", "stat"),
1146 SIC (0, 7, "bfin_sport@1", "stat"),
1147 SIC (0, 8, "bfin_spi@0", "stat"),
1148 SIC (0, 9, "bfin_uart@0", "stat"),
1149 /*SIC (0, 10, reserved),*/
1150 SIC (0, 11, "bfin_dma@12", "di"),
1151 SIC (0, 12, "bfin_dma@13", "di"),
1152 SIC (0, 13, "bfin_dma@14", "di"),
1153 SIC (0, 14, "bfin_dma@15", "di"),
1154 SIC (0, 15, "bfin_dma@16", "di"),
1155 SIC (0, 16, "bfin_dma@17", "di"),
1156 SIC (0, 17, "bfin_dma@18", "di"),
1157 SIC (0, 18, "bfin_dma@19", "di"),
1158 SIC (0, 19, "bfin_dma@20", "di"),
1159 SIC (0, 20, "bfin_dma@21", "di"),
1160 SIC (0, 21, "bfin_dma@22", "di"),
1161 SIC (0, 22, "bfin_dma@23", "di"),
1162 SIC (0, 23, "bfin_dma@0", "di"),
1163 SIC (0, 24, "bfin_dma@1", "di"),
1164 SIC (0, 25, "bfin_dma@2", "di"),
1165 SIC (0, 26, "bfin_dma@3", "di"),
1166 SIC (0, 27, "bfin_dma@4", "di"),
1167 SIC (0, 28, "bfin_dma@5", "di"),
1168 SIC (0, 29, "bfin_dma@6", "di"),
1169 SIC (0, 30, "bfin_dma@7", "di"),
1170 SIC (0, 31, "bfin_dma@8", "di"),
1171 SIC (1, 0, "bfin_dma@9", "di"),
1172 SIC (1, 1, "bfin_dma@10", "di"),
1173 SIC (1, 2, "bfin_dma@11", "di"),
1174 SIC (1, 3, "bfin_gptimer@0", "stat"),
1175 SIC (1, 4, "bfin_gptimer@1", "stat"),
1176 SIC (1, 5, "bfin_gptimer@2", "stat"),
1177 SIC (1, 6, "bfin_gptimer@3", "stat"),
1178 SIC (1, 7, "bfin_gptimer@4", "stat"),
1179 SIC (1, 8, "bfin_gptimer@5", "stat"),
1180 SIC (1, 9, "bfin_gptimer@6", "stat"),
1181 SIC (1, 10, "bfin_gptimer@7", "stat"),
1182 SIC (1, 11, "bfin_gptimer@8", "stat"),
1183 SIC (1, 12, "bfin_gptimer@9", "stat"),
1184 SIC (1, 13, "bfin_gptimer@10", "stat"),
1185 SIC (1, 14, "bfin_gptimer@11", "stat"),
1186 SIC (1, 15, "bfin_gpio@5", "mask_a"),
1187 SIC (1, 16, "bfin_gpio@5", "mask_b"),
1188 SIC (1, 17, "bfin_gpio@6", "mask_a"),
1189 SIC (1, 18, "bfin_gpio@6", "mask_b"),
1190 SIC (1, 19, "bfin_gpio@7", "mask_a"),
1191 SIC (1, 20, "bfin_gpio@7", "mask_b"),
1192 SIC (1, 21, "bfin_dma@256", "di"), /* mdma0 */
1193 SIC (1, 21, "bfin_dma@257", "di"), /* mdma0 */
1194 SIC (1, 22, "bfin_dma@258", "di"), /* mdma1 */
1195 SIC (1, 22, "bfin_dma@259", "di"), /* mdma1 */
1196 SIC (1, 23, "bfin_dma@260", "di"), /* mdma2 */
1197 SIC (1, 23, "bfin_dma@261", "di"), /* mdma2 */
1198 SIC (1, 24, "bfin_dma@262", "di"), /* mdma3 */
1199 SIC (1, 24, "bfin_dma@263", "di"), /* mdma3 */
1200 SIC (1, 25, "bfin_imdma@0", "di"),
1201 SIC (1, 26, "bfin_imdma@1", "di"),
1202 SIC (1, 27, "bfin_wdog@0", "gpi"),
1203 SIC (1, 27, "bfin_wdog@1", "gpi"),
1204 /*SIC (1, 28, reserved),*/
1205 /*SIC (1, 29, reserved),*/
1206 SIC (1, 30, "bfin_sic", "sup_irq@0"),
1207 SIC (1, 31, "bfin_sic", "sup_irq@1"),
1208 };
1209
1210 #define bf592_chipid 0x20cb
1211 static const struct bfin_memory_layout bf592_mem[] =
1212 {
1213 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
1214 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
1215 LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */
1216 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
1217 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */
1218 };
1219 static const struct bfin_dev_layout bf592_dev[] =
1220 {
1221 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
1222 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
1223 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
1224 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
1225 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
1226 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
1227 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
1228 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
1229 DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
1230 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
1231 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
1232 };
1233 static const struct bfin_dmac_layout bf592_dmac[] =
1234 {
1235 /* XXX: there are only 9 channels, but mdma code below assumes that they
1236 start right after the dma channels ... */
1237 { BFIN_MMR_DMAC0_BASE, 12, },
1238 };
1239 static const struct bfin_port_layout bf592_port[] =
1240 {
1241 SIC (0, 0, "bfin_pll", "pll"),
1242 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
1243 SIC (0, 2, "bfin_ppi@0", "stat"),
1244 SIC (0, 3, "bfin_sport@0", "stat"),
1245 SIC (0, 4, "bfin_sport@1", "stat"),
1246 SIC (0, 5, "bfin_spi@0", "stat"),
1247 SIC (0, 6, "bfin_spi@1", "stat"),
1248 SIC (0, 7, "bfin_uart@0", "stat"),
1249 SIC (0, 8, "bfin_dma@0", "di"),
1250 SIC (0, 9, "bfin_dma@1", "di"),
1251 SIC (0, 10, "bfin_dma@2", "di"),
1252 SIC (0, 11, "bfin_dma@3", "di"),
1253 SIC (0, 12, "bfin_dma@4", "di"),
1254 SIC (0, 13, "bfin_dma@5", "di"),
1255 SIC (0, 14, "bfin_dma@6", "di"),
1256 SIC (0, 15, "bfin_dma@7", "di"),
1257 SIC (0, 16, "bfin_dma@8", "di"),
1258 SIC (0, 17, "bfin_gpio@5", "mask_a"),
1259 SIC (0, 18, "bfin_gpio@5", "mask_b"),
1260 SIC (0, 19, "bfin_gptimer@0", "stat"),
1261 SIC (0, 20, "bfin_gptimer@1", "stat"),
1262 SIC (0, 21, "bfin_gptimer@2", "stat"),
1263 SIC (0, 22, "bfin_gpio@6", "mask_a"),
1264 SIC (0, 23, "bfin_gpio@6", "mask_b"),
1265 SIC (0, 24, "bfin_twi@0", "stat"),
1266 /* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */
1267 SIC (0, 25, "bfin_dma@9", "di"),
1268 SIC (0, 26, "bfin_dma@10", "di"),
1269 SIC (0, 27, "bfin_dma@11", "di"),
1270 SIC (0, 28, "bfin_dma@12", "di"),
1271 /*SIC (0, 25, reserved),*/
1272 /*SIC (0, 26, reserved),*/
1273 /*SIC (0, 27, reserved),*/
1274 /*SIC (0, 28, reserved),*/
1275 SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */
1276 SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */
1277 SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */
1278 SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */
1279 SIC (0, 31, "bfin_wdog", "gpi"),
1280 };
1281
1282 static const struct bfin_model_data bfin_model_data[] =
1283 {
1284 #define P(n) \
1285 [MODEL_BF##n] = { \
1286 bf##n##_chipid, n, \
1287 bf##n##_mem , ARRAY_SIZE (bf##n##_mem ), \
1288 bf##n##_dev , ARRAY_SIZE (bf##n##_dev ), \
1289 bf##n##_dmac, ARRAY_SIZE (bf##n##_dmac), \
1290 bf##n##_port, ARRAY_SIZE (bf##n##_port), \
1291 },
1292 #include "proc_list.def"
1293 #undef P
1294 };
1295
1296 #define CORE_DEVICE(dev, DEV) \
1297 DEVICE (BFIN_COREMMR_##DEV##_BASE, BFIN_COREMMR_##DEV##_SIZE, "bfin_"#dev)
1298 static const struct bfin_dev_layout bfin_core_dev[] =
1299 {
1300 CORE_DEVICE (cec, CEC),
1301 CORE_DEVICE (ctimer, CTIMER),
1302 CORE_DEVICE (evt, EVT),
1303 CORE_DEVICE (jtag, JTAG),
1304 CORE_DEVICE (mmu, MMU),
1305 CORE_DEVICE (pfmon, PFMON),
1306 CORE_DEVICE (trace, TRACE),
1307 CORE_DEVICE (wp, WP),
1308 };
1309
1310 static void
1311 dv_bfin_hw_port_parse (SIM_DESC sd, const struct bfin_model_data *mdata,
1312 const char *dev)
1313 {
1314 size_t i;
1315 const char *sdev;
1316
1317 sdev = strchr (dev, '/');
1318 if (sdev)
1319 ++sdev;
1320 else
1321 sdev = dev;
1322
1323 for (i = 0; i < mdata->port_count; ++i)
1324 {
1325 const struct bfin_port_layout *port = &mdata->port[i];
1326
1327 /* There might be more than one mapping. */
1328 if (!strcmp (sdev, port->src))
1329 sim_hw_parse (sd, "/core/%s > %s %s /core/%s", dev,
1330 port->src_port, port->dst_port, port->dst);
1331 }
1332 }
1333
1334 #define dv_bfin_hw_parse(sd, dv, DV) \
1335 do { \
1336 bu32 base = BFIN_MMR_##DV##_BASE; \
1337 bu32 size = BFIN_MMR_##DV##_SIZE; \
1338 sim_hw_parse (sd, "/core/bfin_"#dv"/reg %#x %i", base, size); \
1339 sim_hw_parse (sd, "/core/bfin_"#dv"/type %i", mdata->model_num); \
1340 dv_bfin_hw_port_parse (sd, mdata, "bfin_"#dv); \
1341 } while (0)
1342
1343 static void
1344 bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu)
1345 {
1346 const MODEL *model = CPU_MODEL (cpu);
1347 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1348 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1349 int mnum = MODEL_NUM (model);
1350 unsigned i, j, dma_chan;
1351
1352 /* Map the core devices. */
1353 for (i = 0; i < ARRAY_SIZE (bfin_core_dev); ++i)
1354 {
1355 const struct bfin_dev_layout *dev = &bfin_core_dev[i];
1356 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
1357 }
1358 sim_hw_parse (sd, "/core/bfin_ctimer > ivtmr ivtmr /core/bfin_cec");
1359
1360 if (mnum == MODEL_BF000)
1361 goto done;
1362
1363 /* Map the system devices. */
1364 dv_bfin_hw_parse (sd, sic, SIC);
1365 sim_hw_parse (sd, "/core/bfin_sic/type %i", mdata->model_num);
1366 for (i = 7; i < 16; ++i)
1367 sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i);
1368
1369 dv_bfin_hw_parse (sd, pll, PLL);
1370
1371 dma_chan = 0;
1372 for (i = 0; i < mdata->dmac_count; ++i)
1373 {
1374 const struct bfin_dmac_layout *dmac = &mdata->dmac[i];
1375
1376 sim_hw_parse (sd, "/core/bfin_dmac@%u/type %i", i, mdata->model_num);
1377
1378 /* Hook up the non-mdma channels. */
1379 for (j = 0; j < dmac->dma_count; ++j)
1380 {
1381 char dev[64];
1382
1383 sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, dma_chan);
1384 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev,
1385 dmac->base + j * BFIN_MMR_DMA_SIZE, BFIN_MMR_DMA_SIZE);
1386 dv_bfin_hw_port_parse (sd, mdata, dev);
1387
1388 ++dma_chan;
1389 }
1390
1391 /* Hook up the mdma channels -- assume every DMAC has 4. */
1392 for (j = 0; j < 4; ++j)
1393 {
1394 char dev[64];
1395
1396 sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, j + BFIN_DMAC_MDMA_BASE);
1397 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev,
1398 dmac->base + (j + dmac->dma_count) * BFIN_MMR_DMA_SIZE,
1399 BFIN_MMR_DMA_SIZE);
1400 dv_bfin_hw_port_parse (sd, mdata, dev);
1401 }
1402 }
1403
1404 for (i = 0; i < mdata->dev_count; ++i)
1405 {
1406 const struct bfin_dev_layout *dev = &mdata->dev[i];
1407
1408 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
1409 sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num);
1410 if (strchr (dev->dev, '/'))
1411 continue;
1412 dv_bfin_hw_port_parse (sd, mdata, dev->dev);
1413
1414 if (!strncmp (dev->dev, "bfin_uart", 9)
1415 || !strncmp (dev->dev, "bfin_emac", 9)
1416 || !strncmp (dev->dev, "bfin_sport", 10))
1417 {
1418 const char *sint = dev->dev + 5;
1419 sim_hw_parse (sd, "/core/%s > tx %s_tx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
1420 sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
1421 }
1422 else if (!strncmp (dev->dev, "bfin_wdog", 9))
1423 {
1424 sim_hw_parse (sd, "/core/%s > reset rst /core/bfin_cec", dev->dev);
1425 sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev);
1426 }
1427 }
1428
1429 done:
1430 /* Add any additional user board content. */
1431 if (board->hw_file)
1432 sim_do_commandf (sd, "hw-file %s", board->hw_file);
1433
1434 /* Trigger all the new devices' finish func. */
1435 hw_tree_finish (dv_get_device (cpu, "/"));
1436 }
1437
1438 #include "bfroms/all.h"
1439
1440 struct bfrom {
1441 bu32 addr, len, alias_len;
1442 int sirev;
1443 const char *buf;
1444 };
1445
1446 #define BFROMA(addr, rom, sirev, alias_len) \
1447 { addr, sizeof (bfrom_bf##rom##_0_##sirev), alias_len, \
1448 sirev, bfrom_bf##rom##_0_##sirev, }
1449 #define BFROM(rom, sirev, alias_len) BFROMA (0xef000000, rom, sirev, alias_len)
1450 #define BFROM_STUB { 0, 0, 0, 0, NULL, }
1451 static const struct bfrom bf50x_roms[] =
1452 {
1453 BFROM (50x, 0, 0x1000000),
1454 BFROM_STUB,
1455 };
1456 static const struct bfrom bf51x_roms[] =
1457 {
1458 BFROM (51x, 2, 0x1000000),
1459 BFROM (51x, 1, 0x1000000),
1460 BFROM (51x, 0, 0x1000000),
1461 BFROM_STUB,
1462 };
1463 static const struct bfrom bf526_roms[] =
1464 {
1465 BFROM (526, 2, 0x1000000),
1466 BFROM (526, 1, 0x1000000),
1467 BFROM (526, 0, 0x1000000),
1468 BFROM_STUB,
1469 };
1470 static const struct bfrom bf527_roms[] =
1471 {
1472 BFROM (527, 2, 0x1000000),
1473 BFROM (527, 1, 0x1000000),
1474 BFROM (527, 0, 0x1000000),
1475 BFROM_STUB,
1476 };
1477 static const struct bfrom bf533_roms[] =
1478 {
1479 BFROM (533, 6, 0x1000000),
1480 BFROM (533, 5, 0x1000000),
1481 BFROM (533, 4, 0x1000000),
1482 BFROM (533, 3, 0x1000000),
1483 BFROM (533, 2, 0x1000000),
1484 BFROM (533, 1, 0x1000000),
1485 BFROM_STUB,
1486 };
1487 static const struct bfrom bf537_roms[] =
1488 {
1489 BFROM (537, 3, 0x100000),
1490 BFROM (537, 2, 0x100000),
1491 BFROM (537, 1, 0x100000),
1492 BFROM (537, 0, 0x100000),
1493 BFROM_STUB,
1494 };
1495 static const struct bfrom bf538_roms[] =
1496 {
1497 BFROM (538, 5, 0x1000000),
1498 BFROM (538, 4, 0x1000000),
1499 BFROM (538, 3, 0x1000000),
1500 BFROM (538, 2, 0x1000000),
1501 BFROM (538, 1, 0x1000000),
1502 BFROM (538, 0, 0x1000000),
1503 BFROM_STUB,
1504 };
1505 static const struct bfrom bf54x_roms[] =
1506 {
1507 BFROM (54x, 4, 0),
1508 BFROM (54x, 2, 0),
1509 BFROM (54x, 1, 0),
1510 BFROM (54x, 0, 0),
1511 BFROMA (0xffa14000, 54x_l1, 4, 0),
1512 BFROMA (0xffa14000, 54x_l1, 2, 0),
1513 BFROMA (0xffa14000, 54x_l1, 1, 0),
1514 BFROMA (0xffa14000, 54x_l1, 0, 0),
1515 BFROM_STUB,
1516 };
1517 static const struct bfrom bf561_roms[] =
1518 {
1519 /* XXX: No idea what the actual wrap limit is here. */
1520 BFROM (561, 5, 0),
1521 BFROM_STUB,
1522 };
1523 static const struct bfrom bf59x_roms[] =
1524 {
1525 BFROM (59x, 1, 0x1000000),
1526 BFROM (59x, 0, 0x1000000),
1527 BFROMA (0xffa10000, 59x_l1, 1, 0),
1528 BFROM_STUB,
1529 };
1530
1531 static void
1532 bfin_model_map_bfrom (SIM_DESC sd, SIM_CPU *cpu)
1533 {
1534 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1535 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1536 int mnum = mdata->model_num;
1537 const struct bfrom *bfrom;
1538 unsigned int sirev;
1539
1540 if (mnum >= 500 && mnum <= 509)
1541 bfrom = bf50x_roms;
1542 else if (mnum >= 510 && mnum <= 519)
1543 bfrom = bf51x_roms;
1544 else if (mnum >= 520 && mnum <= 529)
1545 bfrom = (mnum & 1) ? bf527_roms : bf526_roms;
1546 else if (mnum >= 531 && mnum <= 533)
1547 bfrom = bf533_roms;
1548 else if (mnum == 535)
1549 /* Stub. */;
1550 else if (mnum >= 534 && mnum <= 537)
1551 bfrom = bf537_roms;
1552 else if (mnum >= 538 && mnum <= 539)
1553 bfrom = bf538_roms;
1554 else if (mnum >= 540 && mnum <= 549)
1555 bfrom = bf54x_roms;
1556 else if (mnum == 561)
1557 bfrom = bf561_roms;
1558 else if (mnum >= 590 && mnum <= 599)
1559 bfrom = bf59x_roms;
1560 else
1561 return;
1562
1563 if (board->sirev_valid)
1564 sirev = board->sirev;
1565 else
1566 sirev = bfrom->sirev;
1567 while (bfrom->buf)
1568 {
1569 /* Map all the ranges for this model/sirev. */
1570 if (bfrom->sirev == sirev)
1571 sim_core_attach (sd, NULL, 0, access_read_exec, 0, bfrom->addr,
1572 bfrom->alias_len ? : bfrom->len, bfrom->len, NULL,
1573 (char *)bfrom->buf);
1574 ++bfrom;
1575 }
1576 }
1577
1578 void
1579 bfin_model_cpu_init (SIM_DESC sd, SIM_CPU *cpu)
1580 {
1581 const MODEL *model = CPU_MODEL (cpu);
1582 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1583 int mnum = MODEL_NUM (model);
1584 size_t idx;
1585
1586 /* These memory maps are supposed to be cpu-specific, but the common sim
1587 code does not yet allow that (2nd arg is "cpu" rather than "NULL". */
1588 sim_core_attach (sd, NULL, 0, access_read_write, 0, BFIN_L1_SRAM_SCRATCH,
1589 BFIN_L1_SRAM_SCRATCH_SIZE, 0, NULL, NULL);
1590
1591 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
1592 return;
1593
1594 if (mnum == MODEL_BF000)
1595 goto core_only;
1596
1597 /* Map in the on-chip memories (SRAMs). */
1598 mdata = &bfin_model_data[MODEL_NUM (model)];
1599 for (idx = 0; idx < mdata->mem_count; ++idx)
1600 {
1601 const struct bfin_memory_layout *mem = &mdata->mem[idx];
1602 sim_core_attach (sd, NULL, 0, mem->mask, 0, mem->addr,
1603 mem->len, 0, NULL, NULL);
1604 }
1605
1606 /* Map the on-chip ROMs. */
1607 bfin_model_map_bfrom (sd, cpu);
1608
1609 core_only:
1610 /* Finally, build up the tree for this cpu model. */
1611 bfin_model_hw_tree_init (sd, cpu);
1612 }
1613
1614 bu32
1615 bfin_model_get_chipid (SIM_DESC sd)
1616 {
1617 SIM_CPU *cpu = STATE_CPU (sd, 0);
1618 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1619 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1620 return
1621 (board->sirev << 28) |
1622 (mdata->chipid << 12) |
1623 (((0xE5 << 1) | 1) & 0xFF);
1624 }
1625
1626 bu32
1627 bfin_model_get_dspid (SIM_DESC sd)
1628 {
1629 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1630 return
1631 (0xE5 << 24) |
1632 (0x04 << 16) |
1633 (board->sirev);
1634 }
1635
1636 static void
1637 bfin_model_init (SIM_CPU *cpu)
1638 {
1639 CPU_MODEL_DATA (cpu) = (void *) &bfin_model_data[MODEL_NUM (CPU_MODEL (cpu))];
1640 }
1641
1642 static bu32
1643 bfin_extract_unsigned_integer (unsigned char *addr, int len)
1644 {
1645 bu32 retval;
1646 unsigned char * p;
1647 unsigned char * startaddr = (unsigned char *)addr;
1648 unsigned char * endaddr = startaddr + len;
1649
1650 retval = 0;
1651
1652 for (p = endaddr; p > startaddr;)
1653 retval = (retval << 8) | *--p;
1654
1655 return retval;
1656 }
1657
1658 static void
1659 bfin_store_unsigned_integer (unsigned char *addr, int len, bu32 val)
1660 {
1661 unsigned char *p;
1662 unsigned char *startaddr = addr;
1663 unsigned char *endaddr = startaddr + len;
1664
1665 for (p = startaddr; p < endaddr;)
1666 {
1667 *p++ = val & 0xff;
1668 val >>= 8;
1669 }
1670 }
1671
1672 static bu32 *
1673 bfin_get_reg (SIM_CPU *cpu, int rn)
1674 {
1675 switch (rn)
1676 {
1677 case SIM_BFIN_R0_REGNUM: return &DREG (0);
1678 case SIM_BFIN_R1_REGNUM: return &DREG (1);
1679 case SIM_BFIN_R2_REGNUM: return &DREG (2);
1680 case SIM_BFIN_R3_REGNUM: return &DREG (3);
1681 case SIM_BFIN_R4_REGNUM: return &DREG (4);
1682 case SIM_BFIN_R5_REGNUM: return &DREG (5);
1683 case SIM_BFIN_R6_REGNUM: return &DREG (6);
1684 case SIM_BFIN_R7_REGNUM: return &DREG (7);
1685 case SIM_BFIN_P0_REGNUM: return &PREG (0);
1686 case SIM_BFIN_P1_REGNUM: return &PREG (1);
1687 case SIM_BFIN_P2_REGNUM: return &PREG (2);
1688 case SIM_BFIN_P3_REGNUM: return &PREG (3);
1689 case SIM_BFIN_P4_REGNUM: return &PREG (4);
1690 case SIM_BFIN_P5_REGNUM: return &PREG (5);
1691 case SIM_BFIN_SP_REGNUM: return &SPREG;
1692 case SIM_BFIN_FP_REGNUM: return &FPREG;
1693 case SIM_BFIN_I0_REGNUM: return &IREG (0);
1694 case SIM_BFIN_I1_REGNUM: return &IREG (1);
1695 case SIM_BFIN_I2_REGNUM: return &IREG (2);
1696 case SIM_BFIN_I3_REGNUM: return &IREG (3);
1697 case SIM_BFIN_M0_REGNUM: return &MREG (0);
1698 case SIM_BFIN_M1_REGNUM: return &MREG (1);
1699 case SIM_BFIN_M2_REGNUM: return &MREG (2);
1700 case SIM_BFIN_M3_REGNUM: return &MREG (3);
1701 case SIM_BFIN_B0_REGNUM: return &BREG (0);
1702 case SIM_BFIN_B1_REGNUM: return &BREG (1);
1703 case SIM_BFIN_B2_REGNUM: return &BREG (2);
1704 case SIM_BFIN_B3_REGNUM: return &BREG (3);
1705 case SIM_BFIN_L0_REGNUM: return &LREG (0);
1706 case SIM_BFIN_L1_REGNUM: return &LREG (1);
1707 case SIM_BFIN_L2_REGNUM: return &LREG (2);
1708 case SIM_BFIN_L3_REGNUM: return &LREG (3);
1709 case SIM_BFIN_RETS_REGNUM: return &RETSREG;
1710 case SIM_BFIN_A0_DOT_X_REGNUM: return &AXREG (0);
1711 case SIM_BFIN_A0_DOT_W_REGNUM: return &AWREG (0);
1712 case SIM_BFIN_A1_DOT_X_REGNUM: return &AXREG (1);
1713 case SIM_BFIN_A1_DOT_W_REGNUM: return &AWREG (1);
1714 case SIM_BFIN_LC0_REGNUM: return &LCREG (0);
1715 case SIM_BFIN_LT0_REGNUM: return &LTREG (0);
1716 case SIM_BFIN_LB0_REGNUM: return &LBREG (0);
1717 case SIM_BFIN_LC1_REGNUM: return &LCREG (1);
1718 case SIM_BFIN_LT1_REGNUM: return &LTREG (1);
1719 case SIM_BFIN_LB1_REGNUM: return &LBREG (1);
1720 case SIM_BFIN_CYCLES_REGNUM: return &CYCLESREG;
1721 case SIM_BFIN_CYCLES2_REGNUM: return &CYCLES2REG;
1722 case SIM_BFIN_USP_REGNUM: return &USPREG;
1723 case SIM_BFIN_SEQSTAT_REGNUM: return &SEQSTATREG;
1724 case SIM_BFIN_SYSCFG_REGNUM: return &SYSCFGREG;
1725 case SIM_BFIN_RETI_REGNUM: return &RETIREG;
1726 case SIM_BFIN_RETX_REGNUM: return &RETXREG;
1727 case SIM_BFIN_RETN_REGNUM: return &RETNREG;
1728 case SIM_BFIN_RETE_REGNUM: return &RETEREG;
1729 case SIM_BFIN_PC_REGNUM: return &PCREG;
1730 default: return NULL;
1731 }
1732 }
1733
1734 static int
1735 bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1736 {
1737 bu32 value, *reg;
1738
1739 reg = bfin_get_reg (cpu, rn);
1740 if (reg)
1741 value = *reg;
1742 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1743 value = ASTAT;
1744 else if (rn == SIM_BFIN_CC_REGNUM)
1745 value = CCREG;
1746 else
1747 return 0; // will be an error in gdb
1748
1749 /* Handle our KSP/USP shadowing in SP. While in supervisor mode, we
1750 have the normal SP/USP behavior. User mode is tricky though. */
1751 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT
1752 && cec_is_user_mode (cpu))
1753 {
1754 if (rn == SIM_BFIN_SP_REGNUM)
1755 value = KSPREG;
1756 else if (rn == SIM_BFIN_USP_REGNUM)
1757 value = SPREG;
1758 }
1759
1760 bfin_store_unsigned_integer (buf, 4, value);
1761
1762 return -1; // disables size checking in gdb
1763 }
1764
1765 static int
1766 bfin_reg_store (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1767 {
1768 bu32 value, *reg;
1769
1770 value = bfin_extract_unsigned_integer (buf, 4);
1771 reg = bfin_get_reg (cpu, rn);
1772
1773 if (reg)
1774 /* XXX: Need register trace ? */
1775 *reg = value;
1776 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1777 SET_ASTAT (value);
1778 else if (rn == SIM_BFIN_CC_REGNUM)
1779 SET_CCREG (value);
1780 else
1781 return 0; // will be an error in gdb
1782
1783 return -1; // disables size checking in gdb
1784 }
1785
1786 static sim_cia
1787 bfin_pc_get (SIM_CPU *cpu)
1788 {
1789 return PCREG;
1790 }
1791
1792 static void
1793 bfin_pc_set (SIM_CPU *cpu, sim_cia newpc)
1794 {
1795 SET_PCREG (newpc);
1796 }
1797
1798 static const char *
1799 bfin_insn_name (SIM_CPU *cpu, int i)
1800 {
1801 static const char * const insn_name[] = {
1802 #define I(insn) #insn,
1803 #include "insn_list.def"
1804 #undef I
1805 };
1806 return insn_name[i];
1807 }
1808
1809 static void
1810 bfin_init_cpu (SIM_CPU *cpu)
1811 {
1812 CPU_REG_FETCH (cpu) = bfin_reg_fetch;
1813 CPU_REG_STORE (cpu) = bfin_reg_store;
1814 CPU_PC_FETCH (cpu) = bfin_pc_get;
1815 CPU_PC_STORE (cpu) = bfin_pc_set;
1816 CPU_MAX_INSNS (cpu) = BFIN_INSN_MAX;
1817 CPU_INSN_NAME (cpu) = bfin_insn_name;
1818 }
1819
1820 static void
1821 bfin_prepare_run (SIM_CPU *cpu)
1822 {
1823 }
1824
1825 static const MODEL bfin_models[] =
1826 {
1827 #define P(n) { "bf"#n, & bfin_mach, MODEL_BF##n, NULL, bfin_model_init },
1828 #include "proc_list.def"
1829 #undef P
1830 { 0, NULL, 0, NULL, NULL, }
1831 };
1832
1833 static const MACH_IMP_PROPERTIES bfin_imp_properties =
1834 {
1835 sizeof (SIM_CPU),
1836 0,
1837 };
1838
1839 static const MACH bfin_mach =
1840 {
1841 "bfin", "bfin", MACH_BFIN,
1842 32, 32, & bfin_models[0], & bfin_imp_properties,
1843 bfin_init_cpu,
1844 bfin_prepare_run
1845 };
1846
1847 const MACH *sim_machs[] =
1848 {
1849 & bfin_mach,
1850 NULL
1851 };
1852 \f
1853 /* Device option parsing. */
1854
1855 static DECLARE_OPTION_HANDLER (bfin_mach_option_handler);
1856
1857 enum {
1858 OPTION_MACH_SIREV = OPTION_START,
1859 OPTION_MACH_HW_BOARD_FILE,
1860 };
1861
1862 const OPTION bfin_mach_options[] =
1863 {
1864 { {"sirev", required_argument, NULL, OPTION_MACH_SIREV },
1865 '\0', "NUMBER", "Set CPU silicon revision",
1866 bfin_mach_option_handler, NULL },
1867
1868 { {"hw-board-file", required_argument, NULL, OPTION_MACH_HW_BOARD_FILE },
1869 '\0', "FILE", "Add the supplemental devices listed in the file",
1870 bfin_mach_option_handler, NULL },
1871
1872 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
1873 };
1874
1875 static SIM_RC
1876 bfin_mach_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
1877 char *arg, int is_command)
1878 {
1879 struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1880
1881 switch (opt)
1882 {
1883 case OPTION_MACH_SIREV:
1884 board->sirev_valid = 1;
1885 /* Accept (and throw away) a leading "0." in the version. */
1886 if (!strncmp (arg, "0.", 2))
1887 arg += 2;
1888 board->sirev = atoi (arg);
1889 if (board->sirev > 0xf)
1890 {
1891 sim_io_eprintf (sd, "sirev '%s' needs to fit into 4 bits\n", arg);
1892 return SIM_RC_FAIL;
1893 }
1894 return SIM_RC_OK;
1895
1896 case OPTION_MACH_HW_BOARD_FILE:
1897 board->hw_file = xstrdup (arg);
1898 return SIM_RC_OK;
1899
1900 default:
1901 sim_io_eprintf (sd, "Unknown Blackfin option %d\n", opt);
1902 return SIM_RC_FAIL;
1903 }
1904 }
GDB Binutils - Deliverables
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