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sim: bfin: new GPIO model
[deliverable/binutils-gdb.git] / sim / bfin / machs.c
1 /* Simulator for Analog Devices Blackfin processors.
2
3 Copyright (C) 2005-2012 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22
23 #include "sim-main.h"
24 #include "gdb/sim-bfin.h"
25 #include "bfd.h"
26
27 #include "sim-hw.h"
28 #include "devices.h"
29 #include "dv-bfin_cec.h"
30 #include "dv-bfin_dmac.h"
31
32 static const MACH bfin_mach;
33
34 struct bfin_memory_layout {
35 address_word addr, len;
36 unsigned mask; /* see mapmask in sim_core_attach() */
37 };
38 struct bfin_dev_layout {
39 address_word base, len;
40 unsigned int dmac;
41 const char *dev;
42 };
43 struct bfin_dmac_layout {
44 address_word base;
45 unsigned int dma_count;
46 };
47 struct bfin_port_layout {
48 /* Which device this routes to (name/port). */
49 const char *dst, *dst_port;
50 /* Which device this routes from (name/port). */
51 const char *src, *src_port;
52 };
53 struct bfin_model_data {
54 bu32 chipid;
55 int model_num;
56 const struct bfin_memory_layout *mem;
57 size_t mem_count;
58 const struct bfin_dev_layout *dev;
59 size_t dev_count;
60 const struct bfin_dmac_layout *dmac;
61 size_t dmac_count;
62 const struct bfin_port_layout *port;
63 size_t port_count;
64 };
65
66 #define LAYOUT(_addr, _len, _mask) { .addr = _addr, .len = _len, .mask = access_##_mask, }
67 #define _DEVICE(_base, _len, _dev, _dmac) { .base = _base, .len = _len, .dev = _dev, .dmac = _dmac, }
68 #define DEVICE(_base, _len, _dev) _DEVICE(_base, _len, _dev, 0)
69 #define PORT(_dst, _dst_port, _src, _src_port) \
70 { \
71 .dst = _dst, \
72 .dst_port = _dst_port, \
73 .src = _src, \
74 .src_port = _src_port, \
75 }
76 #define SIC(_s, _ip, _d, _op) PORT("bfin_sic", "int"#_ip"@"#_s, _d, _op)
77
78 /* [1] Common sim code can't model exec-only memory.
79 http://sourceware.org/ml/gdb/2010-02/msg00047.html */
80
81 #define bf000_chipid 0
82 static const struct bfin_memory_layout bf000_mem[] = {};
83 static const struct bfin_dev_layout bf000_dev[] = {};
84 static const struct bfin_dmac_layout bf000_dmac[] = {};
85 static const struct bfin_port_layout bf000_port[] = {};
86
87 #define bf50x_chipid 0x2800
88 #define bf504_chipid bf50x_chipid
89 #define bf506_chipid bf50x_chipid
90 static const struct bfin_memory_layout bf50x_mem[] =
91 {
92 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
93 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
94 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
95 LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */
96 LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */
97 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
98 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
99 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
100 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst Cache [1] */
101 };
102 #define bf504_mem bf50x_mem
103 #define bf506_mem bf50x_mem
104 static const struct bfin_dev_layout bf50x_dev[] =
105 {
106 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
107 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
108 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
109 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
110 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
111 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
112 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
113 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
114 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
115 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
116 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
117 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
118 DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
119 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
120 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
121 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
122 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
123 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
124 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
125 };
126 #define bf504_dev bf50x_dev
127 #define bf506_dev bf50x_dev
128 static const struct bfin_dmac_layout bf50x_dmac[] =
129 {
130 { BFIN_MMR_DMAC0_BASE, 12, },
131 };
132 #define bf504_dmac bf50x_dmac
133 #define bf506_dmac bf50x_dmac
134 static const struct bfin_port_layout bf50x_port[] =
135 {
136 SIC (0, 0, "bfin_pll", "pll"),
137 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
138 SIC (0, 2, "bfin_ppi@0", "stat"),
139 SIC (0, 3, "bfin_sport@0", "stat"),
140 SIC (0, 4, "bfin_sport@1", "stat"),
141 SIC (0, 5, "bfin_uart2@0", "stat"),
142 SIC (0, 6, "bfin_uart2@1", "stat"),
143 SIC (0, 7, "bfin_spi@0", "stat"),
144 SIC (0, 8, "bfin_spi@1", "stat"),
145 SIC (0, 9, "bfin_can@0", "stat"),
146 SIC (0, 10, "bfin_rsi@0", "int0"),
147 /*SIC (0, 11, reserved),*/
148 SIC (0, 12, "bfin_counter@0", "stat"),
149 SIC (0, 13, "bfin_counter@1", "stat"),
150 SIC (0, 14, "bfin_dma@0", "di"),
151 SIC (0, 15, "bfin_dma@1", "di"),
152 SIC (0, 16, "bfin_dma@2", "di"),
153 SIC (0, 17, "bfin_dma@3", "di"),
154 SIC (0, 18, "bfin_dma@4", "di"),
155 SIC (0, 19, "bfin_dma@5", "di"),
156 SIC (0, 20, "bfin_dma@6", "di"),
157 SIC (0, 21, "bfin_dma@7", "di"),
158 SIC (0, 22, "bfin_dma@8", "di"),
159 SIC (0, 23, "bfin_dma@9", "di"),
160 SIC (0, 24, "bfin_dma@10", "di"),
161 SIC (0, 25, "bfin_dma@11", "di"),
162 SIC (0, 26, "bfin_can@0", "rx"),
163 SIC (0, 27, "bfin_can@0", "tx"),
164 SIC (0, 28, "bfin_twi@0", "stat"),
165 SIC (0, 29, "bfin_gpio@5", "mask_a"),
166 SIC (0, 30, "bfin_gpio@5", "mask_b"),
167 /*SIC (0, 31, reserved),*/
168 SIC (1, 0, "bfin_gptimer@0", "stat"),
169 SIC (1, 1, "bfin_gptimer@1", "stat"),
170 SIC (1, 2, "bfin_gptimer@2", "stat"),
171 SIC (1, 3, "bfin_gptimer@3", "stat"),
172 SIC (1, 4, "bfin_gptimer@4", "stat"),
173 SIC (1, 5, "bfin_gptimer@5", "stat"),
174 SIC (1, 6, "bfin_gptimer@6", "stat"),
175 SIC (1, 7, "bfin_gptimer@7", "stat"),
176 SIC (1, 8, "bfin_gpio@6", "mask_a"),
177 SIC (1, 9, "bfin_gpio@6", "mask_b"),
178 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
179 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
180 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
181 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
182 SIC (1, 12, "bfin_wdog@0", "gpi"),
183 SIC (1, 13, "bfin_gpio@7", "mask_a"),
184 SIC (1, 14, "bfin_gpio@7", "mask_b"),
185 SIC (1, 15, "bfin_acm@0", "stat"),
186 SIC (1, 16, "bfin_acm@1", "int"),
187 /*SIC (1, 17, reserved),*/
188 /*SIC (1, 18, reserved),*/
189 SIC (1, 19, "bfin_pwm@0", "trip"),
190 SIC (1, 20, "bfin_pwm@0", "sync"),
191 SIC (1, 21, "bfin_pwm@1", "trip"),
192 SIC (1, 22, "bfin_pwm@1", "sync"),
193 SIC (1, 23, "bfin_rsi@0", "int1"),
194 };
195 #define bf504_port bf50x_port
196 #define bf506_port bf50x_port
197
198 #define bf51x_chipid 0x27e8
199 #define bf512_chipid bf51x_chipid
200 #define bf514_chipid bf51x_chipid
201 #define bf516_chipid bf51x_chipid
202 #define bf518_chipid bf51x_chipid
203 static const struct bfin_memory_layout bf51x_mem[] =
204 {
205 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
206 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
207 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
208 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
209 LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */
210 LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */
211 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
212 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
213 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
214 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
215 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
216 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
217 };
218 #define bf512_mem bf51x_mem
219 #define bf514_mem bf51x_mem
220 #define bf516_mem bf51x_mem
221 #define bf518_mem bf51x_mem
222 static const struct bfin_dev_layout bf512_dev[] =
223 {
224 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
225 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
226 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
227 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
228 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
229 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
230 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
231 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
232 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
233 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
234 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
235 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
236 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
237 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
238 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
239 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
240 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
241 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
242 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
243 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
244 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
245 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
246 };
247 #define bf514_dev bf512_dev
248 static const struct bfin_dev_layout bf516_dev[] =
249 {
250 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
251 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
252 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
253 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
254 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
255 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
256 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
257 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
258 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
259 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
260 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
261 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
262 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
263 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
264 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
265 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
266 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
267 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
268 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
269 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
270 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
271 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
272 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
273 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
274 };
275 #define bf518_dev bf516_dev
276 #define bf512_dmac bf50x_dmac
277 #define bf514_dmac bf50x_dmac
278 #define bf516_dmac bf50x_dmac
279 #define bf518_dmac bf50x_dmac
280 static const struct bfin_port_layout bf51x_port[] =
281 {
282 SIC (0, 0, "bfin_pll", "pll"),
283 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
284 SIC (0, 2, "bfin_dmar@0", "block"),
285 SIC (0, 3, "bfin_dmar@1", "block"),
286 SIC (0, 4, "bfin_dmar@0", "overflow"),
287 SIC (0, 5, "bfin_dmar@1", "overflow"),
288 SIC (0, 6, "bfin_ppi@0", "stat"),
289 SIC (0, 7, "bfin_emac", "stat"),
290 SIC (0, 8, "bfin_sport@0", "stat"),
291 SIC (0, 9, "bfin_sport@1", "stat"),
292 SIC (0, 10, "bfin_ptp", "stat"),
293 /*SIC (0, 11, reserved),*/
294 SIC (0, 12, "bfin_uart@0", "stat"),
295 SIC (0, 13, "bfin_uart@1", "stat"),
296 SIC (0, 14, "bfin_rtc", "rtc"),
297 SIC (0, 15, "bfin_dma@0", "di"),
298 SIC (0, 16, "bfin_dma@3", "di"),
299 SIC (0, 17, "bfin_dma@4", "di"),
300 SIC (0, 18, "bfin_dma@5", "di"),
301 SIC (0, 19, "bfin_dma@6", "di"),
302 SIC (0, 20, "bfin_twi@0", "stat"),
303 SIC (0, 21, "bfin_dma@7", "di"),
304 SIC (0, 22, "bfin_dma@8", "di"),
305 SIC (0, 23, "bfin_dma@9", "di"),
306 SIC (0, 24, "bfin_dma@10", "di"),
307 SIC (0, 25, "bfin_dma@11", "di"),
308 SIC (0, 26, "bfin_otp", "stat"),
309 SIC (0, 27, "bfin_counter@0", "stat"),
310 SIC (0, 28, "bfin_dma@1", "di"),
311 SIC (0, 29, "bfin_gpio@7", "mask_a"),
312 SIC (0, 30, "bfin_dma@2", "di"),
313 SIC (0, 31, "bfin_gpio@7", "mask_b"),
314 SIC (1, 0, "bfin_gptimer@0", "stat"),
315 SIC (1, 1, "bfin_gptimer@1", "stat"),
316 SIC (1, 2, "bfin_gptimer@2", "stat"),
317 SIC (1, 3, "bfin_gptimer@3", "stat"),
318 SIC (1, 4, "bfin_gptimer@4", "stat"),
319 SIC (1, 5, "bfin_gptimer@5", "stat"),
320 SIC (1, 6, "bfin_gptimer@6", "stat"),
321 SIC (1, 7, "bfin_gptimer@7", "stat"),
322 SIC (1, 8, "bfin_gpio@6", "mask_a"),
323 SIC (1, 9, "bfin_gpio@6", "mask_b"),
324 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
325 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
326 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
327 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
328 SIC (1, 12, "bfin_wdog@0", "gpi"),
329 SIC (1, 13, "bfin_gpio@5", "mask_a"),
330 SIC (1, 14, "bfin_gpio@5", "mask_b"),
331 SIC (1, 15, "bfin_spi@0", "stat"),
332 SIC (1, 16, "bfin_spi@1", "stat"),
333 /*SIC (1, 17, reserved),*/
334 /*SIC (1, 18, reserved),*/
335 SIC (1, 19, "bfin_rsi@0", "int0"),
336 SIC (1, 20, "bfin_rsi@0", "int1"),
337 SIC (1, 21, "bfin_pwm@0", "trip"),
338 SIC (1, 22, "bfin_pwm@0", "sync"),
339 SIC (1, 23, "bfin_ptp", "stat"),
340 };
341 #define bf512_port bf51x_port
342 #define bf514_port bf51x_port
343 #define bf516_port bf51x_port
344 #define bf518_port bf51x_port
345
346 #define bf522_chipid 0x27e4
347 #define bf523_chipid 0x27e0
348 #define bf524_chipid bf522_chipid
349 #define bf525_chipid bf523_chipid
350 #define bf526_chipid bf522_chipid
351 #define bf527_chipid bf523_chipid
352 static const struct bfin_memory_layout bf52x_mem[] =
353 {
354 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
355 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
356 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
357 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
358 LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */
359 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
360 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
361 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
362 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
363 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
364 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
365 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
366 };
367 #define bf522_mem bf52x_mem
368 #define bf523_mem bf52x_mem
369 #define bf524_mem bf52x_mem
370 #define bf525_mem bf52x_mem
371 #define bf526_mem bf52x_mem
372 #define bf527_mem bf52x_mem
373 static const struct bfin_dev_layout bf522_dev[] =
374 {
375 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
376 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
377 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
378 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
379 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
380 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
381 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
382 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
383 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
384 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
385 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
386 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
387 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
388 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
389 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
390 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
391 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
392 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
393 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
394 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
395 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
396 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
397 };
398 #define bf523_dev bf522_dev
399 #define bf524_dev bf522_dev
400 #define bf525_dev bf522_dev
401 static const struct bfin_dev_layout bf526_dev[] =
402 {
403 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
404 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
405 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
406 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
407 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
408 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
409 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
410 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
411 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
412 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
413 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
414 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
415 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
416 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
417 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
418 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
419 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
420 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
421 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
422 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
423 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
424 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
425 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
426 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
427 };
428 #define bf527_dev bf526_dev
429 #define bf522_dmac bf50x_dmac
430 #define bf523_dmac bf50x_dmac
431 #define bf524_dmac bf50x_dmac
432 #define bf525_dmac bf50x_dmac
433 #define bf526_dmac bf50x_dmac
434 #define bf527_dmac bf50x_dmac
435 static const struct bfin_port_layout bf52x_port[] =
436 {
437 SIC (0, 0, "bfin_pll", "pll"),
438 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
439 SIC (0, 2, "bfin_dmar@0", "block"),
440 SIC (0, 3, "bfin_dmar@1", "block"),
441 SIC (0, 4, "bfin_dmar@0", "overflow"),
442 SIC (0, 5, "bfin_dmar@1", "overflow"),
443 SIC (0, 6, "bfin_ppi@0", "stat"),
444 SIC (0, 7, "bfin_emac", "stat"),
445 SIC (0, 8, "bfin_sport@0", "stat"),
446 SIC (0, 9, "bfin_sport@1", "stat"),
447 /*SIC (0, 10, reserved),*/
448 /*SIC (0, 11, reserved),*/
449 SIC (0, 12, "bfin_uart@0", "stat"),
450 SIC (0, 13, "bfin_uart@1", "stat"),
451 SIC (0, 14, "bfin_rtc", "rtc"),
452 SIC (0, 15, "bfin_dma@0", "di"),
453 SIC (0, 16, "bfin_dma@3", "di"),
454 SIC (0, 17, "bfin_dma@4", "di"),
455 SIC (0, 18, "bfin_dma@5", "di"),
456 SIC (0, 19, "bfin_dma@6", "di"),
457 SIC (0, 20, "bfin_twi@0", "stat"),
458 SIC (0, 21, "bfin_dma@7", "di"),
459 SIC (0, 22, "bfin_dma@8", "di"),
460 SIC (0, 23, "bfin_dma@9", "di"),
461 SIC (0, 24, "bfin_dma@10", "di"),
462 SIC (0, 25, "bfin_dma@11", "di"),
463 SIC (0, 26, "bfin_otp", "stat"),
464 SIC (0, 27, "bfin_counter@0", "stat"),
465 SIC (0, 28, "bfin_dma@1", "di"),
466 SIC (0, 29, "bfin_gpio@7", "mask_a"),
467 SIC (0, 30, "bfin_dma@2", "di"),
468 SIC (0, 31, "bfin_gpio@7", "mask_b"),
469 SIC (1, 0, "bfin_gptimer@0", "stat"),
470 SIC (1, 1, "bfin_gptimer@1", "stat"),
471 SIC (1, 2, "bfin_gptimer@2", "stat"),
472 SIC (1, 3, "bfin_gptimer@3", "stat"),
473 SIC (1, 4, "bfin_gptimer@4", "stat"),
474 SIC (1, 5, "bfin_gptimer@5", "stat"),
475 SIC (1, 6, "bfin_gptimer@6", "stat"),
476 SIC (1, 7, "bfin_gptimer@7", "stat"),
477 SIC (1, 8, "bfin_gpio@6", "mask_a"),
478 SIC (1, 9, "bfin_gpio@6", "mask_b"),
479 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
480 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
481 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
482 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
483 SIC (1, 12, "bfin_wdog@0", "gpi"),
484 SIC (1, 13, "bfin_gpio@5", "mask_a"),
485 SIC (1, 14, "bfin_gpio@5", "mask_b"),
486 SIC (1, 15, "bfin_spi@0", "stat"),
487 SIC (1, 16, "bfin_nfc", "stat"),
488 SIC (1, 17, "bfin_hostdp", "stat"),
489 SIC (1, 18, "bfin_hostdp", "done"),
490 SIC (1, 20, "bfin_usb", "int0"),
491 SIC (1, 21, "bfin_usb", "int1"),
492 SIC (1, 22, "bfin_usb", "int2"),
493 };
494 #define bf522_port bf51x_port
495 #define bf523_port bf51x_port
496 #define bf524_port bf51x_port
497 #define bf525_port bf51x_port
498 #define bf526_port bf51x_port
499 #define bf527_port bf51x_port
500
501 #define bf531_chipid 0x27a5
502 #define bf532_chipid bf531_chipid
503 #define bf533_chipid bf531_chipid
504 static const struct bfin_memory_layout bf531_mem[] =
505 {
506 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
507 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
508 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
509 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
510 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
511 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
512 };
513 static const struct bfin_memory_layout bf532_mem[] =
514 {
515 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
516 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
517 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
518 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
519 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
520 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
521 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
522 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
523 };
524 static const struct bfin_memory_layout bf533_mem[] =
525 {
526 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
527 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
528 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
529 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
530 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
531 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
532 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
533 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
534 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
535 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
536 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
537 };
538 static const struct bfin_dev_layout bf533_dev[] =
539 {
540 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
541 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
542 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
543 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
544 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
545 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
546 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
547 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
548 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
549 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
550 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
551 };
552 #define bf531_dev bf533_dev
553 #define bf532_dev bf533_dev
554 static const struct bfin_dmac_layout bf533_dmac[] =
555 {
556 { BFIN_MMR_DMAC0_BASE, 8, },
557 };
558 #define bf531_dmac bf533_dmac
559 #define bf532_dmac bf533_dmac
560 static const struct bfin_port_layout bf533_port[] =
561 {
562 SIC (0, 0, "bfin_pll", "pll"),
563 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
564 SIC (0, 2, "bfin_ppi@0", "stat"),
565 SIC (0, 3, "bfin_sport@0", "stat"),
566 SIC (0, 4, "bfin_sport@1", "stat"),
567 SIC (0, 5, "bfin_spi@0", "stat"),
568 SIC (0, 6, "bfin_uart@0", "stat"),
569 SIC (0, 7, "bfin_rtc", "rtc"),
570 SIC (0, 8, "bfin_dma@0", "di"),
571 SIC (0, 9, "bfin_dma@1", "di"),
572 SIC (0, 10, "bfin_dma@2", "di"),
573 SIC (0, 11, "bfin_dma@3", "di"),
574 SIC (0, 12, "bfin_dma@4", "di"),
575 SIC (0, 13, "bfin_dma@5", "di"),
576 SIC (0, 14, "bfin_dma@6", "di"),
577 SIC (0, 15, "bfin_dma@7", "di"),
578 SIC (0, 16, "bfin_gptimer@0", "stat"),
579 SIC (0, 17, "bfin_gptimer@1", "stat"),
580 SIC (0, 18, "bfin_gptimer@2", "stat"),
581 SIC (0, 19, "bfin_gpio@5", "mask_a"),
582 SIC (0, 20, "bfin_gpio@5", "mask_b"),
583 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
584 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
585 SIC (0, 22, "bfin_dma@258", "di"), /* mdma */
586 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
587 SIC (0, 23, "bfin_wdog@0", "gpi"),
588 };
589 #define bf531_port bf533_port
590 #define bf532_port bf533_port
591
592 #define bf534_chipid 0x27c6
593 #define bf536_chipid 0x27c8
594 #define bf537_chipid bf536_chipid
595 static const struct bfin_memory_layout bf534_mem[] =
596 {
597 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
598 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
599 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
600 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
601 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
602 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
603 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
604 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
605 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
606 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
607 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
608 };
609 static const struct bfin_memory_layout bf536_mem[] =
610 {
611 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
612 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
613 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
614 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
615 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
616 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
617 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
618 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
619 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
620 };
621 static const struct bfin_memory_layout bf537_mem[] =
622 {
623 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
624 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
625 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
626 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
627 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
628 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
629 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
630 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
631 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
632 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
633 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
634 };
635 static const struct bfin_dev_layout bf534_dev[] =
636 {
637 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
638 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
639 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
640 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
641 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
642 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
643 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
644 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
645 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
646 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
647 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
648 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
649 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
650 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
651 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
652 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
653 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
654 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
655 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
656 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
657 DEVICE (0, 0, "glue-or@1"),
658 DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"),
659 DEVICE (0, 0, "glue-or@2"),
660 DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"),
661 DEVICE (0, 0, "glue-or@17"),
662 DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"),
663 DEVICE (0, 0, "glue-or@18"),
664 DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"),
665 DEVICE (0, 0, "glue-or@27"),
666 DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"),
667 DEVICE (0, 0, "glue-or@31"),
668 DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"),
669 };
670 static const struct bfin_dev_layout bf537_dev[] =
671 {
672 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
673 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
674 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
675 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
676 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
677 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
678 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
679 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
680 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
681 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
682 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
683 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
684 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
685 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
686 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
687 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
688 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
689 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
690 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
691 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
692 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
693 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
694 DEVICE (0, 0, "glue-or@1"),
695 DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"),
696 DEVICE (0, 0, "glue-or@2"),
697 DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"),
698 DEVICE (0, 0, "glue-or@17"),
699 DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"),
700 DEVICE (0, 0, "glue-or@18"),
701 DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"),
702 DEVICE (0, 0, "glue-or@27"),
703 DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"),
704 DEVICE (0, 0, "glue-or@31"),
705 DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"),
706 };
707 #define bf536_dev bf537_dev
708 #define bf534_dmac bf50x_dmac
709 #define bf536_dmac bf50x_dmac
710 #define bf537_dmac bf50x_dmac
711 static const struct bfin_port_layout bf537_port[] =
712 {
713 SIC (0, 0, "bfin_pll", "pll"),
714 SIC (0, 1, "glue-or@1", "int"),
715 /*PORT ("glue-or@1", "int", "bfin_dmac@0", "stat"),*/
716 PORT ("glue-or@1", "int", "bfin_dmar@0", "block"),
717 PORT ("glue-or@1", "int", "bfin_dmar@1", "block"),
718 PORT ("glue-or@1", "int", "bfin_dmar@0", "overflow"),
719 PORT ("glue-or@1", "int", "bfin_dmar@1", "overflow"),
720 SIC (0, 2, "glue-or@2", "int"),
721 PORT ("glue-or@2", "int", "bfin_can@0", "stat"),
722 PORT ("glue-or@2", "int", "bfin_emac", "stat"),
723 PORT ("glue-or@2", "int", "bfin_sport@0", "stat"),
724 PORT ("glue-or@2", "int", "bfin_sport@1", "stat"),
725 PORT ("glue-or@2", "int", "bfin_ppi@0", "stat"),
726 PORT ("glue-or@2", "int", "bfin_spi@0", "stat"),
727 PORT ("glue-or@2", "int", "bfin_uart@0", "stat"),
728 PORT ("glue-or@2", "int", "bfin_uart@1", "stat"),
729 SIC (0, 3, "bfin_rtc", "rtc"),
730 SIC (0, 4, "bfin_dma@0", "di"),
731 SIC (0, 5, "bfin_dma@3", "di"),
732 SIC (0, 6, "bfin_dma@4", "di"),
733 SIC (0, 7, "bfin_dma@5", "di"),
734 SIC (0, 8, "bfin_dma@6", "di"),
735 SIC (0, 9, "bfin_twi@0", "stat"),
736 SIC (0, 10, "bfin_dma@7", "di"),
737 SIC (0, 11, "bfin_dma@8", "di"),
738 SIC (0, 12, "bfin_dma@9", "di"),
739 SIC (0, 13, "bfin_dma@10", "di"),
740 SIC (0, 14, "bfin_dma@11", "di"),
741 SIC (0, 15, "bfin_can@0", "rx"),
742 SIC (0, 16, "bfin_can@0", "tx"),
743 SIC (0, 17, "glue-or@17", "int"),
744 PORT ("glue-or@17", "int", "bfin_dma@1", "di"),
745 PORT ("glue-or@17", "int", "bfin_gpio@7", "mask_a"),
746 SIC (0, 18, "glue-or@18", "int"),
747 PORT ("glue-or@18", "int", "bfin_dma@2", "di"),
748 PORT ("glue-or@18", "int", "bfin_gpio@7", "mask_b"),
749 SIC (0, 19, "bfin_gptimer@0", "stat"),
750 SIC (0, 20, "bfin_gptimer@1", "stat"),
751 SIC (0, 21, "bfin_gptimer@2", "stat"),
752 SIC (0, 22, "bfin_gptimer@3", "stat"),
753 SIC (0, 23, "bfin_gptimer@4", "stat"),
754 SIC (0, 24, "bfin_gptimer@5", "stat"),
755 SIC (0, 25, "bfin_gptimer@6", "stat"),
756 SIC (0, 26, "bfin_gptimer@7", "stat"),
757 SIC (0, 27, "glue-or@27", "int"),
758 PORT ("glue-or@27", "int", "bfin_gpio@5", "mask_a"),
759 PORT ("glue-or@27", "int", "bfin_gpio@6", "mask_a"),
760 SIC (0, 28, "bfin_gpio@6", "mask_b"),
761 SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */
762 SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */
763 SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */
764 SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */
765 SIC (0, 31, "glue-or@31", "int"),
766 PORT ("glue-or@31", "int", "bfin_wdog@0", "gpi"),
767 PORT ("glue-or@31", "int", "bfin_gpio@5", "mask_b"),
768 };
769 #define bf534_port bf537_port
770 #define bf536_port bf537_port
771
772 #define bf538_chipid 0x27c4
773 #define bf539_chipid bf538_chipid
774 static const struct bfin_memory_layout bf538_mem[] =
775 {
776 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
777 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
778 LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */
779 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
780 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
781 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
782 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
783 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
784 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
785 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
786 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
787 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
788 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
789 };
790 #define bf539_mem bf538_mem
791 static const struct bfin_dev_layout bf538_dev[] =
792 {
793 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
794 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
795 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
796 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
797 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
798 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
799 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
800 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
801 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
802 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
803 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
804 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
805 _DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1),
806 _DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1),
807 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
808 _DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1", 1),
809 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
810 };
811 #define bf539_dev bf538_dev
812 static const struct bfin_dmac_layout bf538_dmac[] =
813 {
814 { BFIN_MMR_DMAC0_BASE, 8, },
815 { BFIN_MMR_DMAC1_BASE, 12, },
816 };
817 #define bf539_dmac bf538_dmac
818 static const struct bfin_port_layout bf538_port[] =
819 {
820 SIC (0, 0, "bfin_pll", "pll"),
821 SIC (0, 1, "bfin_dmac@0", "stat"),
822 SIC (0, 2, "bfin_ppi@0", "stat"),
823 SIC (0, 3, "bfin_sport@0", "stat"),
824 SIC (0, 4, "bfin_sport@1", "stat"),
825 SIC (0, 5, "bfin_spi@0", "stat"),
826 SIC (0, 6, "bfin_uart@0", "stat"),
827 SIC (0, 7, "bfin_rtc", "rtc"),
828 SIC (0, 8, "bfin_dma@0", "di"),
829 SIC (0, 9, "bfin_dma@1", "di"),
830 SIC (0, 10, "bfin_dma@2", "di"),
831 SIC (0, 11, "bfin_dma@3", "di"),
832 SIC (0, 12, "bfin_dma@4", "di"),
833 SIC (0, 13, "bfin_dma@5", "di"),
834 SIC (0, 14, "bfin_dma@6", "di"),
835 SIC (0, 15, "bfin_dma@7", "di"),
836 SIC (0, 16, "bfin_gptimer@0", "stat"),
837 SIC (0, 17, "bfin_gptimer@1", "stat"),
838 SIC (0, 18, "bfin_gptimer@2", "stat"),
839 SIC (0, 19, "bfin_gpio@5", "mask_a"),
840 SIC (0, 20, "bfin_gpio@5", "mask_b"),
841 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
842 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
843 SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */
844 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
845 SIC (0, 23, "bfin_wdog@0", "gpi"),
846 SIC (0, 24, "bfin_dmac@1", "stat"),
847 SIC (0, 25, "bfin_sport@2", "stat"),
848 SIC (0, 26, "bfin_sport@3", "stat"),
849 /*SIC (0, 27, reserved),*/
850 SIC (0, 28, "bfin_spi@1", "stat"),
851 SIC (0, 29, "bfin_spi@2", "stat"),
852 SIC (0, 30, "bfin_uart@1", "stat"),
853 SIC (0, 31, "bfin_uart@2", "stat"),
854 SIC (1, 0, "bfin_can@0", "stat"),
855 SIC (1, 1, "bfin_dma@8", "di"),
856 SIC (1, 2, "bfin_dma@9", "di"),
857 SIC (1, 3, "bfin_dma@10", "di"),
858 SIC (1, 4, "bfin_dma@11", "di"),
859 SIC (1, 5, "bfin_dma@12", "di"),
860 SIC (1, 6, "bfin_dma@13", "di"),
861 SIC (1, 7, "bfin_dma@14", "di"),
862 SIC (1, 8, "bfin_dma@15", "di"),
863 SIC (1, 9, "bfin_dma@16", "di"),
864 SIC (1, 10, "bfin_dma@17", "di"),
865 SIC (1, 11, "bfin_dma@18", "di"),
866 SIC (1, 12, "bfin_dma@19", "di"),
867 SIC (1, 13, "bfin_twi@0", "stat"),
868 SIC (1, 14, "bfin_twi@1", "stat"),
869 SIC (1, 15, "bfin_can@0", "rx"),
870 SIC (1, 16, "bfin_can@0", "tx"),
871 SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */
872 SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */
873 SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */
874 SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */
875 };
876 #define bf539_port bf538_port
877
878 #define bf54x_chipid 0x27de
879 #define bf542_chipid bf54x_chipid
880 #define bf544_chipid bf54x_chipid
881 #define bf547_chipid bf54x_chipid
882 #define bf548_chipid bf54x_chipid
883 #define bf549_chipid bf54x_chipid
884 static const struct bfin_memory_layout bf54x_mem[] =
885 {
886 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */
887 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
888 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
889 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
890 LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */
891 LAYOUT (0xFFC03900, 0x100, read_write), /* RSI stub */
892 LAYOUT (0xFFC03C00, 0x500, read_write), /* MUSB stub */
893 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
894 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
895 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
896 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
897 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
898 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
899 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
900 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
901 };
902 #define bf542_mem bf54x_mem
903 #define bf544_mem bf54x_mem
904 #define bf547_mem bf54x_mem
905 #define bf548_mem bf54x_mem
906 #define bf549_mem bf54x_mem
907 static const struct bfin_dev_layout bf542_dev[] =
908 {
909 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
910 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
911 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
912 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
913 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
914 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
915 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
916 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
917 DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"),
918 DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"),
919 DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"),
920 DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"),
921 DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"),
922 DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"),
923 DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"),
924 DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"),
925 DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"),
926 DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"),
927 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
928 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
929 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
930 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
931 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
932 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
933 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
934 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
935 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
936 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
937 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
938 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
939 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
940 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
941 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
942 };
943 static const struct bfin_dev_layout bf544_dev[] =
944 {
945 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
946 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
947 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
948 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
949 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
950 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
951 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
952 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
953 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
954 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
955 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
956 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
957 DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"),
958 DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"),
959 DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"),
960 DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"),
961 DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"),
962 DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"),
963 DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"),
964 DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"),
965 DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"),
966 DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"),
967 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
968 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
969 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
970 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
971 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
972 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
973 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
974 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
975 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
976 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
977 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
978 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
979 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
980 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
981 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
982 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
983 };
984 static const struct bfin_dev_layout bf547_dev[] =
985 {
986 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
987 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
988 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
989 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
990 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
991 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
992 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
993 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
994 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
995 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
996 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
997 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
998 DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"),
999 DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"),
1000 DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"),
1001 DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"),
1002 DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"),
1003 DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"),
1004 DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"),
1005 DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"),
1006 DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"),
1007 DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"),
1008 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
1009 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
1010 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
1011 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
1012 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
1013 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
1014 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
1015 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
1016 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
1017 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
1018 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
1019 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
1020 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
1021 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
1022 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
1023 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
1024 };
1025 #define bf548_dev bf547_dev
1026 #define bf549_dev bf547_dev
1027 static const struct bfin_dmac_layout bf54x_dmac[] =
1028 {
1029 { BFIN_MMR_DMAC0_BASE, 12, },
1030 { BFIN_MMR_DMAC1_BASE, 12, },
1031 };
1032 #define bf542_dmac bf54x_dmac
1033 #define bf544_dmac bf54x_dmac
1034 #define bf547_dmac bf54x_dmac
1035 #define bf548_dmac bf54x_dmac
1036 #define bf549_dmac bf54x_dmac
1037 static const struct bfin_port_layout bf54x_port[] =
1038 {
1039 SIC (0, 0, "bfin_pll", "pll"),
1040 SIC (0, 1, "bfin_dmac@0", "stat"),
1041 SIC (0, 2, "bfin_eppi@0", "stat"),
1042 SIC (0, 3, "bfin_sport@0", "stat"),
1043 SIC (0, 4, "bfin_sport@1", "stat"),
1044 SIC (0, 5, "bfin_spi@0", "stat"),
1045 SIC (0, 6, "bfin_uart2@0", "stat"),
1046 SIC (0, 7, "bfin_rtc", "rtc"),
1047 SIC (0, 8, "bfin_dma@12", "di"),
1048 SIC (0, 9, "bfin_dma@0", "di"),
1049 SIC (0, 10, "bfin_dma@1", "di"),
1050 SIC (0, 11, "bfin_dma@2", "di"),
1051 SIC (0, 12, "bfin_dma@3", "di"),
1052 SIC (0, 13, "bfin_dma@4", "di"),
1053 SIC (0, 14, "bfin_dma@6", "di"),
1054 SIC (0, 15, "bfin_dma@7", "di"),
1055 SIC (0, 16, "bfin_gptimer@8", "stat"),
1056 SIC (0, 17, "bfin_gptimer@9", "stat"),
1057 SIC (0, 18, "bfin_gptimer@10", "stat"),
1058 SIC (0, 19, "bfin_pint@0", "stat"),
1059 SIC (0, 20, "bfin_pint@1", "stat"),
1060 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
1061 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
1062 SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */
1063 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
1064 SIC (0, 23, "bfin_wdog@0", "gpi"),
1065 SIC (0, 24, "bfin_dmac@1", "stat"),
1066 SIC (0, 25, "bfin_sport@2", "stat"),
1067 SIC (0, 26, "bfin_sport@3", "stat"),
1068 SIC (0, 27, "bfin_mxvr", "data"),
1069 SIC (0, 28, "bfin_spi@1", "stat"),
1070 SIC (0, 29, "bfin_spi@2", "stat"),
1071 SIC (0, 30, "bfin_uart2@1", "stat"),
1072 SIC (0, 31, "bfin_uart2@2", "stat"),
1073 SIC (1, 0, "bfin_can@0", "stat"),
1074 SIC (1, 1, "bfin_dma@18", "di"),
1075 SIC (1, 2, "bfin_dma@19", "di"),
1076 SIC (1, 3, "bfin_dma@20", "di"),
1077 SIC (1, 4, "bfin_dma@21", "di"),
1078 SIC (1, 5, "bfin_dma@13", "di"),
1079 SIC (1, 6, "bfin_dma@14", "di"),
1080 SIC (1, 7, "bfin_dma@5", "di"),
1081 SIC (1, 8, "bfin_dma@23", "di"),
1082 SIC (1, 9, "bfin_dma@8", "di"),
1083 SIC (1, 10, "bfin_dma@9", "di"),
1084 SIC (1, 11, "bfin_dma@10", "di"),
1085 SIC (1, 12, "bfin_dma@11", "di"),
1086 SIC (1, 13, "bfin_twi@0", "stat"),
1087 SIC (1, 14, "bfin_twi@1", "stat"),
1088 SIC (1, 15, "bfin_can@0", "rx"),
1089 SIC (1, 16, "bfin_can@0", "tx"),
1090 SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */
1091 SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */
1092 SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */
1093 SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */
1094 SIC (1, 19, "bfin_mxvr", "stat"),
1095 SIC (1, 20, "bfin_mxvr", "message"),
1096 SIC (1, 21, "bfin_mxvr", "packet"),
1097 SIC (1, 22, "bfin_eppi@1", "stat"),
1098 SIC (1, 23, "bfin_eppi@2", "stat"),
1099 SIC (1, 24, "bfin_uart2@3", "stat"),
1100 SIC (1, 25, "bfin_hostdp", "stat"),
1101 /*SIC (1, 26, reserved),*/
1102 SIC (1, 27, "bfin_pixc", "stat"),
1103 SIC (1, 28, "bfin_nfc", "stat"),
1104 SIC (1, 29, "bfin_atapi", "stat"),
1105 SIC (1, 30, "bfin_can@1", "stat"),
1106 SIC (1, 31, "bfin_dmar@0", "block"),
1107 SIC (1, 31, "bfin_dmar@1", "block"),
1108 SIC (1, 31, "bfin_dmar@0", "overflow"),
1109 SIC (1, 31, "bfin_dmar@1", "overflow"),
1110 SIC (2, 0, "bfin_dma@15", "di"),
1111 SIC (2, 1, "bfin_dma@16", "di"),
1112 SIC (2, 2, "bfin_dma@17", "di"),
1113 SIC (2, 3, "bfin_dma@22", "di"),
1114 SIC (2, 4, "bfin_counter@0", "stat"),
1115 SIC (2, 5, "bfin_kpad@0", "stat"),
1116 SIC (2, 6, "bfin_can@1", "rx"),
1117 SIC (2, 7, "bfin_can@1", "tx"),
1118 SIC (2, 8, "bfin_sdh", "mask0"),
1119 SIC (2, 9, "bfin_sdh", "mask1"),
1120 /*SIC (2, 10, reserved),*/
1121 SIC (2, 11, "bfin_usb", "int0"),
1122 SIC (2, 12, "bfin_usb", "int1"),
1123 SIC (2, 13, "bfin_usb", "int2"),
1124 SIC (2, 14, "bfin_usb", "dma"),
1125 SIC (2, 15, "bfin_otp", "stat"),
1126 /*SIC (2, 16, reserved),*/
1127 /*SIC (2, 17, reserved),*/
1128 /*SIC (2, 18, reserved),*/
1129 /*SIC (2, 19, reserved),*/
1130 /*SIC (2, 20, reserved),*/
1131 /*SIC (2, 21, reserved),*/
1132 SIC (2, 22, "bfin_gptimer@0", "stat"),
1133 SIC (2, 23, "bfin_gptimer@1", "stat"),
1134 SIC (2, 24, "bfin_gptimer@2", "stat"),
1135 SIC (2, 25, "bfin_gptimer@3", "stat"),
1136 SIC (2, 26, "bfin_gptimer@4", "stat"),
1137 SIC (2, 27, "bfin_gptimer@5", "stat"),
1138 SIC (2, 28, "bfin_gptimer@6", "stat"),
1139 SIC (2, 29, "bfin_gptimer@7", "stat"),
1140 SIC (2, 30, "bfin_pint@2", "stat"),
1141 SIC (2, 31, "bfin_pint@3", "stat"),
1142 };
1143 #define bf542_port bf54x_port
1144 #define bf544_port bf54x_port
1145 #define bf547_port bf54x_port
1146 #define bf548_port bf54x_port
1147 #define bf549_port bf54x_port
1148
1149 /* This is only Core A of course ... */
1150 #define bf561_chipid 0x27bb
1151 static const struct bfin_memory_layout bf561_mem[] =
1152 {
1153 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
1154 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
1155 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
1156 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
1157 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
1158 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
1159 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
1160 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
1161 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
1162 };
1163 static const struct bfin_dev_layout bf561_dev[] =
1164 {
1165 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
1166 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
1167 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
1168 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
1169 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
1170 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
1171 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
1172 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
1173 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
1174 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
1175 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
1176 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
1177 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
1178 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
1179 _DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1),
1180 DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"),
1181 _DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1),
1182 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
1183 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
1184 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
1185 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
1186 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"),
1187 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
1188 };
1189 static const struct bfin_dmac_layout bf561_dmac[] =
1190 {
1191 { BFIN_MMR_DMAC0_BASE, 12, },
1192 { BFIN_MMR_DMAC1_BASE, 12, },
1193 /* XXX: IMDMA: { 0xFFC01800, 4, }, */
1194 };
1195 static const struct bfin_port_layout bf561_port[] =
1196 {
1197 /* SIC0 */
1198 SIC (0, 0, "bfin_pll", "pll"),
1199 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
1200 /*SIC (0, 2, "bfin_dmac@1", "stat"),*/
1201 /*SIC (0, 3, "bfin_imdmac", "stat"),*/
1202 SIC (0, 4, "bfin_ppi@0", "stat"),
1203 SIC (0, 5, "bfin_ppi@1", "stat"),
1204 SIC (0, 6, "bfin_sport@0", "stat"),
1205 SIC (0, 7, "bfin_sport@1", "stat"),
1206 SIC (0, 8, "bfin_spi@0", "stat"),
1207 SIC (0, 9, "bfin_uart@0", "stat"),
1208 /*SIC (0, 10, reserved),*/
1209 SIC (0, 11, "bfin_dma@12", "di"),
1210 SIC (0, 12, "bfin_dma@13", "di"),
1211 SIC (0, 13, "bfin_dma@14", "di"),
1212 SIC (0, 14, "bfin_dma@15", "di"),
1213 SIC (0, 15, "bfin_dma@16", "di"),
1214 SIC (0, 16, "bfin_dma@17", "di"),
1215 SIC (0, 17, "bfin_dma@18", "di"),
1216 SIC (0, 18, "bfin_dma@19", "di"),
1217 SIC (0, 19, "bfin_dma@20", "di"),
1218 SIC (0, 20, "bfin_dma@21", "di"),
1219 SIC (0, 21, "bfin_dma@22", "di"),
1220 SIC (0, 22, "bfin_dma@23", "di"),
1221 SIC (0, 23, "bfin_dma@0", "di"),
1222 SIC (0, 24, "bfin_dma@1", "di"),
1223 SIC (0, 25, "bfin_dma@2", "di"),
1224 SIC (0, 26, "bfin_dma@3", "di"),
1225 SIC (0, 27, "bfin_dma@4", "di"),
1226 SIC (0, 28, "bfin_dma@5", "di"),
1227 SIC (0, 29, "bfin_dma@6", "di"),
1228 SIC (0, 30, "bfin_dma@7", "di"),
1229 SIC (0, 31, "bfin_dma@8", "di"),
1230 SIC (1, 0, "bfin_dma@9", "di"),
1231 SIC (1, 1, "bfin_dma@10", "di"),
1232 SIC (1, 2, "bfin_dma@11", "di"),
1233 SIC (1, 3, "bfin_gptimer@0", "stat"),
1234 SIC (1, 4, "bfin_gptimer@1", "stat"),
1235 SIC (1, 5, "bfin_gptimer@2", "stat"),
1236 SIC (1, 6, "bfin_gptimer@3", "stat"),
1237 SIC (1, 7, "bfin_gptimer@4", "stat"),
1238 SIC (1, 8, "bfin_gptimer@5", "stat"),
1239 SIC (1, 9, "bfin_gptimer@6", "stat"),
1240 SIC (1, 10, "bfin_gptimer@7", "stat"),
1241 SIC (1, 11, "bfin_gptimer@8", "stat"),
1242 SIC (1, 12, "bfin_gptimer@9", "stat"),
1243 SIC (1, 13, "bfin_gptimer@10", "stat"),
1244 SIC (1, 14, "bfin_gptimer@11", "stat"),
1245 SIC (1, 15, "bfin_gpio@5", "mask_a"),
1246 SIC (1, 16, "bfin_gpio@5", "mask_b"),
1247 SIC (1, 17, "bfin_gpio@6", "mask_a"),
1248 SIC (1, 18, "bfin_gpio@6", "mask_b"),
1249 SIC (1, 19, "bfin_gpio@7", "mask_a"),
1250 SIC (1, 20, "bfin_gpio@7", "mask_b"),
1251 SIC (1, 21, "bfin_dma@256", "di"), /* mdma0 */
1252 SIC (1, 21, "bfin_dma@257", "di"), /* mdma0 */
1253 SIC (1, 22, "bfin_dma@258", "di"), /* mdma1 */
1254 SIC (1, 22, "bfin_dma@259", "di"), /* mdma1 */
1255 SIC (1, 23, "bfin_dma@260", "di"), /* mdma2 */
1256 SIC (1, 23, "bfin_dma@261", "di"), /* mdma2 */
1257 SIC (1, 24, "bfin_dma@262", "di"), /* mdma3 */
1258 SIC (1, 24, "bfin_dma@263", "di"), /* mdma3 */
1259 SIC (1, 25, "bfin_imdma@0", "di"),
1260 SIC (1, 26, "bfin_imdma@1", "di"),
1261 SIC (1, 27, "bfin_wdog@0", "gpi"),
1262 SIC (1, 27, "bfin_wdog@1", "gpi"),
1263 /*SIC (1, 28, reserved),*/
1264 /*SIC (1, 29, reserved),*/
1265 SIC (1, 30, "bfin_sic", "sup_irq@0"),
1266 SIC (1, 31, "bfin_sic", "sup_irq@1"),
1267 };
1268
1269 #define bf592_chipid 0x20cb
1270 static const struct bfin_memory_layout bf592_mem[] =
1271 {
1272 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
1273 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
1274 LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */
1275 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
1276 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */
1277 };
1278 static const struct bfin_dev_layout bf592_dev[] =
1279 {
1280 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
1281 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
1282 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
1283 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
1284 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
1285 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
1286 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
1287 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
1288 DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
1289 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
1290 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
1291 };
1292 static const struct bfin_dmac_layout bf592_dmac[] =
1293 {
1294 /* XXX: there are only 9 channels, but mdma code below assumes that they
1295 start right after the dma channels ... */
1296 { BFIN_MMR_DMAC0_BASE, 12, },
1297 };
1298 static const struct bfin_port_layout bf592_port[] =
1299 {
1300 SIC (0, 0, "bfin_pll", "pll"),
1301 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
1302 SIC (0, 2, "bfin_ppi@0", "stat"),
1303 SIC (0, 3, "bfin_sport@0", "stat"),
1304 SIC (0, 4, "bfin_sport@1", "stat"),
1305 SIC (0, 5, "bfin_spi@0", "stat"),
1306 SIC (0, 6, "bfin_spi@1", "stat"),
1307 SIC (0, 7, "bfin_uart@0", "stat"),
1308 SIC (0, 8, "bfin_dma@0", "di"),
1309 SIC (0, 9, "bfin_dma@1", "di"),
1310 SIC (0, 10, "bfin_dma@2", "di"),
1311 SIC (0, 11, "bfin_dma@3", "di"),
1312 SIC (0, 12, "bfin_dma@4", "di"),
1313 SIC (0, 13, "bfin_dma@5", "di"),
1314 SIC (0, 14, "bfin_dma@6", "di"),
1315 SIC (0, 15, "bfin_dma@7", "di"),
1316 SIC (0, 16, "bfin_dma@8", "di"),
1317 SIC (0, 17, "bfin_gpio@5", "mask_a"),
1318 SIC (0, 18, "bfin_gpio@5", "mask_b"),
1319 SIC (0, 19, "bfin_gptimer@0", "stat"),
1320 SIC (0, 20, "bfin_gptimer@1", "stat"),
1321 SIC (0, 21, "bfin_gptimer@2", "stat"),
1322 SIC (0, 22, "bfin_gpio@6", "mask_a"),
1323 SIC (0, 23, "bfin_gpio@6", "mask_b"),
1324 SIC (0, 24, "bfin_twi@0", "stat"),
1325 /* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */
1326 SIC (0, 25, "bfin_dma@9", "di"),
1327 SIC (0, 26, "bfin_dma@10", "di"),
1328 SIC (0, 27, "bfin_dma@11", "di"),
1329 SIC (0, 28, "bfin_dma@12", "di"),
1330 /*SIC (0, 25, reserved),*/
1331 /*SIC (0, 26, reserved),*/
1332 /*SIC (0, 27, reserved),*/
1333 /*SIC (0, 28, reserved),*/
1334 SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */
1335 SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */
1336 SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */
1337 SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */
1338 SIC (0, 31, "bfin_wdog", "gpi"),
1339 };
1340
1341 static const struct bfin_model_data bfin_model_data[] =
1342 {
1343 #define P(n) \
1344 [MODEL_BF##n] = { \
1345 bf##n##_chipid, n, \
1346 bf##n##_mem , ARRAY_SIZE (bf##n##_mem ), \
1347 bf##n##_dev , ARRAY_SIZE (bf##n##_dev ), \
1348 bf##n##_dmac, ARRAY_SIZE (bf##n##_dmac), \
1349 bf##n##_port, ARRAY_SIZE (bf##n##_port), \
1350 },
1351 #include "proc_list.def"
1352 #undef P
1353 };
1354
1355 #define CORE_DEVICE(dev, DEV) \
1356 DEVICE (BFIN_COREMMR_##DEV##_BASE, BFIN_COREMMR_##DEV##_SIZE, "bfin_"#dev)
1357 static const struct bfin_dev_layout bfin_core_dev[] =
1358 {
1359 CORE_DEVICE (cec, CEC),
1360 CORE_DEVICE (ctimer, CTIMER),
1361 CORE_DEVICE (evt, EVT),
1362 CORE_DEVICE (jtag, JTAG),
1363 CORE_DEVICE (mmu, MMU),
1364 CORE_DEVICE (pfmon, PFMON),
1365 CORE_DEVICE (trace, TRACE),
1366 CORE_DEVICE (wp, WP),
1367 };
1368
1369 static void
1370 dv_bfin_hw_port_parse (SIM_DESC sd, const struct bfin_model_data *mdata,
1371 const char *dev)
1372 {
1373 size_t i;
1374 const char *sdev;
1375
1376 sdev = strchr (dev, '/');
1377 if (sdev)
1378 ++sdev;
1379 else
1380 sdev = dev;
1381
1382 for (i = 0; i < mdata->port_count; ++i)
1383 {
1384 const struct bfin_port_layout *port = &mdata->port[i];
1385
1386 /* There might be more than one mapping. */
1387 if (!strcmp (sdev, port->src))
1388 sim_hw_parse (sd, "/core/%s > %s %s /core/%s", dev,
1389 port->src_port, port->dst_port, port->dst);
1390 }
1391 }
1392
1393 #define dv_bfin_hw_parse(sd, dv, DV) \
1394 do { \
1395 bu32 base = BFIN_MMR_##DV##_BASE; \
1396 bu32 size = BFIN_MMR_##DV##_SIZE; \
1397 sim_hw_parse (sd, "/core/bfin_"#dv"/reg %#x %i", base, size); \
1398 sim_hw_parse (sd, "/core/bfin_"#dv"/type %i", mdata->model_num); \
1399 dv_bfin_hw_port_parse (sd, mdata, "bfin_"#dv); \
1400 } while (0)
1401
1402 static void
1403 bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu)
1404 {
1405 const MODEL *model = CPU_MODEL (cpu);
1406 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1407 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1408 int mnum = MODEL_NUM (model);
1409 unsigned i, j, dma_chan;
1410
1411 /* Map the core devices. */
1412 for (i = 0; i < ARRAY_SIZE (bfin_core_dev); ++i)
1413 {
1414 const struct bfin_dev_layout *dev = &bfin_core_dev[i];
1415 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
1416 }
1417 sim_hw_parse (sd, "/core/bfin_ctimer > ivtmr ivtmr /core/bfin_cec");
1418
1419 if (mnum == MODEL_BF000)
1420 goto done;
1421
1422 /* Map the system devices. */
1423 dv_bfin_hw_parse (sd, sic, SIC);
1424 for (i = 7; i < 16; ++i)
1425 sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i);
1426
1427 dv_bfin_hw_parse (sd, pll, PLL);
1428
1429 dma_chan = 0;
1430 for (i = 0; i < mdata->dmac_count; ++i)
1431 {
1432 const struct bfin_dmac_layout *dmac = &mdata->dmac[i];
1433
1434 sim_hw_parse (sd, "/core/bfin_dmac@%u/type %i", i, mdata->model_num);
1435
1436 /* Hook up the non-mdma channels. */
1437 for (j = 0; j < dmac->dma_count; ++j)
1438 {
1439 char dev[64];
1440
1441 sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, dma_chan);
1442 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev,
1443 dmac->base + j * BFIN_MMR_DMA_SIZE, BFIN_MMR_DMA_SIZE);
1444 dv_bfin_hw_port_parse (sd, mdata, dev);
1445
1446 ++dma_chan;
1447 }
1448
1449 /* Hook up the mdma channels -- assume every DMAC has 4. */
1450 for (j = 0; j < 4; ++j)
1451 {
1452 char dev[64];
1453
1454 sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, j + BFIN_DMAC_MDMA_BASE);
1455 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev,
1456 dmac->base + (j + dmac->dma_count) * BFIN_MMR_DMA_SIZE,
1457 BFIN_MMR_DMA_SIZE);
1458 dv_bfin_hw_port_parse (sd, mdata, dev);
1459 }
1460 }
1461
1462 for (i = 0; i < mdata->dev_count; ++i)
1463 {
1464 const struct bfin_dev_layout *dev = &mdata->dev[i];
1465
1466 if (dev->len)
1467 {
1468 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
1469 sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num);
1470 }
1471 else
1472 {
1473 sim_hw_parse (sd, "/core/%s", dev->dev);
1474 }
1475
1476 dv_bfin_hw_port_parse (sd, mdata, dev->dev);
1477 if (strchr (dev->dev, '/'))
1478 continue;
1479
1480 if (!strncmp (dev->dev, "bfin_uart", 9)
1481 || !strncmp (dev->dev, "bfin_emac", 9)
1482 || !strncmp (dev->dev, "bfin_sport", 10))
1483 {
1484 const char *sint = dev->dev + 5;
1485 sim_hw_parse (sd, "/core/%s > tx %s_tx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
1486 sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
1487 }
1488 else if (!strncmp (dev->dev, "bfin_wdog", 9))
1489 {
1490 sim_hw_parse (sd, "/core/%s > reset rst /core/bfin_cec", dev->dev);
1491 sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev);
1492 }
1493 }
1494
1495 done:
1496 /* Add any additional user board content. */
1497 if (board->hw_file)
1498 sim_do_commandf (sd, "hw-file %s", board->hw_file);
1499
1500 /* Trigger all the new devices' finish func. */
1501 hw_tree_finish (dv_get_device (cpu, "/"));
1502 }
1503
1504 #include "bfroms/all.h"
1505
1506 struct bfrom {
1507 bu32 addr, len, alias_len;
1508 int sirev;
1509 const char *buf;
1510 };
1511
1512 #define BFROMA(addr, rom, sirev, alias_len) \
1513 { addr, sizeof (bfrom_bf##rom##_0_##sirev), alias_len, \
1514 sirev, bfrom_bf##rom##_0_##sirev, }
1515 #define BFROM(rom, sirev, alias_len) BFROMA (0xef000000, rom, sirev, alias_len)
1516 #define BFROM_STUB { 0, 0, 0, 0, NULL, }
1517 static const struct bfrom bf50x_roms[] =
1518 {
1519 BFROM (50x, 0, 0x1000000),
1520 BFROM_STUB,
1521 };
1522 static const struct bfrom bf51x_roms[] =
1523 {
1524 BFROM (51x, 2, 0x1000000),
1525 BFROM (51x, 1, 0x1000000),
1526 BFROM (51x, 0, 0x1000000),
1527 BFROM_STUB,
1528 };
1529 static const struct bfrom bf526_roms[] =
1530 {
1531 BFROM (526, 2, 0x1000000),
1532 BFROM (526, 1, 0x1000000),
1533 BFROM (526, 0, 0x1000000),
1534 BFROM_STUB,
1535 };
1536 static const struct bfrom bf527_roms[] =
1537 {
1538 BFROM (527, 2, 0x1000000),
1539 BFROM (527, 1, 0x1000000),
1540 BFROM (527, 0, 0x1000000),
1541 BFROM_STUB,
1542 };
1543 static const struct bfrom bf533_roms[] =
1544 {
1545 BFROM (533, 6, 0x1000000),
1546 BFROM (533, 5, 0x1000000),
1547 BFROM (533, 4, 0x1000000),
1548 BFROM (533, 3, 0x1000000),
1549 BFROM (533, 2, 0x1000000),
1550 BFROM (533, 1, 0x1000000),
1551 BFROM_STUB,
1552 };
1553 static const struct bfrom bf537_roms[] =
1554 {
1555 BFROM (537, 3, 0x100000),
1556 BFROM (537, 2, 0x100000),
1557 BFROM (537, 1, 0x100000),
1558 BFROM (537, 0, 0x100000),
1559 BFROM_STUB,
1560 };
1561 static const struct bfrom bf538_roms[] =
1562 {
1563 BFROM (538, 5, 0x1000000),
1564 BFROM (538, 4, 0x1000000),
1565 BFROM (538, 3, 0x1000000),
1566 BFROM (538, 2, 0x1000000),
1567 BFROM (538, 1, 0x1000000),
1568 BFROM (538, 0, 0x1000000),
1569 BFROM_STUB,
1570 };
1571 static const struct bfrom bf54x_roms[] =
1572 {
1573 BFROM (54x, 4, 0),
1574 BFROM (54x, 2, 0),
1575 BFROM (54x, 1, 0),
1576 BFROM (54x, 0, 0),
1577 BFROMA (0xffa14000, 54x_l1, 4, 0),
1578 BFROMA (0xffa14000, 54x_l1, 2, 0),
1579 BFROMA (0xffa14000, 54x_l1, 1, 0),
1580 BFROMA (0xffa14000, 54x_l1, 0, 0),
1581 BFROM_STUB,
1582 };
1583 static const struct bfrom bf561_roms[] =
1584 {
1585 /* XXX: No idea what the actual wrap limit is here. */
1586 BFROM (561, 5, 0),
1587 BFROM_STUB,
1588 };
1589 static const struct bfrom bf59x_roms[] =
1590 {
1591 BFROM (59x, 1, 0x1000000),
1592 BFROM (59x, 0, 0x1000000),
1593 BFROMA (0xffa10000, 59x_l1, 1, 0),
1594 BFROM_STUB,
1595 };
1596
1597 static void
1598 bfin_model_map_bfrom (SIM_DESC sd, SIM_CPU *cpu)
1599 {
1600 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1601 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1602 int mnum = mdata->model_num;
1603 const struct bfrom *bfrom;
1604 unsigned int sirev;
1605
1606 if (mnum >= 500 && mnum <= 509)
1607 bfrom = bf50x_roms;
1608 else if (mnum >= 510 && mnum <= 519)
1609 bfrom = bf51x_roms;
1610 else if (mnum >= 520 && mnum <= 529)
1611 bfrom = (mnum & 1) ? bf527_roms : bf526_roms;
1612 else if (mnum >= 531 && mnum <= 533)
1613 bfrom = bf533_roms;
1614 else if (mnum == 535)
1615 return; /* Stub. */
1616 else if (mnum >= 534 && mnum <= 537)
1617 bfrom = bf537_roms;
1618 else if (mnum >= 538 && mnum <= 539)
1619 bfrom = bf538_roms;
1620 else if (mnum >= 540 && mnum <= 549)
1621 bfrom = bf54x_roms;
1622 else if (mnum == 561)
1623 bfrom = bf561_roms;
1624 else if (mnum >= 590 && mnum <= 599)
1625 bfrom = bf59x_roms;
1626 else
1627 return;
1628
1629 if (board->sirev_valid)
1630 sirev = board->sirev;
1631 else
1632 sirev = bfrom->sirev;
1633 while (bfrom->buf)
1634 {
1635 /* Map all the ranges for this model/sirev. */
1636 if (bfrom->sirev == sirev)
1637 sim_core_attach (sd, NULL, 0, access_read_exec, 0, bfrom->addr,
1638 bfrom->alias_len ? : bfrom->len, bfrom->len, NULL,
1639 (char *)bfrom->buf);
1640 ++bfrom;
1641 }
1642 }
1643
1644 void
1645 bfin_model_cpu_init (SIM_DESC sd, SIM_CPU *cpu)
1646 {
1647 const MODEL *model = CPU_MODEL (cpu);
1648 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1649 int mnum = MODEL_NUM (model);
1650 size_t idx;
1651
1652 /* These memory maps are supposed to be cpu-specific, but the common sim
1653 code does not yet allow that (2nd arg is "cpu" rather than "NULL". */
1654 sim_core_attach (sd, NULL, 0, access_read_write, 0, BFIN_L1_SRAM_SCRATCH,
1655 BFIN_L1_SRAM_SCRATCH_SIZE, 0, NULL, NULL);
1656
1657 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
1658 return;
1659
1660 if (mnum == MODEL_BF000)
1661 goto core_only;
1662
1663 /* Map in the on-chip memories (SRAMs). */
1664 mdata = &bfin_model_data[MODEL_NUM (model)];
1665 for (idx = 0; idx < mdata->mem_count; ++idx)
1666 {
1667 const struct bfin_memory_layout *mem = &mdata->mem[idx];
1668 sim_core_attach (sd, NULL, 0, mem->mask, 0, mem->addr,
1669 mem->len, 0, NULL, NULL);
1670 }
1671
1672 /* Map the on-chip ROMs. */
1673 bfin_model_map_bfrom (sd, cpu);
1674
1675 core_only:
1676 /* Finally, build up the tree for this cpu model. */
1677 bfin_model_hw_tree_init (sd, cpu);
1678 }
1679
1680 bu32
1681 bfin_model_get_chipid (SIM_DESC sd)
1682 {
1683 SIM_CPU *cpu = STATE_CPU (sd, 0);
1684 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1685 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1686 return
1687 (board->sirev << 28) |
1688 (mdata->chipid << 12) |
1689 (((0xE5 << 1) | 1) & 0xFF);
1690 }
1691
1692 bu32
1693 bfin_model_get_dspid (SIM_DESC sd)
1694 {
1695 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1696 return
1697 (0xE5 << 24) |
1698 (0x04 << 16) |
1699 (board->sirev);
1700 }
1701
1702 static void
1703 bfin_model_init (SIM_CPU *cpu)
1704 {
1705 CPU_MODEL_DATA (cpu) = (void *) &bfin_model_data[MODEL_NUM (CPU_MODEL (cpu))];
1706 }
1707
1708 static bu32
1709 bfin_extract_unsigned_integer (unsigned char *addr, int len)
1710 {
1711 bu32 retval;
1712 unsigned char * p;
1713 unsigned char * startaddr = (unsigned char *)addr;
1714 unsigned char * endaddr = startaddr + len;
1715
1716 retval = 0;
1717
1718 for (p = endaddr; p > startaddr;)
1719 retval = (retval << 8) | *--p;
1720
1721 return retval;
1722 }
1723
1724 static void
1725 bfin_store_unsigned_integer (unsigned char *addr, int len, bu32 val)
1726 {
1727 unsigned char *p;
1728 unsigned char *startaddr = addr;
1729 unsigned char *endaddr = startaddr + len;
1730
1731 for (p = startaddr; p < endaddr;)
1732 {
1733 *p++ = val & 0xff;
1734 val >>= 8;
1735 }
1736 }
1737
1738 static bu32 *
1739 bfin_get_reg (SIM_CPU *cpu, int rn)
1740 {
1741 switch (rn)
1742 {
1743 case SIM_BFIN_R0_REGNUM: return &DREG (0);
1744 case SIM_BFIN_R1_REGNUM: return &DREG (1);
1745 case SIM_BFIN_R2_REGNUM: return &DREG (2);
1746 case SIM_BFIN_R3_REGNUM: return &DREG (3);
1747 case SIM_BFIN_R4_REGNUM: return &DREG (4);
1748 case SIM_BFIN_R5_REGNUM: return &DREG (5);
1749 case SIM_BFIN_R6_REGNUM: return &DREG (6);
1750 case SIM_BFIN_R7_REGNUM: return &DREG (7);
1751 case SIM_BFIN_P0_REGNUM: return &PREG (0);
1752 case SIM_BFIN_P1_REGNUM: return &PREG (1);
1753 case SIM_BFIN_P2_REGNUM: return &PREG (2);
1754 case SIM_BFIN_P3_REGNUM: return &PREG (3);
1755 case SIM_BFIN_P4_REGNUM: return &PREG (4);
1756 case SIM_BFIN_P5_REGNUM: return &PREG (5);
1757 case SIM_BFIN_SP_REGNUM: return &SPREG;
1758 case SIM_BFIN_FP_REGNUM: return &FPREG;
1759 case SIM_BFIN_I0_REGNUM: return &IREG (0);
1760 case SIM_BFIN_I1_REGNUM: return &IREG (1);
1761 case SIM_BFIN_I2_REGNUM: return &IREG (2);
1762 case SIM_BFIN_I3_REGNUM: return &IREG (3);
1763 case SIM_BFIN_M0_REGNUM: return &MREG (0);
1764 case SIM_BFIN_M1_REGNUM: return &MREG (1);
1765 case SIM_BFIN_M2_REGNUM: return &MREG (2);
1766 case SIM_BFIN_M3_REGNUM: return &MREG (3);
1767 case SIM_BFIN_B0_REGNUM: return &BREG (0);
1768 case SIM_BFIN_B1_REGNUM: return &BREG (1);
1769 case SIM_BFIN_B2_REGNUM: return &BREG (2);
1770 case SIM_BFIN_B3_REGNUM: return &BREG (3);
1771 case SIM_BFIN_L0_REGNUM: return &LREG (0);
1772 case SIM_BFIN_L1_REGNUM: return &LREG (1);
1773 case SIM_BFIN_L2_REGNUM: return &LREG (2);
1774 case SIM_BFIN_L3_REGNUM: return &LREG (3);
1775 case SIM_BFIN_RETS_REGNUM: return &RETSREG;
1776 case SIM_BFIN_A0_DOT_X_REGNUM: return &AXREG (0);
1777 case SIM_BFIN_A0_DOT_W_REGNUM: return &AWREG (0);
1778 case SIM_BFIN_A1_DOT_X_REGNUM: return &AXREG (1);
1779 case SIM_BFIN_A1_DOT_W_REGNUM: return &AWREG (1);
1780 case SIM_BFIN_LC0_REGNUM: return &LCREG (0);
1781 case SIM_BFIN_LT0_REGNUM: return &LTREG (0);
1782 case SIM_BFIN_LB0_REGNUM: return &LBREG (0);
1783 case SIM_BFIN_LC1_REGNUM: return &LCREG (1);
1784 case SIM_BFIN_LT1_REGNUM: return &LTREG (1);
1785 case SIM_BFIN_LB1_REGNUM: return &LBREG (1);
1786 case SIM_BFIN_CYCLES_REGNUM: return &CYCLESREG;
1787 case SIM_BFIN_CYCLES2_REGNUM: return &CYCLES2REG;
1788 case SIM_BFIN_USP_REGNUM: return &USPREG;
1789 case SIM_BFIN_SEQSTAT_REGNUM: return &SEQSTATREG;
1790 case SIM_BFIN_SYSCFG_REGNUM: return &SYSCFGREG;
1791 case SIM_BFIN_RETI_REGNUM: return &RETIREG;
1792 case SIM_BFIN_RETX_REGNUM: return &RETXREG;
1793 case SIM_BFIN_RETN_REGNUM: return &RETNREG;
1794 case SIM_BFIN_RETE_REGNUM: return &RETEREG;
1795 case SIM_BFIN_PC_REGNUM: return &PCREG;
1796 default: return NULL;
1797 }
1798 }
1799
1800 static int
1801 bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1802 {
1803 bu32 value, *reg;
1804
1805 reg = bfin_get_reg (cpu, rn);
1806 if (reg)
1807 value = *reg;
1808 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1809 value = ASTAT;
1810 else if (rn == SIM_BFIN_CC_REGNUM)
1811 value = CCREG;
1812 else
1813 return 0; // will be an error in gdb
1814
1815 /* Handle our KSP/USP shadowing in SP. While in supervisor mode, we
1816 have the normal SP/USP behavior. User mode is tricky though. */
1817 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT
1818 && cec_is_user_mode (cpu))
1819 {
1820 if (rn == SIM_BFIN_SP_REGNUM)
1821 value = KSPREG;
1822 else if (rn == SIM_BFIN_USP_REGNUM)
1823 value = SPREG;
1824 }
1825
1826 bfin_store_unsigned_integer (buf, 4, value);
1827
1828 return -1; // disables size checking in gdb
1829 }
1830
1831 static int
1832 bfin_reg_store (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1833 {
1834 bu32 value, *reg;
1835
1836 value = bfin_extract_unsigned_integer (buf, 4);
1837 reg = bfin_get_reg (cpu, rn);
1838
1839 if (reg)
1840 /* XXX: Need register trace ? */
1841 *reg = value;
1842 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1843 SET_ASTAT (value);
1844 else if (rn == SIM_BFIN_CC_REGNUM)
1845 SET_CCREG (value);
1846 else
1847 return 0; // will be an error in gdb
1848
1849 return -1; // disables size checking in gdb
1850 }
1851
1852 static sim_cia
1853 bfin_pc_get (SIM_CPU *cpu)
1854 {
1855 return PCREG;
1856 }
1857
1858 static void
1859 bfin_pc_set (SIM_CPU *cpu, sim_cia newpc)
1860 {
1861 SET_PCREG (newpc);
1862 }
1863
1864 static const char *
1865 bfin_insn_name (SIM_CPU *cpu, int i)
1866 {
1867 static const char * const insn_name[] = {
1868 #define I(insn) #insn,
1869 #include "insn_list.def"
1870 #undef I
1871 };
1872 return insn_name[i];
1873 }
1874
1875 static void
1876 bfin_init_cpu (SIM_CPU *cpu)
1877 {
1878 CPU_REG_FETCH (cpu) = bfin_reg_fetch;
1879 CPU_REG_STORE (cpu) = bfin_reg_store;
1880 CPU_PC_FETCH (cpu) = bfin_pc_get;
1881 CPU_PC_STORE (cpu) = bfin_pc_set;
1882 CPU_MAX_INSNS (cpu) = BFIN_INSN_MAX;
1883 CPU_INSN_NAME (cpu) = bfin_insn_name;
1884 }
1885
1886 static void
1887 bfin_prepare_run (SIM_CPU *cpu)
1888 {
1889 }
1890
1891 static const MODEL bfin_models[] =
1892 {
1893 #define P(n) { "bf"#n, & bfin_mach, MODEL_BF##n, NULL, bfin_model_init },
1894 #include "proc_list.def"
1895 #undef P
1896 { 0, NULL, 0, NULL, NULL, }
1897 };
1898
1899 static const MACH_IMP_PROPERTIES bfin_imp_properties =
1900 {
1901 sizeof (SIM_CPU),
1902 0,
1903 };
1904
1905 static const MACH bfin_mach =
1906 {
1907 "bfin", "bfin", MACH_BFIN,
1908 32, 32, & bfin_models[0], & bfin_imp_properties,
1909 bfin_init_cpu,
1910 bfin_prepare_run
1911 };
1912
1913 const MACH *sim_machs[] =
1914 {
1915 & bfin_mach,
1916 NULL
1917 };
1918 \f
1919 /* Device option parsing. */
1920
1921 static DECLARE_OPTION_HANDLER (bfin_mach_option_handler);
1922
1923 enum {
1924 OPTION_MACH_SIREV = OPTION_START,
1925 OPTION_MACH_HW_BOARD_FILE,
1926 };
1927
1928 const OPTION bfin_mach_options[] =
1929 {
1930 { {"sirev", required_argument, NULL, OPTION_MACH_SIREV },
1931 '\0', "NUMBER", "Set CPU silicon revision",
1932 bfin_mach_option_handler, NULL },
1933
1934 { {"hw-board-file", required_argument, NULL, OPTION_MACH_HW_BOARD_FILE },
1935 '\0', "FILE", "Add the supplemental devices listed in the file",
1936 bfin_mach_option_handler, NULL },
1937
1938 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
1939 };
1940
1941 static SIM_RC
1942 bfin_mach_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
1943 char *arg, int is_command)
1944 {
1945 struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1946
1947 switch (opt)
1948 {
1949 case OPTION_MACH_SIREV:
1950 board->sirev_valid = 1;
1951 /* Accept (and throw away) a leading "0." in the version. */
1952 if (!strncmp (arg, "0.", 2))
1953 arg += 2;
1954 board->sirev = atoi (arg);
1955 if (board->sirev > 0xf)
1956 {
1957 sim_io_eprintf (sd, "sirev '%s' needs to fit into 4 bits\n", arg);
1958 return SIM_RC_FAIL;
1959 }
1960 return SIM_RC_OK;
1961
1962 case OPTION_MACH_HW_BOARD_FILE:
1963 board->hw_file = xstrdup (arg);
1964 return SIM_RC_OK;
1965
1966 default:
1967 sim_io_eprintf (sd, "Unknown Blackfin option %d\n", opt);
1968 return SIM_RC_FAIL;
1969 }
1970 }
GDB Binutils - Deliverables
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