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sim: bfin: add GPIO device simulation
[deliverable/binutils-gdb.git] / sim / bfin / machs.c
1 /* Simulator for Analog Devices Blackfin processors.
2
3 Copyright (C) 2005-2011 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22
23 #include "sim-main.h"
24 #include "gdb/sim-bfin.h"
25 #include "bfd.h"
26
27 #include "sim-hw.h"
28 #include "devices.h"
29 #include "dv-bfin_cec.h"
30 #include "dv-bfin_ctimer.h"
31 #include "dv-bfin_dma.h"
32 #include "dv-bfin_dmac.h"
33 #include "dv-bfin_ebiu_amc.h"
34 #include "dv-bfin_ebiu_ddrc.h"
35 #include "dv-bfin_ebiu_sdc.h"
36 #include "dv-bfin_emac.h"
37 #include "dv-bfin_eppi.h"
38 #include "dv-bfin_evt.h"
39 #include "dv-bfin_gpio.h"
40 #include "dv-bfin_gptimer.h"
41 #include "dv-bfin_jtag.h"
42 #include "dv-bfin_mmu.h"
43 #include "dv-bfin_nfc.h"
44 #include "dv-bfin_otp.h"
45 #include "dv-bfin_pll.h"
46 #include "dv-bfin_ppi.h"
47 #include "dv-bfin_rtc.h"
48 #include "dv-bfin_sic.h"
49 #include "dv-bfin_spi.h"
50 #include "dv-bfin_trace.h"
51 #include "dv-bfin_twi.h"
52 #include "dv-bfin_uart.h"
53 #include "dv-bfin_uart2.h"
54 #include "dv-bfin_wdog.h"
55 #include "dv-bfin_wp.h"
56
57 static const MACH bfin_mach;
58
59 struct bfin_memory_layout {
60 address_word addr, len;
61 unsigned mask; /* see mapmask in sim_core_attach() */
62 };
63 struct bfin_dev_layout {
64 address_word base, len;
65 unsigned int dmac;
66 const char *dev;
67 };
68 struct bfin_dmac_layout {
69 address_word base;
70 unsigned int dma_count;
71 };
72 struct bfin_model_data {
73 bu32 chipid;
74 int model_num;
75 const struct bfin_memory_layout *mem;
76 size_t mem_count;
77 const struct bfin_dev_layout *dev;
78 size_t dev_count;
79 const struct bfin_dmac_layout *dmac;
80 size_t dmac_count;
81 };
82
83 #define LAYOUT(_addr, _len, _mask) { .addr = _addr, .len = _len, .mask = access_##_mask, }
84 #define _DEVICE(_base, _len, _dev, _dmac) { .base = _base, .len = _len, .dev = _dev, .dmac = _dmac, }
85 #define DEVICE(_base, _len, _dev) _DEVICE(_base, _len, _dev, 0)
86
87 /* [1] Common sim code can't model exec-only memory.
88 http://sourceware.org/ml/gdb/2010-02/msg00047.html */
89
90 #define bf000_chipid 0
91 static const struct bfin_memory_layout bf000_mem[] = {};
92 static const struct bfin_dev_layout bf000_dev[] = {};
93 static const struct bfin_dmac_layout bf000_dmac[] = {};
94
95 #define bf50x_chipid 0x2800
96 #define bf504_chipid bf50x_chipid
97 #define bf506_chipid bf50x_chipid
98 static const struct bfin_memory_layout bf50x_mem[] =
99 {
100 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
101 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
102 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
103 LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */
104 LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */
105 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
106 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
107 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
108 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst Cache [1] */
109 };
110 #define bf504_mem bf50x_mem
111 #define bf506_mem bf50x_mem
112 static const struct bfin_dev_layout bf50x_dev[] =
113 {
114 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
115 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
116 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
117 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
118 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
119 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
120 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
121 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
122 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
123 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
124 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
125 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
126 DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
127 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
128 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
129 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
130 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
131 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
132 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
133 };
134 #define bf504_dev bf50x_dev
135 #define bf506_dev bf50x_dev
136 static const struct bfin_dmac_layout bf50x_dmac[] =
137 {
138 { BFIN_MMR_DMAC0_BASE, 12, },
139 };
140 #define bf504_dmac bf50x_dmac
141 #define bf506_dmac bf50x_dmac
142
143 #define bf51x_chipid 0x27e8
144 #define bf512_chipid bf51x_chipid
145 #define bf514_chipid bf51x_chipid
146 #define bf516_chipid bf51x_chipid
147 #define bf518_chipid bf51x_chipid
148 static const struct bfin_memory_layout bf51x_mem[] =
149 {
150 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
151 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
152 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
153 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
154 LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */
155 LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */
156 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
157 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
158 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
159 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
160 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
161 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
162 };
163 #define bf512_mem bf51x_mem
164 #define bf514_mem bf51x_mem
165 #define bf516_mem bf51x_mem
166 #define bf518_mem bf51x_mem
167 static const struct bfin_dev_layout bf512_dev[] =
168 {
169 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
170 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
171 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
172 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
173 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
174 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
175 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
176 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
177 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
178 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
179 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
180 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
181 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
182 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
183 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
184 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
185 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
186 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
187 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
188 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
189 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
190 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
191 };
192 #define bf514_dev bf512_dev
193 static const struct bfin_dev_layout bf516_dev[] =
194 {
195 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
196 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
197 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
198 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
199 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
200 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
201 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
202 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
203 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
204 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
205 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
206 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
207 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
208 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
209 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
210 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
211 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
212 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
213 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
214 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
215 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
216 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
217 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
218 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
219 };
220 #define bf518_dev bf516_dev
221 #define bf512_dmac bf50x_dmac
222 #define bf514_dmac bf50x_dmac
223 #define bf516_dmac bf50x_dmac
224 #define bf518_dmac bf50x_dmac
225
226 #define bf522_chipid 0x27e4
227 #define bf523_chipid 0x27e0
228 #define bf524_chipid bf522_chipid
229 #define bf525_chipid bf523_chipid
230 #define bf526_chipid bf522_chipid
231 #define bf527_chipid bf523_chipid
232 static const struct bfin_memory_layout bf52x_mem[] =
233 {
234 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
235 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
236 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
237 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
238 LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */
239 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
240 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
241 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
242 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
243 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
244 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
245 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
246 };
247 #define bf522_mem bf52x_mem
248 #define bf523_mem bf52x_mem
249 #define bf524_mem bf52x_mem
250 #define bf525_mem bf52x_mem
251 #define bf526_mem bf52x_mem
252 #define bf527_mem bf52x_mem
253 static const struct bfin_dev_layout bf522_dev[] =
254 {
255 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
256 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
257 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
258 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
259 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
260 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
261 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
262 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
263 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
264 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
265 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
266 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
267 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
268 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
269 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
270 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
271 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
272 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
273 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
274 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
275 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
276 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
277 };
278 #define bf523_dev bf522_dev
279 #define bf524_dev bf522_dev
280 #define bf525_dev bf522_dev
281 static const struct bfin_dev_layout bf526_dev[] =
282 {
283 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
284 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
285 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
286 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
287 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
288 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
289 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
290 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
291 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
292 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
293 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
294 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
295 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
296 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
297 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
298 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
299 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
300 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
301 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
302 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
303 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
304 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
305 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
306 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
307 };
308 #define bf527_dev bf526_dev
309 #define bf522_dmac bf50x_dmac
310 #define bf523_dmac bf50x_dmac
311 #define bf524_dmac bf50x_dmac
312 #define bf525_dmac bf50x_dmac
313 #define bf526_dmac bf50x_dmac
314 #define bf527_dmac bf50x_dmac
315
316 #define bf531_chipid 0x27a5
317 #define bf532_chipid bf531_chipid
318 #define bf533_chipid bf531_chipid
319 static const struct bfin_memory_layout bf531_mem[] =
320 {
321 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
322 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
323 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
324 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
325 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
326 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
327 };
328 static const struct bfin_memory_layout bf532_mem[] =
329 {
330 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
331 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
332 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
333 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
334 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
335 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
336 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
337 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
338 };
339 static const struct bfin_memory_layout bf533_mem[] =
340 {
341 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
342 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
343 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
344 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
345 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
346 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
347 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
348 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
349 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
350 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
351 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
352 };
353 static const struct bfin_dev_layout bf533_dev[] =
354 {
355 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
356 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
357 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
358 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
359 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
360 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
361 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
362 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
363 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
364 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
365 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
366 };
367 #define bf531_dev bf533_dev
368 #define bf532_dev bf533_dev
369 static const struct bfin_dmac_layout bf533_dmac[] =
370 {
371 { BFIN_MMR_DMAC0_BASE, 8, },
372 };
373 #define bf531_dmac bf533_dmac
374 #define bf532_dmac bf533_dmac
375
376 #define bf534_chipid 0x27c6
377 #define bf536_chipid 0x27c8
378 #define bf537_chipid bf536_chipid
379 static const struct bfin_memory_layout bf534_mem[] =
380 {
381 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
382 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
383 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
384 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
385 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
386 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
387 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
388 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
389 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
390 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
391 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
392 };
393 static const struct bfin_memory_layout bf536_mem[] =
394 {
395 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
396 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
397 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
398 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
399 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
400 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
401 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
402 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
403 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
404 };
405 static const struct bfin_memory_layout bf537_mem[] =
406 {
407 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
408 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
409 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
410 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
411 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
412 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
413 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
414 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
415 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
416 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
417 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
418 };
419 static const struct bfin_dev_layout bf534_dev[] =
420 {
421 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
422 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
423 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
424 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
425 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
426 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
427 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
428 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
429 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
430 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
431 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
432 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
433 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
434 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
435 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
436 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
437 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
438 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
439 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
440 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
441 };
442 static const struct bfin_dev_layout bf537_dev[] =
443 {
444 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
445 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
446 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
447 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
448 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
449 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
450 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
451 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
452 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
453 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
454 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
455 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
456 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
457 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
458 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
459 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
460 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
461 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
462 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
463 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
464 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
465 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
466 };
467 #define bf536_dev bf537_dev
468 #define bf534_dmac bf50x_dmac
469 #define bf536_dmac bf50x_dmac
470 #define bf537_dmac bf50x_dmac
471
472 #define bf538_chipid 0x27c4
473 #define bf539_chipid bf538_chipid
474 static const struct bfin_memory_layout bf538_mem[] =
475 {
476 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
477 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
478 LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */
479 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
480 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
481 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
482 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
483 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
484 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
485 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
486 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
487 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
488 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
489 };
490 #define bf539_mem bf538_mem
491 static const struct bfin_dev_layout bf538_dev[] =
492 {
493 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
494 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
495 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
496 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
497 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
498 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
499 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
500 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
501 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
502 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
503 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
504 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
505 _DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1),
506 _DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1),
507 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
508 _DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1", 1),
509 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
510 };
511 #define bf539_dev bf538_dev
512 static const struct bfin_dmac_layout bf538_dmac[] =
513 {
514 { BFIN_MMR_DMAC0_BASE, 8, },
515 { BFIN_MMR_DMAC1_BASE, 12, },
516 };
517 #define bf539_dmac bf538_dmac
518
519 #define bf54x_chipid 0x27de
520 #define bf542_chipid bf54x_chipid
521 #define bf544_chipid bf54x_chipid
522 #define bf547_chipid bf54x_chipid
523 #define bf548_chipid bf54x_chipid
524 #define bf549_chipid bf54x_chipid
525 static const struct bfin_memory_layout bf54x_mem[] =
526 {
527 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */
528 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
529 LAYOUT (0xFFC01400, 0x200, read_write), /* PORT/GPIO stub */
530 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
531 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
532 LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */
533 LAYOUT (0xFFC03900, 0x100, read_write), /* RSI stub */
534 LAYOUT (0xFFC03C00, 0x500, read_write), /* MUSB stub */
535 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
536 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
537 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
538 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
539 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
540 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
541 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
542 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
543 };
544 #define bf542_mem bf54x_mem
545 #define bf544_mem bf54x_mem
546 #define bf547_mem bf54x_mem
547 #define bf548_mem bf54x_mem
548 #define bf549_mem bf54x_mem
549 static const struct bfin_dev_layout bf542_dev[] =
550 {
551 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
552 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
553 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
554 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
555 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
556 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
557 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
558 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
559 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
560 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
561 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
562 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
563 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
564 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
565 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
566 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
567 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
568 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
569 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
570 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
571 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
572 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
573 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
574 };
575 static const struct bfin_dev_layout bf544_dev[] =
576 {
577 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
578 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
579 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
580 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
581 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
582 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
583 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
584 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
585 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
586 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
587 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
588 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
589 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
590 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
591 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
592 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
593 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
594 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
595 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
596 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
597 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
598 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
599 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
600 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
601 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
602 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
603 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
604 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
605 };
606 static const struct bfin_dev_layout bf547_dev[] =
607 {
608 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
609 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
610 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
611 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
612 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
613 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
614 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
615 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
616 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
617 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
618 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
619 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
620 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
621 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
622 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
623 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
624 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
625 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
626 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
627 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
628 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
629 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
630 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
631 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
632 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
633 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
634 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
635 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
636 };
637 #define bf548_dev bf547_dev
638 #define bf549_dev bf547_dev
639 static const struct bfin_dmac_layout bf54x_dmac[] =
640 {
641 { BFIN_MMR_DMAC0_BASE, 12, },
642 { BFIN_MMR_DMAC1_BASE, 12, },
643 };
644 #define bf542_dmac bf54x_dmac
645 #define bf544_dmac bf54x_dmac
646 #define bf547_dmac bf54x_dmac
647 #define bf548_dmac bf54x_dmac
648 #define bf549_dmac bf54x_dmac
649
650 /* This is only Core A of course ... */
651 #define bf561_chipid 0x27bb
652 static const struct bfin_memory_layout bf561_mem[] =
653 {
654 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
655 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
656 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
657 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
658 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
659 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
660 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
661 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
662 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
663 };
664 static const struct bfin_dev_layout bf561_dev[] =
665 {
666 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
667 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
668 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
669 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
670 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
671 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
672 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
673 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
674 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
675 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
676 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
677 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
678 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
679 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
680 _DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1),
681 DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"),
682 _DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1),
683 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
684 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
685 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
686 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
687 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"),
688 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
689 };
690 static const struct bfin_dmac_layout bf561_dmac[] =
691 {
692 { BFIN_MMR_DMAC0_BASE, 12, },
693 { BFIN_MMR_DMAC1_BASE, 12, },
694 /* XXX: IMDMA: { 0xFFC01800, 4, }, */
695 };
696
697 #define bf592_chipid 0x20cb
698 static const struct bfin_memory_layout bf592_mem[] =
699 {
700 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
701 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
702 LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */
703 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
704 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */
705 };
706 static const struct bfin_dev_layout bf592_dev[] =
707 {
708 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
709 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
710 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
711 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
712 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
713 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
714 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
715 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
716 DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
717 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
718 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
719 };
720 static const struct bfin_dmac_layout bf592_dmac[] =
721 {
722 /* XXX: there are only 9 channels, but mdma code below assumes that they
723 start right after the dma channels ... */
724 { BFIN_MMR_DMAC0_BASE, 12, },
725 };
726
727 static const struct bfin_model_data bfin_model_data[] =
728 {
729 #define P(n) \
730 [MODEL_BF##n] = { \
731 bf##n##_chipid, n, \
732 bf##n##_mem , ARRAY_SIZE (bf##n##_mem ), \
733 bf##n##_dev , ARRAY_SIZE (bf##n##_dev ), \
734 bf##n##_dmac, ARRAY_SIZE (bf##n##_dmac), \
735 },
736 #include "proc_list.def"
737 #undef P
738 };
739
740 #define CORE_DEVICE(dev, DEV) \
741 DEVICE (BFIN_COREMMR_##DEV##_BASE, BFIN_COREMMR_##DEV##_SIZE, "bfin_"#dev)
742 static const struct bfin_dev_layout bfin_core_dev[] =
743 {
744 CORE_DEVICE (cec, CEC),
745 CORE_DEVICE (ctimer, CTIMER),
746 CORE_DEVICE (evt, EVT),
747 CORE_DEVICE (jtag, JTAG),
748 CORE_DEVICE (mmu, MMU),
749 CORE_DEVICE (trace, TRACE),
750 CORE_DEVICE (wp, WP),
751 };
752
753 #define dv_bfin_hw_parse(sd, dv, DV) \
754 do { \
755 bu32 base = BFIN_MMR_##DV##_BASE; \
756 bu32 size = BFIN_MMR_##DV##_SIZE; \
757 sim_hw_parse (sd, "/core/bfin_"#dv"/reg %#x %i", base, size); \
758 sim_hw_parse (sd, "/core/bfin_"#dv"/type %i", mdata->model_num); \
759 } while (0)
760
761 static void
762 bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu)
763 {
764 const MODEL *model = CPU_MODEL (cpu);
765 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
766 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
767 int mnum = MODEL_NUM (model);
768 unsigned i, j, dma_chan;
769
770 /* Map the core devices. */
771 for (i = 0; i < ARRAY_SIZE (bfin_core_dev); ++i)
772 {
773 const struct bfin_dev_layout *dev = &bfin_core_dev[i];
774 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
775 }
776 sim_hw_parse (sd, "/core/bfin_ctimer > ivtmr ivtmr /core/bfin_cec");
777
778 if (mnum == MODEL_BF000)
779 goto done;
780
781 /* Map the system devices. */
782 dv_bfin_hw_parse (sd, sic, SIC);
783 sim_hw_parse (sd, "/core/bfin_sic/type %i", mdata->model_num);
784 for (i = 7; i < 16; ++i)
785 sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i);
786
787 dv_bfin_hw_parse (sd, pll, PLL);
788 sim_hw_parse (sd, "/core/bfin_pll > pll pll /core/bfin_sic");
789
790 dma_chan = 0;
791 for (i = 0; i < mdata->dmac_count; ++i)
792 {
793 const struct bfin_dmac_layout *dmac = &mdata->dmac[i];
794
795 sim_hw_parse (sd, "/core/bfin_dmac@%u/type %i", i, mdata->model_num);
796
797 /* Hook up the non-mdma channels. */
798 for (j = 0; j < dmac->dma_count; ++j)
799 {
800 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u/reg %#x %i", i,
801 dma_chan, dmac->base + j * BFIN_MMR_DMA_SIZE,
802 BFIN_MMR_DMA_SIZE);
803
804 /* Could route these into the bfin_dmac and let that
805 forward it to the SIC, but not much value. */
806 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u > di dma@%u /core/bfin_sic",
807 i, dma_chan, dma_chan);
808
809 ++dma_chan;
810 }
811
812 /* Hook up the mdma channels -- assume every DMAC has 4. */
813 for (j = 0; j < 4; ++j)
814 {
815 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u/reg %#x %i",
816 i, j + BFIN_DMAC_MDMA_BASE,
817 dmac->base + (j + dmac->dma_count) * BFIN_MMR_DMA_SIZE,
818 BFIN_MMR_DMA_SIZE);
819 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u > di mdma@%u /core/bfin_sic",
820 i, j + BFIN_DMAC_MDMA_BASE, (2 * i) + (j / 2));
821 }
822 }
823
824 for (i = 0; i < mdata->dev_count; ++i)
825 {
826 const struct bfin_dev_layout *dev = &mdata->dev[i];
827 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
828 sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num);
829 if (strchr (dev->dev, '/'))
830 continue;
831 if (!strncmp (dev->dev, "bfin_uart", 9)
832 || !strncmp (dev->dev, "bfin_emac", 9)
833 || !strncmp (dev->dev, "bfin_sport", 10))
834 {
835 const char *sint = dev->dev + 5;
836 sim_hw_parse (sd, "/core/%s > tx %s_tx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
837 sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
838 sim_hw_parse (sd, "/core/%s > stat %s_stat /core/bfin_sic", dev->dev, sint);
839 }
840 else if (!strncmp (dev->dev, "bfin_gptimer", 12)
841 || !strncmp (dev->dev, "bfin_ppi", 8)
842 || !strncmp (dev->dev, "bfin_spi", 8)
843 || !strncmp (dev->dev, "bfin_twi", 8))
844 {
845 const char *sint = dev->dev + 5;
846 sim_hw_parse (sd, "/core/%s > stat %s /core/bfin_sic", dev->dev, sint);
847 }
848 else if (!strncmp (dev->dev, "bfin_rtc", 8))
849 {
850 const char *sint = dev->dev + 5;
851 sim_hw_parse (sd, "/core/%s > %s %s /core/bfin_sic", dev->dev, sint, sint);
852 }
853 else if (!strncmp (dev->dev, "bfin_wdog", 9))
854 {
855 sim_hw_parse (sd, "/core/%s > reset rst /core/bfin_cec", dev->dev);
856 sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev);
857 sim_hw_parse (sd, "/core/%s > gpi wdog /core/bfin_sic", dev->dev);
858 }
859 else if (!strncmp (dev->dev, "bfin_gpio", 9))
860 {
861 sim_hw_parse (sd, "/core/%s > mask_a port%c_irq_a /core/bfin_sic",
862 dev->dev, dev->dev[10]);
863 sim_hw_parse (sd, "/core/%s > mask_b port%c_irq_b /core/bfin_sic",
864 dev->dev, dev->dev[10]);
865 }
866 }
867
868 done:
869 /* Add any additional user board content. */
870 if (board->hw_file)
871 sim_do_commandf (sd, "hw-file %s", board->hw_file);
872
873 /* Trigger all the new devices' finish func. */
874 hw_tree_finish (dv_get_device (cpu, "/"));
875 }
876
877 #include "bfroms/all.h"
878
879 struct bfrom {
880 bu32 addr, len, alias_len;
881 int sirev;
882 const char *buf;
883 };
884
885 #define BFROMA(addr, rom, sirev, alias_len) \
886 { addr, sizeof (bfrom_bf##rom##_0_##sirev), alias_len, \
887 sirev, bfrom_bf##rom##_0_##sirev, }
888 #define BFROM(rom, sirev, alias_len) BFROMA (0xef000000, rom, sirev, alias_len)
889 #define BFROM_STUB { 0, 0, 0, 0, NULL, }
890 static const struct bfrom bf50x_roms[] =
891 {
892 BFROM (50x, 0, 0x1000000),
893 BFROM_STUB,
894 };
895 static const struct bfrom bf51x_roms[] =
896 {
897 BFROM (51x, 2, 0x1000000),
898 BFROM (51x, 1, 0x1000000),
899 BFROM (51x, 0, 0x1000000),
900 BFROM_STUB,
901 };
902 static const struct bfrom bf526_roms[] =
903 {
904 BFROM (526, 1, 0x1000000),
905 BFROM (526, 0, 0x1000000),
906 BFROM_STUB,
907 };
908 static const struct bfrom bf527_roms[] =
909 {
910 BFROM (527, 2, 0x1000000),
911 BFROM (527, 1, 0x1000000),
912 BFROM (527, 0, 0x1000000),
913 BFROM_STUB,
914 };
915 static const struct bfrom bf533_roms[] =
916 {
917 BFROM (533, 6, 0x1000000),
918 BFROM (533, 5, 0x1000000),
919 BFROM (533, 4, 0x1000000),
920 BFROM (533, 3, 0x1000000),
921 BFROM (533, 2, 0x1000000),
922 BFROM (533, 1, 0x1000000),
923 BFROM_STUB,
924 };
925 static const struct bfrom bf537_roms[] =
926 {
927 BFROM (537, 3, 0x100000),
928 BFROM (537, 2, 0x100000),
929 BFROM (537, 1, 0x100000),
930 BFROM (537, 0, 0x100000),
931 BFROM_STUB,
932 };
933 static const struct bfrom bf538_roms[] =
934 {
935 BFROM (538, 5, 0x1000000),
936 BFROM (538, 4, 0x1000000),
937 BFROM (538, 3, 0x1000000),
938 BFROM (538, 2, 0x1000000),
939 BFROM (538, 1, 0x1000000),
940 BFROM (538, 0, 0x1000000),
941 BFROM_STUB,
942 };
943 static const struct bfrom bf54x_roms[] =
944 {
945 BFROM (54x, 2, 0),
946 BFROM (54x, 1, 0),
947 BFROM (54x, 0, 0),
948 BFROMA (0xffa14000, 54x_l1, 2, 0),
949 BFROMA (0xffa14000, 54x_l1, 1, 0),
950 BFROMA (0xffa14000, 54x_l1, 0, 0),
951 BFROM_STUB,
952 };
953 static const struct bfrom bf561_roms[] =
954 {
955 /* XXX: No idea what the actual wrap limit is here. */
956 BFROM (561, 5, 0),
957 BFROM_STUB,
958 };
959 static const struct bfrom bf59x_roms[] =
960 {
961 BFROM (59x, 1, 0x1000000),
962 BFROM (59x, 0, 0x1000000),
963 BFROMA (0xffa10000, 59x_l1, 1, 0),
964 BFROM_STUB,
965 };
966
967 static void
968 bfin_model_map_bfrom (SIM_DESC sd, SIM_CPU *cpu)
969 {
970 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
971 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
972 int mnum = mdata->model_num;
973 const struct bfrom *bfrom;
974 unsigned int sirev;
975
976 if (mnum >= 500 && mnum <= 509)
977 bfrom = bf50x_roms;
978 else if (mnum >= 510 && mnum <= 519)
979 bfrom = bf51x_roms;
980 else if (mnum >= 520 && mnum <= 529)
981 bfrom = (mnum & 1) ? bf527_roms : bf526_roms;
982 else if (mnum >= 531 && mnum <= 533)
983 bfrom = bf533_roms;
984 else if (mnum == 535)
985 /* Stub. */;
986 else if (mnum >= 534 && mnum <= 537)
987 bfrom = bf537_roms;
988 else if (mnum >= 538 && mnum <= 539)
989 bfrom = bf538_roms;
990 else if (mnum >= 540 && mnum <= 549)
991 bfrom = bf54x_roms;
992 else if (mnum == 561)
993 bfrom = bf561_roms;
994 else if (mnum >= 590 && mnum <= 599)
995 bfrom = bf59x_roms;
996 else
997 return;
998
999 if (board->sirev_valid)
1000 sirev = board->sirev;
1001 else
1002 sirev = bfrom->sirev;
1003 while (bfrom->buf)
1004 {
1005 /* Map all the ranges for this model/sirev. */
1006 if (bfrom->sirev == sirev)
1007 sim_core_attach (sd, NULL, 0, access_read_exec, 0, bfrom->addr,
1008 bfrom->alias_len ? : bfrom->len, bfrom->len, NULL,
1009 (char *)bfrom->buf);
1010 ++bfrom;
1011 }
1012 }
1013
1014 void
1015 bfin_model_cpu_init (SIM_DESC sd, SIM_CPU *cpu)
1016 {
1017 const MODEL *model = CPU_MODEL (cpu);
1018 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1019 int mnum = MODEL_NUM (model);
1020 size_t idx;
1021
1022 /* These memory maps are supposed to be cpu-specific, but the common sim
1023 code does not yet allow that (2nd arg is "cpu" rather than "NULL". */
1024 sim_core_attach (sd, NULL, 0, access_read_write, 0, BFIN_L1_SRAM_SCRATCH,
1025 BFIN_L1_SRAM_SCRATCH_SIZE, 0, NULL, NULL);
1026
1027 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
1028 return;
1029
1030 if (mnum == MODEL_BF000)
1031 goto core_only;
1032
1033 /* Map in the on-chip memories (SRAMs). */
1034 mdata = &bfin_model_data[MODEL_NUM (model)];
1035 for (idx = 0; idx < mdata->mem_count; ++idx)
1036 {
1037 const struct bfin_memory_layout *mem = &mdata->mem[idx];
1038 sim_core_attach (sd, NULL, 0, mem->mask, 0, mem->addr,
1039 mem->len, 0, NULL, NULL);
1040 }
1041
1042 /* Map the on-chip ROMs. */
1043 bfin_model_map_bfrom (sd, cpu);
1044
1045 core_only:
1046 /* Finally, build up the tree for this cpu model. */
1047 bfin_model_hw_tree_init (sd, cpu);
1048 }
1049
1050 bu32
1051 bfin_model_get_chipid (SIM_DESC sd)
1052 {
1053 SIM_CPU *cpu = STATE_CPU (sd, 0);
1054 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1055 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1056 return
1057 (board->sirev << 28) |
1058 (mdata->chipid << 12) |
1059 (((0xE5 << 1) | 1) & 0xFF);
1060 }
1061
1062 bu32
1063 bfin_model_get_dspid (SIM_DESC sd)
1064 {
1065 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1066 return
1067 (0xE5 << 24) |
1068 (0x04 << 16) |
1069 (board->sirev);
1070 }
1071
1072 static void
1073 bfin_model_init (SIM_CPU *cpu)
1074 {
1075 CPU_MODEL_DATA (cpu) = (void *) &bfin_model_data[MODEL_NUM (CPU_MODEL (cpu))];
1076 }
1077
1078 static bu32
1079 bfin_extract_unsigned_integer (unsigned char *addr, int len)
1080 {
1081 bu32 retval;
1082 unsigned char * p;
1083 unsigned char * startaddr = (unsigned char *)addr;
1084 unsigned char * endaddr = startaddr + len;
1085
1086 retval = 0;
1087
1088 for (p = endaddr; p > startaddr;)
1089 retval = (retval << 8) | *--p;
1090
1091 return retval;
1092 }
1093
1094 static void
1095 bfin_store_unsigned_integer (unsigned char *addr, int len, bu32 val)
1096 {
1097 unsigned char *p;
1098 unsigned char *startaddr = addr;
1099 unsigned char *endaddr = startaddr + len;
1100
1101 for (p = startaddr; p < endaddr;)
1102 {
1103 *p++ = val & 0xff;
1104 val >>= 8;
1105 }
1106 }
1107
1108 static bu32 *
1109 bfin_get_reg (SIM_CPU *cpu, int rn)
1110 {
1111 switch (rn)
1112 {
1113 case SIM_BFIN_R0_REGNUM: return &DREG (0);
1114 case SIM_BFIN_R1_REGNUM: return &DREG (1);
1115 case SIM_BFIN_R2_REGNUM: return &DREG (2);
1116 case SIM_BFIN_R3_REGNUM: return &DREG (3);
1117 case SIM_BFIN_R4_REGNUM: return &DREG (4);
1118 case SIM_BFIN_R5_REGNUM: return &DREG (5);
1119 case SIM_BFIN_R6_REGNUM: return &DREG (6);
1120 case SIM_BFIN_R7_REGNUM: return &DREG (7);
1121 case SIM_BFIN_P0_REGNUM: return &PREG (0);
1122 case SIM_BFIN_P1_REGNUM: return &PREG (1);
1123 case SIM_BFIN_P2_REGNUM: return &PREG (2);
1124 case SIM_BFIN_P3_REGNUM: return &PREG (3);
1125 case SIM_BFIN_P4_REGNUM: return &PREG (4);
1126 case SIM_BFIN_P5_REGNUM: return &PREG (5);
1127 case SIM_BFIN_SP_REGNUM: return &SPREG;
1128 case SIM_BFIN_FP_REGNUM: return &FPREG;
1129 case SIM_BFIN_I0_REGNUM: return &IREG (0);
1130 case SIM_BFIN_I1_REGNUM: return &IREG (1);
1131 case SIM_BFIN_I2_REGNUM: return &IREG (2);
1132 case SIM_BFIN_I3_REGNUM: return &IREG (3);
1133 case SIM_BFIN_M0_REGNUM: return &MREG (0);
1134 case SIM_BFIN_M1_REGNUM: return &MREG (1);
1135 case SIM_BFIN_M2_REGNUM: return &MREG (2);
1136 case SIM_BFIN_M3_REGNUM: return &MREG (3);
1137 case SIM_BFIN_B0_REGNUM: return &BREG (0);
1138 case SIM_BFIN_B1_REGNUM: return &BREG (1);
1139 case SIM_BFIN_B2_REGNUM: return &BREG (2);
1140 case SIM_BFIN_B3_REGNUM: return &BREG (3);
1141 case SIM_BFIN_L0_REGNUM: return &LREG (0);
1142 case SIM_BFIN_L1_REGNUM: return &LREG (1);
1143 case SIM_BFIN_L2_REGNUM: return &LREG (2);
1144 case SIM_BFIN_L3_REGNUM: return &LREG (3);
1145 case SIM_BFIN_RETS_REGNUM: return &RETSREG;
1146 case SIM_BFIN_A0_DOT_X_REGNUM: return &AXREG (0);
1147 case SIM_BFIN_A0_DOT_W_REGNUM: return &AWREG (0);
1148 case SIM_BFIN_A1_DOT_X_REGNUM: return &AXREG (1);
1149 case SIM_BFIN_A1_DOT_W_REGNUM: return &AWREG (1);
1150 case SIM_BFIN_LC0_REGNUM: return &LCREG (0);
1151 case SIM_BFIN_LT0_REGNUM: return &LTREG (0);
1152 case SIM_BFIN_LB0_REGNUM: return &LBREG (0);
1153 case SIM_BFIN_LC1_REGNUM: return &LCREG (1);
1154 case SIM_BFIN_LT1_REGNUM: return &LTREG (1);
1155 case SIM_BFIN_LB1_REGNUM: return &LBREG (1);
1156 case SIM_BFIN_CYCLES_REGNUM: return &CYCLESREG;
1157 case SIM_BFIN_CYCLES2_REGNUM: return &CYCLES2REG;
1158 case SIM_BFIN_USP_REGNUM: return &USPREG;
1159 case SIM_BFIN_SEQSTAT_REGNUM: return &SEQSTATREG;
1160 case SIM_BFIN_SYSCFG_REGNUM: return &SYSCFGREG;
1161 case SIM_BFIN_RETI_REGNUM: return &RETIREG;
1162 case SIM_BFIN_RETX_REGNUM: return &RETXREG;
1163 case SIM_BFIN_RETN_REGNUM: return &RETNREG;
1164 case SIM_BFIN_RETE_REGNUM: return &RETEREG;
1165 case SIM_BFIN_PC_REGNUM: return &PCREG;
1166 default: return NULL;
1167 }
1168 }
1169
1170 static int
1171 bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1172 {
1173 bu32 value, *reg;
1174
1175 reg = bfin_get_reg (cpu, rn);
1176 if (reg)
1177 value = *reg;
1178 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1179 value = ASTAT;
1180 else if (rn == SIM_BFIN_CC_REGNUM)
1181 value = CCREG;
1182 else
1183 return 0; // will be an error in gdb
1184
1185 /* Handle our KSP/USP shadowing in SP. While in supervisor mode, we
1186 have the normal SP/USP behavior. User mode is tricky though. */
1187 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT
1188 && cec_is_user_mode (cpu))
1189 {
1190 if (rn == SIM_BFIN_SP_REGNUM)
1191 value = KSPREG;
1192 else if (rn == SIM_BFIN_USP_REGNUM)
1193 value = SPREG;
1194 }
1195
1196 bfin_store_unsigned_integer (buf, 4, value);
1197
1198 return -1; // disables size checking in gdb
1199 }
1200
1201 static int
1202 bfin_reg_store (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1203 {
1204 bu32 value, *reg;
1205
1206 value = bfin_extract_unsigned_integer (buf, 4);
1207 reg = bfin_get_reg (cpu, rn);
1208
1209 if (reg)
1210 /* XXX: Need register trace ? */
1211 *reg = value;
1212 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1213 SET_ASTAT (value);
1214 else if (rn == SIM_BFIN_CC_REGNUM)
1215 SET_CCREG (value);
1216 else
1217 return 0; // will be an error in gdb
1218
1219 return -1; // disables size checking in gdb
1220 }
1221
1222 static sim_cia
1223 bfin_pc_get (SIM_CPU *cpu)
1224 {
1225 return PCREG;
1226 }
1227
1228 static void
1229 bfin_pc_set (SIM_CPU *cpu, sim_cia newpc)
1230 {
1231 SET_PCREG (newpc);
1232 }
1233
1234 static const char *
1235 bfin_insn_name (SIM_CPU *cpu, int i)
1236 {
1237 static const char * const insn_name[] = {
1238 #define I(insn) #insn,
1239 #include "insn_list.def"
1240 #undef I
1241 };
1242 return insn_name[i];
1243 }
1244
1245 static void
1246 bfin_init_cpu (SIM_CPU *cpu)
1247 {
1248 CPU_REG_FETCH (cpu) = bfin_reg_fetch;
1249 CPU_REG_STORE (cpu) = bfin_reg_store;
1250 CPU_PC_FETCH (cpu) = bfin_pc_get;
1251 CPU_PC_STORE (cpu) = bfin_pc_set;
1252 CPU_MAX_INSNS (cpu) = BFIN_INSN_MAX;
1253 CPU_INSN_NAME (cpu) = bfin_insn_name;
1254 }
1255
1256 static void
1257 bfin_prepare_run (SIM_CPU *cpu)
1258 {
1259 }
1260
1261 static const MODEL bfin_models[] =
1262 {
1263 #define P(n) { "bf"#n, & bfin_mach, MODEL_BF##n, NULL, bfin_model_init },
1264 #include "proc_list.def"
1265 #undef P
1266 { 0, NULL, 0, NULL, NULL, }
1267 };
1268
1269 static const MACH_IMP_PROPERTIES bfin_imp_properties =
1270 {
1271 sizeof (SIM_CPU),
1272 0,
1273 };
1274
1275 static const MACH bfin_mach =
1276 {
1277 "bfin", "bfin", MACH_BFIN,
1278 32, 32, & bfin_models[0], & bfin_imp_properties,
1279 bfin_init_cpu,
1280 bfin_prepare_run
1281 };
1282
1283 const MACH *sim_machs[] =
1284 {
1285 & bfin_mach,
1286 NULL
1287 };
1288 \f
1289 /* Device option parsing. */
1290
1291 static DECLARE_OPTION_HANDLER (bfin_mach_option_handler);
1292
1293 enum {
1294 OPTION_MACH_SIREV = OPTION_START,
1295 OPTION_MACH_HW_BOARD_FILE,
1296 };
1297
1298 const OPTION bfin_mach_options[] =
1299 {
1300 { {"sirev", required_argument, NULL, OPTION_MACH_SIREV },
1301 '\0', "NUMBER", "Set CPU silicon revision",
1302 bfin_mach_option_handler, NULL },
1303
1304 { {"hw-board-file", required_argument, NULL, OPTION_MACH_HW_BOARD_FILE },
1305 '\0', "FILE", "Add the supplemental devices listed in the file",
1306 bfin_mach_option_handler, NULL },
1307
1308 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
1309 };
1310
1311 static SIM_RC
1312 bfin_mach_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
1313 char *arg, int is_command)
1314 {
1315 struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1316
1317 switch (opt)
1318 {
1319 case OPTION_MACH_SIREV:
1320 board->sirev_valid = 1;
1321 /* Accept (and throw away) a leading "0." in the version. */
1322 if (!strncmp (arg, "0.", 2))
1323 arg += 2;
1324 board->sirev = atoi (arg);
1325 if (board->sirev > 0xf)
1326 {
1327 sim_io_eprintf (sd, "sirev '%s' needs to fit into 4 bits\n", arg);
1328 return SIM_RC_FAIL;
1329 }
1330 return SIM_RC_OK;
1331
1332 case OPTION_MACH_HW_BOARD_FILE:
1333 board->hw_file = xstrdup (arg);
1334 return SIM_RC_OK;
1335
1336 default:
1337 sim_io_eprintf (sd, "Unknown Blackfin option %d\n", opt);
1338 return SIM_RC_FAIL;
1339 }
1340 }
GDB Binutils - Deliverables
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