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sim: bfin: add a performance monitor stub
[deliverable/binutils-gdb.git] / sim / bfin / machs.c
1 /* Simulator for Analog Devices Blackfin processors.
2
3 Copyright (C) 2005-2011 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22
23 #include "sim-main.h"
24 #include "gdb/sim-bfin.h"
25 #include "bfd.h"
26
27 #include "sim-hw.h"
28 #include "devices.h"
29 #include "dv-bfin_cec.h"
30 #include "dv-bfin_ctimer.h"
31 #include "dv-bfin_dma.h"
32 #include "dv-bfin_dmac.h"
33 #include "dv-bfin_ebiu_amc.h"
34 #include "dv-bfin_ebiu_ddrc.h"
35 #include "dv-bfin_ebiu_sdc.h"
36 #include "dv-bfin_emac.h"
37 #include "dv-bfin_eppi.h"
38 #include "dv-bfin_evt.h"
39 #include "dv-bfin_gpio.h"
40 #include "dv-bfin_gptimer.h"
41 #include "dv-bfin_jtag.h"
42 #include "dv-bfin_mmu.h"
43 #include "dv-bfin_nfc.h"
44 #include "dv-bfin_otp.h"
45 #include "dv-bfin_pfmon.h"
46 #include "dv-bfin_pll.h"
47 #include "dv-bfin_ppi.h"
48 #include "dv-bfin_rtc.h"
49 #include "dv-bfin_sic.h"
50 #include "dv-bfin_spi.h"
51 #include "dv-bfin_trace.h"
52 #include "dv-bfin_twi.h"
53 #include "dv-bfin_uart.h"
54 #include "dv-bfin_uart2.h"
55 #include "dv-bfin_wdog.h"
56 #include "dv-bfin_wp.h"
57
58 static const MACH bfin_mach;
59
60 struct bfin_memory_layout {
61 address_word addr, len;
62 unsigned mask; /* see mapmask in sim_core_attach() */
63 };
64 struct bfin_dev_layout {
65 address_word base, len;
66 unsigned int dmac;
67 const char *dev;
68 };
69 struct bfin_dmac_layout {
70 address_word base;
71 unsigned int dma_count;
72 };
73 struct bfin_model_data {
74 bu32 chipid;
75 int model_num;
76 const struct bfin_memory_layout *mem;
77 size_t mem_count;
78 const struct bfin_dev_layout *dev;
79 size_t dev_count;
80 const struct bfin_dmac_layout *dmac;
81 size_t dmac_count;
82 };
83
84 #define LAYOUT(_addr, _len, _mask) { .addr = _addr, .len = _len, .mask = access_##_mask, }
85 #define _DEVICE(_base, _len, _dev, _dmac) { .base = _base, .len = _len, .dev = _dev, .dmac = _dmac, }
86 #define DEVICE(_base, _len, _dev) _DEVICE(_base, _len, _dev, 0)
87
88 /* [1] Common sim code can't model exec-only memory.
89 http://sourceware.org/ml/gdb/2010-02/msg00047.html */
90
91 #define bf000_chipid 0
92 static const struct bfin_memory_layout bf000_mem[] = {};
93 static const struct bfin_dev_layout bf000_dev[] = {};
94 static const struct bfin_dmac_layout bf000_dmac[] = {};
95
96 #define bf50x_chipid 0x2800
97 #define bf504_chipid bf50x_chipid
98 #define bf506_chipid bf50x_chipid
99 static const struct bfin_memory_layout bf50x_mem[] =
100 {
101 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
102 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
103 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
104 LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */
105 LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */
106 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
107 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
108 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
109 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst Cache [1] */
110 };
111 #define bf504_mem bf50x_mem
112 #define bf506_mem bf50x_mem
113 static const struct bfin_dev_layout bf50x_dev[] =
114 {
115 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
116 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
117 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
118 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
119 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
120 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
121 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
122 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
123 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
124 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
125 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
126 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
127 DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
128 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
129 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
130 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
131 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
132 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
133 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
134 };
135 #define bf504_dev bf50x_dev
136 #define bf506_dev bf50x_dev
137 static const struct bfin_dmac_layout bf50x_dmac[] =
138 {
139 { BFIN_MMR_DMAC0_BASE, 12, },
140 };
141 #define bf504_dmac bf50x_dmac
142 #define bf506_dmac bf50x_dmac
143
144 #define bf51x_chipid 0x27e8
145 #define bf512_chipid bf51x_chipid
146 #define bf514_chipid bf51x_chipid
147 #define bf516_chipid bf51x_chipid
148 #define bf518_chipid bf51x_chipid
149 static const struct bfin_memory_layout bf51x_mem[] =
150 {
151 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
152 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
153 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
154 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
155 LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */
156 LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */
157 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
158 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
159 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
160 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
161 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
162 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
163 };
164 #define bf512_mem bf51x_mem
165 #define bf514_mem bf51x_mem
166 #define bf516_mem bf51x_mem
167 #define bf518_mem bf51x_mem
168 static const struct bfin_dev_layout bf512_dev[] =
169 {
170 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
171 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
172 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
173 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
174 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
175 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
176 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
177 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
178 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
179 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
180 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
181 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
182 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
183 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
184 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
185 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
186 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
187 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
188 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
189 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
190 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
191 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
192 };
193 #define bf514_dev bf512_dev
194 static const struct bfin_dev_layout bf516_dev[] =
195 {
196 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
197 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
198 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
199 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
200 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
201 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
202 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
203 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
204 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
205 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
206 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
207 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
208 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
209 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
210 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
211 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
212 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
213 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
214 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
215 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
216 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
217 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
218 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
219 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
220 };
221 #define bf518_dev bf516_dev
222 #define bf512_dmac bf50x_dmac
223 #define bf514_dmac bf50x_dmac
224 #define bf516_dmac bf50x_dmac
225 #define bf518_dmac bf50x_dmac
226
227 #define bf522_chipid 0x27e4
228 #define bf523_chipid 0x27e0
229 #define bf524_chipid bf522_chipid
230 #define bf525_chipid bf523_chipid
231 #define bf526_chipid bf522_chipid
232 #define bf527_chipid bf523_chipid
233 static const struct bfin_memory_layout bf52x_mem[] =
234 {
235 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
236 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
237 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
238 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
239 LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */
240 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
241 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
242 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
243 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
244 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
245 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
246 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
247 };
248 #define bf522_mem bf52x_mem
249 #define bf523_mem bf52x_mem
250 #define bf524_mem bf52x_mem
251 #define bf525_mem bf52x_mem
252 #define bf526_mem bf52x_mem
253 #define bf527_mem bf52x_mem
254 static const struct bfin_dev_layout bf522_dev[] =
255 {
256 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
257 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
258 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
259 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
260 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
261 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
262 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
263 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
264 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
265 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
266 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
267 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
268 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
269 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
270 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
271 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
272 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
273 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
274 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
275 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
276 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
277 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
278 };
279 #define bf523_dev bf522_dev
280 #define bf524_dev bf522_dev
281 #define bf525_dev bf522_dev
282 static const struct bfin_dev_layout bf526_dev[] =
283 {
284 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
285 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
286 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
287 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
288 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
289 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
290 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
291 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
292 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
293 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
294 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
295 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
296 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
297 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
298 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
299 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
300 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
301 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
302 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
303 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
304 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
305 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
306 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
307 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
308 };
309 #define bf527_dev bf526_dev
310 #define bf522_dmac bf50x_dmac
311 #define bf523_dmac bf50x_dmac
312 #define bf524_dmac bf50x_dmac
313 #define bf525_dmac bf50x_dmac
314 #define bf526_dmac bf50x_dmac
315 #define bf527_dmac bf50x_dmac
316
317 #define bf531_chipid 0x27a5
318 #define bf532_chipid bf531_chipid
319 #define bf533_chipid bf531_chipid
320 static const struct bfin_memory_layout bf531_mem[] =
321 {
322 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
323 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
324 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
325 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
326 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
327 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
328 };
329 static const struct bfin_memory_layout bf532_mem[] =
330 {
331 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
332 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
333 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
334 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
335 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
336 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
337 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
338 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
339 };
340 static const struct bfin_memory_layout bf533_mem[] =
341 {
342 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
343 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
344 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
345 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
346 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
347 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
348 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
349 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
350 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
351 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
352 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
353 };
354 static const struct bfin_dev_layout bf533_dev[] =
355 {
356 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
357 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
358 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
359 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
360 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
361 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
362 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
363 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
364 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
365 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
366 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
367 };
368 #define bf531_dev bf533_dev
369 #define bf532_dev bf533_dev
370 static const struct bfin_dmac_layout bf533_dmac[] =
371 {
372 { BFIN_MMR_DMAC0_BASE, 8, },
373 };
374 #define bf531_dmac bf533_dmac
375 #define bf532_dmac bf533_dmac
376
377 #define bf534_chipid 0x27c6
378 #define bf536_chipid 0x27c8
379 #define bf537_chipid bf536_chipid
380 static const struct bfin_memory_layout bf534_mem[] =
381 {
382 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
383 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
384 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
385 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
386 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
387 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
388 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
389 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
390 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
391 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
392 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
393 };
394 static const struct bfin_memory_layout bf536_mem[] =
395 {
396 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
397 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
398 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
399 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
400 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
401 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
402 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
403 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
404 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
405 };
406 static const struct bfin_memory_layout bf537_mem[] =
407 {
408 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
409 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
410 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
411 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
412 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
413 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
414 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
415 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
416 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
417 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
418 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
419 };
420 static const struct bfin_dev_layout bf534_dev[] =
421 {
422 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
423 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
424 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
425 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
426 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
427 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
428 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
429 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
430 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
431 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
432 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
433 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
434 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
435 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
436 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
437 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
438 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
439 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
440 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
441 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
442 };
443 static const struct bfin_dev_layout bf537_dev[] =
444 {
445 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
446 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
447 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
448 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
449 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
450 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
451 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
452 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
453 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
454 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
455 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
456 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
457 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
458 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
459 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
460 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
461 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
462 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
463 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
464 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
465 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
466 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
467 };
468 #define bf536_dev bf537_dev
469 #define bf534_dmac bf50x_dmac
470 #define bf536_dmac bf50x_dmac
471 #define bf537_dmac bf50x_dmac
472
473 #define bf538_chipid 0x27c4
474 #define bf539_chipid bf538_chipid
475 static const struct bfin_memory_layout bf538_mem[] =
476 {
477 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
478 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
479 LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */
480 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
481 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
482 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
483 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
484 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
485 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
486 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
487 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
488 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
489 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
490 };
491 #define bf539_mem bf538_mem
492 static const struct bfin_dev_layout bf538_dev[] =
493 {
494 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
495 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
496 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
497 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
498 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
499 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
500 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
501 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
502 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
503 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
504 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
505 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
506 _DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1),
507 _DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1),
508 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
509 _DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1", 1),
510 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
511 };
512 #define bf539_dev bf538_dev
513 static const struct bfin_dmac_layout bf538_dmac[] =
514 {
515 { BFIN_MMR_DMAC0_BASE, 8, },
516 { BFIN_MMR_DMAC1_BASE, 12, },
517 };
518 #define bf539_dmac bf538_dmac
519
520 #define bf54x_chipid 0x27de
521 #define bf542_chipid bf54x_chipid
522 #define bf544_chipid bf54x_chipid
523 #define bf547_chipid bf54x_chipid
524 #define bf548_chipid bf54x_chipid
525 #define bf549_chipid bf54x_chipid
526 static const struct bfin_memory_layout bf54x_mem[] =
527 {
528 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */
529 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
530 LAYOUT (0xFFC01400, 0x200, read_write), /* PORT/GPIO stub */
531 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
532 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
533 LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */
534 LAYOUT (0xFFC03900, 0x100, read_write), /* RSI stub */
535 LAYOUT (0xFFC03C00, 0x500, read_write), /* MUSB stub */
536 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
537 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
538 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
539 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
540 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
541 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
542 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
543 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
544 };
545 #define bf542_mem bf54x_mem
546 #define bf544_mem bf54x_mem
547 #define bf547_mem bf54x_mem
548 #define bf548_mem bf54x_mem
549 #define bf549_mem bf54x_mem
550 static const struct bfin_dev_layout bf542_dev[] =
551 {
552 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
553 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
554 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
555 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
556 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
557 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
558 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
559 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
560 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
561 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
562 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
563 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
564 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
565 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
566 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
567 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
568 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
569 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
570 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
571 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
572 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
573 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
574 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
575 };
576 static const struct bfin_dev_layout bf544_dev[] =
577 {
578 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
579 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
580 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
581 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
582 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
583 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
584 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
585 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
586 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
587 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
588 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
589 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
590 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
591 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
592 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
593 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
594 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
595 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
596 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
597 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
598 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
599 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
600 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
601 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
602 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
603 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
604 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
605 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
606 };
607 static const struct bfin_dev_layout bf547_dev[] =
608 {
609 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
610 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
611 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
612 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
613 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
614 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
615 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
616 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
617 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
618 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
619 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
620 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
621 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
622 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
623 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
624 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
625 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
626 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
627 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
628 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
629 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
630 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
631 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
632 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
633 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
634 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
635 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
636 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
637 };
638 #define bf548_dev bf547_dev
639 #define bf549_dev bf547_dev
640 static const struct bfin_dmac_layout bf54x_dmac[] =
641 {
642 { BFIN_MMR_DMAC0_BASE, 12, },
643 { BFIN_MMR_DMAC1_BASE, 12, },
644 };
645 #define bf542_dmac bf54x_dmac
646 #define bf544_dmac bf54x_dmac
647 #define bf547_dmac bf54x_dmac
648 #define bf548_dmac bf54x_dmac
649 #define bf549_dmac bf54x_dmac
650
651 /* This is only Core A of course ... */
652 #define bf561_chipid 0x27bb
653 static const struct bfin_memory_layout bf561_mem[] =
654 {
655 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
656 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
657 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
658 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
659 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
660 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
661 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
662 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
663 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
664 };
665 static const struct bfin_dev_layout bf561_dev[] =
666 {
667 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
668 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
669 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
670 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
671 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
672 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
673 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
674 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
675 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
676 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
677 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
678 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
679 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
680 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
681 _DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1),
682 DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"),
683 _DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1),
684 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
685 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
686 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
687 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
688 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"),
689 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
690 };
691 static const struct bfin_dmac_layout bf561_dmac[] =
692 {
693 { BFIN_MMR_DMAC0_BASE, 12, },
694 { BFIN_MMR_DMAC1_BASE, 12, },
695 /* XXX: IMDMA: { 0xFFC01800, 4, }, */
696 };
697
698 #define bf592_chipid 0x20cb
699 static const struct bfin_memory_layout bf592_mem[] =
700 {
701 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
702 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
703 LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */
704 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
705 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */
706 };
707 static const struct bfin_dev_layout bf592_dev[] =
708 {
709 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
710 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
711 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
712 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
713 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
714 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
715 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
716 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
717 DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
718 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
719 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
720 };
721 static const struct bfin_dmac_layout bf592_dmac[] =
722 {
723 /* XXX: there are only 9 channels, but mdma code below assumes that they
724 start right after the dma channels ... */
725 { BFIN_MMR_DMAC0_BASE, 12, },
726 };
727
728 static const struct bfin_model_data bfin_model_data[] =
729 {
730 #define P(n) \
731 [MODEL_BF##n] = { \
732 bf##n##_chipid, n, \
733 bf##n##_mem , ARRAY_SIZE (bf##n##_mem ), \
734 bf##n##_dev , ARRAY_SIZE (bf##n##_dev ), \
735 bf##n##_dmac, ARRAY_SIZE (bf##n##_dmac), \
736 },
737 #include "proc_list.def"
738 #undef P
739 };
740
741 #define CORE_DEVICE(dev, DEV) \
742 DEVICE (BFIN_COREMMR_##DEV##_BASE, BFIN_COREMMR_##DEV##_SIZE, "bfin_"#dev)
743 static const struct bfin_dev_layout bfin_core_dev[] =
744 {
745 CORE_DEVICE (cec, CEC),
746 CORE_DEVICE (ctimer, CTIMER),
747 CORE_DEVICE (evt, EVT),
748 CORE_DEVICE (jtag, JTAG),
749 CORE_DEVICE (mmu, MMU),
750 CORE_DEVICE (pfmon, PFMON),
751 CORE_DEVICE (trace, TRACE),
752 CORE_DEVICE (wp, WP),
753 };
754
755 #define dv_bfin_hw_parse(sd, dv, DV) \
756 do { \
757 bu32 base = BFIN_MMR_##DV##_BASE; \
758 bu32 size = BFIN_MMR_##DV##_SIZE; \
759 sim_hw_parse (sd, "/core/bfin_"#dv"/reg %#x %i", base, size); \
760 sim_hw_parse (sd, "/core/bfin_"#dv"/type %i", mdata->model_num); \
761 } while (0)
762
763 static void
764 bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu)
765 {
766 const MODEL *model = CPU_MODEL (cpu);
767 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
768 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
769 int mnum = MODEL_NUM (model);
770 unsigned i, j, dma_chan;
771
772 /* Map the core devices. */
773 for (i = 0; i < ARRAY_SIZE (bfin_core_dev); ++i)
774 {
775 const struct bfin_dev_layout *dev = &bfin_core_dev[i];
776 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
777 }
778 sim_hw_parse (sd, "/core/bfin_ctimer > ivtmr ivtmr /core/bfin_cec");
779
780 if (mnum == MODEL_BF000)
781 goto done;
782
783 /* Map the system devices. */
784 dv_bfin_hw_parse (sd, sic, SIC);
785 sim_hw_parse (sd, "/core/bfin_sic/type %i", mdata->model_num);
786 for (i = 7; i < 16; ++i)
787 sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i);
788
789 dv_bfin_hw_parse (sd, pll, PLL);
790 sim_hw_parse (sd, "/core/bfin_pll > pll pll /core/bfin_sic");
791
792 dma_chan = 0;
793 for (i = 0; i < mdata->dmac_count; ++i)
794 {
795 const struct bfin_dmac_layout *dmac = &mdata->dmac[i];
796
797 sim_hw_parse (sd, "/core/bfin_dmac@%u/type %i", i, mdata->model_num);
798
799 /* Hook up the non-mdma channels. */
800 for (j = 0; j < dmac->dma_count; ++j)
801 {
802 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u/reg %#x %i", i,
803 dma_chan, dmac->base + j * BFIN_MMR_DMA_SIZE,
804 BFIN_MMR_DMA_SIZE);
805
806 /* Could route these into the bfin_dmac and let that
807 forward it to the SIC, but not much value. */
808 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u > di dma@%u /core/bfin_sic",
809 i, dma_chan, dma_chan);
810
811 ++dma_chan;
812 }
813
814 /* Hook up the mdma channels -- assume every DMAC has 4. */
815 for (j = 0; j < 4; ++j)
816 {
817 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u/reg %#x %i",
818 i, j + BFIN_DMAC_MDMA_BASE,
819 dmac->base + (j + dmac->dma_count) * BFIN_MMR_DMA_SIZE,
820 BFIN_MMR_DMA_SIZE);
821 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u > di mdma@%u /core/bfin_sic",
822 i, j + BFIN_DMAC_MDMA_BASE, (2 * i) + (j / 2));
823 }
824 }
825
826 for (i = 0; i < mdata->dev_count; ++i)
827 {
828 const struct bfin_dev_layout *dev = &mdata->dev[i];
829 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
830 sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num);
831 if (strchr (dev->dev, '/'))
832 continue;
833 if (!strncmp (dev->dev, "bfin_uart", 9)
834 || !strncmp (dev->dev, "bfin_emac", 9)
835 || !strncmp (dev->dev, "bfin_sport", 10))
836 {
837 const char *sint = dev->dev + 5;
838 sim_hw_parse (sd, "/core/%s > tx %s_tx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
839 sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
840 sim_hw_parse (sd, "/core/%s > stat %s_stat /core/bfin_sic", dev->dev, sint);
841 }
842 else if (!strncmp (dev->dev, "bfin_gptimer", 12)
843 || !strncmp (dev->dev, "bfin_ppi", 8)
844 || !strncmp (dev->dev, "bfin_spi", 8)
845 || !strncmp (dev->dev, "bfin_twi", 8))
846 {
847 const char *sint = dev->dev + 5;
848 sim_hw_parse (sd, "/core/%s > stat %s /core/bfin_sic", dev->dev, sint);
849 }
850 else if (!strncmp (dev->dev, "bfin_rtc", 8))
851 {
852 const char *sint = dev->dev + 5;
853 sim_hw_parse (sd, "/core/%s > %s %s /core/bfin_sic", dev->dev, sint, sint);
854 }
855 else if (!strncmp (dev->dev, "bfin_wdog", 9))
856 {
857 sim_hw_parse (sd, "/core/%s > reset rst /core/bfin_cec", dev->dev);
858 sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev);
859 sim_hw_parse (sd, "/core/%s > gpi wdog /core/bfin_sic", dev->dev);
860 }
861 else if (!strncmp (dev->dev, "bfin_gpio", 9))
862 {
863 char port = 'a' + strtol(&dev->dev[10], NULL, 0);
864 sim_hw_parse (sd, "/core/%s > mask_a port%c_irq_a /core/bfin_sic",
865 dev->dev, port);
866 sim_hw_parse (sd, "/core/%s > mask_b port%c_irq_b /core/bfin_sic",
867 dev->dev, port);
868 }
869 }
870
871 done:
872 /* Add any additional user board content. */
873 if (board->hw_file)
874 sim_do_commandf (sd, "hw-file %s", board->hw_file);
875
876 /* Trigger all the new devices' finish func. */
877 hw_tree_finish (dv_get_device (cpu, "/"));
878 }
879
880 #include "bfroms/all.h"
881
882 struct bfrom {
883 bu32 addr, len, alias_len;
884 int sirev;
885 const char *buf;
886 };
887
888 #define BFROMA(addr, rom, sirev, alias_len) \
889 { addr, sizeof (bfrom_bf##rom##_0_##sirev), alias_len, \
890 sirev, bfrom_bf##rom##_0_##sirev, }
891 #define BFROM(rom, sirev, alias_len) BFROMA (0xef000000, rom, sirev, alias_len)
892 #define BFROM_STUB { 0, 0, 0, 0, NULL, }
893 static const struct bfrom bf50x_roms[] =
894 {
895 BFROM (50x, 0, 0x1000000),
896 BFROM_STUB,
897 };
898 static const struct bfrom bf51x_roms[] =
899 {
900 BFROM (51x, 2, 0x1000000),
901 BFROM (51x, 1, 0x1000000),
902 BFROM (51x, 0, 0x1000000),
903 BFROM_STUB,
904 };
905 static const struct bfrom bf526_roms[] =
906 {
907 BFROM (526, 2, 0x1000000),
908 BFROM (526, 1, 0x1000000),
909 BFROM (526, 0, 0x1000000),
910 BFROM_STUB,
911 };
912 static const struct bfrom bf527_roms[] =
913 {
914 BFROM (527, 2, 0x1000000),
915 BFROM (527, 1, 0x1000000),
916 BFROM (527, 0, 0x1000000),
917 BFROM_STUB,
918 };
919 static const struct bfrom bf533_roms[] =
920 {
921 BFROM (533, 6, 0x1000000),
922 BFROM (533, 5, 0x1000000),
923 BFROM (533, 4, 0x1000000),
924 BFROM (533, 3, 0x1000000),
925 BFROM (533, 2, 0x1000000),
926 BFROM (533, 1, 0x1000000),
927 BFROM_STUB,
928 };
929 static const struct bfrom bf537_roms[] =
930 {
931 BFROM (537, 3, 0x100000),
932 BFROM (537, 2, 0x100000),
933 BFROM (537, 1, 0x100000),
934 BFROM (537, 0, 0x100000),
935 BFROM_STUB,
936 };
937 static const struct bfrom bf538_roms[] =
938 {
939 BFROM (538, 5, 0x1000000),
940 BFROM (538, 4, 0x1000000),
941 BFROM (538, 3, 0x1000000),
942 BFROM (538, 2, 0x1000000),
943 BFROM (538, 1, 0x1000000),
944 BFROM (538, 0, 0x1000000),
945 BFROM_STUB,
946 };
947 static const struct bfrom bf54x_roms[] =
948 {
949 BFROM (54x, 4, 0),
950 BFROM (54x, 2, 0),
951 BFROM (54x, 1, 0),
952 BFROM (54x, 0, 0),
953 BFROMA (0xffa14000, 54x_l1, 4, 0),
954 BFROMA (0xffa14000, 54x_l1, 2, 0),
955 BFROMA (0xffa14000, 54x_l1, 1, 0),
956 BFROMA (0xffa14000, 54x_l1, 0, 0),
957 BFROM_STUB,
958 };
959 static const struct bfrom bf561_roms[] =
960 {
961 /* XXX: No idea what the actual wrap limit is here. */
962 BFROM (561, 5, 0),
963 BFROM_STUB,
964 };
965 static const struct bfrom bf59x_roms[] =
966 {
967 BFROM (59x, 1, 0x1000000),
968 BFROM (59x, 0, 0x1000000),
969 BFROMA (0xffa10000, 59x_l1, 1, 0),
970 BFROM_STUB,
971 };
972
973 static void
974 bfin_model_map_bfrom (SIM_DESC sd, SIM_CPU *cpu)
975 {
976 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
977 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
978 int mnum = mdata->model_num;
979 const struct bfrom *bfrom;
980 unsigned int sirev;
981
982 if (mnum >= 500 && mnum <= 509)
983 bfrom = bf50x_roms;
984 else if (mnum >= 510 && mnum <= 519)
985 bfrom = bf51x_roms;
986 else if (mnum >= 520 && mnum <= 529)
987 bfrom = (mnum & 1) ? bf527_roms : bf526_roms;
988 else if (mnum >= 531 && mnum <= 533)
989 bfrom = bf533_roms;
990 else if (mnum == 535)
991 /* Stub. */;
992 else if (mnum >= 534 && mnum <= 537)
993 bfrom = bf537_roms;
994 else if (mnum >= 538 && mnum <= 539)
995 bfrom = bf538_roms;
996 else if (mnum >= 540 && mnum <= 549)
997 bfrom = bf54x_roms;
998 else if (mnum == 561)
999 bfrom = bf561_roms;
1000 else if (mnum >= 590 && mnum <= 599)
1001 bfrom = bf59x_roms;
1002 else
1003 return;
1004
1005 if (board->sirev_valid)
1006 sirev = board->sirev;
1007 else
1008 sirev = bfrom->sirev;
1009 while (bfrom->buf)
1010 {
1011 /* Map all the ranges for this model/sirev. */
1012 if (bfrom->sirev == sirev)
1013 sim_core_attach (sd, NULL, 0, access_read_exec, 0, bfrom->addr,
1014 bfrom->alias_len ? : bfrom->len, bfrom->len, NULL,
1015 (char *)bfrom->buf);
1016 ++bfrom;
1017 }
1018 }
1019
1020 void
1021 bfin_model_cpu_init (SIM_DESC sd, SIM_CPU *cpu)
1022 {
1023 const MODEL *model = CPU_MODEL (cpu);
1024 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1025 int mnum = MODEL_NUM (model);
1026 size_t idx;
1027
1028 /* These memory maps are supposed to be cpu-specific, but the common sim
1029 code does not yet allow that (2nd arg is "cpu" rather than "NULL". */
1030 sim_core_attach (sd, NULL, 0, access_read_write, 0, BFIN_L1_SRAM_SCRATCH,
1031 BFIN_L1_SRAM_SCRATCH_SIZE, 0, NULL, NULL);
1032
1033 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
1034 return;
1035
1036 if (mnum == MODEL_BF000)
1037 goto core_only;
1038
1039 /* Map in the on-chip memories (SRAMs). */
1040 mdata = &bfin_model_data[MODEL_NUM (model)];
1041 for (idx = 0; idx < mdata->mem_count; ++idx)
1042 {
1043 const struct bfin_memory_layout *mem = &mdata->mem[idx];
1044 sim_core_attach (sd, NULL, 0, mem->mask, 0, mem->addr,
1045 mem->len, 0, NULL, NULL);
1046 }
1047
1048 /* Map the on-chip ROMs. */
1049 bfin_model_map_bfrom (sd, cpu);
1050
1051 core_only:
1052 /* Finally, build up the tree for this cpu model. */
1053 bfin_model_hw_tree_init (sd, cpu);
1054 }
1055
1056 bu32
1057 bfin_model_get_chipid (SIM_DESC sd)
1058 {
1059 SIM_CPU *cpu = STATE_CPU (sd, 0);
1060 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1061 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1062 return
1063 (board->sirev << 28) |
1064 (mdata->chipid << 12) |
1065 (((0xE5 << 1) | 1) & 0xFF);
1066 }
1067
1068 bu32
1069 bfin_model_get_dspid (SIM_DESC sd)
1070 {
1071 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1072 return
1073 (0xE5 << 24) |
1074 (0x04 << 16) |
1075 (board->sirev);
1076 }
1077
1078 static void
1079 bfin_model_init (SIM_CPU *cpu)
1080 {
1081 CPU_MODEL_DATA (cpu) = (void *) &bfin_model_data[MODEL_NUM (CPU_MODEL (cpu))];
1082 }
1083
1084 static bu32
1085 bfin_extract_unsigned_integer (unsigned char *addr, int len)
1086 {
1087 bu32 retval;
1088 unsigned char * p;
1089 unsigned char * startaddr = (unsigned char *)addr;
1090 unsigned char * endaddr = startaddr + len;
1091
1092 retval = 0;
1093
1094 for (p = endaddr; p > startaddr;)
1095 retval = (retval << 8) | *--p;
1096
1097 return retval;
1098 }
1099
1100 static void
1101 bfin_store_unsigned_integer (unsigned char *addr, int len, bu32 val)
1102 {
1103 unsigned char *p;
1104 unsigned char *startaddr = addr;
1105 unsigned char *endaddr = startaddr + len;
1106
1107 for (p = startaddr; p < endaddr;)
1108 {
1109 *p++ = val & 0xff;
1110 val >>= 8;
1111 }
1112 }
1113
1114 static bu32 *
1115 bfin_get_reg (SIM_CPU *cpu, int rn)
1116 {
1117 switch (rn)
1118 {
1119 case SIM_BFIN_R0_REGNUM: return &DREG (0);
1120 case SIM_BFIN_R1_REGNUM: return &DREG (1);
1121 case SIM_BFIN_R2_REGNUM: return &DREG (2);
1122 case SIM_BFIN_R3_REGNUM: return &DREG (3);
1123 case SIM_BFIN_R4_REGNUM: return &DREG (4);
1124 case SIM_BFIN_R5_REGNUM: return &DREG (5);
1125 case SIM_BFIN_R6_REGNUM: return &DREG (6);
1126 case SIM_BFIN_R7_REGNUM: return &DREG (7);
1127 case SIM_BFIN_P0_REGNUM: return &PREG (0);
1128 case SIM_BFIN_P1_REGNUM: return &PREG (1);
1129 case SIM_BFIN_P2_REGNUM: return &PREG (2);
1130 case SIM_BFIN_P3_REGNUM: return &PREG (3);
1131 case SIM_BFIN_P4_REGNUM: return &PREG (4);
1132 case SIM_BFIN_P5_REGNUM: return &PREG (5);
1133 case SIM_BFIN_SP_REGNUM: return &SPREG;
1134 case SIM_BFIN_FP_REGNUM: return &FPREG;
1135 case SIM_BFIN_I0_REGNUM: return &IREG (0);
1136 case SIM_BFIN_I1_REGNUM: return &IREG (1);
1137 case SIM_BFIN_I2_REGNUM: return &IREG (2);
1138 case SIM_BFIN_I3_REGNUM: return &IREG (3);
1139 case SIM_BFIN_M0_REGNUM: return &MREG (0);
1140 case SIM_BFIN_M1_REGNUM: return &MREG (1);
1141 case SIM_BFIN_M2_REGNUM: return &MREG (2);
1142 case SIM_BFIN_M3_REGNUM: return &MREG (3);
1143 case SIM_BFIN_B0_REGNUM: return &BREG (0);
1144 case SIM_BFIN_B1_REGNUM: return &BREG (1);
1145 case SIM_BFIN_B2_REGNUM: return &BREG (2);
1146 case SIM_BFIN_B3_REGNUM: return &BREG (3);
1147 case SIM_BFIN_L0_REGNUM: return &LREG (0);
1148 case SIM_BFIN_L1_REGNUM: return &LREG (1);
1149 case SIM_BFIN_L2_REGNUM: return &LREG (2);
1150 case SIM_BFIN_L3_REGNUM: return &LREG (3);
1151 case SIM_BFIN_RETS_REGNUM: return &RETSREG;
1152 case SIM_BFIN_A0_DOT_X_REGNUM: return &AXREG (0);
1153 case SIM_BFIN_A0_DOT_W_REGNUM: return &AWREG (0);
1154 case SIM_BFIN_A1_DOT_X_REGNUM: return &AXREG (1);
1155 case SIM_BFIN_A1_DOT_W_REGNUM: return &AWREG (1);
1156 case SIM_BFIN_LC0_REGNUM: return &LCREG (0);
1157 case SIM_BFIN_LT0_REGNUM: return &LTREG (0);
1158 case SIM_BFIN_LB0_REGNUM: return &LBREG (0);
1159 case SIM_BFIN_LC1_REGNUM: return &LCREG (1);
1160 case SIM_BFIN_LT1_REGNUM: return &LTREG (1);
1161 case SIM_BFIN_LB1_REGNUM: return &LBREG (1);
1162 case SIM_BFIN_CYCLES_REGNUM: return &CYCLESREG;
1163 case SIM_BFIN_CYCLES2_REGNUM: return &CYCLES2REG;
1164 case SIM_BFIN_USP_REGNUM: return &USPREG;
1165 case SIM_BFIN_SEQSTAT_REGNUM: return &SEQSTATREG;
1166 case SIM_BFIN_SYSCFG_REGNUM: return &SYSCFGREG;
1167 case SIM_BFIN_RETI_REGNUM: return &RETIREG;
1168 case SIM_BFIN_RETX_REGNUM: return &RETXREG;
1169 case SIM_BFIN_RETN_REGNUM: return &RETNREG;
1170 case SIM_BFIN_RETE_REGNUM: return &RETEREG;
1171 case SIM_BFIN_PC_REGNUM: return &PCREG;
1172 default: return NULL;
1173 }
1174 }
1175
1176 static int
1177 bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1178 {
1179 bu32 value, *reg;
1180
1181 reg = bfin_get_reg (cpu, rn);
1182 if (reg)
1183 value = *reg;
1184 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1185 value = ASTAT;
1186 else if (rn == SIM_BFIN_CC_REGNUM)
1187 value = CCREG;
1188 else
1189 return 0; // will be an error in gdb
1190
1191 /* Handle our KSP/USP shadowing in SP. While in supervisor mode, we
1192 have the normal SP/USP behavior. User mode is tricky though. */
1193 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT
1194 && cec_is_user_mode (cpu))
1195 {
1196 if (rn == SIM_BFIN_SP_REGNUM)
1197 value = KSPREG;
1198 else if (rn == SIM_BFIN_USP_REGNUM)
1199 value = SPREG;
1200 }
1201
1202 bfin_store_unsigned_integer (buf, 4, value);
1203
1204 return -1; // disables size checking in gdb
1205 }
1206
1207 static int
1208 bfin_reg_store (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1209 {
1210 bu32 value, *reg;
1211
1212 value = bfin_extract_unsigned_integer (buf, 4);
1213 reg = bfin_get_reg (cpu, rn);
1214
1215 if (reg)
1216 /* XXX: Need register trace ? */
1217 *reg = value;
1218 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1219 SET_ASTAT (value);
1220 else if (rn == SIM_BFIN_CC_REGNUM)
1221 SET_CCREG (value);
1222 else
1223 return 0; // will be an error in gdb
1224
1225 return -1; // disables size checking in gdb
1226 }
1227
1228 static sim_cia
1229 bfin_pc_get (SIM_CPU *cpu)
1230 {
1231 return PCREG;
1232 }
1233
1234 static void
1235 bfin_pc_set (SIM_CPU *cpu, sim_cia newpc)
1236 {
1237 SET_PCREG (newpc);
1238 }
1239
1240 static const char *
1241 bfin_insn_name (SIM_CPU *cpu, int i)
1242 {
1243 static const char * const insn_name[] = {
1244 #define I(insn) #insn,
1245 #include "insn_list.def"
1246 #undef I
1247 };
1248 return insn_name[i];
1249 }
1250
1251 static void
1252 bfin_init_cpu (SIM_CPU *cpu)
1253 {
1254 CPU_REG_FETCH (cpu) = bfin_reg_fetch;
1255 CPU_REG_STORE (cpu) = bfin_reg_store;
1256 CPU_PC_FETCH (cpu) = bfin_pc_get;
1257 CPU_PC_STORE (cpu) = bfin_pc_set;
1258 CPU_MAX_INSNS (cpu) = BFIN_INSN_MAX;
1259 CPU_INSN_NAME (cpu) = bfin_insn_name;
1260 }
1261
1262 static void
1263 bfin_prepare_run (SIM_CPU *cpu)
1264 {
1265 }
1266
1267 static const MODEL bfin_models[] =
1268 {
1269 #define P(n) { "bf"#n, & bfin_mach, MODEL_BF##n, NULL, bfin_model_init },
1270 #include "proc_list.def"
1271 #undef P
1272 { 0, NULL, 0, NULL, NULL, }
1273 };
1274
1275 static const MACH_IMP_PROPERTIES bfin_imp_properties =
1276 {
1277 sizeof (SIM_CPU),
1278 0,
1279 };
1280
1281 static const MACH bfin_mach =
1282 {
1283 "bfin", "bfin", MACH_BFIN,
1284 32, 32, & bfin_models[0], & bfin_imp_properties,
1285 bfin_init_cpu,
1286 bfin_prepare_run
1287 };
1288
1289 const MACH *sim_machs[] =
1290 {
1291 & bfin_mach,
1292 NULL
1293 };
1294 \f
1295 /* Device option parsing. */
1296
1297 static DECLARE_OPTION_HANDLER (bfin_mach_option_handler);
1298
1299 enum {
1300 OPTION_MACH_SIREV = OPTION_START,
1301 OPTION_MACH_HW_BOARD_FILE,
1302 };
1303
1304 const OPTION bfin_mach_options[] =
1305 {
1306 { {"sirev", required_argument, NULL, OPTION_MACH_SIREV },
1307 '\0', "NUMBER", "Set CPU silicon revision",
1308 bfin_mach_option_handler, NULL },
1309
1310 { {"hw-board-file", required_argument, NULL, OPTION_MACH_HW_BOARD_FILE },
1311 '\0', "FILE", "Add the supplemental devices listed in the file",
1312 bfin_mach_option_handler, NULL },
1313
1314 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
1315 };
1316
1317 static SIM_RC
1318 bfin_mach_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
1319 char *arg, int is_command)
1320 {
1321 struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1322
1323 switch (opt)
1324 {
1325 case OPTION_MACH_SIREV:
1326 board->sirev_valid = 1;
1327 /* Accept (and throw away) a leading "0." in the version. */
1328 if (!strncmp (arg, "0.", 2))
1329 arg += 2;
1330 board->sirev = atoi (arg);
1331 if (board->sirev > 0xf)
1332 {
1333 sim_io_eprintf (sd, "sirev '%s' needs to fit into 4 bits\n", arg);
1334 return SIM_RC_FAIL;
1335 }
1336 return SIM_RC_OK;
1337
1338 case OPTION_MACH_HW_BOARD_FILE:
1339 board->hw_file = xstrdup (arg);
1340 return SIM_RC_OK;
1341
1342 default:
1343 sim_io_eprintf (sd, "Unknown Blackfin option %d\n", opt);
1344 return SIM_RC_FAIL;
1345 }
1346 }
GDB Binutils - Deliverables
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