1 /* Simulator for Analog Devices Blackfin processors.
3 Copyright (C) 2005-2019 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #ifndef _BFIN_MACHS_H_
22 #define _BFIN_MACHS_H_
24 #define CPU_MODEL_NUM(cpu) MODEL_NUM (CPU_MODEL (cpu))
26 /* XXX: Some of this probably belongs in CPU_MODEL. */
27 struct bfin_board_data
{
28 unsigned int sirev
, sirev_valid
;
32 void bfin_model_cpu_init (SIM_DESC
, SIM_CPU
*);
33 bu32
bfin_model_get_chipid (SIM_DESC
);
34 bu32
bfin_model_get_dspid (SIM_DESC
);
36 #define BFIN_COREMMR_CEC_BASE 0xFFE02100
37 #define BFIN_COREMMR_CEC_SIZE (4 * 5)
38 #define BFIN_COREMMR_CTIMER_BASE 0xFFE03000
39 #define BFIN_COREMMR_CTIMER_SIZE (4 * 4)
40 #define BFIN_COREMMR_EVT_BASE 0xFFE02000
41 #define BFIN_COREMMR_EVT_SIZE (4 * 16)
42 #define BFIN_COREMMR_JTAG_BASE 0xFFE05000
43 #define BFIN_COREMMR_JTAG_SIZE (4 * 3)
44 #define BFIN_COREMMR_MMU_BASE 0xFFE00000
45 #define BFIN_COREMMR_MMU_SIZE 0x2000
46 #define BFIN_COREMMR_PFMON_BASE 0xFFE08000
47 #define BFIN_COREMMR_PFMON_SIZE 0x108
48 #define BFIN_COREMMR_TRACE_BASE 0xFFE06000
49 #define BFIN_COREMMR_TRACE_SIZE (4 * 65)
50 #define BFIN_COREMMR_WP_BASE 0xFFE07000
51 #define BFIN_COREMMR_WP_SIZE 0x204
53 #define BFIN_MMR_DMA_SIZE (4 * 16)
54 #define BFIN_MMR_DMAC0_BASE 0xFFC00C00
55 #define BFIN_MMR_DMAC1_BASE 0xFFC01C00
56 #define BFIN_MMR_EBIU_AMC_SIZE (4 * 3)
57 #define BF50X_MMR_EBIU_AMC_SIZE 0x28
58 #define BF54X_MMR_EBIU_AMC_SIZE (4 * 7)
59 #define BFIN_MMR_EBIU_DDRC_SIZE 0xb0
60 #define BFIN_MMR_EBIU_SDC_SIZE (4 * 4)
61 #define BFIN_MMR_EMAC_BASE 0xFFC03000
62 #define BFIN_MMR_EMAC_SIZE 0x200
63 #define BFIN_MMR_EPPI_SIZE 0x40
64 #define BFIN_MMR_GPIO_SIZE (17 * 4)
65 #define BFIN_MMR_GPIO2_SIZE (8 * 4)
66 #define BFIN_MMR_GPTIMER_SIZE (4 * 4)
67 #define BFIN_MMR_NFC_SIZE 0x50
68 /* XXX: Not exactly true; it's two sets of 4 regs near each other:
69 0xFFC03600 0x10 - Control
70 0xFFC03680 0x10 - Data */
71 #define BFIN_MMR_OTP_SIZE 0xa0
72 #define BFIN_MMR_PINT_SIZE 0x28
73 #define BFIN_MMR_PLL_BASE 0xFFC00000
74 #define BFIN_MMR_PLL_SIZE (4 * 6)
75 #define BFIN_MMR_PPI_SIZE (4 * 5)
76 #define BFIN_MMR_RTC_SIZE (4 * 6)
77 #define BFIN_MMR_SIC_BASE 0xFFC00100
78 #define BFIN_MMR_SIC_SIZE 0x100
79 #define BFIN_MMR_SPI_SIZE (4 * 7)
80 #define BFIN_MMR_TWI_SIZE 0x90
81 #define BFIN_MMR_WDOG_SIZE (4 * 3)
82 #define BFIN_MMR_UART_SIZE 0x30
83 #define BFIN_MMR_UART2_SIZE 0x30
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