sim/common/cgen-engine.h

   1 /* Engine header for Cpu tools GENerated simulators.
   2    Copyright (C) 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 /* This file must be included after eng.h and before ${cpu}.h.  */
  22
  23 /* Semantic functions come in six versions on two axes:
  24    fast/full-featured, and using one of the simple/scache/compilation engines.
  25    A full featured simulator is always provided.  --enable-sim-fast includes
  26    support for fast execution by duplicating the semantic code but leaving
  27    out all features like tracing and profiling.
  28    Using the scache is selected with --enable-sim-scache.  */
  29 /* FIXME: --enable-sim-fast not implemented yet.  */
  30 /* FIXME: undecided how to handle WITH_SCACHE_PBB.  */
  31
  32 #ifndef CGEN_ENGINE_H
  33 #define CGEN_ENGINE_H
  34
  35 /* Instruction field support macros.  */
  36
  37 #define EXTRACT_MSB0_INT(val, total, start, length) \
  38 (((INT) (val) << ((sizeof (INT) * 8) - (total) + (start))) \
  39  >> ((sizeof (INT) * 8) - (length)))
  40 #define EXTRACT_MSB0_UINT(val, total, start, length) \
  41 (((UINT) (val) << ((sizeof (UINT) * 8) - (total) + (start))) \
  42  >> ((sizeof (UINT) * 8) - (length)))
  43
  44 #define EXTRACT_LSB0_INT(val, total, start, length) \
  45 (((INT) (val) << ((sizeof (INT) * 8) - (start) - (length))) \
  46  >> ((sizeof (INT) * 8) - (length)))
  47 #define EXTRACT_LSB0_UINT(val, total, start, length) \
  48 (((UINT) (val) << ((sizeof (UINT) * 8) - (start) - (length))) \
  49  >> ((sizeof (UINT) * 8) - (length)))
  50
  51 #if CGEN_INSN_LSB0_P
  52
  53 #define EXTRACT_INT(val, total, start, length) \
  54   EXTRACT_LSB0_INT ((val), (total), (start), (length))
  55 #define EXTRACT_UINT(val, total, start, length) \
  56   EXTRACT_LSB0_UINT ((val), (total), (start), (length))
  57
  58 #else
  59
  60 #define EXTRACT_INT(val, total, start, length) \
  61   EXTRACT_MSB0_INT ((val), (total), (start), (length))
  62 #define EXTRACT_UINT(val, total, start, length) \
  63   EXTRACT_MSB0_UINT ((val), (total), (start), (length))
  64
  65 #endif
  66 \f
  67 /* union sem */
  68
  69 /* Types of the machine generated extract and semantic fns.  */
  70 typedef void (EXTRACT_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *);
  71 #if HAVE_PARALLEL_INSNS
  72 typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *);
  73 #else
  74 typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG);
  75 #endif
  76
  77 union sem {
  78 #if ! WITH_SEM_SWITCH_FULL
  79   SEMANTIC_FN *sem_full;
  80 #endif
  81 #if ! WITH_SEM_SWITCH_FAST
  82   SEMANTIC_FN *sem_fast;
  83 #endif
  84 #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
  85 #ifdef __GNUC__
  86   void *sem_case;
  87 #else
  88   int sem_case;
  89 #endif
  90 #endif
  91 };
  92
  93 /* Set the appropriate semantic handler in ABUF.  */
  94
  95 #if WITH_SEM_SWITCH_FULL
  96 #ifdef __GNUC__
  97 #define SEM_SET_FULL_CODE(abuf, idesc) \
  98   do { (abuf)->semantic.sem_case = (idesc)->sem_full_lab; } while (0)
  99 #else
 100 #define SEM_SET_FULL_CODE(abuf, idesc) \
 101   do { (abuf)->semantic.sem_case = (idesc)->num; } while (0)
 102 #endif
 103 #else
 104 #define SEM_SET_FULL_CODE(abuf, idesc) \
 105   do { (abuf)->semantic.sem_full = (idesc)->sem_full; } while (0)
 106 #endif
 107
 108 #if WITH_SEM_SWITCH_FAST
 109 #ifdef __GNUC__
 110 #define SEM_SET_FAST_CODE(abuf, idesc) \
 111   do { (abuf)->semantic.sem_case = (idesc)->sem_fast_lab; } while (0)
 112 #else
 113 #define SEM_SET_FAST_CODE(abuf, idesc) \
 114   do { (abuf)->semantic.sem_case = (idesc)->num; } while (0)
 115 #endif
 116 #else
 117 #define SEM_SET_FAST_CODE(abuf, idesc) \
 118   do { (abuf)->semantic.sem_fast = (idesc)->sem_fast; } while (0)
 119 #endif
 120
 121 #define SEM_SET_CODE(abuf, idesc, fast_p) \
 122 do { \
 123   if (fast_p) \
 124     SEM_SET_FAST_CODE ((abuf), (idesc)); \
 125   else \
 126     SEM_SET_FULL_CODE ((abuf), (idesc)); \
 127 } while (0)
 128 \f
 129 #define IDESC_CTI_P(idesc) \
 130      ((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->opcode)) \
 131        & (CGEN_ATTR_MASK (CGEN_INSN_COND_CTI) \
 132           | CGEN_ATTR_MASK (CGEN_INSN_UNCOND_CTI))) \
 133       != 0)
 134 #define IDESC_SKIP_P(idesc) \
 135      ((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->opcode)) \
 136        & CGEN_ATTR_MASK (CGEN_INSN_SKIP_CTI)) \
 137       != 0)
 138
 139 /* These are used so that we can compile two copies of the semantic code,
 140    one with full feature support and one without that runs fast(er).  */
 141 #define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
 142 #define SEMF_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
 143
 144 #if WITH_SCACHE
 145
 146 #define CIA_ADDR(cia) (cia)
 147
 148 /* semantics.c support */
 149 #define SEM_ARGBUF(sem_arg) (& (sem_arg) -> argbuf)
 150 #define SEM_INSN(sem_arg) shouldnt_be_used
 151
 152 #if WITH_SCACHE_PBB
 153
 154 /* Return the scache pointer of the current insn.  */
 155 #define SEM_SEM_ARG(vpc, sc) (vpc)
 156 /* Return the virtual pc of the next insn to execute
 157    (assuming this isn't a cti).  */
 158 #define SEM_NEXT_VPC(sem_arg, pc, len) ((sem_arg) + 1)
 159
 160 /* Update the instruction counter.  */
 161 #define PBB_UPDATE_INSN_COUNT(cpu,sc) \
 162   (CPU_INSN_COUNT (cpu) += SEM_ARGBUF (sc) -> fields.chain.insn_count)
 163
 164 /* Value for br_addr_ptr indicating branch wasn't taken.  */
 165 #define SEM_BRANCH_UNTAKEN ((SEM_PC *) 0)
 166 /* Value for br_addr_ptr indicating branch was taken to uncacheable
 167    address (e.g. j reg).  */
 168 #define SEM_BRANCH_UNCACHEABLE ((SEM_PC *) 1)
 169
 170 /* Initialize next-pbb link for SEM_BRANCH_VIA_CACHE.  */
 171 #define SEM_BRANCH_INIT_EXTRACT(abuf) \
 172 do { (abuf)->fields.cti.addr_cache = 0; } while (0)
 173
 174 /* Do not append a `;' to invocations of this.
 175    npc,npc_ptr are for communication between the cti insn and cti-chain.  */
 176 #define SEM_BRANCH_INIT \
 177   PCADDR npc = 0; /* assign a value for -Wall */ \
 178   SEM_PC *npc_ptr = SEM_BRANCH_UNTAKEN;
 179 /* SEM_IN_SWITCH is defined at the top of the mainloop.c files
 180    generated by genmloop.sh.  It exists so generated semantic code needn't
 181    care whether it's being put in a switch or in a function.  */
 182 #ifdef SEM_IN_SWITCH
 183 #define SEM_BRANCH_FINI(pcvar) \
 184 do { \
 185   pbb_br_npc = npc; \
 186   pbb_br_npc_ptr = npc_ptr; \
 187 } while (0)
 188 #else /* 1 semantic function per instruction */
 189 #define SEM_BRANCH_FINI(pcvar) \
 190 do { \
 191   CPU_PBB_BR_NPC (current_cpu) = npc; \
 192   CPU_PBB_BR_NPC_PTR (current_cpu) = npc_ptr; \
 193 } while (0)
 194 #endif
 195
 196 /* Return address of cached branch address value.  */
 197 #define SEM_BRANCH_ADDR_CACHE(sem_arg) \
 198   (& SEM_ARGBUF (sem_arg)->fields.cti.addr_cache)
 199 #define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar, cachevarptr) \
 200 do { \
 201   npc = (newval); \
 202   npc_ptr = (cachevarptr); \
 203 } while (0)
 204 #define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
 205 do { \
 206   npc = (newval); \
 207   npc_ptr = SEM_BRANCH_UNCACHEABLE; \
 208 } while (0)
 209
 210 #else /* ! WITH_SCACHE_PBB */
 211
 212 #define SEM_SEM_ARG(vpc, sc) (sc)
 213 #define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
 214
 215 #define SEM_BRANCH_INIT_EXTRACT(abuf) do { } while (0)
 216
 217 #define SEM_BRANCH_INIT \
 218   int taken_p = 0;
 219 #ifndef TARGET_SEM_BRANCH_FINI(pcvar, taken_p)
 220 #define TARGET_SEM_BRANCH_FINI(pcvar, taken_p)
 221 #endif
 222 #define SEM_BRANCH_FINI(pcvar) \
 223   do { TARGET_SEM_BRANCH_FINI (pcvar, taken_p); } while (0)
 224
 225 #define SEM_BRANCH_ADDR_CACHE(sem_arg) shouldnt_be_used
 226 #define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar, cachevar) \
 227 do { \
 228   (pcvar) = (newval); \
 229   taken_p = 1; \
 230 } while (0)
 231 #define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
 232 do { \
 233   (pcvar) = (newval); \
 234   taken_p = 1; \
 235 } while (0)
 236
 237 #endif /* ! WITH_SCACHE_PBB */
 238
 239 #else /* ! WITH_SCACHE */
 240
 241 #define CIA_ADDR(cia) (cia)
 242
 243 /* semantics.c support */
 244 #define SEM_ARGBUF(sem_arg) (sem_arg)
 245 #define SEM_INSN(sem_arg) (SEM_ARGBUF (sem_arg) -> base_insn)
 246
 247 #define SEM_SEM_ARG(vpc, sc) (sc)
 248 #define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
 249
 250 #define SEM_BRANCH_INIT \
 251   int taken_p = 0;
 252 #ifndef TARGET_SEM_BRANCH_FINI
 253 #define TARGET_SEM_BRANCH_FINI(pcvar, taken_p)
 254 #endif
 255 #define SEM_BRANCH_FINI(pcvar) \
 256   do { TARGET_SEM_BRANCH_FINI (pcvar, taken_p); } while (0)
 257
 258 #define SEM_BRANCH_ADDR_CACHE(sem_arg) shouldnt_be_used
 259 #define SEM_BRANCH_VIA_CACHE(cpu, abuf, newval, pcvar, cachevar) \
 260 do { \
 261   (pcvar) = (newval); \
 262   taken_p = 1; \
 263 } while (0)
 264 #define SEM_BRANCH_VIA_ADDR(cpu, abuf, newval, pcvar) \
 265 do { \
 266   (pcvar) = (newval); \
 267   taken_p = 1; \
 268 } while (0)
 269
 270 #endif /* ! WITH_SCACHE */
 271 \f
 272 /* Tracing/profiling.  */
 273
 274 /* Return non-zero if a before/after handler is needed.
 275    When tracing/profiling a selected range there's no need to slow
 276    down simulation of the other insns (except to get more accurate data!).
 277
 278    ??? May wish to profile all insns if doing insn tracing, or to
 279    get more accurate cycle data.
 280
 281    First test ANY_P so we avoid a potentially expensive HIT_P call
 282    [if there are lots of address ranges].  */
 283
 284 #define PC_IN_TRACE_RANGE_P(cpu, pc) \
 285   (TRACE_ANY_P (cpu) \
 286    && ADDR_RANGE_HIT_P (TRACE_RANGE (CPU_TRACE_DATA (cpu)), (pc)))
 287 #define PC_IN_PROFILE_RANGE_P(cpu, pc) \
 288   (PROFILE_ANY_P (cpu) \
 289    && ADDR_RANGE_HIT_P (PROFILE_RANGE (CPU_PROFILE_DATA (cpu)), (pc)))
 290
 291 #endif /* CGEN_ENGINE_H */