sim/common/cgen-engine.h

   1 /* Engine header for Cpu tools GENerated simulators.
   2    Copyright (C) 1998, 1999, 2007, 2008, 2009 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 /* This file is included by ${cpu}.h.
  21    It needs CGEN_INSN_WORD which is defined by ${cpu}.h.
  22    ??? A lot of this could be moved to genmloop.sh to be put in eng.h
  23    and thus remove some conditional compilation.  We'd still need
  24    CGEN_INSN_WORD though.  */
  25
  26 /* Semantic functions come in six versions on two axes:
  27    fast/full-featured, and using one of the simple/scache/compilation engines.
  28    A full featured simulator is always provided.  --enable-sim-fast includes
  29    support for fast execution by duplicating the semantic code but leaving
  30    out all features like tracing and profiling.
  31    Using the scache is selected with --enable-sim-scache.  */
  32 /* FIXME: --enable-sim-fast not implemented yet.  */
  33 /* FIXME: undecided how to handle WITH_SCACHE_PBB.  */
  34
  35 /* There are several styles of engines, all generally supported by the
  36    same code:
  37
  38    WITH_SCACHE && WITH_SCACHE_PBB - pseudo-basic-block scaching
  39    WITH_SCACHE && !WITH_SCACHE_PBB - scaching on an insn by insn basis
  40    !WITH_SCACHE - simple engine: fetch an insn, execute an insn
  41
  42    The !WITH_SCACHE case can also be broken up into two flavours:
  43    extract the fields of the insn into an ARGBUF struct, or defer the
  44    extraction to the semantic handler.  The former can be viewed as the
  45    WITH_SCACHE case with a cache size of 1 (thus there's no need for a
  46    WITH_EXTRACTION macro).  The WITH_SCACHE case always extracts the fields
  47    into an ARGBUF struct.  */
  48
  49 #ifndef CGEN_ENGINE_H
  50 #define CGEN_ENGINE_H
  51
  52 /* Instruction field support macros.  */
  53
  54 #define EXTRACT_MSB0_INT(val, total, start, length) \
  55 (((INT) (val) << ((sizeof (INT) * 8) - (total) + (start))) \
  56  >> ((sizeof (INT) * 8) - (length)))
  57 #define EXTRACT_MSB0_UINT(val, total, start, length) \
  58 (((UINT) (val) << ((sizeof (UINT) * 8) - (total) + (start))) \
  59  >> ((sizeof (UINT) * 8) - (length)))
  60
  61 #define EXTRACT_LSB0_INT(val, total, start, length) \
  62 (((INT) (val) << ((sizeof (INT) * 8) - (start) - 1)) \
  63  >> ((sizeof (INT) * 8) - (length)))
  64 #define EXTRACT_LSB0_UINT(val, total, start, length) \
  65 (((UINT) (val) << ((sizeof (UINT) * 8) - (start) - 1)) \
  66  >> ((sizeof (UINT) * 8) - (length)))
  67
  68 #define EXTRACT_MSB0_LGSINT(val, total, start, length) \
  69 (((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (total) + (start))) \
  70  >> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length)))
  71 #define EXTRACT_MSB0_LGUINT(val, total, start, length) \
  72 (((CGEN_INSN_UINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (total) + (start))) \
  73  >> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length)))
  74
  75 #define EXTRACT_LSB0_LGSINT(val, total, start, length) \
  76 (((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (start) - 1)) \
  77  >> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length)))
  78 #define EXTRACT_LSB0_LGUINT(val, total, start, length) \
  79 (((CGEN_INSN_LGUINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (start) - 1)) \
  80  >> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length)))
  81 \f
  82 /* Semantic routines.  */
  83
  84 /* Type of the machine generated extraction fns.  */
  85 /* ??? No longer used.  */
  86 typedef void (EXTRACT_FN) (SIM_CPU *, IADDR, CGEN_INSN_WORD, ARGBUF *);
  87
  88 /* Type of the machine generated semantic fns.  */
  89
  90 #if WITH_SCACHE
  91
  92 /* Instruction fields are extracted into ARGBUF before calling the
  93    semantic routine.  */
  94 #if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE
  95 typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *);
  96 #else
  97 typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG);
  98 #endif
  99
 100 #else
 101
 102 /* Result of semantic routines is a status indicator (wip).  */
 103 typedef unsigned int SEM_STATUS;
 104
 105 /* Instruction fields are extracted by the semantic routine.
 106    ??? TODO: multi word insns.  */
 107 #if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE
 108 typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *, CGEN_INSN_WORD);
 109 #else
 110 typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, CGEN_INSN_WORD);
 111 #endif
 112
 113 #endif
 114
 115 /* In the ARGBUF struct, a pointer to the semantic routine for the insn.  */
 116
 117 union sem {
 118 #if ! WITH_SEM_SWITCH_FULL
 119   SEMANTIC_FN *sem_full;
 120 #endif
 121 #if ! WITH_SEM_SWITCH_FAST
 122   SEMANTIC_FN *sem_fast;
 123 #endif
 124 #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
 125 #ifdef __GNUC__
 126   void *sem_case;
 127 #else
 128   int sem_case;
 129 #endif
 130 #endif
 131 };
 132
 133 /* Set the appropriate semantic handler in ABUF.  */
 134
 135 #if WITH_SEM_SWITCH_FULL
 136 #ifdef __GNUC__
 137 #define SEM_SET_FULL_CODE(abuf, idesc) \
 138   do { (abuf)->semantic.sem_case = (idesc)->sem_full_lab; } while (0)
 139 #else
 140 #define SEM_SET_FULL_CODE(abuf, idesc) \
 141   do { (abuf)->semantic.sem_case = (idesc)->num; } while (0)
 142 #endif
 143 #else
 144 #define SEM_SET_FULL_CODE(abuf, idesc) \
 145   do { (abuf)->semantic.sem_full = (idesc)->sem_full; } while (0)
 146 #endif
 147
 148 #if WITH_SEM_SWITCH_FAST
 149 #ifdef __GNUC__
 150 #define SEM_SET_FAST_CODE(abuf, idesc) \
 151   do { (abuf)->semantic.sem_case = (idesc)->sem_fast_lab; } while (0)
 152 #else
 153 #define SEM_SET_FAST_CODE(abuf, idesc) \
 154   do { (abuf)->semantic.sem_case = (idesc)->num; } while (0)
 155 #endif
 156 #else
 157 #define SEM_SET_FAST_CODE(abuf, idesc) \
 158   do { (abuf)->semantic.sem_fast = (idesc)->sem_fast; } while (0)
 159 #endif
 160
 161 #define SEM_SET_CODE(abuf, idesc, fast_p) \
 162 do { \
 163   if (fast_p) \
 164     SEM_SET_FAST_CODE ((abuf), (idesc)); \
 165   else \
 166     SEM_SET_FULL_CODE ((abuf), (idesc)); \
 167 } while (0)
 168 \f
 169 /* Return non-zero if IDESC is a conditional or unconditional CTI.  */
 170
 171 #define IDESC_CTI_P(idesc) \
 172      ((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) \
 173        & (CGEN_ATTR_MASK (CGEN_INSN_COND_CTI) \
 174           | CGEN_ATTR_MASK (CGEN_INSN_UNCOND_CTI))) \
 175       != 0)
 176
 177 /* Return non-zero if IDESC is a skip insn.  */
 178
 179 #define IDESC_SKIP_P(idesc) \
 180      ((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) \
 181        & CGEN_ATTR_MASK (CGEN_INSN_SKIP_CTI)) \
 182       != 0)
 183
 184 /* Return pointer to ARGBUF given ptr to SCACHE.  */
 185 #define SEM_ARGBUF(sem_arg) (& (sem_arg) -> argbuf)
 186
 187 /* There are several styles of engines, all generally supported by the
 188    same code:
 189
 190    WITH_SCACHE && WITH_SCACHE_PBB - pseudo-basic-block scaching
 191    WITH_SCACHE && !WITH_SCACHE_PBB - scaching on an insn by insn basis
 192    !WITH_SCACHE - simple engine: fetch an insn, execute an insn
 193
 194    ??? The !WITH_SCACHE case can also be broken up into two flavours:
 195    extract the fields of the insn into an ARGBUF struct, or defer the
 196    extraction to the semantic handler.  The WITH_SCACHE case always
 197    extracts the fields into an ARGBUF struct.  */
 198
 199 #if WITH_SCACHE
 200
 201 #define CIA_ADDR(cia) (cia)
 202
 203 #if WITH_SCACHE_PBB
 204
 205 /* Return the scache pointer of the current insn.  */
 206 #define SEM_SEM_ARG(vpc, sc) (vpc)
 207
 208 /* Return the virtual pc of the next insn to execute
 209    (assuming this isn't a cti or the branch isn't taken).  */
 210 #define SEM_NEXT_VPC(sem_arg, pc, len) ((sem_arg) + 1)
 211
 212 /* Update the instruction counter.  */
 213 #define PBB_UPDATE_INSN_COUNT(cpu,sc) \
 214   (CPU_INSN_COUNT (cpu) += SEM_ARGBUF (sc) -> fields.chain.insn_count)
 215
 216 /* Do not append a `;' to invocations of this.
 217    npc,br_type are for communication between the cti insn and cti-chain.  */
 218 #define SEM_BRANCH_INIT \
 219   IADDR npc = 0; /* assign a value for -Wall */ \
 220   SEM_BRANCH_TYPE br_type = SEM_BRANCH_UNTAKEN;
 221
 222 /* SEM_IN_SWITCH is defined at the top of the mainloop.c files
 223    generated by genmloop.sh.  It exists so generated semantic code needn't
 224    care whether it's being put in a switch or in a function.  */
 225 #ifdef SEM_IN_SWITCH
 226 #define SEM_BRANCH_FINI(pcvar) \
 227 do { \
 228   pbb_br_npc = npc; \
 229   pbb_br_type = br_type; \
 230 } while (0)
 231 #else /* 1 semantic function per instruction */
 232 #define SEM_BRANCH_FINI(pcvar) \
 233 do { \
 234   CPU_PBB_BR_NPC (current_cpu) = npc; \
 235   CPU_PBB_BR_TYPE (current_cpu) = br_type; \
 236 } while (0)
 237 #endif
 238
 239 #define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \
 240 do { \
 241   npc = (newval); \
 242   br_type = SEM_BRANCH_CACHEABLE; \
 243 } while (0)
 244
 245 #define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
 246 do { \
 247   npc = (newval); \
 248   br_type = SEM_BRANCH_UNCACHEABLE; \
 249 } while (0)
 250
 251 #define SEM_SKIP_COMPILE(cpu, sc, skip) \
 252 do { \
 253   SEM_ARGBUF (sc) -> skip_count = (skip); \
 254 } while (0)
 255
 256 #define SEM_SKIP_INSN(cpu, sc, vpcvar) \
 257 do { \
 258   (vpcvar) += SEM_ARGBUF (sc) -> skip_count; \
 259 } while (0)
 260
 261 #else /* ! WITH_SCACHE_PBB */
 262
 263 #define SEM_SEM_ARG(vpc, sc) (sc)
 264
 265 #define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
 266
 267 /* ??? May wish to move taken_p out of here and make it explicit.  */
 268 #define SEM_BRANCH_INIT \
 269   int taken_p = 0;
 270
 271 #ifndef TARGET_SEM_BRANCH_FINI
 272 #define TARGET_SEM_BRANCH_FINI(pcvar, taken_p)
 273 #endif
 274 #define SEM_BRANCH_FINI(pcvar) \
 275   do { TARGET_SEM_BRANCH_FINI (pcvar, taken_p); } while (0)
 276
 277 #define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \
 278 do { \
 279   (pcvar) = (newval); \
 280   taken_p = 1; \
 281 } while (0)
 282
 283 #define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
 284 do { \
 285   (pcvar) = (newval); \
 286   taken_p = 1; \
 287 } while (0)
 288
 289 #endif /* ! WITH_SCACHE_PBB */
 290
 291 #else /* ! WITH_SCACHE */
 292
 293 /* This is the "simple" engine case.  */
 294
 295 #define CIA_ADDR(cia) (cia)
 296
 297 #define SEM_SEM_ARG(vpc, sc) (sc)
 298
 299 #define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
 300
 301 #define SEM_BRANCH_INIT \
 302   int taken_p = 0;
 303
 304 #define SEM_BRANCH_VIA_CACHE(cpu, abuf, newval, pcvar) \
 305 do { \
 306   (pcvar) = (newval); \
 307   taken_p = 1; \
 308 } while (0)
 309
 310 #define SEM_BRANCH_VIA_ADDR(cpu, abuf, newval, pcvar) \
 311 do { \
 312   (pcvar) = (newval); \
 313   taken_p = 1; \
 314 } while (0)
 315
 316 /* Finish off branch insns.
 317    The target must define TARGET_SEM_BRANCH_FINI.
 318    ??? This can probably go away when define-execute is finished.  */
 319 #define SEM_BRANCH_FINI(pcvar, bool_attrs) \
 320   do { TARGET_SEM_BRANCH_FINI ((pcvar), (bool_attrs), taken_p); } while (0)
 321
 322 /* Finish off non-branch insns.
 323    The target must define TARGET_SEM_NBRANCH_FINI.
 324    ??? This can probably go away when define-execute is finished.  */
 325 #define SEM_NBRANCH_FINI(pcvar, bool_attrs) \
 326   do { TARGET_SEM_NBRANCH_FINI ((pcvar), (bool_attrs)); } while (0)
 327
 328 #endif /* ! WITH_SCACHE */
 329 \f
 330 /* Instruction information.  */
 331
 332 /* Sanity check, at most one of these may be true.  */
 333 #if WITH_PARALLEL_READ + WITH_PARALLEL_WRITE + WITH_PARALLEL_GENWRITE > 1
 334 #error "At most one of WITH_PARALLEL_{READ,WRITE,GENWRITE} can be true."
 335 #endif
 336
 337 /* Compile time computable instruction data.  */
 338
 339 struct insn_sem {
 340   /* The instruction type (a number that identifies each insn over the
 341      entire architecture).  */
 342   CGEN_INSN_TYPE type;
 343
 344   /* Index in IDESC table.  */
 345   int index;
 346
 347   /* Semantic format number.  */
 348   int sfmt;
 349
 350 #if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_ONLY
 351   /* Index in IDESC table of parallel handler.  */
 352   int par_index;
 353 #endif
 354
 355 #if WITH_PARALLEL_READ
 356   /* Index in IDESC table of read handler.  */
 357   int read_index;
 358 #endif
 359
 360 #if WITH_PARALLEL_WRITE
 361   /* Index in IDESC table of writeback handler.  */
 362   int write_index;
 363 #endif
 364 };
 365
 366 /* Entry in semantic function table.
 367    This information is copied to the insn descriptor table at run-time.  */
 368
 369 struct sem_fn_desc {
 370   /* Index in IDESC table.  */
 371   int index;
 372
 373   /* Function to perform the semantics of the insn.  */
 374   SEMANTIC_FN *fn;
 375 };
 376
 377 /* Run-time computed instruction descriptor.  */
 378
 379 struct idesc {
 380 #if WITH_SEM_SWITCH_FAST
 381 #ifdef __GNUC__
 382   void *sem_fast_lab;
 383 #else
 384   /* nothing needed, switch's on `num' member */
 385 #endif
 386 #else
 387   SEMANTIC_FN *sem_fast;
 388 #endif
 389
 390 #if WITH_SEM_SWITCH_FULL
 391 #ifdef __GNUC__
 392   void *sem_full_lab;
 393 #else
 394   /* nothing needed, switch's on `num' member */
 395 #endif
 396 #else
 397   SEMANTIC_FN *sem_full;
 398 #endif
 399
 400   /* Parallel support.  */
 401 #if HAVE_PARALLEL_INSNS && (! WITH_PARALLEL_ONLY || (WITH_PARALLEL_ONLY && ! WITH_PARALLEL_GENWRITE))
 402   /* Pointer to parallel handler if serial insn.
 403      Pointer to readahead/writeback handler if parallel insn.  */
 404   struct idesc *par_idesc;
 405 #endif
 406
 407   /* Instruction number (index in IDESC table, profile table).
 408      Also used to switch on in non-gcc semantic switches.  */
 409   int num;
 410
 411   /* Semantic format id.  */
 412   int sfmt;
 413
 414   /* instruction data (name, attributes, size, etc.) */
 415   const CGEN_INSN *idata;
 416
 417   /* instruction attributes, copied from `idata' for speed */
 418   const CGEN_INSN_ATTR_TYPE *attrs;
 419
 420   /* instruction length in bytes, copied from `idata' for speed */
 421   int length;
 422
 423   /* profiling/modelling support */
 424   const INSN_TIMING *timing;
 425 };
 426 \f
 427 /* Tracing/profiling.  */
 428
 429 /* Return non-zero if a before/after handler is needed.
 430    When tracing/profiling a selected range there's no need to slow
 431    down simulation of the other insns (except to get more accurate data!).
 432
 433    ??? May wish to profile all insns if doing insn tracing, or to
 434    get more accurate cycle data.
 435
 436    First test ANY_P so we avoid a potentially expensive HIT_P call
 437    [if there are lots of address ranges].  */
 438
 439 #define PC_IN_TRACE_RANGE_P(cpu, pc) \
 440   (TRACE_ANY_P (cpu) \
 441    && ADDR_RANGE_HIT_P (TRACE_RANGE (CPU_TRACE_DATA (cpu)), (pc)))
 442 #define PC_IN_PROFILE_RANGE_P(cpu, pc) \
 443   (PROFILE_ANY_P (cpu) \
 444    && ADDR_RANGE_HIT_P (PROFILE_RANGE (CPU_PROFILE_DATA (cpu)), (pc)))
 445
 446 #endif /* CGEN_ENGINE_H */