1 /* Simulator header for cgen parallel support.
2 Copyright (C) 1999 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of the GNU instruction set simulator.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* Kinds of writes stored on the write queue. */
25 enum cgen_write_queue_kind
{
26 CGEN_BI_WRITE
, CGEN_QI_WRITE
, CGEN_SI_WRITE
, CGEN_SF_WRITE
,
28 CGEN_FN_HI_WRITE
, CGEN_FN_SI_WRITE
, CGEN_FN_DI_WRITE
, CGEN_FN_DF_WRITE
,
29 CGEN_FN_XI_WRITE
, CGEN_FN_PC_WRITE
,
30 CGEN_MEM_QI_WRITE
, CGEN_MEM_HI_WRITE
, CGEN_MEM_SI_WRITE
, CGEN_MEM_DI_WRITE
,
31 CGEN_MEM_DF_WRITE
, CGEN_MEM_XI_WRITE
,
32 CGEN_FN_MEM_QI_WRITE
, CGEN_FN_MEM_HI_WRITE
, CGEN_FN_MEM_SI_WRITE
,
33 CGEN_FN_MEM_DI_WRITE
, CGEN_FN_MEM_DF_WRITE
, CGEN_FN_MEM_XI_WRITE
,
37 /* Element of the write queue. */
39 enum cgen_write_queue_kind kind
; /* Used to select union member below. */
40 IADDR insn_address
; /* Address of the insn performing the write. */
64 void (*function
)(SIM_CPU
*, UINT
, UHI
);
69 void (*function
)(SIM_CPU
*, UINT
, USI
);
74 void (*function
)(SIM_CPU
*, UINT
, DI
);
79 void (*function
)(SIM_CPU
*, UINT
, DF
);
84 void (*function
)(SIM_CPU
*, UINT
, SI
*);
88 void (*function
)(SIM_CPU
*, USI
);
117 void (*function
)(SIM_CPU
*, IADDR
, SI
, QI
);
122 void (*function
)(SIM_CPU
*, IADDR
, SI
, HI
);
127 void (*function
)(SIM_CPU
*, IADDR
, SI
, SI
);
132 void (*function
)(SIM_CPU
*, IADDR
, SI
, DI
);
137 void (*function
)(SIM_CPU
*, IADDR
, SI
, DF
);
142 void (*function
)(SIM_CPU
*, IADDR
, SI
, SI
*);
145 } CGEN_WRITE_QUEUE_ELEMENT
;
147 #define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
148 #define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address)
150 extern void cgen_write_queue_element_execute (
151 SIM_CPU
*, CGEN_WRITE_QUEUE_ELEMENT
*
154 /* Instance of the queue for parallel write-after support. */
155 /* FIXME: Should be dynamic? */
156 #define CGEN_WRITE_QUEUE_SIZE (64 * 4) /* 64 writes x 4 insns -- for now. */
160 CGEN_WRITE_QUEUE_ELEMENT q
[CGEN_WRITE_QUEUE_SIZE
];
163 #define CGEN_WRITE_QUEUE_CLEAR(queue) ((queue)->index = 0)
164 #define CGEN_WRITE_QUEUE_INDEX(queue) ((queue)->index)
165 #define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])
167 #define CGEN_WRITE_QUEUE_NEXT(queue) ( \
168 (queue)->index < CGEN_WRITE_QUEUE_SIZE \
169 ? &(queue)->q[(queue)->index++] \
170 : cgen_write_queue_overflow (queue) \
173 extern CGEN_WRITE_QUEUE_ELEMENT
*cgen_write_queue_overflow (CGEN_WRITE_QUEUE
*);
175 /* Functions for queuing writes. Used by semantic code. */
176 extern void sim_queue_bi_write (SIM_CPU
*, BI
*, BI
);
177 extern void sim_queue_qi_write (SIM_CPU
*, UQI
*, UQI
);
178 extern void sim_queue_si_write (SIM_CPU
*, SI
*, SI
);
179 extern void sim_queue_sf_write (SIM_CPU
*, SI
*, SF
);
181 extern void sim_queue_pc_write (SIM_CPU
*, USI
);
183 extern void sim_queue_fn_hi_write (SIM_CPU
*, void (*)(SIM_CPU
*, UINT
, UHI
), UINT
, UHI
);
184 extern void sim_queue_fn_si_write (SIM_CPU
*, void (*)(SIM_CPU
*, UINT
, USI
), UINT
, SI
);
185 extern void sim_queue_fn_di_write (SIM_CPU
*, void (*)(SIM_CPU
*, UINT
, DI
), UINT
, DI
);
186 extern void sim_queue_fn_df_write (SIM_CPU
*, void (*)(SIM_CPU
*, UINT
, DF
), UINT
, DF
);
187 extern void sim_queue_fn_xi_write (SIM_CPU
*, void (*)(SIM_CPU
*, UINT
, SI
*), UINT
, SI
*);
188 extern void sim_queue_fn_pc_write (SIM_CPU
*, void (*)(SIM_CPU
*, USI
), USI
);
190 extern void sim_queue_mem_qi_write (SIM_CPU
*, SI
, QI
);
191 extern void sim_queue_mem_hi_write (SIM_CPU
*, SI
, HI
);
192 extern void sim_queue_mem_si_write (SIM_CPU
*, SI
, SI
);
193 extern void sim_queue_mem_di_write (SIM_CPU
*, SI
, DI
);
194 extern void sim_queue_mem_df_write (SIM_CPU
*, SI
, DF
);
195 extern void sim_queue_mem_xi_write (SIM_CPU
*, SI
, SI
*);
197 extern void sim_queue_fn_mem_qi_write (SIM_CPU
*, void (*)(SIM_CPU
*, IADDR
, SI
, QI
), SI
, QI
);
198 extern void sim_queue_fn_mem_hi_write (SIM_CPU
*, void (*)(SIM_CPU
*, IADDR
, SI
, HI
), SI
, HI
);
199 extern void sim_queue_fn_mem_si_write (SIM_CPU
*, void (*)(SIM_CPU
*, IADDR
, SI
, SI
), SI
, SI
);
200 extern void sim_queue_fn_mem_di_write (SIM_CPU
*, void (*)(SIM_CPU
*, IADDR
, SI
, DI
), SI
, DI
);
201 extern void sim_queue_fn_mem_df_write (SIM_CPU
*, void (*)(SIM_CPU
*, IADDR
, SI
, DF
), SI
, DF
);
202 extern void sim_queue_fn_mem_xi_write (SIM_CPU
*, void (*)(SIM_CPU
*, IADDR
, SI
, SI
*), SI
, SI
*);
204 #endif /* CGEN_PAR_H */