1 /* Simulator header for cgen parallel support.
2 Copyright (C) 1999 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of the GNU instruction set simulator.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* Kinds of writes stored on the write queue. */
25 enum cgen_write_queue_kind
{
26 CGEN_BI_WRITE
, CGEN_QI_WRITE
, CGEN_SI_WRITE
, CGEN_SF_WRITE
,
28 CGEN_FN_HI_WRITE
, CGEN_FN_SI_WRITE
, CGEN_FN_DI_WRITE
, CGEN_FN_DF_WRITE
,
29 CGEN_FN_XI_WRITE
, CGEN_FN_PC_WRITE
,
30 CGEN_MEM_QI_WRITE
, CGEN_MEM_HI_WRITE
, CGEN_MEM_SI_WRITE
, CGEN_MEM_DI_WRITE
,
31 CGEN_MEM_DF_WRITE
, CGEN_MEM_XI_WRITE
,
35 /* Element of the write queue. */
37 enum cgen_write_queue_kind kind
; /* Used to select union member below. */
38 IADDR insn_address
; /* Address of the insn performing the write. */
62 void (*function
)(SIM_CPU
*, UINT
, UHI
);
67 void (*function
)(SIM_CPU
*, UINT
, USI
);
72 void (*function
)(SIM_CPU
*, UINT
, DI
);
77 void (*function
)(SIM_CPU
*, UINT
, DI
);
82 void (*function
)(SIM_CPU
*, UINT
, SI
*);
86 void (*function
)(SIM_CPU
*, USI
);
113 } CGEN_WRITE_QUEUE_ELEMENT
;
115 #define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
116 #define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address)
118 extern void cgen_write_queue_element_execute (
119 SIM_CPU
*, CGEN_WRITE_QUEUE_ELEMENT
*
122 /* Instance of the queue for parallel write-after support. */
123 /* FIXME: Should be dynamic? */
124 #define CGEN_WRITE_QUEUE_SIZE (4 * 4) /* 4 writes x 4 insns -- for now. */
128 CGEN_WRITE_QUEUE_ELEMENT q
[CGEN_WRITE_QUEUE_SIZE
];
131 #define CGEN_WRITE_QUEUE_CLEAR(queue) ((queue)->index = 0)
132 #define CGEN_WRITE_QUEUE_INDEX(queue) ((queue)->index)
133 #define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])
135 #define CGEN_WRITE_QUEUE_NEXT(queue) ( \
136 (queue)->index < CGEN_WRITE_QUEUE_SIZE \
137 ? &(queue)->q[(queue)->index++] \
138 : cgen_write_queue_overflow (queue) \
141 extern CGEN_WRITE_QUEUE_ELEMENT
*cgen_write_queue_overflow (CGEN_WRITE_QUEUE
*);
143 /* Functions for queuing writes. Used by semantic code. */
144 extern void sim_queue_bi_write (SIM_CPU
*, BI
*, BI
);
145 extern void sim_queue_qi_write (SIM_CPU
*, UQI
*, UQI
);
146 extern void sim_queue_si_write (SIM_CPU
*, SI
*, SI
);
147 extern void sim_queue_sf_write (SIM_CPU
*, SI
*, SF
);
149 extern void sim_queue_pc_write (SIM_CPU
*, USI
);
151 extern void sim_queue_fn_hi_write (SIM_CPU
*, void (*)(SIM_CPU
*, UINT
, UHI
), UINT
, UHI
);
152 extern void sim_queue_fn_si_write (SIM_CPU
*, void (*)(SIM_CPU
*, UINT
, USI
), UINT
, SI
);
153 extern void sim_queue_fn_di_write (SIM_CPU
*, void (*)(SIM_CPU
*, UINT
, DI
), UINT
, DI
);
154 extern void sim_queue_fn_df_write (SIM_CPU
*, void (*)(SIM_CPU
*, UINT
, DI
), UINT
, DF
);
155 extern void sim_queue_fn_xi_write (SIM_CPU
*, void (*)(SIM_CPU
*, UINT
, SI
*), UINT
, SI
*);
156 extern void sim_queue_fn_pc_write (SIM_CPU
*, void (*)(SIM_CPU
*, USI
), USI
);
158 extern void sim_queue_mem_qi_write (SIM_CPU
*, SI
, QI
);
159 extern void sim_queue_mem_hi_write (SIM_CPU
*, SI
, HI
);
160 extern void sim_queue_mem_si_write (SIM_CPU
*, SI
, SI
);
161 extern void sim_queue_mem_di_write (SIM_CPU
*, SI
, DI
);
162 extern void sim_queue_mem_df_write (SIM_CPU
*, SI
, DF
);
163 extern void sim_queue_mem_xi_write (SIM_CPU
*, SI
, SI
*);
165 #endif /* CGEN_PAR_H */