sim/common/cgen-par.h

   1 /* Simulator header for cgen parallel support.
   2    Copyright (C) 1999 Free Software Foundation, Inc.
   3    Contributed by Cygnus Solutions.
   4
   5 This file is part of the GNU instruction set simulator.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef CGEN_PAR_H
  22 #define CGEN_PAR_H
  23
  24 /* Kinds of writes stored on the write queue.  */
  25 enum cgen_write_queue_kind {
  26   CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
  27   CGEN_PC_WRITE,
  28   CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
  29   CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE,
  30   CGEN_NUM_WRITE_KINDS
  31 };
  32
  33 /* Element of the write queue.  */
  34 typedef struct {
  35   enum cgen_write_queue_kind kind; /* Used to select union member below.  */
  36   union {
  37     struct {
  38       BI  *target;
  39       BI   value;
  40     } bi_write;
  41     struct {
  42       UQI *target;
  43       QI   value;
  44     } qi_write;
  45     struct {
  46       SI *target;
  47       SI  value;
  48     } si_write;
  49     struct {
  50       SI *target;
  51       SF  value;
  52     } sf_write;
  53     struct {
  54       USI value;
  55     } pc_write;
  56     struct {
  57       UINT regno;
  58       UHI   value;
  59       void (*function)(SIM_CPU *, UINT, UHI);
  60     } fn_hi_write;
  61     struct {
  62       UINT regno;
  63       SI   value;
  64       void (*function)(SIM_CPU *, UINT, USI);
  65     } fn_si_write;
  66     struct {
  67       UINT regno;
  68       DI   value;
  69       void (*function)(SIM_CPU *, UINT, DI);
  70     } fn_di_write;
  71     struct {
  72       UINT regno;
  73       DI   value;
  74       void (*function)(SIM_CPU *, UINT, DI);
  75     } fn_df_write;
  76     struct {
  77       SI   address;
  78       QI   value;
  79     } mem_qi_write;
  80     struct {
  81       SI   address;
  82       HI   value;
  83     } mem_hi_write;
  84     struct {
  85       SI   address;
  86       SI   value;
  87     } mem_si_write;
  88   } kinds;
  89 } CGEN_WRITE_QUEUE_ELEMENT;
  90
  91 #define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
  92
  93 extern void cgen_write_queue_element_execute (
  94   SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *
  95 );
  96
  97 /* Instance of the queue for parallel write-after support.  */
  98 /* FIXME: Should be dynamic?  */
  99 #define CGEN_WRITE_QUEUE_SIZE (4 * 4) /* 4 writes x 4 insns -- for now.  */
 100
 101 typedef struct {
 102   int index;
 103   CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE];
 104 } CGEN_WRITE_QUEUE;
 105
 106 #define CGEN_WRITE_QUEUE_CLEAR(queue)       ((queue)->index = 0)
 107 #define CGEN_WRITE_QUEUE_INDEX(queue)       ((queue)->index)
 108 #define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])
 109
 110 #define CGEN_WRITE_QUEUE_NEXT(queue) (   \
 111   (queue)->index < CGEN_WRITE_QUEUE_SIZE \
 112     ? &(queue)->q[(queue)->index++]      \
 113     : cgen_write_queue_overflow (queue)  \
 114 )
 115
 116 extern CGEN_WRITE_QUEUE_ELEMENT *cgen_write_queue_overflow (CGEN_WRITE_QUEUE *);
 117
 118 /* Functions for queuing writes.  Used by semantic code.  */
 119 extern void sim_queue_bi_write (SIM_CPU *, BI *, BI);
 120 extern void sim_queue_qi_write (SIM_CPU *, UQI *, UQI);
 121 extern void sim_queue_si_write (SIM_CPU *, SI *, SI);
 122 extern void sim_queue_sf_write (SIM_CPU *, SI *, SF);
 123
 124 extern void sim_queue_pc_write (SIM_CPU *, USI);
 125
 126 extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UINT, UHI);
 127 extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, SI);
 128 extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI);
 129 extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DF);
 130
 131 extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
 132 extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
 133 extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);
 134
 135 #endif /* CGEN_PAR_H */