sim/common/cgen-par.h

   1 /* Simulator header for cgen parallel support.
   2    Copyright (C) 1999 Free Software Foundation, Inc.
   3    Contributed by Cygnus Solutions.
   4
   5 This file is part of the GNU instruction set simulator.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef CGEN_PAR_H
  22 #define CGEN_PAR_H
  23
  24 /* Kinds of writes stored on the write queue.  */
  25 enum cgen_write_queue_kind {
  26   CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
  27   CGEN_PC_WRITE,
  28   CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
  29   CGEN_FN_XI_WRITE, CGEN_FN_PC_WRITE,
  30   CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE, CGEN_MEM_DI_WRITE,
  31   CGEN_MEM_DF_WRITE, CGEN_MEM_XI_WRITE,
  32   CGEN_FN_MEM_QI_WRITE, CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE,
  33   CGEN_FN_MEM_DI_WRITE, CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE,
  34   CGEN_NUM_WRITE_KINDS
  35 };
  36
  37 /* Element of the write queue.  */
  38 typedef struct {
  39   enum cgen_write_queue_kind kind; /* Used to select union member below.  */
  40   IADDR insn_address;       /* Address of the insn performing the write.  */
  41   union {
  42     struct {
  43       BI  *target;
  44       BI   value;
  45     } bi_write;
  46     struct {
  47       UQI *target;
  48       QI   value;
  49     } qi_write;
  50     struct {
  51       SI *target;
  52       SI  value;
  53     } si_write;
  54     struct {
  55       SI *target;
  56       SF  value;
  57     } sf_write;
  58     struct {
  59       USI value;
  60     } pc_write;
  61     struct {
  62       UINT regno;
  63       UHI   value;
  64       void (*function)(SIM_CPU *, UINT, UHI);
  65     } fn_hi_write;
  66     struct {
  67       UINT regno;
  68       SI   value;
  69       void (*function)(SIM_CPU *, UINT, USI);
  70     } fn_si_write;
  71     struct {
  72       UINT regno;
  73       DI   value;
  74       void (*function)(SIM_CPU *, UINT, DI);
  75     } fn_di_write;
  76     struct {
  77       UINT regno;
  78       DF   value;
  79       void (*function)(SIM_CPU *, UINT, DF);
  80     } fn_df_write;
  81     struct {
  82       UINT regno;
  83       SI   value[4];
  84       void (*function)(SIM_CPU *, UINT, SI *);
  85     } fn_xi_write;
  86     struct {
  87       USI  value;
  88       void (*function)(SIM_CPU *, USI);
  89     } fn_pc_write;
  90     struct {
  91       SI   address;
  92       QI   value;
  93     } mem_qi_write;
  94     struct {
  95       SI   address;
  96       HI   value;
  97     } mem_hi_write;
  98     struct {
  99       SI   address;
 100       SI   value;
 101     } mem_si_write;
 102     struct {
 103       SI   address;
 104       DI   value;
 105     } mem_di_write;
 106     struct {
 107       SI   address;
 108       DF   value;
 109     } mem_df_write;
 110     struct {
 111       SI   address;
 112       SI   value[4];
 113     } mem_xi_write;
 114     struct {
 115       SI   address;
 116       QI   value;
 117       void (*function)(SIM_CPU *, IADDR, SI, QI);
 118     } fn_mem_qi_write;
 119     struct {
 120       SI   address;
 121       HI   value;
 122       void (*function)(SIM_CPU *, IADDR, SI, HI);
 123     } fn_mem_hi_write;
 124     struct {
 125       SI   address;
 126       SI   value;
 127       void (*function)(SIM_CPU *, IADDR, SI, SI);
 128     } fn_mem_si_write;
 129     struct {
 130       SI   address;
 131       DI   value;
 132       void (*function)(SIM_CPU *, IADDR, SI, DI);
 133     } fn_mem_di_write;
 134     struct {
 135       SI   address;
 136       DF   value;
 137       void (*function)(SIM_CPU *, IADDR, SI, DF);
 138     } fn_mem_df_write;
 139     struct {
 140       SI   address;
 141       SI   value[4];
 142       void (*function)(SIM_CPU *, IADDR, SI, SI *);
 143     } fn_mem_xi_write;
 144   } kinds;
 145 } CGEN_WRITE_QUEUE_ELEMENT;
 146
 147 #define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
 148 #define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address)
 149
 150 extern void cgen_write_queue_element_execute (
 151   SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *
 152 );
 153
 154 /* Instance of the queue for parallel write-after support.  */
 155 /* FIXME: Should be dynamic?  */
 156 #define CGEN_WRITE_QUEUE_SIZE (64 * 4) /* 64 writes x 4 insns -- for now.  */
 157
 158 typedef struct {
 159   int index;
 160   CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE];
 161 } CGEN_WRITE_QUEUE;
 162
 163 #define CGEN_WRITE_QUEUE_CLEAR(queue)       ((queue)->index = 0)
 164 #define CGEN_WRITE_QUEUE_INDEX(queue)       ((queue)->index)
 165 #define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])
 166
 167 #define CGEN_WRITE_QUEUE_NEXT(queue) (   \
 168   (queue)->index < CGEN_WRITE_QUEUE_SIZE \
 169     ? &(queue)->q[(queue)->index++]      \
 170     : cgen_write_queue_overflow (queue)  \
 171 )
 172
 173 extern CGEN_WRITE_QUEUE_ELEMENT *cgen_write_queue_overflow (CGEN_WRITE_QUEUE *);
 174
 175 /* Functions for queuing writes.  Used by semantic code.  */
 176 extern void sim_queue_bi_write (SIM_CPU *, BI *, BI);
 177 extern void sim_queue_qi_write (SIM_CPU *, UQI *, UQI);
 178 extern void sim_queue_si_write (SIM_CPU *, SI *, SI);
 179 extern void sim_queue_sf_write (SIM_CPU *, SI *, SF);
 180
 181 extern void sim_queue_pc_write (SIM_CPU *, USI);
 182
 183 extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UINT, UHI);
 184 extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, SI);
 185 extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI);
 186 extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DF), UINT, DF);
 187 extern void sim_queue_fn_xi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SI *), UINT, SI *);
 188 extern void sim_queue_fn_pc_write (SIM_CPU *, void (*)(SIM_CPU *, USI), USI);
 189
 190 extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
 191 extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
 192 extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);
 193 extern void sim_queue_mem_di_write (SIM_CPU *, SI, DI);
 194 extern void sim_queue_mem_df_write (SIM_CPU *, SI, DF);
 195 extern void sim_queue_mem_xi_write (SIM_CPU *, SI, SI *);
 196
 197 extern void sim_queue_fn_mem_qi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, QI), SI, QI);
 198 extern void sim_queue_fn_mem_hi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, HI), SI, HI);
 199 extern void sim_queue_fn_mem_si_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI), SI, SI);
 200 extern void sim_queue_fn_mem_di_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DI), SI, DI);
 201 extern void sim_queue_fn_mem_df_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DF), SI, DF);
 202 extern void sim_queue_fn_mem_xi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI *), SI, SI *);
 203
 204 #endif /* CGEN_PAR_H */