1 /* Tracing support for CGEN-based simulators.
2 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #define min(a,b) ((a) < (b) ? (a) : (b))
29 #ifndef SIZE_INSTRUCTION
30 #define SIZE_INSTRUCTION 16
34 #define SIZE_LOCATION 20
41 #ifndef SIZE_LINE_NUMBER
42 #define SIZE_LINE_NUMBER 4
45 #ifndef SIZE_CYCLE_COUNT
46 #define SIZE_CYCLE_COUNT 2
49 #ifndef SIZE_TOTAL_CYCLE_COUNT
50 #define SIZE_TOTAL_CYCLE_COUNT 9
53 #ifndef SIZE_TRACE_BUF
54 #define SIZE_TRACE_BUF 1024
58 disassemble_insn (SIM_CPU
*, const CGEN_INSN
*,
59 const struct argbuf
*, IADDR
, char *);
61 /* Text is queued in TRACE_BUF because we want to output the insn's cycle
62 count first but that isn't known until after the insn has executed.
63 This also handles the queueing of trace results, TRACE_RESULT may be
64 called multiple times for one insn. */
65 static char trace_buf
[SIZE_TRACE_BUF
];
66 /* If NULL, output to stdout directly. */
69 /* Non-zero if this is the first insn in a set of parallel insns. */
70 static int first_insn_p
;
72 /* For communication between trace_insn and trace_result. */
73 static int printed_result_p
;
75 /* Insn and its extracted fields.
76 Set by trace_insn, used by trace_insn_fini.
77 ??? Move to SIM_CPU to support heterogeneous multi-cpu case. */
78 static const struct cgen_insn
*current_insn
;
79 static const struct argbuf
*current_abuf
;
82 trace_insn_init (SIM_CPU
*cpu
, int first_p
)
86 first_insn_p
= first_p
;
88 /* Set to NULL so trace_insn_fini can know if trace_insn was called. */
94 trace_insn_fini (SIM_CPU
*cpu
, const struct argbuf
*abuf
, int last_p
)
96 SIM_DESC sd
= CPU_STATE (cpu
);
98 /* Was insn traced? It might not be if trace ranges are in effect. */
99 if (current_insn
== NULL
)
102 /* The first thing printed is current and total cycle counts. */
104 if (PROFILE_MODEL_P (cpu
)
105 && ARGBUF_PROFILE_P (current_abuf
))
107 unsigned long total
= PROFILE_MODEL_TOTAL_CYCLES (CPU_PROFILE_DATA (cpu
));
108 unsigned long this_insn
= PROFILE_MODEL_CUR_INSN_CYCLES (CPU_PROFILE_DATA (cpu
));
112 trace_printf (sd
, cpu
, "%-*ld %-*ld ",
113 SIZE_CYCLE_COUNT
, this_insn
,
114 SIZE_TOTAL_CYCLE_COUNT
, total
);
118 trace_printf (sd
, cpu
, "%-*ld %-*s ",
119 SIZE_CYCLE_COUNT
, this_insn
,
120 SIZE_TOTAL_CYCLE_COUNT
, "---");
124 /* Print the disassembled insn. */
126 trace_printf (sd
, cpu
, "%s", TRACE_PREFIX (CPU_TRACE_DATA (cpu
)));
129 /* Print insn results. */
131 const CGEN_OPINST
*opinst
= CGEN_INSN_OPERANDS (current_insn
);
136 int indices
[MAX_OPERAND_INSTANCES
];
138 /* Fetch the operands used by the insn. */
139 /* FIXME: Add fn ptr to CGEN_CPU_DESC. */
140 CGEN_SYM (get_insn_operands
) (CPU_CPU_DESC (cpu
), current_insn
,
141 0, CGEN_FIELDS_BITSIZE (&insn_fields
),
145 CGEN_OPINST_TYPE (opinst
) != CGEN_OPINST_END
;
148 if (CGEN_OPINST_TYPE (opinst
) == CGEN_OPINST_OUTPUT
)
149 trace_result (cpu
, current_insn
, opinst
, indices
[i
]);
155 /* Print anything else requested. */
158 trace_printf (sd
, cpu
, " %s\n", trace_buf
);
160 trace_printf (sd
, cpu
, "\n");
164 trace_insn (SIM_CPU
*cpu
, const struct cgen_insn
*opcode
,
165 const struct argbuf
*abuf
, IADDR pc
)
169 printed_result_p
= 0;
170 current_insn
= opcode
;
173 if (CGEN_INSN_VIRTUAL_P (opcode
))
175 trace_prefix (CPU_STATE (cpu
), cpu
, NULL_CIA
, pc
, 0,
176 NULL
, 0, CGEN_INSN_NAME (opcode
));
180 CPU_DISASSEMBLER (cpu
) (cpu
, opcode
, abuf
, pc
, disasm_buf
);
181 trace_prefix (CPU_STATE (cpu
), cpu
, NULL_CIA
, pc
, TRACE_LINENUM_P (cpu
),
184 first_insn_p
? " " : "|",
185 SIZE_INSTRUCTION
, disasm_buf
);
189 trace_extract (SIM_CPU
*cpu
, IADDR pc
, char *name
, ...)
192 int printed_one_p
= 0;
195 va_start (args
, name
);
197 trace_printf (CPU_STATE (cpu
), cpu
, "Extract: 0x%.*lx: %s ",
203 fmt
= va_arg (args
, char *);
208 trace_printf (CPU_STATE (cpu
), cpu
, ", ");
210 type
= va_arg (args
, int);
214 ival
= va_arg (args
, int);
215 trace_printf (CPU_STATE (cpu
), cpu
, fmt
, ival
);
224 trace_printf (CPU_STATE (cpu
), cpu
, "\n");
228 trace_result (SIM_CPU
*cpu
, char *name
, int type
, ...)
232 va_start (args
, type
);
233 if (printed_result_p
)
234 cgen_trace_printf (cpu
, ", ");
240 cgen_trace_printf (cpu
, "%s <- 0x%x", name
, va_arg (args
, int));
245 /* this is separated from previous line for sunos cc */
246 di
= va_arg (args
, DI
);
247 cgen_trace_printf (cpu
, "%s <- 0x%x%08x", name
,
248 GETHIDI(di
), GETLODI (di
));
253 printed_result_p
= 1;
257 /* Print trace output to BUFPTR if active, otherwise print normally.
258 This is only for tracing semantic code. */
261 cgen_trace_printf (SIM_CPU
*cpu
, char *fmt
, ...)
265 va_start (args
, fmt
);
269 if (TRACE_FILE (CPU_TRACE_DATA (cpu
)) == NULL
)
270 (* STATE_CALLBACK (CPU_STATE (cpu
))->evprintf_filtered
)
271 (STATE_CALLBACK (CPU_STATE (cpu
)), fmt
, args
);
273 vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu
)), fmt
, args
);
277 vsprintf (bufptr
, fmt
, args
);
278 bufptr
+= strlen (bufptr
);
279 /* ??? Need version of SIM_ASSERT that is always enabled. */
280 if (bufptr
- trace_buf
> SIZE_TRACE_BUF
)
287 /* Disassembly support. */
289 /* sprintf to a "stream" */
292 sim_disasm_sprintf
VPARAMS ((SFILE
*f
, const char *format
, ...))
301 VA_START (args
, format
);
303 f
= va_arg (args
, SFILE
*);
304 format
= va_arg (args
, char *);
306 vsprintf (f
->current
, format
, args
);
307 f
->current
+= n
= strlen (f
->current
);
312 /* Memory read support for an opcodes disassembler. */
315 sim_disasm_read_memory (bfd_vma memaddr
, bfd_byte
*myaddr
, int length
,
316 struct disassemble_info
*info
)
318 SIM_CPU
*cpu
= (SIM_CPU
*) info
->application_data
;
319 SIM_DESC sd
= CPU_STATE (cpu
);
322 length_read
= sim_core_read_buffer (sd
, cpu
, read_map
, myaddr
, memaddr
,
324 if (length_read
!= length
)
329 /* Memory error support for an opcodes disassembler. */
332 sim_disasm_perror_memory (int status
, bfd_vma memaddr
,
333 struct disassemble_info
*info
)
337 info
->fprintf_func (info
->stream
, "Unknown error %d.", status
);
339 /* Actually, address between memaddr and memaddr + len was
341 info
->fprintf_func (info
->stream
,
342 "Address 0x%x is out of bounds.",
346 /* Disassemble using the CGEN opcode table.
347 ??? While executing an instruction, the insn has been decoded and all its
348 fields have been extracted. It is certainly possible to do the disassembly
349 with that data. This seems simpler, but maybe in the future the already
350 extracted fields will be used. */
353 sim_cgen_disassemble_insn (SIM_CPU
*cpu
, const CGEN_INSN
*insn
,
354 const ARGBUF
*abuf
, IADDR pc
, char *buf
)
357 unsigned int base_length
;
358 unsigned long insn_value
;
359 struct disassemble_info disasm_info
;
362 unsigned8 bytes
[CGEN_MAX_INSN_SIZE
];
363 unsigned16 shorts
[8];
366 SIM_DESC sd
= CPU_STATE (cpu
);
367 CGEN_CPU_DESC cd
= CPU_CPU_DESC (cpu
);
368 CGEN_EXTRACT_INFO ex_info
;
369 CGEN_FIELDS
*fields
= alloca (CGEN_CPU_SIZEOF_FIELDS (cd
));
370 int insn_bit_length
= CGEN_INSN_BITSIZE (insn
);
371 int insn_length
= insn_bit_length
/ 8;
373 sfile
.buffer
= sfile
.current
= buf
;
374 INIT_DISASSEMBLE_INFO (disasm_info
, (FILE *) &sfile
,
375 (fprintf_ftype
) sim_disasm_sprintf
);
377 (bfd_big_endian (STATE_PROG_BFD (sd
)) ? BFD_ENDIAN_BIG
378 : bfd_little_endian (STATE_PROG_BFD (sd
)) ? BFD_ENDIAN_LITTLE
379 : BFD_ENDIAN_UNKNOWN
);
381 length
= sim_core_read_buffer (sd
, cpu
, read_map
, &insn_buf
, pc
,
384 if (length
!= insn_length
)
386 sim_io_error (sd
, "unable to read address %x", pc
);
389 /* If the entire insn will fit into an integer, then do it. Otherwise, just
390 use the bits of the base_insn. */
391 if (insn_bit_length
<= 32)
392 base_length
= insn_bit_length
;
394 base_length
= min (cd
->base_insn_bitsize
, insn_bit_length
);
397 case 0 : return; /* fake insn, typically "compile" (aka "invalid") */
398 case 8 : insn_value
= insn_buf
.bytes
[0]; break;
399 case 16 : insn_value
= T2H_2 (insn_buf
.shorts
[0]); break;
400 case 32 : insn_value
= T2H_4 (insn_buf
.words
[0]); break;
404 disasm_info
.buffer_vma
= pc
;
405 disasm_info
.buffer
= insn_buf
.bytes
;
406 disasm_info
.buffer_length
= length
;
408 ex_info
.dis_info
= (PTR
) &disasm_info
;
409 ex_info
.valid
= (1 << length
) - 1;
410 ex_info
.insn_bytes
= insn_buf
.bytes
;
412 length
= (*CGEN_EXTRACT_FN (cd
, insn
)) (cd
, insn
, &ex_info
, insn_value
, fields
, pc
);
413 /* Result of extract fn is in bits. */
414 /* ??? This assumes that each instruction has a fixed length (and thus
415 for insns with multiple versions of variable lengths they would each
416 have their own table entry). */
417 if (length
== insn_bit_length
)
419 (*CGEN_PRINT_FN (cd
, insn
)) (cd
, &disasm_info
, insn
, fields
, pc
, length
);
423 /* This shouldn't happen, but aborting is too drastic. */
424 strcpy (buf
, "***unknown***");