1 /* Tracing support for CGEN-based simulators.
2 Copyright (C) 1996-2014 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
28 #define min(a,b) ((a) < (b) ? (a) : (b))
30 #ifndef SIZE_INSTRUCTION
31 #define SIZE_INSTRUCTION 16
35 #define SIZE_LOCATION 20
42 #ifndef SIZE_LINE_NUMBER
43 #define SIZE_LINE_NUMBER 4
46 #ifndef SIZE_CYCLE_COUNT
47 #define SIZE_CYCLE_COUNT 2
50 #ifndef SIZE_TOTAL_CYCLE_COUNT
51 #define SIZE_TOTAL_CYCLE_COUNT 9
54 #ifndef SIZE_TRACE_BUF
55 #define SIZE_TRACE_BUF 1024
58 /* Text is queued in TRACE_BUF because we want to output the insn's cycle
59 count first but that isn't known until after the insn has executed.
60 This also handles the queueing of trace results, TRACE_RESULT may be
61 called multiple times for one insn. */
62 static char trace_buf
[SIZE_TRACE_BUF
];
63 /* If NULL, output to stdout directly. */
66 /* Non-zero if this is the first insn in a set of parallel insns. */
67 static int first_insn_p
;
69 /* For communication between trace_insn and trace_result. */
70 static int printed_result_p
;
72 /* Insn and its extracted fields.
73 Set by trace_insn, used by trace_insn_fini.
74 ??? Move to SIM_CPU to support heterogeneous multi-cpu case. */
75 static const struct cgen_insn
*current_insn
;
76 static const struct argbuf
*current_abuf
;
79 trace_insn_init (SIM_CPU
*cpu
, int first_p
)
83 first_insn_p
= first_p
;
85 /* Set to NULL so trace_insn_fini can know if trace_insn was called. */
91 trace_insn_fini (SIM_CPU
*cpu
, const struct argbuf
*abuf
, int last_p
)
93 SIM_DESC sd
= CPU_STATE (cpu
);
95 /* Was insn traced? It might not be if trace ranges are in effect. */
96 if (current_insn
== NULL
)
99 /* The first thing printed is current and total cycle counts. */
101 if (PROFILE_MODEL_P (cpu
)
102 && ARGBUF_PROFILE_P (current_abuf
))
104 unsigned long total
= PROFILE_MODEL_TOTAL_CYCLES (CPU_PROFILE_DATA (cpu
));
105 unsigned long this_insn
= PROFILE_MODEL_CUR_INSN_CYCLES (CPU_PROFILE_DATA (cpu
));
109 trace_printf (sd
, cpu
, "%-*ld %-*ld ",
110 SIZE_CYCLE_COUNT
, this_insn
,
111 SIZE_TOTAL_CYCLE_COUNT
, total
);
115 trace_printf (sd
, cpu
, "%-*ld %-*s ",
116 SIZE_CYCLE_COUNT
, this_insn
,
117 SIZE_TOTAL_CYCLE_COUNT
, "---");
121 /* Print the disassembled insn. */
123 trace_printf (sd
, cpu
, "%s", TRACE_PREFIX (CPU_TRACE_DATA (cpu
)));
126 /* Print insn results. */
128 const CGEN_OPINST
*opinst
= CGEN_INSN_OPERANDS (current_insn
);
133 int indices
[MAX_OPERAND_INSTANCES
];
135 /* Fetch the operands used by the insn. */
136 /* FIXME: Add fn ptr to CGEN_CPU_DESC. */
137 CGEN_SYM (get_insn_operands
) (CPU_CPU_DESC (cpu
), current_insn
,
138 0, CGEN_FIELDS_BITSIZE (&insn_fields
),
142 CGEN_OPINST_TYPE (opinst
) != CGEN_OPINST_END
;
145 if (CGEN_OPINST_TYPE (opinst
) == CGEN_OPINST_OUTPUT
)
146 trace_result (cpu
, current_insn
, opinst
, indices
[i
]);
152 /* Print anything else requested. */
155 trace_printf (sd
, cpu
, " %s\n", trace_buf
);
157 trace_printf (sd
, cpu
, "\n");
161 trace_insn (SIM_CPU
*cpu
, const struct cgen_insn
*opcode
,
162 const struct argbuf
*abuf
, IADDR pc
)
166 printed_result_p
= 0;
167 current_insn
= opcode
;
170 if (CGEN_INSN_VIRTUAL_P (opcode
))
172 trace_prefix (CPU_STATE (cpu
), cpu
, NULL_CIA
, pc
, 0,
173 NULL
, 0, CGEN_INSN_NAME (opcode
));
177 CPU_DISASSEMBLER (cpu
) (cpu
, opcode
, abuf
, pc
, disasm_buf
);
178 trace_prefix (CPU_STATE (cpu
), cpu
, NULL_CIA
, pc
, TRACE_LINENUM_P (cpu
),
181 first_insn_p
? " " : "|",
182 SIZE_INSTRUCTION
, disasm_buf
);
186 trace_extract (SIM_CPU
*cpu
, IADDR pc
, char *name
, ...)
189 int printed_one_p
= 0;
192 va_start (args
, name
);
194 trace_printf (CPU_STATE (cpu
), cpu
, "Extract: 0x%.*lx: %s ",
195 SIZE_PC
, (unsigned long) pc
, name
);
200 fmt
= va_arg (args
, char *);
205 trace_printf (CPU_STATE (cpu
), cpu
, ", ");
207 type
= va_arg (args
, int);
211 ival
= va_arg (args
, int);
212 trace_printf (CPU_STATE (cpu
), cpu
, fmt
, ival
);
221 trace_printf (CPU_STATE (cpu
), cpu
, "\n");
225 trace_result (SIM_CPU
*cpu
, char *name
, int type
, ...)
229 va_start (args
, type
);
230 if (printed_result_p
)
231 cgen_trace_printf (cpu
, ", ");
237 cgen_trace_printf (cpu
, "%s <- 0x%x", name
, va_arg (args
, int));
244 /* this is separated from previous line for sunos cc */
245 di
= va_arg (args
, DI
);
246 sim_fpu_64to (&f
, di
);
248 cgen_trace_printf (cpu
, "%s <- ", name
);
249 sim_fpu_printn_fpu (&f
, (sim_fpu_print_func
*) cgen_trace_printf
, 4, cpu
);
255 /* this is separated from previous line for sunos cc */
256 di
= va_arg (args
, DI
);
257 cgen_trace_printf (cpu
, "%s <- 0x%x%08x", name
,
258 GETHIDI(di
), GETLODI (di
));
263 printed_result_p
= 1;
267 /* Print trace output to BUFPTR if active, otherwise print normally.
268 This is only for tracing semantic code. */
271 cgen_trace_printf (SIM_CPU
*cpu
, char *fmt
, ...)
275 va_start (args
, fmt
);
279 if (TRACE_FILE (CPU_TRACE_DATA (cpu
)) == NULL
)
280 (* STATE_CALLBACK (CPU_STATE (cpu
))->evprintf_filtered
)
281 (STATE_CALLBACK (CPU_STATE (cpu
)), fmt
, args
);
283 vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu
)), fmt
, args
);
287 vsprintf (bufptr
, fmt
, args
);
288 bufptr
+= strlen (bufptr
);
289 /* ??? Need version of SIM_ASSERT that is always enabled. */
290 if (bufptr
- trace_buf
> SIZE_TRACE_BUF
)
297 /* Disassembly support. */
299 /* sprintf to a "stream" */
302 sim_disasm_sprintf (SFILE
*f
, const char *format
, ...)
311 va_start (args
, format
);
313 f
= va_arg (args
, SFILE
*);
314 format
= va_arg (args
, char *);
316 vsprintf (f
->current
, format
, args
);
317 f
->current
+= n
= strlen (f
->current
);
322 /* Memory read support for an opcodes disassembler. */
325 sim_disasm_read_memory (bfd_vma memaddr
, bfd_byte
*myaddr
, unsigned int length
,
326 struct disassemble_info
*info
)
328 SIM_CPU
*cpu
= (SIM_CPU
*) info
->application_data
;
329 SIM_DESC sd
= CPU_STATE (cpu
);
330 unsigned length_read
;
332 length_read
= sim_core_read_buffer (sd
, cpu
, read_map
, myaddr
, memaddr
,
334 if (length_read
!= length
)
339 /* Memory error support for an opcodes disassembler. */
342 sim_disasm_perror_memory (int status
, bfd_vma memaddr
,
343 struct disassemble_info
*info
)
347 info
->fprintf_func (info
->stream
, "Unknown error %d.", status
);
349 /* Actually, address between memaddr and memaddr + len was
351 info
->fprintf_func (info
->stream
,
352 "Address 0x%x is out of bounds.",
356 /* Disassemble using the CGEN opcode table.
357 ??? While executing an instruction, the insn has been decoded and all its
358 fields have been extracted. It is certainly possible to do the disassembly
359 with that data. This seems simpler, but maybe in the future the already
360 extracted fields will be used. */
363 sim_cgen_disassemble_insn (SIM_CPU
*cpu
, const CGEN_INSN
*insn
,
364 const ARGBUF
*abuf
, IADDR pc
, char *buf
)
367 unsigned int base_length
;
368 unsigned long insn_value
;
369 struct disassemble_info disasm_info
;
372 unsigned8 bytes
[CGEN_MAX_INSN_SIZE
];
373 unsigned16 shorts
[8];
376 SIM_DESC sd
= CPU_STATE (cpu
);
377 CGEN_CPU_DESC cd
= CPU_CPU_DESC (cpu
);
378 CGEN_EXTRACT_INFO ex_info
;
379 CGEN_FIELDS
*fields
= alloca (CGEN_CPU_SIZEOF_FIELDS (cd
));
380 int insn_bit_length
= CGEN_INSN_BITSIZE (insn
);
381 int insn_length
= insn_bit_length
/ 8;
383 sfile
.buffer
= sfile
.current
= buf
;
384 INIT_DISASSEMBLE_INFO (disasm_info
, (FILE *) &sfile
,
385 (fprintf_ftype
) sim_disasm_sprintf
);
387 (bfd_big_endian (STATE_PROG_BFD (sd
)) ? BFD_ENDIAN_BIG
388 : bfd_little_endian (STATE_PROG_BFD (sd
)) ? BFD_ENDIAN_LITTLE
389 : BFD_ENDIAN_UNKNOWN
);
391 length
= sim_core_read_buffer (sd
, cpu
, read_map
, &insn_buf
, pc
,
394 if (length
!= insn_length
)
396 sim_io_error (sd
, "unable to read address %x", pc
);
399 /* If the entire insn will fit into an integer, then do it. Otherwise, just
400 use the bits of the base_insn. */
401 if (insn_bit_length
<= 32)
402 base_length
= insn_bit_length
;
404 base_length
= min (cd
->base_insn_bitsize
, insn_bit_length
);
407 case 0 : return; /* fake insn, typically "compile" (aka "invalid") */
408 case 8 : insn_value
= insn_buf
.bytes
[0]; break;
409 case 16 : insn_value
= T2H_2 (insn_buf
.shorts
[0]); break;
410 case 32 : insn_value
= T2H_4 (insn_buf
.words
[0]); break;
414 disasm_info
.buffer_vma
= pc
;
415 disasm_info
.buffer
= insn_buf
.bytes
;
416 disasm_info
.buffer_length
= length
;
418 ex_info
.dis_info
= (PTR
) &disasm_info
;
419 ex_info
.valid
= (1 << length
) - 1;
420 ex_info
.insn_bytes
= insn_buf
.bytes
;
422 length
= (*CGEN_EXTRACT_FN (cd
, insn
)) (cd
, insn
, &ex_info
, insn_value
, fields
, pc
);
423 /* Result of extract fn is in bits. */
424 /* ??? This assumes that each instruction has a fixed length (and thus
425 for insns with multiple versions of variable lengths they would each
426 have their own table entry). */
427 if (length
== insn_bit_length
)
429 (*CGEN_PRINT_FN (cd
, insn
)) (cd
, &disasm_info
, insn
, fields
, pc
, length
);
433 /* This shouldn't happen, but aborting is too drastic. */
434 strcpy (buf
, "***unknown***");