1 /* Tracing support for CGEN-based simulators.
2 Copyright (C) 1996-2021 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* This must come before any other includes. */
29 #include "sim/callback.h"
31 #ifndef SIZE_INSTRUCTION
32 #define SIZE_INSTRUCTION 16
36 #define SIZE_LOCATION 20
43 #ifndef SIZE_LINE_NUMBER
44 #define SIZE_LINE_NUMBER 4
47 #ifndef SIZE_CYCLE_COUNT
48 #define SIZE_CYCLE_COUNT 2
51 #ifndef SIZE_TOTAL_CYCLE_COUNT
52 #define SIZE_TOTAL_CYCLE_COUNT 9
55 #ifndef SIZE_TRACE_BUF
56 #define SIZE_TRACE_BUF 1024
59 /* Text is queued in TRACE_BUF because we want to output the insn's cycle
60 count first but that isn't known until after the insn has executed.
61 This also handles the queueing of trace results, TRACE_RESULT may be
62 called multiple times for one insn. */
63 static char trace_buf
[SIZE_TRACE_BUF
];
64 /* If NULL, output to stdout directly. */
67 /* Non-zero if this is the first insn in a set of parallel insns. */
68 static int first_insn_p
;
70 /* For communication between cgen_trace_insn and cgen_trace_result. */
71 static int printed_result_p
;
73 /* Insn and its extracted fields.
74 Set by cgen_trace_insn, used by cgen_trace_insn_fini.
75 ??? Move to SIM_CPU to support heterogeneous multi-cpu case. */
76 static const struct cgen_insn
*current_insn
;
77 static const struct argbuf
*current_abuf
;
80 cgen_trace_insn_init (SIM_CPU
*cpu
, int first_p
)
84 first_insn_p
= first_p
;
86 /* Set to NULL so cgen_trace_insn_fini can know if cgen_trace_insn was
93 cgen_trace_insn_fini (SIM_CPU
*cpu
, const struct argbuf
*abuf
, int last_p
)
95 SIM_DESC sd
= CPU_STATE (cpu
);
97 /* Was insn traced? It might not be if trace ranges are in effect. */
98 if (current_insn
== NULL
)
101 /* The first thing printed is current and total cycle counts. */
103 if (PROFILE_MODEL_P (cpu
)
104 && ARGBUF_PROFILE_P (current_abuf
))
106 unsigned long total
= PROFILE_MODEL_TOTAL_CYCLES (CPU_PROFILE_DATA (cpu
));
107 unsigned long this_insn
= PROFILE_MODEL_CUR_INSN_CYCLES (CPU_PROFILE_DATA (cpu
));
111 trace_printf (sd
, cpu
, "%-*ld %-*ld ",
112 SIZE_CYCLE_COUNT
, this_insn
,
113 SIZE_TOTAL_CYCLE_COUNT
, total
);
117 trace_printf (sd
, cpu
, "%-*ld %-*s ",
118 SIZE_CYCLE_COUNT
, this_insn
,
119 SIZE_TOTAL_CYCLE_COUNT
, "---");
123 /* Print the disassembled insn. */
125 trace_printf (sd
, cpu
, "%s", TRACE_PREFIX (CPU_TRACE_DATA (cpu
)));
128 /* Print insn results. */
130 const CGEN_OPINST
*opinst
= CGEN_INSN_OPERANDS (current_insn
);
135 int indices
[MAX_OPERAND_INSTANCES
];
137 /* Fetch the operands used by the insn. */
138 /* FIXME: Add fn ptr to CGEN_CPU_DESC. */
139 CGEN_SYM (get_insn_operands
) (CPU_CPU_DESC (cpu
), current_insn
,
140 0, CGEN_FIELDS_BITSIZE (&insn_fields
),
144 CGEN_OPINST_TYPE (opinst
) != CGEN_OPINST_END
;
147 if (CGEN_OPINST_TYPE (opinst
) == CGEN_OPINST_OUTPUT
)
148 cgen_trace_result (cpu
, current_insn
, opinst
, indices
[i
]);
154 /* Print anything else requested. */
157 trace_printf (sd
, cpu
, " %s\n", trace_buf
);
159 trace_printf (sd
, cpu
, "\n");
163 cgen_trace_insn (SIM_CPU
*cpu
, const struct cgen_insn
*opcode
,
164 const struct argbuf
*abuf
, IADDR pc
)
168 printed_result_p
= 0;
169 current_insn
= opcode
;
172 if (CGEN_INSN_VIRTUAL_P (opcode
))
174 trace_prefix (CPU_STATE (cpu
), cpu
, NULL_CIA
, pc
, 0,
175 NULL
, 0, "%s", CGEN_INSN_NAME (opcode
));
179 CPU_DISASSEMBLER (cpu
) (cpu
, opcode
, abuf
, pc
, disasm_buf
);
180 trace_prefix (CPU_STATE (cpu
), cpu
, NULL_CIA
, pc
, TRACE_LINENUM_P (cpu
),
183 first_insn_p
? " " : "|",
184 SIZE_INSTRUCTION
, disasm_buf
);
188 cgen_trace_extract (SIM_CPU
*cpu
, IADDR pc
, char *name
, ...)
191 int printed_one_p
= 0;
194 va_start (args
, name
);
196 trace_printf (CPU_STATE (cpu
), cpu
, "Extract: 0x%.*lx: %s ",
197 SIZE_PC
, (unsigned long) pc
, name
);
202 fmt
= va_arg (args
, char *);
207 trace_printf (CPU_STATE (cpu
), cpu
, ", ");
209 type
= va_arg (args
, int);
213 ival
= va_arg (args
, int);
214 trace_printf (CPU_STATE (cpu
), cpu
, fmt
, ival
);
223 trace_printf (CPU_STATE (cpu
), cpu
, "\n");
227 cgen_trace_result (SIM_CPU
*cpu
, char *name
, int type
, ...)
231 va_start (args
, type
);
232 if (printed_result_p
)
233 cgen_trace_printf (cpu
, ", ");
239 cgen_trace_printf (cpu
, "%s <- 0x%x", name
, va_arg (args
, int));
246 /* this is separated from previous line for sunos cc */
247 di
= va_arg (args
, DI
);
248 sim_fpu_64to (&f
, di
);
250 cgen_trace_printf (cpu
, "%s <- ", name
);
251 sim_fpu_printn_fpu (&f
, (sim_fpu_print_func
*) cgen_trace_printf
, 4, cpu
);
257 /* this is separated from previous line for sunos cc */
258 di
= va_arg (args
, DI
);
259 cgen_trace_printf (cpu
, "%s <- 0x%x%08x", name
,
260 GETHIDI(di
), GETLODI (di
));
265 printed_result_p
= 1;
269 /* Print trace output to BUFPTR if active, otherwise print normally.
270 This is only for tracing semantic code. */
273 cgen_trace_printf (SIM_CPU
*cpu
, char *fmt
, ...)
277 va_start (args
, fmt
);
281 if (TRACE_FILE (CPU_TRACE_DATA (cpu
)) == NULL
)
282 (* STATE_CALLBACK (CPU_STATE (cpu
))->evprintf_filtered
)
283 (STATE_CALLBACK (CPU_STATE (cpu
)), fmt
, args
);
285 vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu
)), fmt
, args
);
289 vsprintf (bufptr
, fmt
, args
);
290 bufptr
+= strlen (bufptr
);
291 /* ??? Need version of SIM_ASSERT that is always enabled. */
292 if (bufptr
- trace_buf
> SIZE_TRACE_BUF
)
299 /* Disassembly support. */
301 /* sprintf to a "stream" */
304 sim_disasm_sprintf (SFILE
*f
, const char *format
, ...)
309 va_start (args
, format
);
310 vsprintf (f
->current
, format
, args
);
311 f
->current
+= n
= strlen (f
->current
);
316 /* Memory read support for an opcodes disassembler. */
319 sim_disasm_read_memory (bfd_vma memaddr
, bfd_byte
*myaddr
, unsigned int length
,
320 struct disassemble_info
*info
)
322 SIM_CPU
*cpu
= (SIM_CPU
*) info
->application_data
;
323 SIM_DESC sd
= CPU_STATE (cpu
);
324 unsigned length_read
;
326 length_read
= sim_core_read_buffer (sd
, cpu
, read_map
, myaddr
, memaddr
,
328 if (length_read
!= length
)
333 /* Memory error support for an opcodes disassembler. */
336 sim_disasm_perror_memory (int status
, bfd_vma memaddr
,
337 struct disassemble_info
*info
)
341 info
->fprintf_func (info
->stream
, "Unknown error %d.", status
);
343 /* Actually, address between memaddr and memaddr + len was
345 info
->fprintf_func (info
->stream
,
346 "Address 0x%" BFD_VMA_FMT
"x is out of bounds.",
350 /* Disassemble using the CGEN opcode table.
351 ??? While executing an instruction, the insn has been decoded and all its
352 fields have been extracted. It is certainly possible to do the disassembly
353 with that data. This seems simpler, but maybe in the future the already
354 extracted fields will be used. */
357 sim_cgen_disassemble_insn (SIM_CPU
*cpu
, const CGEN_INSN
*insn
,
358 const ARGBUF
*abuf
, IADDR pc
, char *buf
)
361 unsigned int base_length
;
362 unsigned long insn_value
;
363 struct disassemble_info disasm_info
;
366 unsigned8 bytes
[CGEN_MAX_INSN_SIZE
];
367 unsigned16 shorts
[8];
370 SIM_DESC sd
= CPU_STATE (cpu
);
371 CGEN_CPU_DESC cd
= CPU_CPU_DESC (cpu
);
372 CGEN_EXTRACT_INFO ex_info
;
373 CGEN_FIELDS
*fields
= alloca (CGEN_CPU_SIZEOF_FIELDS (cd
));
374 int insn_bit_length
= CGEN_INSN_BITSIZE (insn
);
375 int insn_length
= insn_bit_length
/ 8;
377 sfile
.buffer
= sfile
.current
= buf
;
378 INIT_DISASSEMBLE_INFO (disasm_info
, (FILE *) &sfile
,
379 (fprintf_ftype
) sim_disasm_sprintf
);
381 (bfd_big_endian (STATE_PROG_BFD (sd
)) ? BFD_ENDIAN_BIG
382 : bfd_little_endian (STATE_PROG_BFD (sd
)) ? BFD_ENDIAN_LITTLE
383 : BFD_ENDIAN_UNKNOWN
);
385 length
= sim_core_read_buffer (sd
, cpu
, read_map
, &insn_buf
, pc
,
388 if (length
!= insn_length
)
390 sim_io_error (sd
, "unable to read address %" PRIxTA
, pc
);
393 /* If the entire insn will fit into an integer, then do it. Otherwise, just
394 use the bits of the base_insn. */
395 if (insn_bit_length
<= 32)
396 base_length
= insn_bit_length
;
398 base_length
= min (cd
->base_insn_bitsize
, insn_bit_length
);
401 case 0 : return; /* fake insn, typically "compile" (aka "invalid") */
402 case 8 : insn_value
= insn_buf
.bytes
[0]; break;
403 case 16 : insn_value
= T2H_2 (insn_buf
.shorts
[0]); break;
404 case 32 : insn_value
= T2H_4 (insn_buf
.words
[0]); break;
408 disasm_info
.buffer_vma
= pc
;
409 disasm_info
.buffer
= insn_buf
.bytes
;
410 disasm_info
.buffer_length
= length
;
412 ex_info
.dis_info
= (PTR
) &disasm_info
;
413 ex_info
.valid
= (1 << length
) - 1;
414 ex_info
.insn_bytes
= insn_buf
.bytes
;
416 length
= (*CGEN_EXTRACT_FN (cd
, insn
)) (cd
, insn
, &ex_info
, insn_value
, fields
, pc
);
417 /* Result of extract fn is in bits. */
418 /* ??? This assumes that each instruction has a fixed length (and thus
419 for insns with multiple versions of variable lengths they would each
420 have their own table entry). */
421 if (length
== insn_bit_length
)
423 (*CGEN_PRINT_FN (cd
, insn
)) (cd
, &disasm_info
, insn
, fields
, pc
, length
);
427 /* This shouldn't happen, but aborting is too drastic. */
428 strcpy (buf
, "***unknown***");