sim/common/cgen-utils.c

   1 /* Support code for various pieces of CGEN simulators.
   2    Copyright (C) 1996-2021 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 /* This must come before any other includes.  */
  21 #include "defs.h"
  22
  23 #include "bfd.h"
  24 #include "sim-main.h"
  25 #include "sim-signal.h"
  26 #include "dis-asm.h"
  27
  28 #define MEMOPS_DEFINE_INLINE
  29 #include "cgen-mem.h"
  30
  31 #define SEMOPS_DEFINE_INLINE
  32 #include "cgen-ops.h"
  33
  34 const char * const cgen_mode_names[] = {
  35   "VOID",
  36   "BI",
  37   "QI",
  38   "HI",
  39   "SI",
  40   "DI",
  41   "UQI",
  42   "UHI",
  43   "USI",
  44   "UDI",
  45   "SF",
  46   "DF",
  47   "XF",
  48   "TF",
  49   0, /* MODE_TARGET_MAX */
  50   "INT",
  51   "UINT",
  52   "PTR"
  53 };
  54
  55 /* Opcode table for virtual insns used by the simulator.  */
  56
  57 #define V CGEN_ATTR_MASK (CGEN_INSN_VIRTUAL)
  58
  59 static const CGEN_IBASE virtual_insn_entries[] =
  60 {
  61   {
  62     VIRTUAL_INSN_X_INVALID, "--invalid--", NULL, 0, { V, {} }
  63   },
  64   {
  65     VIRTUAL_INSN_X_BEFORE, "--before--", NULL, 0, { V, {} }
  66   },
  67   {
  68     VIRTUAL_INSN_X_AFTER, "--after--", NULL, 0, { V, {} }
  69   },
  70   {
  71     VIRTUAL_INSN_X_BEGIN, "--begin--", NULL, 0, { V, {} }
  72   },
  73   {
  74     VIRTUAL_INSN_X_CHAIN, "--chain--", NULL, 0, { V, {} }
  75   },
  76   {
  77     VIRTUAL_INSN_X_CTI_CHAIN, "--cti-chain--", NULL, 0, { V, {} }
  78   }
  79 };
  80
  81 #undef V
  82
  83 const CGEN_INSN cgen_virtual_insn_table[] =
  84 {
  85   { & virtual_insn_entries[0] },
  86   { & virtual_insn_entries[1] },
  87   { & virtual_insn_entries[2] },
  88   { & virtual_insn_entries[3] },
  89   { & virtual_insn_entries[4] },
  90   { & virtual_insn_entries[5] }
  91 };
  92
  93 /* Return the name of insn number I.  */
  94
  95 const char *
  96 cgen_insn_name (SIM_CPU *cpu, int i)
  97 {
  98   return CGEN_INSN_NAME ((* CPU_GET_IDATA (cpu)) ((cpu), (i)));
  99 }
 100
 101 /* Return the maximum number of extra bytes required for a SIM_CPU struct.  */
 102
 103 int
 104 cgen_cpu_max_extra_bytes (SIM_DESC sd)
 105 {
 106   const SIM_MACH * const *machp;
 107   int extra = 0;
 108
 109   SIM_ASSERT (STATE_MACHS (sd) != NULL);
 110
 111   for (machp = STATE_MACHS (sd); *machp != NULL; ++machp)
 112     {
 113       int size = IMP_PROPS_SIM_CPU_SIZE (MACH_IMP_PROPS (*machp));
 114       if (size > extra)
 115         extra = size;
 116     }
 117   return extra;
 118 }
 119 \f
 120 #ifdef DI_FN_SUPPORT
 121
 122 DI
 123 ANDDI (a, b)
 124      DI a, b;
 125 {
 126   SI ahi = GETHIDI (a);
 127   SI alo = GETLODI (a);
 128   SI bhi = GETHIDI (b);
 129   SI blo = GETLODI (b);
 130   return MAKEDI (ahi & bhi, alo & blo);
 131 }
 132
 133 DI
 134 ORDI (a, b)
 135      DI a, b;
 136 {
 137   SI ahi = GETHIDI (a);
 138   SI alo = GETLODI (a);
 139   SI bhi = GETHIDI (b);
 140   SI blo = GETLODI (b);
 141   return MAKEDI (ahi | bhi, alo | blo);
 142 }
 143
 144 DI
 145 ADDDI (a, b)
 146      DI a, b;
 147 {
 148   USI ahi = GETHIDI (a);
 149   USI alo = GETLODI (a);
 150   USI bhi = GETHIDI (b);
 151   USI blo = GETLODI (b);
 152   USI x = alo + blo;
 153   return MAKEDI (ahi + bhi + (x < alo), x);
 154 }
 155
 156 DI
 157 MULDI (a, b)
 158      DI a, b;
 159 {
 160   USI ahi = GETHIDI (a);
 161   USI alo = GETLODI (a);
 162   USI bhi = GETHIDI (b);
 163   USI blo = GETLODI (b);
 164   USI rhi,rlo;
 165   USI x0, x1, x2, x3;
 166
 167   x0 = alo * blo;
 168   x1 = alo * bhi;
 169   x2 = ahi * blo;
 170   x3 = ahi * bhi;
 171
 172 #define SI_TYPE_SIZE 32
 173 #define BITS4 (SI_TYPE_SIZE / 4)
 174 #define ll_B (1L << (SI_TYPE_SIZE / 2))
 175 #define ll_lowpart(t) ((USI) (t) % ll_B)
 176 #define ll_highpart(t) ((USI) (t) / ll_B)
 177   x1 += ll_highpart (x0);       /* this can't give carry */
 178   x1 += x2;                     /* but this indeed can */
 179   if (x1 < x2)                  /* did we get it? */
 180     x3 += ll_B;                 /* yes, add it in the proper pos. */
 181
 182   rhi = x3 + ll_highpart (x1);
 183   rlo = ll_lowpart (x1) * ll_B + ll_lowpart (x0);
 184   return MAKEDI (rhi + (alo * bhi) + (ahi * blo), rlo);
 185 }
 186
 187 DI
 188 SHLDI (val, shift)
 189      DI val;
 190      SI shift;
 191 {
 192   USI hi = GETHIDI (val);
 193   USI lo = GETLODI (val);
 194   /* FIXME: Need to worry about shift < 0 || shift >= 32.  */
 195   return MAKEDI ((hi << shift) | (lo >> (32 - shift)), lo << shift);
 196 }
 197
 198 DI
 199 SLADI (val, shift)
 200      DI val;
 201      SI shift;
 202 {
 203   SI hi = GETHIDI (val);
 204   USI lo = GETLODI (val);
 205   /* FIXME: Need to worry about shift < 0 || shift >= 32.  */
 206   return MAKEDI ((hi << shift) | (lo >> (32 - shift)), lo << shift);
 207 }
 208
 209 DI
 210 SRADI (val, shift)
 211      DI val;
 212      SI shift;
 213 {
 214   SI hi = GETHIDI (val);
 215   USI lo = GETLODI (val);
 216   /* We use SRASI because the result is implementation defined if hi < 0.  */
 217   /* FIXME: Need to worry about shift < 0 || shift >= 32.  */
 218   return MAKEDI (SRASI (hi, shift), (hi << (32 - shift)) | (lo >> shift));
 219 }
 220
 221 int
 222 GEDI (a, b)
 223      DI a, b;
 224 {
 225   SI ahi = GETHIDI (a);
 226   USI alo = GETLODI (a);
 227   SI bhi = GETHIDI (b);
 228   USI blo = GETLODI (b);
 229   if (ahi > bhi)
 230     return 1;
 231   if (ahi == bhi)
 232     return alo >= blo;
 233   return 0;
 234 }
 235
 236 int
 237 LEDI (a, b)
 238      DI a, b;
 239 {
 240   SI ahi = GETHIDI (a);
 241   USI alo = GETLODI (a);
 242   SI bhi = GETHIDI (b);
 243   USI blo = GETLODI (b);
 244   if (ahi < bhi)
 245     return 1;
 246   if (ahi == bhi)
 247     return alo <= blo;
 248   return 0;
 249 }
 250
 251 DI
 252 CONVHIDI (val)
 253      HI val;
 254 {
 255   if (val < 0)
 256     return MAKEDI (-1, val);
 257   else
 258     return MAKEDI (0, val);
 259 }
 260
 261 DI
 262 CONVSIDI (val)
 263      SI val;
 264 {
 265   if (val < 0)
 266     return MAKEDI (-1, val);
 267   else
 268     return MAKEDI (0, val);
 269 }
 270
 271 SI
 272 CONVDISI (val)
 273      DI val;
 274 {
 275   return GETLODI (val);
 276 }
 277
 278 #endif /* DI_FN_SUPPORT */
 279 \f
 280 QI
 281 RORQI (QI val, int shift)
 282 {
 283   if (shift != 0)
 284     {
 285       int remain = 8 - shift;
 286       int mask = (1 << shift) - 1;
 287       QI result = (val & mask) << remain;
 288       mask = (1 << remain) - 1;
 289       result |= (val >> shift) & mask;
 290       return result;
 291     }
 292   return val;
 293 }
 294
 295 QI
 296 ROLQI (QI val, int shift)
 297 {
 298   if (shift != 0)
 299     {
 300       int remain = 8 - shift;
 301       int mask = (1 << remain) - 1;
 302       QI result = (val & mask) << shift;
 303       mask = (1 << shift) - 1;
 304       result |= (val >> remain) & mask;
 305       return result;
 306     }
 307   return val;
 308 }
 309
 310 HI
 311 RORHI (HI val, int shift)
 312 {
 313   if (shift != 0)
 314     {
 315       int remain = 16 - shift;
 316       int mask = (1 << shift) - 1;
 317       HI result = (val & mask) << remain;
 318       mask = (1 << remain) - 1;
 319       result |= (val >> shift) & mask;
 320       return result;
 321     }
 322   return val;
 323 }
 324
 325 HI
 326 ROLHI (HI val, int shift)
 327 {
 328   if (shift != 0)
 329     {
 330       int remain = 16 - shift;
 331       int mask = (1 << remain) - 1;
 332       HI result = (val & mask) << shift;
 333       mask = (1 << shift) - 1;
 334       result |= (val >> remain) & mask;
 335       return result;
 336     }
 337   return val;
 338 }
 339
 340 SI
 341 RORSI (SI val, int shift)
 342 {
 343   if (shift != 0)
 344     {
 345       int remain = 32 - shift;
 346       int mask = (1 << shift) - 1;
 347       SI result = (val & mask) << remain;
 348       mask = (1 << remain) - 1;
 349       result |= (val >> shift) & mask;
 350       return result;
 351     }
 352   return val;
 353 }
 354
 355 SI
 356 ROLSI (SI val, int shift)
 357 {
 358   if (shift != 0)
 359     {
 360       int remain = 32 - shift;
 361       int mask = (1 << remain) - 1;
 362       SI result = (val & mask) << shift;
 363       mask = (1 << shift) - 1;
 364       result |= (val >> remain) & mask;
 365       return result;
 366     }
 367
 368   return val;
 369 }
 370
 371 /* Emit an error message from CGEN RTL.  */
 372
 373 void
 374 cgen_rtx_error (SIM_CPU *cpu, const char * msg)
 375 {
 376   SIM_DESC sd = CPU_STATE (cpu);
 377
 378   sim_io_printf (sd, "%s", msg);
 379   sim_io_printf (sd, "\n");
 380
 381   sim_engine_halt (sd, cpu, NULL, CPU_PC_GET (cpu), sim_stopped, SIM_SIGTRAP);
 382 }