1 # Generate the main loop of the simulator.
2 # Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
3 # Contributed by Cygnus Support.
5 # This file is part of the GNU simulators.
7 # This program is free software; you can redistribute it and/or modify
8 # it under the terms of the GNU General Public License as published by
9 # the Free Software Foundation; either version 2, or (at your option)
12 # This program is distributed in the hope that it will be useful,
13 # but WITHOUT ANY WARRANTY; without even the implied warranty of
14 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 # GNU General Public License for more details.
17 # You should have received a copy of the GNU General Public License along
18 # with this program; if not, write to the Free Software Foundation, Inc.,
19 # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 # This file creates two files: eng.hin and mloop.cin.
22 # eng.hin defines a few macros that specify what kind of engine was selected
23 # based on the arguments to this script.
24 # mloop.cin contains the engine.
26 # ??? Rename mloop.c to eng.c?
27 # ??? Rename mainloop.in to engine.in?
28 # ??? Add options to specify output file names?
29 # ??? Rename this file to genengine.sh?
31 # Syntax: genmloop.sh [options]
36 # - specify single cpu or multiple cpus (number specifyable at runtime),
37 # maximum number is a configuration parameter
40 # -fast: include support for fast execution in addition to full featured mode
42 # Full featured mode is for tracing, profiling, etc. and is always
43 # provided. Fast mode contains no frills, except speed.
44 # A target need only provide a "full" version of one of
45 # simple,scache,pbb. If the target wants it can also provide a fast
46 # version of same. It can't provide more than this.
47 # ??? Later add ability to have another set of full/fast semantics
48 # for use in with-devices/with-smp situations (pbb can be inappropriate
51 # -full-switch: same as -fast but for full featured version of -switch
52 # Only needed if -fast present.
54 # -simple: simple execution engine (the default)
56 # This engine fetches and executes one instruction at a time.
57 # Field extraction is done in the semantic routines.
59 # ??? There are two possible flavours of -simple. One that extracts
60 # fields in the semantic routine (which is what is implemented here),
61 # and one that stores the extracted fields in ARGBUF before calling the
62 # semantic routine. The latter is essentially the -scache case with a
63 # cache size of one (and the scache lookup code removed). There are no
64 # current uses of this and it's not clear when doing this would be a win.
65 # More complicated ISA's that want to use -simple may find this a win.
66 # Should this ever be desirable, implement a new engine style here and
67 # call it -extract (or some such). It's believed that the CGEN-generated
68 # code for the -scache case would be usable here, so no new code
69 # generation option would be needed for CGEN.
71 # -scache: use the scache to speed things up (not always a win)
73 # This engine caches the extracted instruction before executing it.
74 # When executing instructions they are first looked up in the scache.
76 # -pbb: same as -scache but extract a (pseudo-) basic block at a time
78 # This engine is basically identical to the scache version except that
79 # extraction is done a pseudo-basic-block at a time and the address of
80 # the scache entry of a branch target is recorded as well.
81 # Additional speedups are then possible by defering Ctrl-C checking
82 # to the end of basic blocks and by threading the insns together.
83 # We call them pseudo-basic-block's instead of just basic-blocks because
84 # they're not necessarily basic-blocks, though normally are.
86 # -parallel-read: support parallel execution with read-before-exec support.
87 # -parallel-write: support parallel execution with write-after-exec support.
89 # One of these options is specified in addition to -simple, -scache,
90 # -pbb. Note that while the code can determine if the cpu supports
91 # parallel execution with HAVE_PARALLEL_INSNS [and thus this option is
92 # technically unnecessary], having this option cuts down on the clutter
95 # -switch file: specify file containing semantics implemented as a switch()
99 # Specify the cpu family name.
101 # -infile <input-file>
103 # Specify the mainloop.in input file.
105 # Only one of -scache/-pbb may be selected.
106 # -simple is the default.
111 # - build mainloop.in from .cpu file
127 -multi) type=multi
;;
130 -full-switch) full_switch
=yes ;;
132 -scache) scache
=yes ;;
135 -parallel-read) parallel
=read ;;
136 -parallel-write) parallel
=write ;;
137 -switch) shift ; switch
=$1 ;;
138 -cpu) shift ; cpu
=$1 ;;
139 -infile) shift ; infile
=$1 ;;
140 *) echo "unknown option: $1" >&2 ; exit 1 ;;
145 # Argument validation.
147 if [ x
$scache = xyes
-a x
$pbb = xyes
] ; then
148 echo "only one of -scache and -pbb may be selected" >&2
152 if [ "x$cpu" = xunknown
] ; then
153 echo "cpu family not specified" >&2
157 if [ "x$infile" = x
] ; then
158 echo "mainloop.in not specified" >&2
162 lowercase
='abcdefghijklmnopqrstuvwxyz'
163 uppercase
='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
164 CPU
=`echo ${cpu} | tr "${lowercase}" "${uppercase}"`
166 ##########################################################################
171 echo "/* engine configuration for ${cpu} */"
174 echo "/* WITH_FAST: non-zero if a fast version of the engine is available"
175 echo " in addition to the full-featured version. */"
176 if [ x
$fast = xyes
] ; then
177 echo "#define WITH_FAST 1"
179 echo "#define WITH_FAST 0"
183 echo "/* WITH_SCACHE_PBB_${CPU}: non-zero if the pbb engine was selected. */"
184 if [ x
$pbb = xyes
] ; then
185 echo "#define WITH_SCACHE_PBB_${CPU} 1"
187 echo "#define WITH_SCACHE_PBB_${CPU} 0"
191 echo "/* HAVE_PARALLEL_INSNS: non-zero if cpu can parallelly execute > 1 insn. */"
192 if [ x
$parallel != xno
] ; then
193 echo "#define HAVE_PARALLEL_INSNS 1"
194 if [ x
$parallel = xread
] ; then
195 echo "/* Parallel execution is supported by read-before-exec. */"
196 echo "#define WITH_PARALLEL_READ 1"
197 echo "#define WITH_PARALLEL_WRITE 0"
199 echo "/* Parallel execution is supported by write-after-exec. */"
200 echo "#define WITH_PARALLEL_READ 0"
201 echo "#define WITH_PARALLEL_WRITE 1"
204 echo "#define HAVE_PARALLEL_INSNS 0"
205 echo "#define WITH_PARALLEL_READ 0"
206 echo "#define WITH_PARALLEL_WRITE 0"
209 if [ "x$switch" != x
] ; then
211 echo "/* WITH_SEM_SWITCH_FULL: non-zero if full-featured engine is"
212 echo " implemented as a switch(). */"
213 if [ x
$fast != xyes
-o x
$full_switch = xyes
] ; then
214 echo "#define WITH_SEM_SWITCH_FULL 1"
216 echo "#define WITH_SEM_SWITCH_FULL 0"
219 echo "/* WITH_SEM_SWITCH_FAST: non-zero if fast engine is"
220 echo " implemented as a switch(). */"
221 if [ x
$fast = xyes
] ; then
222 echo "#define WITH_SEM_SWITCH_FAST 1"
224 echo "#define WITH_SEM_SWITCH_FAST 0"
228 # Decls of functions we define.
231 echo "/* Functions defined in the generated mainloop.c file"
232 echo " (which doesn't necessarily have that file name). */"
234 echo "extern ENGINE_FN ${cpu}_engine_run_full;"
235 echo "extern ENGINE_FN ${cpu}_engine_run_fast;"
237 if [ x
$pbb = xyes
] ; then
239 echo "extern SEM_PC ${cpu}_pbb_begin (SIM_CPU *, int);"
240 echo "extern SEM_PC ${cpu}_pbb_chain (SIM_CPU *, SEM_ARG);"
241 echo "extern SEM_PC ${cpu}_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_PC *, PCADDR);"
242 echo "extern void ${cpu}_pbb_before (SIM_CPU *, SCACHE *);"
243 echo "extern void ${cpu}_pbb_after (SIM_CPU *, SCACHE *);"
246 ##########################################################################
248 rm -f tmp-mloop.cin mloop.cin
251 # We use @cpu@ instead of ${cpu} because we still need to run sed to handle
252 # transformation of @cpu@ for mainloop.in, so there's no need to use ${cpu}
256 /* This file is generated by the genmloop script. DO NOT EDIT! */
258 /* Enable switch() support in cgen headers. */
259 #define SEM_IN_SWITCH
261 #define WANT_CPU @cpu@
262 #define WANT_CPU_@CPU@
264 #include "sim-main.h"
266 #include "cgen-mem.h"
267 #include "cgen-ops.h"
268 #include "sim-assert.h"
270 /* Fill in the administrative ARGBUF fields required by all insns,
274 @cpu@_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
275 PCADDR pc, int fast_p)
278 SEM_SET_CODE (abuf, idesc, fast_p);
279 ARGBUF_ADDR (abuf) = pc;
281 ARGBUF_IDESC (abuf) = idesc;
284 /* Fill in tracing/profiling fields of an ARGBUF. */
287 @cpu@_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
288 int trace_p, int profile_p)
290 ARGBUF_TRACE_P (abuf) = trace_p;
291 ARGBUF_PROFILE_P (abuf) = profile_p;
296 /* Emit the "x-before" handler.
297 x-before is emitted before each insn (serial or parallel).
298 This is as opposed to x-after which is only emitted at the end of a group
299 of parallel insns. */
302 @cpu@_emit_before (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc, int first_p)
304 ARGBUF *abuf = &sc[0].argbuf;
305 const IDESC *id = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEFORE];
307 abuf->fields.before.first_p = first_p;
308 @cpu@_fill_argbuf (current_cpu, abuf, id, pc, 0);
309 /* no need to set trace_p,profile_p */
312 /* Emit the "x-after" handler.
313 x-after is emitted after a serial insn or at the end of a group of
317 @cpu@_emit_after (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc)
319 ARGBUF *abuf = &sc[0].argbuf;
320 const IDESC *id = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_AFTER];
322 @cpu@_fill_argbuf (current_cpu, abuf, id, pc, 0);
323 /* no need to set trace_p,profile_p */
326 #endif /* WITH_SCACHE_PBB */
330 ${SHELL} $infile support
332 ##########################################################################
334 # Simple engine: fetch an instruction, execute the instruction.
336 # Instruction fields are not extracted into ARGBUF, they are extracted in
337 # the semantic routines themselves. However, there is still a need to pass
338 # and return misc. information to the semantic routines so we still use ARGBUF.
339 # [One could certainly implement things differently and remove ARGBUF.
340 # It's not clear this is necessarily always a win.]
341 # ??? The use of the SCACHE struct is for consistency with the with-scache
342 # case though it might be a source of confusion.
344 if [ x
$scache != xyes
-a x
$pbb != xyes
] ; then
351 @cpu@_engine_run_full (SIM_CPU *current_cpu)
354 SIM_DESC current_state = CPU_STATE (current_cpu);
355 /* ??? Use of SCACHE is a bit of a hack as we don't actually use the scache.
356 We do however use ARGBUF so for consistency with the other engine flavours
357 the SCACHE type is used. */
358 SCACHE cache[MAX_LIW_INSNS];
359 SCACHE *sc = &cache[0];
363 if [ x
$parallel != xno
] ; then
365 PAREXEC pbufs[MAX_PARALLEL_INSNS];
371 # Any initialization code before looping starts.
372 # Note that this code may declare some locals.
373 ${SHELL} $infile init
375 if [ x
$parallel != xno
] ; then
378 #if defined (HAVE_PARALLEL_EXEC) && defined (__GNUC__)
380 if (! CPU_IDESC_READ_INIT_P (current_cpu))
382 /* ??? Later maybe paste read.c in when building mainloop.c. */
383 #define DEFINE_LABELS
385 CPU_IDESC_READ_INIT_P (current_cpu) = 1;
395 #if WITH_SEM_SWITCH_FULL && defined (__GNUC__)
397 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
399 /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
400 #define DEFINE_LABELS
402 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
409 /* begin full-exec-simple */
412 ${SHELL} $infile full-exec-simple
415 /* end full-exec-simple */
417 ++ CPU_INSN_COUNT (current_cpu);
419 while (0 /*CPU_RUNNING_P (current_cpu)*/);
426 ####################################
428 # Simple engine: fast version.
429 # ??? A somewhat dubious effort, but for completeness' sake.
431 if [ x
$fast = xyes
] ; then
437 FIXME: "fast simple version unimplemented, delete -fast arg to genmloop.sh."
447 ##########################################################################
449 # Scache engine: lookup insn in scache, fetch if missing, then execute it.
451 if [ x
$scache = xyes
] ; then
455 static INLINE SCACHE *
456 @cpu@_scache_lookup (SIM_CPU *current_cpu, PCADDR vpc, SCACHE *scache,
457 unsigned int hash_mask, int FAST_P)
459 /* First step: look up current insn in hash table. */
460 SCACHE *sc = scache + SCACHE_HASH_PC (vpc, hash_mask);
462 /* If the entry isn't the one we want (cache miss),
463 fetch and decode the instruction. */
464 if (sc->argbuf.addr != vpc)
467 PROFILE_COUNT_SCACHE_MISS (current_cpu);
469 /* begin extract-scache */
472 ${SHELL} $infile extract-scache
475 /* end extract-scache */
479 PROFILE_COUNT_SCACHE_HIT (current_cpu);
480 /* Make core access statistics come out right.
481 The size is a guess, but it's currently not used either. */
482 PROFILE_COUNT_CORE (current_cpu, vpc, 2, exec_map);
491 @cpu@_engine_run_full (SIM_CPU *current_cpu)
493 SIM_DESC current_state = CPU_STATE (current_cpu);
494 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
495 unsigned int hash_mask = CPU_SCACHE_HASH_MASK (current_cpu);
500 if [ x
$parallel != xno
] ; then
502 PAREXEC pbufs[MAX_PARALLEL_INSNS];
508 # Any initialization code before looping starts.
509 # Note that this code may declare some locals.
510 ${SHELL} $infile init
512 if [ x
$parallel != xno
] ; then
515 #if defined (HAVE_PARALLEL_EXEC) && defined (__GNUC__)
517 if (! CPU_IDESC_READ_INIT_P (current_cpu))
519 /* ??? Later maybe paste read.c in when building mainloop.c. */
520 #define DEFINE_LABELS
522 CPU_IDESC_READ_INIT_P (current_cpu) = 1;
538 sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P);
540 /* begin full-exec-scache */
543 ${SHELL} $infile full-exec-scache
546 /* end full-exec-scache */
550 ++ CPU_INSN_COUNT (current_cpu);
552 while (0 /*CPU_RUNNING_P (current_cpu)*/);
559 ####################################
561 # Scache engine: fast version.
563 if [ x
$fast = xyes
] ; then
570 @cpu@_engine_run_fast (SIM_CPU *current_cpu)
572 SIM_DESC current_state = CPU_STATE (current_cpu);
573 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
574 unsigned int hash_mask = CPU_SCACHE_HASH_MASK (current_cpu);
579 if [ x
$parallel != xno
] ; then
581 PAREXEC pbufs[MAX_PARALLEL_INSNS];
587 # Any initialization code before looping starts.
588 # Note that this code may declare some locals.
589 ${SHELL} $infile init
591 if [ x
$parallel != xno
] ; then
594 #if defined (HAVE_PARALLEL_EXEC) && defined (__GNUC__)
596 if (! CPU_IDESC_READ_INIT_P (current_cpu))
598 /* ??? Later maybe paste read.c in when building mainloop.c. */
599 #define DEFINE_LABELS
601 CPU_IDESC_READ_INIT_P (current_cpu) = 1;
611 #if WITH_SEM_SWITCH_FAST && defined (__GNUC__)
613 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
615 /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
616 #define DEFINE_LABELS
618 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
629 sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P);
631 /* begin fast-exec-scache */
634 ${SHELL} $infile fast-exec-scache
637 /* end fast-exec-scache */
641 ++ CPU_INSN_COUNT (current_cpu);
643 while (0 /*CPU_RUNNING_P (current_cpu)*/);
654 ##########################################################################
656 # Compilation engine: lookup insn in scache, extract a pbb
657 # (pseudo-basic-block) if missing, then execute the pbb.
658 # A "pbb" is a sequence of insns up to the next cti insn or until
659 # some prespecified maximum.
660 # CTI: control transfer instruction.
662 if [ x
$pbb = xyes
] ; then
666 /* Record address of cti terminating a pbb. */
667 #define SET_CTI_VPC(sc) do { _cti_sc = (sc); } while (0)
668 /* Record number of [real] insns in pbb. */
669 #define SET_INSN_COUNT(n) do { _insn_count = (n); } while (0)
671 /* Fetch and extract a pseudo-basic-block.
672 FAST_P is non-zero if no tracing/profiling/etc. is wanted. */
675 @cpu@_pbb_begin (SIM_CPU *current_cpu, int FAST_P)
680 int max_insns = CPU_SCACHE_MAX_CHAIN_LENGTH (current_cpu);
684 new_vpc = scache_lookup_or_alloc (current_cpu, pc, max_insns, &sc);
687 /* Leading '_' to avoid collision with mainloop.in. */
689 SCACHE *orig_sc = sc;
690 SCACHE *_cti_sc = NULL;
691 int slice_insns = CPU_MAX_SLICE_INSNS (current_cpu);
693 /* First figure out how many instructions to compile.
694 MAX_INSNS is the size of the allocated buffer, which includes space
695 for before/after handlers if they're being used.
696 SLICE_INSNS is the maxinum number of real insns that can be
697 executed. Zero means "as many as we want". */
698 /* ??? max_insns is serving two incompatible roles.
699 1) Number of slots available in scache buffer.
700 2) Number of real insns to execute.
701 They're incompatible because there are virtual insns emitted too
702 (chain,cti-chain,before,after handlers). */
704 if (slice_insns == 1)
706 /* No need to worry about extra slots required for virtual insns
707 and parallel exec support because MAX_CHAIN_LENGTH is
708 guaranteed to be big enough to execute at least 1 insn! */
713 /* Allow enough slop so that while compiling insns, if max_insns > 0
714 then there's guaranteed to be enough space to emit one real insn.
715 MAX_CHAIN_LENGTH is typically much longer than
716 the normal number of insns between cti's anyway. */
717 max_insns -= (1 /* one for the trailing chain insn */
720 : (1 + MAX_PARALLEL_INSNS) /* before+after */)
721 + (MAX_PARALLEL_INSNS > 1
722 ? (MAX_PARALLEL_INSNS * 2)
725 /* Account for before/after handlers. */
730 && slice_insns < max_insns)
731 max_insns = slice_insns;
736 /* SC,PC must be updated to point passed the last entry used.
737 SET_CTI_VPC must be called if pbb is terminated by a cti.
738 SET_INSN_COUNT must be called to record number of real insns in
739 pbb [could be computed by us of course, extra cpu but perhaps
740 negligible enough]. */
742 /* begin extract-pbb */
745 ${SHELL} $infile extract-pbb
748 /* end extract-pbb */
750 /* The last one is a pseudo-insn to link to the next chain.
751 It is also used to record the insn count for this chain. */
755 /* Was pbb terminated by a cti? */
758 id = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_CTI_CHAIN];
762 id = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_CHAIN];
764 SEM_SET_CODE (&sc->argbuf, id, FAST_P);
765 sc->argbuf.idesc = id;
766 sc->argbuf.addr = pc;
767 sc->argbuf.fields.chain.insn_count = _insn_count;
768 sc->argbuf.fields.chain.next = 0;
772 /* Update the pointer to the next free entry, may not have used as
773 many entries as was asked for. */
774 CPU_SCACHE_NEXT_FREE (current_cpu) = sc;
775 /* Record length of chain if profiling.
776 This includes virtual insns since they count against
779 PROFILE_COUNT_SCACHE_CHAIN_LENGTH (current_cpu, sc - orig_sc);
785 /* Chain to the next block from a non-cti terminated previous block. */
788 @cpu@_pbb_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg)
790 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
792 PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
794 SET_H_PC (abuf->addr);
796 /* If not running forever, exit back to main loop. */
797 if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
798 /* Also exit back to main loop if there's an event.
799 Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
800 at the "right" time, but then that was what was asked for.
801 There is no silver bullet for simulator engines.
802 ??? Clearly this needs a cleaner interface.
803 At present it's just so Ctrl-C works. */
804 || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
805 CPU_RUNNING_P (current_cpu) = 0;
807 /* If chained to next block, go straight to it. */
808 if (abuf->fields.chain.next)
809 return abuf->fields.chain.next;
810 /* See if next block has already been compiled. */
811 abuf->fields.chain.next = scache_lookup (current_cpu, abuf->addr);
812 if (abuf->fields.chain.next)
813 return abuf->fields.chain.next;
814 /* Nope, so next insn is a virtual insn to invoke the compiler
816 return CPU_SCACHE_PBB_BEGIN (current_cpu);
819 /* Chain to the next block from a cti terminated previous block.
820 NEW_VPC_PTR is one of SEM_BRANCH_UNTAKEN, SEM_BRANCH_UNCACHEABLE, or
821 a pointer to a location containing the SEM_PC of the branch's address.
822 NEW_PC is the target's branch address, and is only valid if
823 NEW_VPC_PTR != SEM_BRANCH_UNTAKEN. */
826 @cpu@_pbb_cti_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg,
827 SEM_PC *new_vpc_ptr, PCADDR new_pc)
829 PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
831 /* If not running forever, exit back to main loop. */
832 if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
833 /* Also exit back to main loop if there's an event.
834 Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
835 at the "right" time, but then that was what was asked for.
836 There is no silver bullet for simulator engines.
837 ??? Clearly this needs a cleaner interface.
838 At present it's just so Ctrl-C works. */
839 || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
840 CPU_RUNNING_P (current_cpu) = 0;
842 /* Restart compiler if we branched to an uncacheable address
844 if (new_vpc_ptr == SEM_BRANCH_UNCACHEABLE)
847 return CPU_SCACHE_PBB_BEGIN (current_cpu);
850 /* If branch wasn't taken, update the pc and set BR_ADDR_PTR to our
852 if (new_vpc_ptr == SEM_BRANCH_UNTAKEN)
854 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
855 SET_H_PC (abuf->addr);
856 new_vpc_ptr = &abuf->fields.chain.next;
863 /* If chained to next block, go straight to it. */
866 /* See if next block has already been compiled. */
867 *new_vpc_ptr = scache_lookup (current_cpu, GET_H_PC ());
870 /* Nope, so next insn is a virtual insn to invoke the compiler
872 return CPU_SCACHE_PBB_BEGIN (current_cpu);
876 This is called before each insn. */
879 @cpu@_pbb_before (SIM_CPU *current_cpu, SCACHE *sc)
881 SEM_ARG sem_arg = sc;
882 const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
883 int first_p = abuf->fields.before.first_p;
884 const ARGBUF *cur_abuf = SEM_ARGBUF (sc + 1);
885 const IDESC *cur_idesc = cur_abuf->idesc;
886 PCADDR pc = cur_abuf->addr;
888 if (ARGBUF_PROFILE_P (cur_abuf))
889 PROFILE_COUNT_INSN (current_cpu, pc, cur_idesc->num);
891 /* If this isn't the first insn, finish up the previous one. */
895 if (PROFILE_MODEL_P (current_cpu))
897 const SEM_ARG prev_sem_arg = sc - 1;
898 const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
899 const IDESC *prev_idesc = prev_abuf->idesc;
902 /* ??? May want to measure all insns if doing insn tracing. */
903 if (ARGBUF_PROFILE_P (prev_abuf))
905 cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
906 @cpu@_model_insn_after (current_cpu, 0 /*last_p*/, cycles);
910 TRACE_INSN_FINI (current_cpu, cur_abuf, 0 /*last_p*/);
913 /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
914 if (PROFILE_MODEL_P (current_cpu)
915 && ARGBUF_PROFILE_P (cur_abuf))
916 @cpu@_model_insn_before (current_cpu, first_p);
918 TRACE_INSN_INIT (current_cpu, cur_abuf, first_p);
919 TRACE_INSN (current_cpu, cur_idesc->idata, cur_abuf, pc);
923 This is called after a serial insn or at the end of a group of parallel
927 @cpu@_pbb_after (SIM_CPU *current_cpu, SCACHE *sc)
929 SEM_ARG sem_arg = sc;
930 const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
931 const SEM_ARG prev_sem_arg = sc - 1;
932 const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
934 /* ??? May want to measure all insns if doing insn tracing. */
935 if (PROFILE_MODEL_P (current_cpu)
936 && ARGBUF_PROFILE_P (prev_abuf))
938 const IDESC *prev_idesc = prev_abuf->idesc;
941 cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
942 @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
944 TRACE_INSN_FINI (current_cpu, prev_abuf, 1 /*last_p*/);
950 @cpu@_engine_run_full (SIM_CPU *current_cpu)
952 SIM_DESC current_state = CPU_STATE (current_cpu);
953 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
954 /* virtual program counter */
956 #if WITH_SEM_SWITCH_FULL
957 /* For communication between cti's and cti-chain. */
959 SEM_PC *pbb_br_npc_ptr;
964 if [ x
$parallel != xno
] ; then
966 PAREXEC pbufs[MAX_PARALLEL_INSNS];
967 PAREXEC *par_exec = &pbufs[0];
972 # Any initialization code before looping starts.
973 # Note that this code may declare some locals.
974 ${SHELL} $infile init
978 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
980 /* ??? 'twould be nice to move this up a level and only call it once.
981 On the other hand, in the "let's go fast" case the test is only done
982 once per pbb (since we only return to the main loop at the end of
983 a pbb). And in the "let's run until we're done" case we don't return
984 until the program exits. */
986 #if WITH_SEM_SWITCH_FULL && defined (__GNUC__)
987 /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
988 #define DEFINE_LABELS
992 /* Initialize the "begin (compile) a pbb" virtual insn. */
993 vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
994 SEM_SET_FULL_CODE (SEM_ARGBUF (vpc),
995 & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEGIN]);
996 vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEGIN];
998 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
1001 CPU_RUNNING_P (current_cpu) = 1;
1002 /* ??? In the case where we're returning to the main loop after every
1003 pbb we don't want to call pbb_begin each time (which hashes on the pc
1004 and does a table lookup). A way to speed this up is to save vpc
1006 vpc = @cpu@_pbb_begin (current_cpu, FAST_P);
1010 /* begin full-exec-pbb */
1013 ${SHELL} $infile full-exec-pbb
1016 /* end full-exec-pbb */
1018 while (CPU_RUNNING_P (current_cpu));
1025 ####################################
1027 # Compile engine: fast version.
1029 if [ x
$fast = xyes
] ; then
1036 @cpu@_engine_run_fast (SIM_CPU *current_cpu)
1038 SIM_DESC current_state = CPU_STATE (current_cpu);
1039 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
1040 /* virtual program counter */
1042 #if WITH_SEM_SWITCH_FAST
1043 /* For communication between cti's and cti-chain. */
1045 SEM_PC *pbb_br_npc_ptr;
1050 if [ x
$parallel != xno
] ; then
1052 PAREXEC pbufs[MAX_PARALLEL_INSNS];
1053 PAREXEC *par_exec = &pbufs[0];
1058 # Any initialization code before looping starts.
1059 # Note that this code may declare some locals.
1060 ${SHELL} $infile init
1064 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
1066 /* ??? 'twould be nice to move this up a level and only call it once.
1067 On the other hand, in the "let's go fast" case the test is only done
1068 once per pbb (since we only return to the main loop at the end of
1069 a pbb). And in the "let's run until we're done" case we don't return
1070 until the program exits. */
1072 #if WITH_SEM_SWITCH_FAST && defined (__GNUC__)
1073 /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
1074 #define DEFINE_LABELS
1078 /* Initialize the "begin (compile) a pbb" virtual insn. */
1079 vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
1080 SEM_SET_FAST_CODE (SEM_ARGBUF (vpc),
1081 & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEGIN]);
1082 vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEGIN];
1084 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
1087 CPU_RUNNING_P (current_cpu) = 1;
1088 /* ??? In the case where we're returning to the main loop after every
1089 pbb we don't want to call pbb_begin each time (which hashes on the pc
1090 and does a table lookup). A way to speed this up is to save vpc
1092 vpc = @cpu@_pbb_begin (current_cpu, FAST_P);
1096 /* begin fast-exec-pbb */
1099 ${SHELL} $infile fast-exec-pbb
1102 /* end fast-exec-pbb */
1104 while (CPU_RUNNING_P (current_cpu));
1114 # Process @cpu@,@CPU@ appearing in mainloop.in.
1115 sed -e "s/@cpu@/$cpu/g" -e "s/@CPU@/$CPU/g" < tmp-mloop.cin
> mloop.cin
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