1 /* This file is part of the program psim.
3 Copyright (C) 1994-1998, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 /* declared in sim-basics.h, this object is used everywhere */
26 /* typedef struct _device device; */
31 As explained in earlier sections, the device, device instance,
32 property and ports lie at the heart of PSIM's device model.
34 In the below a synopsis of the device object and the operations it
41 The devices are created using a sequence of steps. In particular:
43 o A tree framework is created.
45 At this point, properties can be modified and extra
46 devices inserted (or removed?).
50 Any properties that have a run-time value (eg ihandle
51 or device instance pointer properties) are entered
52 into the device tree using a named reference to the
53 corresponding runtime object that is to be created.
57 o Real devices are created for all the dummy devices.
59 A device can assume that all of its parents have been
62 A device can assume that all non run-time properties
63 have been initialized.
65 As part of being created, the device normally attaches
66 itself to its parent bus.
70 Device instance data is initialized.
76 o Any run-time properties are created.
82 o Some devices, as part of their initialization
83 might want to refer to ihandle properties
90 o It is important to separate the creation
91 of an actual device from the creation
92 of the tree. The alternative creating
93 the device in two stages: As a separate
94 entity and then as a part of the tree.
97 o Run-time properties can not be created
98 until after the devices in the tree
99 have been created. Hence an extra pass
107 A device is able to determine its relationship to other devices
108 within the tree. Operations include querying for a devices parent,
109 sibling, child, name, and path (from the root).
114 #define hw_parent(hw) ((hw)->parent_of_hw + 0)
116 #define hw_sibling(hw) ((hw)->sibling_of_hw + 0)
118 #define hw_child(hw) ((hw)->child_of_hw + 0)
126 #define hw_family(hw) ((hw)->family_of_hw + 0)
128 #define hw_name(hw) ((hw)->name_of_hw + 0)
130 #define hw_args(hw) ((hw)->args_of_hw + 0)
132 #define hw_path(hw) ((hw)->path_of_hw + 0)
136 /* Short cut to the root node of the tree */
138 #define hw_root(hw) ((hw)->root_of_hw + 0)
140 /* Short cut back to the simulator object */
142 #define hw_system(hw) ((hw)->system_of_hw)
144 /* For requests initiated by a CPU the cpu that initiated the request */
146 struct _sim_cpu
*hw_system_cpu (struct hw
*hw
);
149 /* Device private data */
151 #define hw_data(hw) ((hw)->data_of_hw)
155 /* Perform a soft reset of the device */
157 typedef unsigned (hw_reset_callback
)
160 #define hw_reset(hw) ((hw)->to_reset (hw))
163 /* Hardware operations:
165 Connecting a parent to its children is a common bus. The parent
166 node is described as the bus owner and is responisble for
167 co-ordinating bus operations. On the bus, a SPACE:ADDR pair is used
168 to specify an address. A device that is both a bus owner (parent)
169 and bus client (child) are refered to as a bridging device.
171 A child performing a data (DMA) transfer will pass its request to
172 the bus owner (the devices parent). The bus owner will then either
173 reflect the request to one of the other devices attached to the bus
174 (a child of the bus owner) or bridge the request up the tree to the
178 /* Children attached to a bus can register (attach) themselves to
179 specific addresses on their attached bus.
181 (A device may also be implicitly attached to certain bus
184 The SPACE:ADDR pair specify an address on the common bus that
185 connects the parent and child devices. */
187 typedef void (hw_attach_address_callback
)
192 address_word nr_bytes
,
193 struct hw
*client
); /*callback/default*/
195 #define hw_attach_address(me, level, space, addr, nr_bytes, client) \
196 ((me)->to_attach_address (me, level, space, addr, nr_bytes, client))
199 typedef void (hw_detach_address_callback
)
204 address_word nr_bytes
,
205 struct hw
*client
); /*callback/default*/
207 #define hw_detach_address(me, level, space, addr, nr_bytes, client) \
208 ((me)->to_detach_address (me, level, space, addr, nr_bytes, client))
211 /* An IO operation from a parent to a child via the conecting bus.
213 The SPACE:ADDR pair specify an address on the bus shared between
214 the parent and child devices. */
216 typedef unsigned (hw_io_read_buffer_callback
)
223 #define hw_io_read_buffer(hw, dest, space, addr, nr_bytes) \
224 ((hw)->to_io_read_buffer (hw, dest, space, addr, nr_bytes))
226 typedef unsigned (hw_io_write_buffer_callback
)
233 #define hw_io_write_buffer(hw, src, space, addr, nr_bytes) \
234 ((hw)->to_io_write_buffer (hw, src, space, addr, nr_bytes))
238 /* Conversly, the device pci1000,1@1 may need to perform a dma transfer
239 into the cpu/memory core. Just as I/O moves towards the leaves,
240 dma transfers move towards the core via the initiating devices
241 parent nodes. The root device (special) converts the DMA transfer
242 into reads/writes to memory.
244 The SPACE:ADDR pair specify an address on the common bus connecting
245 the parent and child devices. */
247 typedef unsigned (hw_dma_read_buffer_callback
)
254 #define hw_dma_read_buffer(bus, dest, space, addr, nr_bytes) \
255 ((bus)->to_dma_read_buffer (bus, dest, space, addr, nr_bytes))
257 typedef unsigned (hw_dma_write_buffer_callback
)
263 int violate_read_only_section
);
265 #define hw_dma_write_buffer(bus, src, space, addr, nr_bytes, violate_ro) \
266 ((bus)->to_dma_write_buffer (bus, src, space, addr, nr_bytes, violate_ro))
268 /* Address/size specs for devices are encoded following a convention
269 similar to that used by OpenFirmware. In particular, an
270 address/size is packed into a sequence of up to four cell words.
271 The number of words determined by the number of {address,size}
272 cells attributes of the device. */
274 typedef struct _hw_unit
{
276 unsigned_cell cells
[4]; /* unused cells are zero */
280 /* For the given bus, the number of address and size cells used in a
283 #define hw_unit_nr_address_cells(bus) ((bus)->nr_address_cells_of_hw_unit + 0)
285 #define hw_unit_nr_size_cells(bus) ((bus)->nr_size_cells_of_hw_unit + 0)
288 /* For the given device, its identifying hw_unit address.
290 Each device has an identifying hw_unit address. That address is
291 used when identifying one of a number of identical devices on a
292 common controller bus. ex fd0&fd1. */
294 const hw_unit
*hw_unit_address
298 /* Convert between a textual and the internal representation of a
299 hw_unit address/size.
301 NOTE: A device asks its parent to translate between a hw_unit and
302 textual representation. This is because the textual address of a
303 device is specified using the parent busses notation. */
305 typedef int (hw_unit_decode_callback
)
310 #define hw_unit_decode(bus, encoded, unit) \
311 ((bus)->to_unit_decode (bus, encoded, unit))
314 typedef int (hw_unit_encode_callback
)
320 #define hw_unit_encode(bus, unit, encoded, sizeof_encoded) \
321 ((bus)->to_unit_encode (bus, unit, encoded, sizeof_encoded))
325 /* As the bus that the device is attached too, to translate a devices
326 hw_unit address/size into a form suitable for an attach address
329 Return a zero result if the address should be ignored when looking
330 for attach addresses. */
332 typedef int (hw_unit_address_to_attach_address_callback
)
334 const hw_unit
*unit_addr
,
336 unsigned_word
*attach_addr
,
339 #define hw_unit_address_to_attach_address(bus, unit_addr, attach_space, attach_addr, client) \
340 ((bus)->to_unit_address_to_attach_address (bus, unit_addr, attach_space, attach_addr, client))
343 typedef int (hw_unit_size_to_attach_size_callback
)
345 const hw_unit
*unit_size
,
346 unsigned *attach_size
,
349 #define hw_unit_size_to_attach_size(bus, unit_size, attach_size, client) \
350 ((bus)->to_unit_size_to_attach_size (bus, unit_size, attach_size, client))
354 extern char *hw_strdup (struct hw
*me
, const char *str
);
363 Often devices require `out of band' operations to be performed.
364 For instance a pal device may need to notify a PCI bridge device
365 that an interrupt ack cycle needs to be performed on the PCI bus.
366 Within PSIM such operations are performed by using the generic
367 ioctl call <<hw_ioctl()>>.
372 hw_ioctl_break
, /* unsigned_word requested_break */
373 hw_ioctl_set_trace
, /* void */
374 hw_ioctl_create_stack
, /* unsigned_word *sp, char **argv, char **envp */
375 hw_ioctl_change_media
, /* const char *new_image (possibly NULL) */
376 nr_hw_ioctl_requests
,
379 typedef int (hw_ioctl_callback
)
381 hw_ioctl_request request
,
386 hw_ioctl_request request
,
392 So that errors originating from devices appear in a consistent
393 format, the <<hw_abort()>> function can be used. Formats and
394 outputs the error message before aborting the simulation
396 Devices should use this function to abort the simulation except
397 when the abort reason leaves the simulation in a hazardous
398 condition (for instance a failed malloc).
405 ...) __attribute__ ((format (printf
, 2, 3)));
418 #define hw_trace_p(hw) ((hw)->trace_of_hw_p + 0)
423 ...) __attribute__ ((format (printf
, 2, 3)));
425 #define HW_TRACE(ARGS) \
427 if (hw_trace_p (me)) \
434 /* Some of the related functions require specific types */
436 struct hw_property_data
;
439 struct hw_alloc_data
;
440 struct hw_event_data
;
442 /* Finally the hardware device - keep your grubby little mits off of
443 these internals! :-) */
448 struct hw
*parent_of_hw
;
449 struct hw
*sibling_of_hw
;
450 struct hw
*child_of_hw
;
453 const char *name_of_hw
;
454 const char *family_of_hw
;
455 const char *args_of_hw
;
456 const char *path_of_hw
;
462 struct hw
*root_of_hw
;
463 struct sim_state
*system_of_hw
;
465 /* identifying data */
466 hw_unit unit_address_of_hw
;
467 int nr_address_cells_of_hw_unit
;
468 int nr_size_cells_of_hw_unit
;
471 hw_reset_callback
*to_reset
;
473 /* Basic callbacks */
474 hw_io_read_buffer_callback
*to_io_read_buffer
;
475 hw_io_write_buffer_callback
*to_io_write_buffer
;
476 hw_dma_read_buffer_callback
*to_dma_read_buffer
;
477 hw_dma_write_buffer_callback
*to_dma_write_buffer
;
478 hw_attach_address_callback
*to_attach_address
;
479 hw_detach_address_callback
*to_detach_address
;
481 /* More complicated callbacks */
482 hw_ioctl_callback
*to_ioctl
;
485 /* address callbacks */
486 hw_unit_decode_callback
*to_unit_decode
;
487 hw_unit_encode_callback
*to_unit_encode
;
488 hw_unit_address_to_attach_address_callback
*to_unit_address_to_attach_address
;
489 hw_unit_size_to_attach_size_callback
*to_unit_size_to_attach_size
;
492 struct hw_property_data
*properties_of_hw
;
493 struct hw_port_data
*ports_of_hw
;
494 struct hw_base_data
*base_of_hw
;
495 struct hw_alloc_data
*alloc_of_hw
;
496 struct hw_event_data
*events_of_hw
;