Start of implementation of a distributed (between processors)
[deliverable/binutils-gdb.git] / sim / common / sim-base.h
1 /* Simulator pseudo baseclass.
2 Copyright (C) 1997 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21
22 /* Simulator state pseudo baseclass.
23
24 Each simulator is required to have a sim-main.h file that includes
25 sim-basics.h, defines the base type sim_cia (the data type that
26 contains the complete current instruction address information), and
27 then sim-base.h:
28
29 #include "sim-basics.h"
30 typedef address_word sim_cia;
31 #include "sim-base.h"
32
33 and defines two key simulator structures. Firstly, struct
34 _sim_cpu:
35
36 struct _sim_cpu {
37 ... simulator specific members ...
38 sim_cpu_base base;
39 };
40
41 and secondly, struct sim_state (which uses the sim_cpu structure):
42
43 struct sim_state {
44 sim_cpu cpu[MAX_NR_PROCESSORS];
45 #if (WITH_SMP)
46 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
47 #else
48 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
49 #endif
50 ... simulator specific members ...
51 sim_state_base base;
52 };
53
54 Note that `base' appears last. This makes `base.magic' appear last
55 in the entire struct and helps catch miscompilation errors. */
56
57
58 #ifndef SIM_BASE_H
59 #define SIM_BASE_H
60
61 /* Pre-declare certain types. */
62
63 /* typedef <target-dependant> sim_cia; */
64 #ifndef NULL_CIA
65 #define NULL_CIA ((sim_cia) 0)
66 #endif
67 typedef struct _sim_cpu sim_cpu;
68
69 #include "sim-module.h"
70 #include "sim-trace.h"
71 #include "sim-profile.h"
72 #include "sim-model.h"
73 #include "sim-core.h"
74 #include "sim-events.h"
75 #include "sim-io.h"
76
77
78 /* Global pointer to current state while sim_resume is running.
79 On a machine with lots of registers, it might be possible to reserve
80 one of them for current_state. However on a machine with few registers
81 current_state can't permanently live in one and indirecting through it
82 will be slower [in which case one can have sim_resume set globals from
83 current_state for faster access].
84 If CURRENT_STATE_REG is defined, it means current_state is living in
85 a global register. */
86
87
88 #ifdef CURRENT_STATE_REG
89 /* FIXME: wip */
90 #else
91 extern struct sim_state *current_state;
92 #endif
93
94
95 /* The simulator may provide different (and faster) definition. */
96 #ifndef CURRENT_STATE
97 #define CURRENT_STATE current_state
98 #endif
99
100
101 typedef struct {
102
103 /* Simulator's argv[0]. */
104 const char *my_name;
105 #define STATE_MY_NAME(sd) ((sd)->base.my_name)
106
107 /* Who opened the simulator. */
108 SIM_OPEN_KIND open_kind;
109 #define STATE_OPEN_KIND(sd) ((sd)->base.open_kind)
110
111 /* The host callbacks. */
112 struct host_callback_struct *callback;
113 #define STATE_CALLBACK(sd) ((sd)->base.callback)
114
115 #if 0 /* FIXME: Not ready yet. */
116 /* Stuff defined in sim-config.h. */
117 struct sim_config config;
118 #define STATE_CONFIG(sd) ((sd)->base.config)
119 #endif
120
121 /* List of installed module `init' handlers. */
122 MODULE_INIT_LIST *init_list;
123 #define STATE_INIT_LIST(sd) ((sd)->base.init_list)
124 /* List of installed module `uninstall' handlers. */
125 MODULE_UNINSTALL_LIST *uninstall_list;
126 #define STATE_UNINSTALL_LIST(sd) ((sd)->base.uninstall_list)
127
128 /* ??? This might be more appropriate in sim_cpu. */
129 /* Machine tables for this cpu. See sim-model.h. */
130 const MODEL *model;
131 #define STATE_MODEL(sd) ((sd)->base.model)
132
133 /* Supported options. */
134 struct option_list *options;
135 #define STATE_OPTIONS(sd) ((sd)->base.options)
136
137 /* Non-zero if -v specified. */
138 int verbose_p;
139 #define STATE_VERBOSE_P(sd) ((sd)->base.verbose_p)
140
141 /* In standalone simulator, this is the program's arguments passed
142 on the command line. */
143 char **prog_argv;
144 #define STATE_PROG_ARGV(sd) ((sd)->base.prog_argv)
145
146 /* The program's bfd. */
147 struct _bfd *prog_bfd;
148 #define STATE_PROG_BFD(sd) ((sd)->base.prog_bfd)
149
150 /* The program's text section. */
151 struct sec *text_section;
152 /* Starting and ending text section addresses from the bfd. */
153 SIM_ADDR text_start, text_end;
154 #define STATE_TEXT_SECTION(sd) ((sd)->base.text_section)
155 #define STATE_TEXT_START(sd) ((sd)->base.text_start)
156 #define STATE_TEXT_END(sd) ((sd)->base.text_end)
157
158 /* Start address, set when the program is loaded from the bfd. */
159 SIM_ADDR start_addr;
160 #define STATE_START_ADDR(sd) ((sd)->base.start_addr)
161
162 #if WITH_SCACHE
163 /* Size of the simulator's cache, if any.
164 This is not the target's cache. It is the cache the simulator uses
165 to process instructions. */
166 unsigned int scache_size;
167 #define STATE_SCACHE_SIZE(sd) ((sd)->base.scache_size)
168 #endif
169
170 /* FIXME: Move to top level sim_state struct (as some struct)? */
171 #ifdef SIM_HAVE_FLATMEM
172 unsigned int mem_size;
173 #define STATE_MEM_SIZE(sd) ((sd)->base.mem_size)
174 unsigned char *memory;
175 #define STATE_MEMORY(sd) ((sd)->base.memory)
176 #endif
177
178 /* core memory bus */
179 #define STATE_CORE(sd) (&(sd)->base.core)
180 sim_core core;
181
182 /* event handler */
183 #define STATE_EVENTS(sd) (&(sd)->base.events)
184 sim_events events;
185
186 /* Marker for those wanting to do sanity checks.
187 This should remain the last member of this struct to help catch
188 miscompilation errors. */
189 int magic;
190 #define SIM_MAGIC_NUMBER 0x4242
191 #define STATE_MAGIC(sd) ((sd)->base.magic)
192
193 } sim_state_base;
194
195
196 /* Pseudo baseclass for each cpu. */
197
198 typedef struct {
199
200 /* Backlink to main state struct. */
201 SIM_DESC state;
202 #define CPU_STATE(cpu) ((cpu)->base.state)
203
204 /* Processor specific core data */
205 #define CPU_CORE(cpu) (& (cpu)->base.core)
206 sim_cpu_core core;
207
208 /* Trace data. See sim-trace.h. */
209 TRACE_DATA trace_data;
210 #define CPU_TRACE_DATA(cpu) (& (cpu)->base.trace_data)
211
212 /* Maximum number of debuggable entities.
213 This debugging is not intended for normal use.
214 It is only enabled when the simulator is configured with --with-debug
215 which shouldn't normally be specified. */
216 #ifndef MAX_DEBUG_VALUES
217 #define MAX_DEBUG_VALUES 4
218 #endif
219
220 /* Boolean array of specified debugging flags. */
221 char debug_flags[MAX_DEBUG_VALUES];
222 #define CPU_DEBUG_FLAGS(cpu) ((cpu)->base.debug_flags)
223 /* Standard values. */
224 #define DEBUG_INSN_IDX 0
225 #define DEBUG_NEXT_IDX 2 /* simulator specific debug bits begin here */
226
227 /* Debugging output goes to this or stderr if NULL.
228 We can't store `stderr' here as stderr goes through a callback. */
229 FILE *debug_file;
230 #define CPU_DEBUG_FILE(cpu) ((cpu)->base.debug_file)
231
232 /* Profile data. See sim-profile.h. */
233 PROFILE_DATA profile_data;
234 #define CPU_PROFILE_DATA(cpu) (& (cpu)->base.profile_data)
235
236 } sim_cpu_base;
237
238
239 /* Functions for allocating/freeing a sim_state. */
240 SIM_DESC sim_state_alloc PARAMS ((void));
241 void sim_state_free PARAMS ((SIM_DESC));
242
243
244 #endif /* SIM_BASE_H */
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