sim/common/sim-core.c

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 #ifndef _SIM_CORE_C_
  23 #define _SIM_CORE_C_
  24
  25 #include "sim-main.h"
  26 #include "sim-assert.h"
  27
  28
  29 /* "core" module install handler.
  30
  31    This is called via sim_module_install to install the "core" subsystem
  32    into the simulator.  */
  33
  34 static MODULE_INIT_FN sim_core_init;
  35 static MODULE_UNINSTALL_FN sim_core_uninstall;
  36
  37 EXTERN_SIM_CORE\
  38 (SIM_RC)
  39 sim_core_install (SIM_DESC sd)
  40 {
  41   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
  42
  43   /* establish the other handlers */
  44   sim_module_add_uninstall_fn (sd, sim_core_uninstall);
  45   sim_module_add_init_fn (sd, sim_core_init);
  46
  47   /* establish any initial data structures - none */
  48   return SIM_RC_OK;
  49 }
  50
  51
  52 /* Uninstall the "core" subsystem from the simulator.  */
  53
  54 STATIC_SIM_CORE\
  55 (void)
  56 sim_core_uninstall (SIM_DESC sd)
  57 {
  58   sim_core *core = STATE_CORE(sd);
  59   sim_core_maps map;
  60   /* blow away any mappings */
  61   for (map = 0; map < nr_sim_core_maps; map++) {
  62     sim_core_mapping *curr = core->common.map[map].first;
  63     while (curr != NULL) {
  64       sim_core_mapping *tbd = curr;
  65       curr = curr->next;
  66       if (tbd->free_buffer) {
  67         SIM_ASSERT(tbd->buffer != NULL);
  68         zfree(tbd->buffer);
  69       }
  70       zfree(tbd);
  71     }
  72     core->common.map[map].first = NULL;
  73   }
  74 }
  75
  76
  77 STATIC_SIM_CORE\
  78 (SIM_RC)
  79 sim_core_init (SIM_DESC sd)
  80 {
  81   /* Nothing to do */
  82   return SIM_RC_OK;
  83 }
  84
  85
  86
  87 #ifndef SIM_CORE_SIGNAL
  88 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  89 sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  90
  91 STATIC_SIM_CORE\
  92 (void)
  93 sim_core_signal (SIM_DESC sd,
  94                  sim_cpu *cpu,
  95                  sim_cia cia,
  96                  sim_core_maps map,
  97                  int nr_bytes,
  98                  address_word addr,
  99                  transfer_type transfer,
 100                  sim_core_signals sig)
 101 {
 102   const char *copy = (transfer == read_transfer ? "read" : "write");
 103   switch (sig)
 104     {
 105     case sim_core_unmapped_signal:
 106       sim_engine_abort (sd, cpu, cia, "sim-core: %d byte %s to unmaped address 0x%lx",
 107                         nr_bytes, copy, (unsigned long) addr);
 108       break;
 109     case sim_core_unaligned_signal:
 110       sim_engine_abort (sd, cpu, cia, "sim-core: %d byte misaligned %s to address 0x%lx",
 111                         nr_bytes, copy, (unsigned long) addr);
 112       break;
 113     default:
 114       sim_engine_abort (sd, cpu, cia, "sim_core_signal - internal error - bad switch");
 115     }
 116 }
 117 #endif
 118
 119
 120 STATIC_INLINE_SIM_CORE\
 121 (const char *)
 122 sim_core_map_to_str (sim_core_maps map)
 123 {
 124   switch (map)
 125     {
 126     case sim_core_read_map: return "read";
 127     case sim_core_write_map: return "write";
 128     case sim_core_execute_map: return "exec";
 129     default: return "(invalid-map)";
 130     }
 131 }
 132
 133
 134 STATIC_SIM_CORE\
 135 (sim_core_mapping *)
 136 new_sim_core_mapping (SIM_DESC sd,
 137                       attach_type attach,
 138                       int space,
 139                       address_word addr,
 140                       address_word nr_bytes,
 141                       unsigned modulo,
 142                       device *device,
 143                       void *buffer,
 144                       int free_buffer)
 145 {
 146   sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping);
 147   /* common */
 148   new_mapping->level = attach;
 149   new_mapping->space = space;
 150   new_mapping->base = addr;
 151   new_mapping->nr_bytes = nr_bytes;
 152   new_mapping->bound = addr + (nr_bytes - 1);
 153   if (modulo == 0)
 154     new_mapping->mask = (unsigned) 0 - 1;
 155   else
 156     new_mapping->mask = modulo - 1;
 157   if (attach == attach_raw_memory)
 158     {
 159       new_mapping->buffer = buffer;
 160       new_mapping->free_buffer = free_buffer;
 161     }
 162   else if (attach >= attach_callback)
 163     {
 164       new_mapping->device = device;
 165     }
 166   else {
 167     sim_io_error (sd, "new_sim_core_mapping - internal error - unknown attach type %d\n",
 168                   attach);
 169   }
 170   return new_mapping;
 171 }
 172
 173
 174 STATIC_SIM_CORE\
 175 (void)
 176 sim_core_map_attach (SIM_DESC sd,
 177                      sim_core_map *access_map,
 178                      attach_type attach,
 179                      int space,
 180                      address_word addr,
 181                      address_word nr_bytes,
 182                      unsigned modulo,
 183                      device *client, /*callback/default*/
 184                      void *buffer, /*raw_memory*/
 185                      int free_buffer) /*raw_memory*/
 186 {
 187   /* find the insertion point for this additional mapping and then
 188      insert */
 189   sim_core_mapping *next_mapping;
 190   sim_core_mapping **last_mapping;
 191
 192   SIM_ASSERT ((attach >= attach_callback)
 193               <= (client != NULL && buffer == NULL && !free_buffer));
 194   SIM_ASSERT ((attach == attach_raw_memory)
 195               <= (client == NULL && buffer != NULL));
 196
 197   /* actually do occasionally get a zero size map */
 198   if (nr_bytes == 0)
 199     {
 200 #if (WITH_DEVICES)
 201       device_error(client, "called on sim_core_map_attach with size zero");
 202 #else
 203       sim_io_error (sd, "called on sim_core_map_attach with size zero");
 204 #endif
 205     }
 206
 207   /* find the insertion point (between last/next) */
 208   next_mapping = access_map->first;
 209   last_mapping = &access_map->first;
 210   while(next_mapping != NULL
 211         && (next_mapping->level < (int) attach
 212             || (next_mapping->level == (int) attach
 213                 && next_mapping->bound < addr)))
 214     {
 215       /* provided levels are the same */
 216       /* assert: next_mapping->base > all bases before next_mapping */
 217       /* assert: next_mapping->bound >= all bounds before next_mapping */
 218       last_mapping = &next_mapping->next;
 219       next_mapping = next_mapping->next;
 220     }
 221
 222   /* check insertion point correct */
 223   SIM_ASSERT (next_mapping == NULL || next_mapping->level >= (int) attach);
 224   if (next_mapping != NULL && next_mapping->level == (int) attach
 225       && next_mapping->base < (addr + (nr_bytes - 1)))
 226     {
 227 #if (WITH_DEVICES)
 228       device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
 229                     space,
 230                     (long) addr,
 231                     (long) nr_bytes,
 232                     (long) (addr + (nr_bytes - 1)),
 233                     next_mapping->space,
 234                     (long) next_mapping->base,
 235                     (long) next_mapping->bound,
 236                     (long) next_mapping->nr_bytes);
 237 #else
 238       sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
 239                     space,
 240                     (long) addr,
 241                     (long) nr_bytes,
 242                     (long) (addr + (nr_bytes - 1)),
 243                     next_mapping->space,
 244                     (long) next_mapping->base,
 245                     (long) next_mapping->bound,
 246                     (long) next_mapping->nr_bytes);
 247 #endif
 248   }
 249
 250   /* create/insert the new mapping */
 251   *last_mapping = new_sim_core_mapping(sd,
 252                                        attach,
 253                                        space, addr, nr_bytes, modulo,
 254                                        client, buffer, free_buffer);
 255   (*last_mapping)->next = next_mapping;
 256 }
 257
 258
 259 EXTERN_SIM_CORE\
 260 (void)
 261 sim_core_attach (SIM_DESC sd,
 262                  sim_cpu *cpu,
 263                  attach_type attach,
 264                  access_type access,
 265                  int space,
 266                  address_word addr,
 267                  address_word nr_bytes,
 268                  unsigned modulo,
 269                  device *client,
 270                  void *optional_buffer)
 271 {
 272   sim_core *memory = STATE_CORE(sd);
 273   sim_core_maps map;
 274   void *buffer;
 275   int buffer_freed;
 276
 277   /* check for for attempt to use unimplemented per-processor core map */
 278   if (cpu != NULL)
 279     sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported");
 280
 281   if ((access & access_read_write_exec) == 0
 282       || (access & ~access_read_write_exec) != 0)
 283     {
 284 #if (WITH_DEVICES)
 285       device_error(client, "invalid access for core attach");
 286 #else
 287       sim_io_error (sd, "invalid access for core attach");
 288 #endif
 289     }
 290
 291   /* verify the attach type */
 292   if (attach == attach_raw_memory)
 293     {
 294       if (WITH_MODULO_MEMORY && modulo != 0)
 295         {
 296           unsigned mask = modulo - 1;
 297           if (mask < 7) /* 8 is minimum modulo */
 298             mask = 0;
 299           while (mask > 1) /* no zero bits */
 300             if ((mask & 1) == 0)
 301               mask = 0;
 302           if (mask == 0)
 303             {
 304 #if (WITH_DEVICES)
 305               device_error (client, "sim_core_attach - internal error - modulo not power of two");
 306 #else
 307               sim_io_error (sd, "sim_core_attach - internal error - modulo not power of two");
 308 #endif
 309             }
 310         }
 311       else if (WITH_MODULO_MEMORY && modulo != 0)
 312         {
 313 #if (WITH_DEVICES)
 314           device_error (client, "sim_core_attach - internal error - modulo memory disabled");
 315 #else
 316           sim_io_error (sd, "sim_core_attach - internal error - modulo memory disabled");
 317 #endif
 318         }
 319       if (optional_buffer == NULL)
 320         {
 321           buffer = zalloc (modulo == 0 ? nr_bytes : modulo);
 322           buffer_freed = 0;
 323         }
 324       else
 325         {
 326           buffer = optional_buffer;
 327           buffer_freed = 1;
 328         }
 329     }
 330   else if (attach >= attach_callback)
 331     {
 332       buffer = NULL;
 333       buffer_freed = 1;
 334     }
 335   else
 336     {
 337 #if (WITH_DEVICES)
 338       device_error (client, "sim_core_attach - internal error - conflicting buffer and attach arguments");
 339 #else
 340       sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments");
 341 #endif
 342       buffer = NULL;
 343       buffer_freed = 1;
 344     }
 345
 346   /* attach the region to all applicable access maps */
 347   for (map = 0;
 348        map < nr_sim_core_maps;
 349        map++)
 350     {
 351       switch (map)
 352         {
 353         case sim_core_read_map:
 354           if (access & access_read)
 355             sim_core_map_attach (sd, &memory->common.map[map],
 356                                  attach,
 357                                  space, addr, nr_bytes, modulo,
 358                                  client, buffer, !buffer_freed);
 359           buffer_freed ++;
 360           break;
 361         case sim_core_write_map:
 362           if (access & access_write)
 363             sim_core_map_attach (sd, &memory->common.map[map],
 364                                  attach,
 365                                  space, addr, nr_bytes, modulo,
 366                                  client, buffer, !buffer_freed);
 367           buffer_freed ++;
 368           break;
 369         case sim_core_execute_map:
 370           if (access & access_exec)
 371             sim_core_map_attach (sd, &memory->common.map[map],
 372                                  attach,
 373                                  space, addr, nr_bytes, modulo,
 374                                  client, buffer, !buffer_freed);
 375           buffer_freed ++;
 376           break;
 377         case nr_sim_core_maps:
 378           sim_io_error (sd, "sim_core_attach - internal error - bad switch");
 379           break;
 380         }
 381     }
 382
 383   /* Just copy this map to each of the processor specific data structures.
 384      FIXME - later this will be replaced by true processor specific
 385      maps. */
 386   {
 387     int i;
 388     for (i = 0; i < MAX_NR_PROCESSORS; i++)
 389       {
 390         CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
 391       }
 392   }
 393 }
 394
 395
 396 /* Remove any memory reference related to this address */
 397 STATIC_INLINE_SIM_CORE\
 398 (void)
 399 sim_core_map_detach (SIM_DESC sd,
 400                      sim_core_map *access_map,
 401                      attach_type attach,
 402                      int space,
 403                      address_word addr)
 404 {
 405   sim_core_mapping **entry;
 406   for (entry = &access_map->first;
 407        (*entry) != NULL;
 408        entry = &(*entry)->next)
 409     {
 410       if ((*entry)->base == addr
 411           && (*entry)->level == (int) attach
 412           && (*entry)->space == space)
 413         {
 414           sim_core_mapping *dead = (*entry);
 415           (*entry) = dead->next;
 416           if (dead->free_buffer)
 417             zfree (dead->buffer);
 418           zfree (dead);
 419           return;
 420         }
 421     }
 422 }
 423
 424 EXTERN_SIM_CORE\
 425 (void)
 426 sim_core_detach (SIM_DESC sd,
 427                  sim_cpu *cpu,
 428                  attach_type attach,
 429                  int address_space,
 430                  address_word addr)
 431 {
 432   sim_core *memory = STATE_CORE (sd);
 433   sim_core_maps map;
 434   for (map = 0; map < nr_sim_core_maps; map++)
 435     {
 436       sim_core_map_detach (sd, &memory->common.map[map],
 437                            attach, address_space, addr);
 438     }
 439   /* Just copy this update to each of the processor specific data
 440      structures.  FIXME - later this will be replaced by true
 441      processor specific maps. */
 442   {
 443     int i;
 444     for (i = 0; i < MAX_NR_PROCESSORS; i++)
 445       {
 446         CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
 447       }
 448   }
 449 }
 450
 451
 452 STATIC_INLINE_SIM_CORE\
 453 (sim_core_mapping *)
 454 sim_core_find_mapping(sim_core_common *core,
 455                       sim_core_maps map,
 456                       address_word addr,
 457                       unsigned nr_bytes,
 458                       transfer_type transfer,
 459                       int abort, /*either 0 or 1 - hint to inline/-O */
 460                       sim_cpu *cpu, /* abort => cpu != NULL */
 461                       sim_cia cia)
 462 {
 463   sim_core_mapping *mapping = core->map[map].first;
 464   ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */
 465   ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
 466   ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */
 467   while (mapping != NULL)
 468     {
 469       if (addr >= mapping->base
 470           && (addr + (nr_bytes - 1)) <= mapping->bound)
 471         return mapping;
 472       mapping = mapping->next;
 473     }
 474   if (abort)
 475     {
 476       SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer,
 477                        sim_core_unmapped_signal);
 478     }
 479   return NULL;
 480 }
 481
 482
 483 STATIC_INLINE_SIM_CORE\
 484 (void *)
 485 sim_core_translate (sim_core_mapping *mapping,
 486                     address_word addr)
 487 {
 488   if (WITH_MODULO_MEMORY)
 489     return (void *)((unsigned8 *) mapping->buffer
 490                     + ((addr - mapping->base) & mapping->mask));
 491   else
 492     return (void *)((unsigned8 *) mapping->buffer
 493                     + addr - mapping->base);
 494 }
 495
 496
 497 EXTERN_SIM_CORE\
 498 (unsigned)
 499 sim_core_read_buffer (SIM_DESC sd,
 500                       sim_cpu *cpu,
 501                       sim_core_maps map,
 502                       void *buffer,
 503                       address_word addr,
 504                       unsigned len)
 505 {
 506   sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
 507   unsigned count = 0;
 508   while (count < len) {
 509     unsigned_word raddr = addr + count;
 510     sim_core_mapping *mapping =
 511       sim_core_find_mapping(core, map,
 512                             raddr, /*nr-bytes*/1,
 513                             read_transfer,
 514                             0 /*dont-abort*/, NULL, NULL_CIA);
 515     if (mapping == NULL)
 516       break;
 517 #if (WITH_DEVICES)
 518     if (mapping->device != NULL) {
 519       int nr_bytes = len - count;
 520       if (raddr + nr_bytes - 1> mapping->bound)
 521         nr_bytes = mapping->bound - raddr + 1;
 522       if (device_io_read_buffer(mapping->device,
 523                                 (unsigned_1*)buffer + count,
 524                                 mapping->space,
 525                                 raddr,
 526                                 nr_bytes) != nr_bytes)
 527         break;
 528       count += nr_bytes;
 529     }
 530     else
 531 #endif
 532       {
 533         ((unsigned_1*)buffer)[count] =
 534           *(unsigned_1*)sim_core_translate(mapping, raddr);
 535         count += 1;
 536       }
 537   }
 538   return count;
 539 }
 540
 541
 542 EXTERN_SIM_CORE\
 543 (unsigned)
 544 sim_core_write_buffer (SIM_DESC sd,
 545                        sim_cpu *cpu,
 546                        sim_core_maps map,
 547                        const void *buffer,
 548                        address_word addr,
 549                        unsigned len)
 550 {
 551   sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
 552   unsigned count = 0;
 553   while (count < len) {
 554     unsigned_word raddr = addr + count;
 555     sim_core_mapping *mapping =
 556       sim_core_find_mapping(core, map,
 557                             raddr, /*nr-bytes*/1,
 558                             write_transfer,
 559                             0 /*dont-abort*/, NULL, NULL_CIA);
 560     if (mapping == NULL)
 561       break;
 562 #if (WITH_DEVICES)
 563     if (WITH_CALLBACK_MEMORY
 564         && mapping->device != NULL) {
 565       int nr_bytes = len - count;
 566       if (raddr + nr_bytes - 1 > mapping->bound)
 567         nr_bytes = mapping->bound - raddr + 1;
 568       if (device_io_write_buffer(mapping->device,
 569                                  (unsigned_1*)buffer + count,
 570                                  mapping->space,
 571                                  raddr,
 572                                  nr_bytes) != nr_bytes)
 573         break;
 574       count += nr_bytes;
 575     }
 576     else
 577 #endif
 578       {
 579         *(unsigned_1*)sim_core_translate(mapping, raddr) =
 580           ((unsigned_1*)buffer)[count];
 581         count += 1;
 582       }
 583   }
 584   return count;
 585 }
 586
 587
 588 EXTERN_SIM_CORE\
 589 (void)
 590 sim_core_set_xor (SIM_DESC sd,
 591                   sim_cpu *cpu,
 592                   int is_xor)
 593 {
 594   /* set up the XOR map if required. */
 595   if (WITH_XOR_ENDIAN) {
 596     {
 597       sim_core *core = STATE_CORE (sd);
 598       sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL);
 599       if (cpu_core != NULL)
 600         {
 601           int i = 1;
 602           unsigned mask;
 603           if (is_xor)
 604             mask = WITH_XOR_ENDIAN - 1;
 605           else
 606             mask = 0;
 607           while (i - 1 < WITH_XOR_ENDIAN)
 608             {
 609               cpu_core->xor[i-1] = mask;
 610               mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
 611               i = (i << 1);
 612             }
 613         }
 614       else
 615         {
 616           if (is_xor)
 617             core->byte_xor = WITH_XOR_ENDIAN - 1;
 618           else
 619             core->byte_xor = 0;
 620         }
 621     }
 622   }
 623   else {
 624     if (is_xor)
 625       sim_engine_abort (sd, cpu, NULL_CIA,
 626                         "Attempted to enable xor-endian mode when permenantly disabled.");
 627   }
 628 }
 629
 630 STATIC_INLINE_SIM_CORE\
 631 (void)
 632 reverse_n (unsigned_1 *dest,
 633            const unsigned_1 *src,
 634            int nr_bytes)
 635 {
 636   int i;
 637   for (i = 0; i < nr_bytes; i++)
 638     {
 639       dest [nr_bytes - i - 1] = src [i];
 640     }
 641 }
 642
 643
 644 EXTERN_SIM_CORE\
 645 (unsigned)
 646 sim_core_xor_read_buffer (SIM_DESC sd,
 647                           sim_cpu *cpu,
 648                           sim_core_maps map,
 649                           void *buffer,
 650                           address_word addr,
 651                           unsigned nr_bytes)
 652 {
 653   address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
 654   if (!WITH_XOR_ENDIAN || !byte_xor)
 655     return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes);
 656   else
 657     /* only break up transfers when xor-endian is both selected and enabled */
 658     {
 659       unsigned_1 x[WITH_XOR_ENDIAN];
 660       unsigned nr_transfered = 0;
 661       address_word start = addr;
 662       unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
 663       address_word stop;
 664       /* initial and intermediate transfers are broken when they cross
 665          an XOR endian boundary */
 666       while (nr_transfered + nr_this_transfer < nr_bytes)
 667         /* initial/intermediate transfers */
 668         {
 669           /* since xor-endian is enabled stop^xor defines the start
 670              address of the transfer */
 671           stop = start + nr_this_transfer - 1;
 672           SIM_ASSERT (start <= stop);
 673           SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
 674           if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 675               != nr_this_transfer)
 676             return nr_transfered;
 677           reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
 678           nr_transfered += nr_this_transfer;
 679           nr_this_transfer = WITH_XOR_ENDIAN;
 680           start = stop + 1;
 681         }
 682       /* final transfer */
 683       nr_this_transfer = nr_bytes - nr_transfered;
 684       stop = start + nr_this_transfer - 1;
 685       SIM_ASSERT (stop == (addr + nr_bytes - 1));
 686       if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 687           != nr_this_transfer)
 688         return nr_transfered;
 689       reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
 690       return nr_bytes;
 691     }
 692 }
 693
 694
 695 EXTERN_SIM_CORE\
 696 (unsigned)
 697 sim_core_xor_write_buffer (SIM_DESC sd,
 698                            sim_cpu *cpu,
 699                            sim_core_maps map,
 700                            const void *buffer,
 701                            address_word addr,
 702                            unsigned nr_bytes)
 703 {
 704   address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
 705   if (!WITH_XOR_ENDIAN || !byte_xor)
 706     return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes);
 707   else
 708     /* only break up transfers when xor-endian is both selected and enabled */
 709     {
 710       unsigned_1 x[WITH_XOR_ENDIAN];
 711       unsigned nr_transfered = 0;
 712       address_word start = addr;
 713       unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
 714       address_word stop;
 715       /* initial and intermediate transfers are broken when they cross
 716          an XOR endian boundary */
 717       while (nr_transfered + nr_this_transfer < nr_bytes)
 718         /* initial/intermediate transfers */
 719         {
 720           /* since xor-endian is enabled stop^xor defines the start
 721              address of the transfer */
 722           stop = start + nr_this_transfer - 1;
 723           SIM_ASSERT (start <= stop);
 724           SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
 725           reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
 726           if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 727               != nr_this_transfer)
 728             return nr_transfered;
 729           nr_transfered += nr_this_transfer;
 730           nr_this_transfer = WITH_XOR_ENDIAN;
 731           start = stop + 1;
 732         }
 733       /* final transfer */
 734       nr_this_transfer = nr_bytes - nr_transfered;
 735       stop = start + nr_this_transfer - 1;
 736       SIM_ASSERT (stop == (addr + nr_bytes - 1));
 737       reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
 738       if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 739           != nr_this_transfer)
 740         return nr_transfered;
 741       return nr_bytes;
 742     }
 743 }
 744
 745
 746
 747 /* define the read/write 1/2/4/8/word functions */
 748
 749 #define N 1
 750 #include "sim-n-core.h"
 751 #undef N
 752
 753 #define N 2
 754 #include "sim-n-core.h"
 755 #undef N
 756
 757 #define N 4
 758 #include "sim-n-core.h"
 759 #undef N
 760
 761 #define N 8
 762 #include "sim-n-core.h"
 763 #undef N
 764
 765 #define N word
 766 #include "sim-n-core.h"
 767 #undef N
 768
 769 #endif