sim/common/sim-core.c

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 #ifndef _SIM_CORE_C_
  23 #define _SIM_CORE_C_
  24
  25 #include "libiberty.h"
  26 #include "sim-main.h"
  27 #include "sim-assert.h"
  28
  29 /* "core" module install handler.
  30
  31    This is called via sim_module_install to install the "core" subsystem
  32    into the simulator.  */
  33
  34 static MODULE_INIT_FN sim_core_init;
  35 static MODULE_UNINSTALL_FN sim_core_uninstall;
  36
  37 #if (WITH_DEVICES)
  38 /* TODO: create sim/common/device.h */
  39 void device_error (device *me, char* message, ...);
  40 int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
  41 int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
  42 #endif
  43
  44 EXTERN_SIM_CORE\
  45 (SIM_RC)
  46 sim_core_install (SIM_DESC sd)
  47 {
  48   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
  49
  50   /* establish the other handlers */
  51   sim_module_add_uninstall_fn (sd, sim_core_uninstall);
  52   sim_module_add_init_fn (sd, sim_core_init);
  53
  54   /* establish any initial data structures - none */
  55   return SIM_RC_OK;
  56 }
  57
  58
  59 /* Uninstall the "core" subsystem from the simulator.  */
  60
  61 STATIC_SIM_CORE\
  62 (void)
  63 sim_core_uninstall (SIM_DESC sd)
  64 {
  65   sim_core *core = STATE_CORE(sd);
  66   sim_core_maps map;
  67   /* blow away any mappings */
  68   for (map = 0; map < nr_sim_core_maps; map++) {
  69     sim_core_mapping *curr = core->common.map[map].first;
  70     while (curr != NULL) {
  71       sim_core_mapping *tbd = curr;
  72       curr = curr->next;
  73       if (tbd->free_buffer != NULL) {
  74         SIM_ASSERT(tbd->buffer != NULL);
  75         zfree(tbd->free_buffer);
  76       }
  77       zfree(tbd);
  78     }
  79     core->common.map[map].first = NULL;
  80   }
  81 }
  82
  83
  84 STATIC_SIM_CORE\
  85 (SIM_RC)
  86 sim_core_init (SIM_DESC sd)
  87 {
  88   /* Nothing to do */
  89   return SIM_RC_OK;
  90 }
  91
  92
  93
  94 #ifndef SIM_CORE_SIGNAL
  95 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  96 sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  97
  98 STATIC_SIM_CORE\
  99 (void)
 100 sim_core_signal (SIM_DESC sd,
 101                  sim_cpu *cpu,
 102                  sim_cia cia,
 103                  sim_core_maps map,
 104                  int nr_bytes,
 105                  address_word addr,
 106                  transfer_type transfer,
 107                  sim_core_signals sig)
 108 {
 109   const char *copy = (transfer == read_transfer ? "read" : "write");
 110   address_word ip = CIA_ADDR (cia);
 111   switch (sig)
 112     {
 113     case sim_core_unmapped_signal:
 114       sim_io_eprintf (sd, "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
 115                       nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
 116       sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGSEGV);
 117       break;
 118     case sim_core_unaligned_signal:
 119       sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
 120                       nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
 121       sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGBUS);
 122       break;
 123     default:
 124       sim_engine_abort (sd, cpu, cia,
 125                         "sim_core_signal - internal error - bad switch");
 126     }
 127 }
 128 #endif
 129
 130
 131 EXTERN_SIM_CORE\
 132 (const char *)
 133 sim_core_map_to_str (sim_core_maps map)
 134 {
 135   switch (map)
 136     {
 137     case sim_core_read_map: return "read";
 138     case sim_core_write_map: return "write";
 139     case sim_core_execute_map: return "exec";
 140     default: return "(invalid-map)";
 141     }
 142 }
 143
 144
 145 STATIC_SIM_CORE\
 146 (sim_core_mapping *)
 147 new_sim_core_mapping (SIM_DESC sd,
 148                       int level,
 149                       int space,
 150                       address_word addr,
 151                       address_word nr_bytes,
 152                       unsigned modulo,
 153                       device *device,
 154                       void *buffer,
 155                       void *free_buffer)
 156 {
 157   sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping);
 158   /* common */
 159   new_mapping->level = level;
 160   new_mapping->space = space;
 161   new_mapping->base = addr;
 162   new_mapping->nr_bytes = nr_bytes;
 163   new_mapping->bound = addr + (nr_bytes - 1);
 164   if (modulo == 0)
 165     new_mapping->mask = (unsigned) 0 - 1;
 166   else
 167     new_mapping->mask = modulo - 1;
 168   new_mapping->buffer = buffer;
 169   new_mapping->free_buffer = free_buffer;
 170   new_mapping->device = device;
 171   return new_mapping;
 172 }
 173
 174
 175 STATIC_SIM_CORE\
 176 (void)
 177 sim_core_map_attach (SIM_DESC sd,
 178                      sim_core_map *access_map,
 179                      int level,
 180                      int space,
 181                      address_word addr,
 182                      address_word nr_bytes,
 183                      unsigned modulo,
 184                      device *client, /*callback/default*/
 185                      void *buffer, /*raw_memory*/
 186                      void *free_buffer) /*raw_memory*/
 187 {
 188   /* find the insertion point for this additional mapping and then
 189      insert */
 190   sim_core_mapping *next_mapping;
 191   sim_core_mapping **last_mapping;
 192
 193   SIM_ASSERT ((client == NULL) != (buffer == NULL));
 194   SIM_ASSERT ((client == NULL) >= (free_buffer != NULL));
 195
 196   /* actually do occasionally get a zero size map */
 197   if (nr_bytes == 0)
 198     {
 199 #if (WITH_DEVICES)
 200       device_error(client, "called on sim_core_map_attach with size zero");
 201 #else
 202       sim_io_error (sd, "called on sim_core_map_attach with size zero");
 203 #endif
 204     }
 205
 206   /* find the insertion point (between last/next) */
 207   next_mapping = access_map->first;
 208   last_mapping = &access_map->first;
 209   while(next_mapping != NULL
 210         && (next_mapping->level < level
 211             || (next_mapping->level == level
 212                 && next_mapping->bound < addr)))
 213     {
 214       /* provided levels are the same */
 215       /* assert: next_mapping->base > all bases before next_mapping */
 216       /* assert: next_mapping->bound >= all bounds before next_mapping */
 217       last_mapping = &next_mapping->next;
 218       next_mapping = next_mapping->next;
 219     }
 220
 221   /* check insertion point correct */
 222   SIM_ASSERT (next_mapping == NULL || next_mapping->level >= level);
 223   if (next_mapping != NULL && next_mapping->level == level
 224       && next_mapping->base < (addr + (nr_bytes - 1)))
 225     {
 226 #if (WITH_DEVICES)
 227       device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
 228                     space,
 229                     (long) addr,
 230                     (long) nr_bytes,
 231                     (long) (addr + (nr_bytes - 1)),
 232                     next_mapping->space,
 233                     (long) next_mapping->base,
 234                     (long) next_mapping->bound,
 235                     (long) next_mapping->nr_bytes);
 236 #else
 237       sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
 238                     space,
 239                     (long) addr,
 240                     (long) nr_bytes,
 241                     (long) (addr + (nr_bytes - 1)),
 242                     next_mapping->space,
 243                     (long) next_mapping->base,
 244                     (long) next_mapping->bound,
 245                     (long) next_mapping->nr_bytes);
 246 #endif
 247   }
 248
 249   /* create/insert the new mapping */
 250   *last_mapping = new_sim_core_mapping(sd,
 251                                        level,
 252                                        space, addr, nr_bytes, modulo,
 253                                        client, buffer, free_buffer);
 254   (*last_mapping)->next = next_mapping;
 255 }
 256
 257
 258 EXTERN_SIM_CORE\
 259 (void)
 260 sim_core_attach (SIM_DESC sd,
 261                  sim_cpu *cpu,
 262                  int level,
 263                  access_type access,
 264                  int space,
 265                  address_word addr,
 266                  address_word nr_bytes,
 267                  unsigned modulo,
 268                  device *client,
 269                  void *optional_buffer)
 270 {
 271   sim_core *memory = STATE_CORE(sd);
 272   sim_core_maps map;
 273   void *buffer;
 274   void *free_buffer;
 275
 276   /* check for for attempt to use unimplemented per-processor core map */
 277   if (cpu != NULL)
 278     sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported");
 279
 280   if ((access & access_read_write_exec) == 0
 281       || (access & ~access_read_write_exec) != 0)
 282     {
 283 #if (WITH_DEVICES)
 284       device_error(client, "invalid access for core attach");
 285 #else
 286       sim_io_error (sd, "invalid access for core attach");
 287 #endif
 288     }
 289
 290   /* verify modulo memory */
 291   if (!WITH_MODULO_MEMORY && modulo != 0)
 292     {
 293 #if (WITH_DEVICES)
 294       device_error (client, "sim_core_attach - internal error - modulo memory disabled");
 295 #else
 296       sim_io_error (sd, "sim_core_attach - internal error - modulo memory disabled");
 297 #endif
 298     }
 299   if (client != NULL && modulo != 0)
 300     {
 301 #if (WITH_DEVICES)
 302       device_error (client, "sim_core_attach - internal error - modulo and callback memory conflict");
 303 #else
 304       sim_io_error (sd, "sim_core_attach - internal error - modulo and callback memory conflict");
 305 #endif
 306     }
 307   if (modulo != 0)
 308     {
 309       unsigned mask = modulo - 1;
 310       /* any zero bits */
 311       while (mask >= sizeof (unsigned64)) /* minimum modulo */
 312         {
 313           if ((mask & 1) == 0)
 314             mask = 0;
 315           else
 316             mask >>= 1;
 317         }
 318       if (mask != sizeof (unsigned64) - 1)
 319         {
 320 #if (WITH_DEVICES)
 321           device_error (client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
 322 #else
 323           sim_io_error (sd, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
 324 #endif
 325         }
 326     }
 327
 328   /* verify consistency between device and buffer */
 329   if (client != NULL && optional_buffer != NULL)
 330     {
 331 #if (WITH_DEVICES)
 332       device_error (client, "sim_core_attach - internal error - conflicting buffer and attach arguments");
 333 #else
 334       sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments");
 335 #endif
 336     }
 337   if (client == NULL)
 338     {
 339       if (optional_buffer == NULL)
 340         {
 341           int padding = (addr % sizeof (unsigned64));
 342           unsigned int bytes = (modulo == 0 ? nr_bytes : modulo) + padding;
 343           free_buffer = xmalloc (bytes);
 344           /* #if WITH_DETERMINISTIC_SIMULATION? */
 345           memset (free_buffer, 0xa5, bytes);
 346           buffer = (char*) free_buffer + padding;
 347         }
 348       else
 349         {
 350           buffer = optional_buffer;
 351           free_buffer = NULL;
 352         }
 353     }
 354   else
 355     {
 356       /* a device */
 357       buffer = NULL;
 358       free_buffer = NULL;
 359     }
 360
 361   /* attach the region to all applicable access maps */
 362   for (map = 0;
 363        map < nr_sim_core_maps;
 364        map++)
 365     {
 366       switch (map)
 367         {
 368         case sim_core_read_map:
 369           if (access & access_read)
 370             sim_core_map_attach (sd, &memory->common.map[map],
 371                                  level, space, addr, nr_bytes, modulo,
 372                                  client, buffer, free_buffer);
 373           free_buffer = NULL;
 374           break;
 375         case sim_core_write_map:
 376           if (access & access_write)
 377             sim_core_map_attach (sd, &memory->common.map[map],
 378                                  level, space, addr, nr_bytes, modulo,
 379                                  client, buffer, free_buffer);
 380           free_buffer = NULL;
 381           break;
 382         case sim_core_execute_map:
 383           if (access & access_exec)
 384             sim_core_map_attach (sd, &memory->common.map[map],
 385                                  level, space, addr, nr_bytes, modulo,
 386                                  client, buffer, free_buffer);
 387           free_buffer = NULL;
 388           break;
 389         case nr_sim_core_maps:
 390           sim_io_error (sd, "sim_core_attach - internal error - bad switch");
 391           break;
 392         }
 393     }
 394
 395   /* Just copy this map to each of the processor specific data structures.
 396      FIXME - later this will be replaced by true processor specific
 397      maps. */
 398   {
 399     int i;
 400     for (i = 0; i < MAX_NR_PROCESSORS; i++)
 401       {
 402         CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
 403       }
 404   }
 405 }
 406
 407
 408 /* Remove any memory reference related to this address */
 409 STATIC_INLINE_SIM_CORE\
 410 (void)
 411 sim_core_map_detach (SIM_DESC sd,
 412                      sim_core_map *access_map,
 413                      int level,
 414                      int space,
 415                      address_word addr)
 416 {
 417   sim_core_mapping **entry;
 418   for (entry = &access_map->first;
 419        (*entry) != NULL;
 420        entry = &(*entry)->next)
 421     {
 422       if ((*entry)->base == addr
 423           && (*entry)->level == level
 424           && (*entry)->space == space)
 425         {
 426           sim_core_mapping *dead = (*entry);
 427           (*entry) = dead->next;
 428           if (dead->free_buffer != NULL)
 429             free (dead->free_buffer);
 430           zfree (dead);
 431           return;
 432         }
 433     }
 434 }
 435
 436 EXTERN_SIM_CORE\
 437 (void)
 438 sim_core_detach (SIM_DESC sd,
 439                  sim_cpu *cpu,
 440                  int level,
 441                  int address_space,
 442                  address_word addr)
 443 {
 444   sim_core *memory = STATE_CORE (sd);
 445   sim_core_maps map;
 446   for (map = 0; map < nr_sim_core_maps; map++)
 447     {
 448       sim_core_map_detach (sd, &memory->common.map[map],
 449                            level, address_space, addr);
 450     }
 451   /* Just copy this update to each of the processor specific data
 452      structures.  FIXME - later this will be replaced by true
 453      processor specific maps. */
 454   {
 455     int i;
 456     for (i = 0; i < MAX_NR_PROCESSORS; i++)
 457       {
 458         CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
 459       }
 460   }
 461 }
 462
 463
 464 STATIC_INLINE_SIM_CORE\
 465 (sim_core_mapping *)
 466 sim_core_find_mapping(sim_core_common *core,
 467                       sim_core_maps map,
 468                       address_word addr,
 469                       unsigned nr_bytes,
 470                       transfer_type transfer,
 471                       int abort, /*either 0 or 1 - hint to inline/-O */
 472                       sim_cpu *cpu, /* abort => cpu != NULL */
 473                       sim_cia cia)
 474 {
 475   sim_core_mapping *mapping = core->map[map].first;
 476   ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */
 477   ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
 478   ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */
 479   while (mapping != NULL)
 480     {
 481       if (addr >= mapping->base
 482           && (addr + (nr_bytes - 1)) <= mapping->bound)
 483         return mapping;
 484       mapping = mapping->next;
 485     }
 486   if (abort)
 487     {
 488       SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer,
 489                        sim_core_unmapped_signal);
 490     }
 491   return NULL;
 492 }
 493
 494
 495 STATIC_INLINE_SIM_CORE\
 496 (void *)
 497 sim_core_translate (sim_core_mapping *mapping,
 498                     address_word addr)
 499 {
 500   if (WITH_MODULO_MEMORY)
 501     return (void *)((unsigned8 *) mapping->buffer
 502                     + ((addr - mapping->base) & mapping->mask));
 503   else
 504     return (void *)((unsigned8 *) mapping->buffer
 505                     + addr - mapping->base);
 506 }
 507
 508
 509 EXTERN_SIM_CORE\
 510 (unsigned)
 511 sim_core_read_buffer (SIM_DESC sd,
 512                       sim_cpu *cpu,
 513                       sim_core_maps map,
 514                       void *buffer,
 515                       address_word addr,
 516                       unsigned len)
 517 {
 518   sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
 519   unsigned count = 0;
 520   while (count < len) {
 521     unsigned_word raddr = addr + count;
 522     sim_core_mapping *mapping =
 523       sim_core_find_mapping(core, map,
 524                             raddr, /*nr-bytes*/1,
 525                             read_transfer,
 526                             0 /*dont-abort*/, NULL, NULL_CIA);
 527     if (mapping == NULL)
 528       break;
 529 #if (WITH_DEVICES)
 530     if (mapping->device != NULL) {
 531       int nr_bytes = len - count;
 532       if (raddr + nr_bytes - 1> mapping->bound)
 533         nr_bytes = mapping->bound - raddr + 1;
 534       if (device_io_read_buffer(mapping->device,
 535                                 (unsigned_1*)buffer + count,
 536                                 mapping->space,
 537                                 raddr,
 538                                 nr_bytes,
 539                                 cpu,
 540                                 CIA_GET(cpu)) != nr_bytes)
 541         break;
 542       count += nr_bytes;
 543     }
 544     else
 545 #endif
 546       {
 547         ((unsigned_1*)buffer)[count] =
 548           *(unsigned_1*)sim_core_translate(mapping, raddr);
 549         count += 1;
 550       }
 551   }
 552   return count;
 553 }
 554
 555
 556 EXTERN_SIM_CORE\
 557 (unsigned)
 558 sim_core_write_buffer (SIM_DESC sd,
 559                        sim_cpu *cpu,
 560                        sim_core_maps map,
 561                        const void *buffer,
 562                        address_word addr,
 563                        unsigned len)
 564 {
 565   sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
 566   unsigned count = 0;
 567   while (count < len) {
 568     unsigned_word raddr = addr + count;
 569     sim_core_mapping *mapping =
 570       sim_core_find_mapping(core, map,
 571                             raddr, /*nr-bytes*/1,
 572                             write_transfer,
 573                             0 /*dont-abort*/, NULL, NULL_CIA);
 574     if (mapping == NULL)
 575       break;
 576 #if (WITH_DEVICES)
 577     if (WITH_CALLBACK_MEMORY
 578         && mapping->device != NULL) {
 579       int nr_bytes = len - count;
 580       if (raddr + nr_bytes - 1 > mapping->bound)
 581         nr_bytes = mapping->bound - raddr + 1;
 582       if (device_io_write_buffer(mapping->device,
 583                                  (unsigned_1*)buffer + count,
 584                                  mapping->space,
 585                                  raddr,
 586                                  nr_bytes,
 587                                  cpu,
 588                                  CIA_GET(cpu)) != nr_bytes)
 589         break;
 590       count += nr_bytes;
 591     }
 592     else
 593 #endif
 594       {
 595         *(unsigned_1*)sim_core_translate(mapping, raddr) =
 596           ((unsigned_1*)buffer)[count];
 597         count += 1;
 598       }
 599   }
 600   return count;
 601 }
 602
 603
 604 EXTERN_SIM_CORE\
 605 (void)
 606 sim_core_set_xor (SIM_DESC sd,
 607                   sim_cpu *cpu,
 608                   int is_xor)
 609 {
 610   /* set up the XOR map if required. */
 611   if (WITH_XOR_ENDIAN) {
 612     {
 613       sim_core *core = STATE_CORE (sd);
 614       sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL);
 615       if (cpu_core != NULL)
 616         {
 617           int i = 1;
 618           unsigned mask;
 619           if (is_xor)
 620             mask = WITH_XOR_ENDIAN - 1;
 621           else
 622             mask = 0;
 623           while (i - 1 < WITH_XOR_ENDIAN)
 624             {
 625               cpu_core->xor[i-1] = mask;
 626               mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
 627               i = (i << 1);
 628             }
 629         }
 630       else
 631         {
 632           if (is_xor)
 633             core->byte_xor = WITH_XOR_ENDIAN - 1;
 634           else
 635             core->byte_xor = 0;
 636         }
 637     }
 638   }
 639   else {
 640     if (is_xor)
 641       sim_engine_abort (sd, cpu, NULL_CIA,
 642                         "Attempted to enable xor-endian mode when permenantly disabled.");
 643   }
 644 }
 645
 646 STATIC_INLINE_SIM_CORE\
 647 (void)
 648 reverse_n (unsigned_1 *dest,
 649            const unsigned_1 *src,
 650            int nr_bytes)
 651 {
 652   int i;
 653   for (i = 0; i < nr_bytes; i++)
 654     {
 655       dest [nr_bytes - i - 1] = src [i];
 656     }
 657 }
 658
 659
 660 EXTERN_SIM_CORE\
 661 (unsigned)
 662 sim_core_xor_read_buffer (SIM_DESC sd,
 663                           sim_cpu *cpu,
 664                           sim_core_maps map,
 665                           void *buffer,
 666                           address_word addr,
 667                           unsigned nr_bytes)
 668 {
 669   address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
 670   if (!WITH_XOR_ENDIAN || !byte_xor)
 671     return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes);
 672   else
 673     /* only break up transfers when xor-endian is both selected and enabled */
 674     {
 675       unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
 676       unsigned nr_transfered = 0;
 677       address_word start = addr;
 678       unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
 679       address_word stop;
 680       /* initial and intermediate transfers are broken when they cross
 681          an XOR endian boundary */
 682       while (nr_transfered + nr_this_transfer < nr_bytes)
 683         /* initial/intermediate transfers */
 684         {
 685           /* since xor-endian is enabled stop^xor defines the start
 686              address of the transfer */
 687           stop = start + nr_this_transfer - 1;
 688           SIM_ASSERT (start <= stop);
 689           SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
 690           if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 691               != nr_this_transfer)
 692             return nr_transfered;
 693           reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
 694           nr_transfered += nr_this_transfer;
 695           nr_this_transfer = WITH_XOR_ENDIAN;
 696           start = stop + 1;
 697         }
 698       /* final transfer */
 699       nr_this_transfer = nr_bytes - nr_transfered;
 700       stop = start + nr_this_transfer - 1;
 701       SIM_ASSERT (stop == (addr + nr_bytes - 1));
 702       if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 703           != nr_this_transfer)
 704         return nr_transfered;
 705       reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
 706       return nr_bytes;
 707     }
 708 }
 709
 710
 711 EXTERN_SIM_CORE\
 712 (unsigned)
 713 sim_core_xor_write_buffer (SIM_DESC sd,
 714                            sim_cpu *cpu,
 715                            sim_core_maps map,
 716                            const void *buffer,
 717                            address_word addr,
 718                            unsigned nr_bytes)
 719 {
 720   address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
 721   if (!WITH_XOR_ENDIAN || !byte_xor)
 722     return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes);
 723   else
 724     /* only break up transfers when xor-endian is both selected and enabled */
 725     {
 726       unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */
 727       unsigned nr_transfered = 0;
 728       address_word start = addr;
 729       unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
 730       address_word stop;
 731       /* initial and intermediate transfers are broken when they cross
 732          an XOR endian boundary */
 733       while (nr_transfered + nr_this_transfer < nr_bytes)
 734         /* initial/intermediate transfers */
 735         {
 736           /* since xor-endian is enabled stop^xor defines the start
 737              address of the transfer */
 738           stop = start + nr_this_transfer - 1;
 739           SIM_ASSERT (start <= stop);
 740           SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
 741           reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
 742           if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 743               != nr_this_transfer)
 744             return nr_transfered;
 745           nr_transfered += nr_this_transfer;
 746           nr_this_transfer = WITH_XOR_ENDIAN;
 747           start = stop + 1;
 748         }
 749       /* final transfer */
 750       nr_this_transfer = nr_bytes - nr_transfered;
 751       stop = start + nr_this_transfer - 1;
 752       SIM_ASSERT (stop == (addr + nr_bytes - 1));
 753       reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
 754       if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 755           != nr_this_transfer)
 756         return nr_transfered;
 757       return nr_bytes;
 758     }
 759 }
 760
 761
 762
 763 /* define the read/write 1/2/4/8/16/word functions */
 764
 765 #define N 16
 766 #include "sim-n-core.h"
 767
 768 #define N 8
 769 #include "sim-n-core.h"
 770
 771 #define N 7
 772 #define M 8
 773 #include "sim-n-core.h"
 774
 775 #define N 6
 776 #define M 8
 777 #include "sim-n-core.h"
 778
 779 #define N 5
 780 #define M 8
 781 #include "sim-n-core.h"
 782
 783 #define N 4
 784 #include "sim-n-core.h"
 785
 786 #define N 3
 787 #define M 4
 788 #include "sim-n-core.h"
 789
 790 #define N 2
 791 #include "sim-n-core.h"
 792
 793 #define N 1
 794 #include "sim-n-core.h"
 795
 796 #endif