sim/common/sim-core.c

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 #ifndef _SIM_CORE_C_
  23 #define _SIM_CORE_C_
  24
  25 #include "sim-main.h"
  26 #include "sim-assert.h"
  27
  28 /* "core" module install handler.
  29
  30    This is called via sim_module_install to install the "core" subsystem
  31    into the simulator.  */
  32
  33 static MODULE_INIT_FN sim_core_init;
  34 static MODULE_UNINSTALL_FN sim_core_uninstall;
  35
  36 EXTERN_SIM_CORE\
  37 (SIM_RC)
  38 sim_core_install (SIM_DESC sd)
  39 {
  40   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
  41
  42   /* establish the other handlers */
  43   sim_module_add_uninstall_fn (sd, sim_core_uninstall);
  44   sim_module_add_init_fn (sd, sim_core_init);
  45
  46   /* establish any initial data structures - none */
  47   return SIM_RC_OK;
  48 }
  49
  50
  51 /* Uninstall the "core" subsystem from the simulator.  */
  52
  53 STATIC_SIM_CORE\
  54 (void)
  55 sim_core_uninstall (SIM_DESC sd)
  56 {
  57   sim_core *core = STATE_CORE(sd);
  58   sim_core_maps map;
  59   /* blow away any mappings */
  60   for (map = 0; map < nr_sim_core_maps; map++) {
  61     sim_core_mapping *curr = core->common.map[map].first;
  62     while (curr != NULL) {
  63       sim_core_mapping *tbd = curr;
  64       curr = curr->next;
  65       if (tbd->free_buffer != NULL) {
  66         SIM_ASSERT(tbd->buffer != NULL);
  67         zfree(tbd->free_buffer);
  68       }
  69       zfree(tbd);
  70     }
  71     core->common.map[map].first = NULL;
  72   }
  73 }
  74
  75
  76 STATIC_SIM_CORE\
  77 (SIM_RC)
  78 sim_core_init (SIM_DESC sd)
  79 {
  80   /* Nothing to do */
  81   return SIM_RC_OK;
  82 }
  83
  84
  85
  86 #ifndef SIM_CORE_SIGNAL
  87 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  88 sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  89
  90 STATIC_SIM_CORE\
  91 (void)
  92 sim_core_signal (SIM_DESC sd,
  93                  sim_cpu *cpu,
  94                  sim_cia cia,
  95                  sim_core_maps map,
  96                  int nr_bytes,
  97                  address_word addr,
  98                  transfer_type transfer,
  99                  sim_core_signals sig)
 100 {
 101   const char *copy = (transfer == read_transfer ? "read" : "write");
 102   address_word ip = CIA_ADDR (cia);
 103   switch (sig)
 104     {
 105     case sim_core_unmapped_signal:
 106       sim_io_eprintf (sd, "core: %d byte %s to unmaped address 0x%lx at 0x%lx\n",
 107                       nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
 108       sim_engine_halt (sd, cpu, NULL, cia, sim_signalled, SIM_SIGSEGV);
 109       break;
 110     case sim_core_unaligned_signal:
 111       sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
 112                       nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
 113       sim_engine_halt (sd, cpu, NULL, cia, sim_signalled, SIM_SIGBUS);
 114       break;
 115     default:
 116       sim_engine_abort (sd, cpu, cia,
 117                         "sim_core_signal - internal error - bad switch");
 118     }
 119 }
 120 #endif
 121
 122
 123 STATIC_INLINE_SIM_CORE\
 124 (const char *)
 125 sim_core_map_to_str (sim_core_maps map)
 126 {
 127   switch (map)
 128     {
 129     case sim_core_read_map: return "read";
 130     case sim_core_write_map: return "write";
 131     case sim_core_execute_map: return "exec";
 132     default: return "(invalid-map)";
 133     }
 134 }
 135
 136
 137 STATIC_SIM_CORE\
 138 (sim_core_mapping *)
 139 new_sim_core_mapping (SIM_DESC sd,
 140                       int level,
 141                       int space,
 142                       address_word addr,
 143                       address_word nr_bytes,
 144                       unsigned modulo,
 145                       device *device,
 146                       void *buffer,
 147                       void *free_buffer)
 148 {
 149   sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping);
 150   /* common */
 151   new_mapping->level = level;
 152   new_mapping->space = space;
 153   new_mapping->base = addr;
 154   new_mapping->nr_bytes = nr_bytes;
 155   new_mapping->bound = addr + (nr_bytes - 1);
 156   if (modulo == 0)
 157     new_mapping->mask = (unsigned) 0 - 1;
 158   else
 159     new_mapping->mask = modulo - 1;
 160   new_mapping->buffer = buffer;
 161   new_mapping->free_buffer = free_buffer;
 162   new_mapping->device = device;
 163   return new_mapping;
 164 }
 165
 166
 167 STATIC_SIM_CORE\
 168 (void)
 169 sim_core_map_attach (SIM_DESC sd,
 170                      sim_core_map *access_map,
 171                      int level,
 172                      int space,
 173                      address_word addr,
 174                      address_word nr_bytes,
 175                      unsigned modulo,
 176                      device *client, /*callback/default*/
 177                      void *buffer, /*raw_memory*/
 178                      void *free_buffer) /*raw_memory*/
 179 {
 180   /* find the insertion point for this additional mapping and then
 181      insert */
 182   sim_core_mapping *next_mapping;
 183   sim_core_mapping **last_mapping;
 184
 185   SIM_ASSERT ((client == NULL) != (buffer == NULL));
 186   SIM_ASSERT ((client == NULL) >= (free_buffer != NULL));
 187
 188   /* actually do occasionally get a zero size map */
 189   if (nr_bytes == 0)
 190     {
 191 #if (WITH_DEVICES)
 192       device_error(client, "called on sim_core_map_attach with size zero");
 193 #else
 194       sim_io_error (sd, "called on sim_core_map_attach with size zero");
 195 #endif
 196     }
 197
 198   /* find the insertion point (between last/next) */
 199   next_mapping = access_map->first;
 200   last_mapping = &access_map->first;
 201   while(next_mapping != NULL
 202         && (next_mapping->level < level
 203             || (next_mapping->level == level
 204                 && next_mapping->bound < addr)))
 205     {
 206       /* provided levels are the same */
 207       /* assert: next_mapping->base > all bases before next_mapping */
 208       /* assert: next_mapping->bound >= all bounds before next_mapping */
 209       last_mapping = &next_mapping->next;
 210       next_mapping = next_mapping->next;
 211     }
 212
 213   /* check insertion point correct */
 214   SIM_ASSERT (next_mapping == NULL || next_mapping->level >= level);
 215   if (next_mapping != NULL && next_mapping->level == level
 216       && next_mapping->base < (addr + (nr_bytes - 1)))
 217     {
 218 #if (WITH_DEVICES)
 219       device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
 220                     space,
 221                     (long) addr,
 222                     (long) nr_bytes,
 223                     (long) (addr + (nr_bytes - 1)),
 224                     next_mapping->space,
 225                     (long) next_mapping->base,
 226                     (long) next_mapping->bound,
 227                     (long) next_mapping->nr_bytes);
 228 #else
 229       sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
 230                     space,
 231                     (long) addr,
 232                     (long) nr_bytes,
 233                     (long) (addr + (nr_bytes - 1)),
 234                     next_mapping->space,
 235                     (long) next_mapping->base,
 236                     (long) next_mapping->bound,
 237                     (long) next_mapping->nr_bytes);
 238 #endif
 239   }
 240
 241   /* create/insert the new mapping */
 242   *last_mapping = new_sim_core_mapping(sd,
 243                                        level,
 244                                        space, addr, nr_bytes, modulo,
 245                                        client, buffer, free_buffer);
 246   (*last_mapping)->next = next_mapping;
 247 }
 248
 249
 250 EXTERN_SIM_CORE\
 251 (void)
 252 sim_core_attach (SIM_DESC sd,
 253                  sim_cpu *cpu,
 254                  int level,
 255                  access_type access,
 256                  int space,
 257                  address_word addr,
 258                  address_word nr_bytes,
 259                  unsigned modulo,
 260                  device *client,
 261                  void *optional_buffer)
 262 {
 263   sim_core *memory = STATE_CORE(sd);
 264   sim_core_maps map;
 265   void *buffer;
 266   void *free_buffer;
 267
 268   /* check for for attempt to use unimplemented per-processor core map */
 269   if (cpu != NULL)
 270     sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported");
 271
 272   if ((access & access_read_write_exec) == 0
 273       || (access & ~access_read_write_exec) != 0)
 274     {
 275 #if (WITH_DEVICES)
 276       device_error(client, "invalid access for core attach");
 277 #else
 278       sim_io_error (sd, "invalid access for core attach");
 279 #endif
 280     }
 281
 282   /* verify modulo memory */
 283   if (!WITH_MODULO_MEMORY && modulo != 0)
 284     {
 285 #if (WITH_DEVICES)
 286       device_error (client, "sim_core_attach - internal error - modulo memory disabled");
 287 #else
 288       sim_io_error (sd, "sim_core_attach - internal error - modulo memory disabled");
 289 #endif
 290     }
 291   if (client != NULL && modulo != 0)
 292     {
 293 #if (WITH_DEVICES)
 294       device_error (client, "sim_core_attach - internal error - modulo and callback memory conflict");
 295 #else
 296       sim_io_error (sd, "sim_core_attach - internal error - modulo and callback memory conflict");
 297 #endif
 298     }
 299   if (modulo != 0)
 300     {
 301       unsigned mask = modulo - 1;
 302       /* any zero bits */
 303       while (mask >= sizeof (unsigned64)) /* minimum modulo */
 304         {
 305           if ((mask & 1) == 0)
 306             mask = 0;
 307           else
 308             mask >>= 1;
 309         }
 310       if (mask != sizeof (unsigned64) - 1)
 311         {
 312 #if (WITH_DEVICES)
 313           device_error (client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
 314 #else
 315           sim_io_error (sd, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
 316 #endif
 317         }
 318     }
 319
 320   /* verify consistency between device and buffer */
 321   if (client != NULL && optional_buffer != NULL)
 322     {
 323 #if (WITH_DEVICES)
 324       device_error (client, "sim_core_attach - internal error - conflicting buffer and attach arguments");
 325 #else
 326       sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments");
 327 #endif
 328     }
 329   if (client == NULL)
 330     {
 331       if (optional_buffer == NULL)
 332         {
 333           int padding = (addr % sizeof (unsigned64));
 334           free_buffer = zalloc ((modulo == 0 ? nr_bytes : modulo) + padding);
 335           buffer = (char*) free_buffer + padding;
 336         }
 337       else
 338         {
 339           buffer = optional_buffer;
 340           free_buffer = NULL;
 341         }
 342     }
 343   else
 344     {
 345       /* a device */
 346       buffer = NULL;
 347       free_buffer = NULL;
 348     }
 349
 350   /* attach the region to all applicable access maps */
 351   for (map = 0;
 352        map < nr_sim_core_maps;
 353        map++)
 354     {
 355       switch (map)
 356         {
 357         case sim_core_read_map:
 358           if (access & access_read)
 359             sim_core_map_attach (sd, &memory->common.map[map],
 360                                  level, space, addr, nr_bytes, modulo,
 361                                  client, buffer, free_buffer);
 362           free_buffer = NULL;
 363           break;
 364         case sim_core_write_map:
 365           if (access & access_write)
 366             sim_core_map_attach (sd, &memory->common.map[map],
 367                                  level, space, addr, nr_bytes, modulo,
 368                                  client, buffer, free_buffer);
 369           free_buffer = NULL;
 370           break;
 371         case sim_core_execute_map:
 372           if (access & access_exec)
 373             sim_core_map_attach (sd, &memory->common.map[map],
 374                                  level, space, addr, nr_bytes, modulo,
 375                                  client, buffer, free_buffer);
 376           free_buffer = NULL;
 377           break;
 378         case nr_sim_core_maps:
 379           sim_io_error (sd, "sim_core_attach - internal error - bad switch");
 380           break;
 381         }
 382     }
 383
 384   /* Just copy this map to each of the processor specific data structures.
 385      FIXME - later this will be replaced by true processor specific
 386      maps. */
 387   {
 388     int i;
 389     for (i = 0; i < MAX_NR_PROCESSORS; i++)
 390       {
 391         CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
 392       }
 393   }
 394 }
 395
 396
 397 /* Remove any memory reference related to this address */
 398 STATIC_INLINE_SIM_CORE\
 399 (void)
 400 sim_core_map_detach (SIM_DESC sd,
 401                      sim_core_map *access_map,
 402                      int level,
 403                      int space,
 404                      address_word addr)
 405 {
 406   sim_core_mapping **entry;
 407   for (entry = &access_map->first;
 408        (*entry) != NULL;
 409        entry = &(*entry)->next)
 410     {
 411       if ((*entry)->base == addr
 412           && (*entry)->level == level
 413           && (*entry)->space == space)
 414         {
 415           sim_core_mapping *dead = (*entry);
 416           (*entry) = dead->next;
 417           if (dead->free_buffer != NULL)
 418             zfree (dead->free_buffer);
 419           zfree (dead);
 420           return;
 421         }
 422     }
 423 }
 424
 425 EXTERN_SIM_CORE\
 426 (void)
 427 sim_core_detach (SIM_DESC sd,
 428                  sim_cpu *cpu,
 429                  int level,
 430                  int address_space,
 431                  address_word addr)
 432 {
 433   sim_core *memory = STATE_CORE (sd);
 434   sim_core_maps map;
 435   for (map = 0; map < nr_sim_core_maps; map++)
 436     {
 437       sim_core_map_detach (sd, &memory->common.map[map],
 438                            level, address_space, addr);
 439     }
 440   /* Just copy this update to each of the processor specific data
 441      structures.  FIXME - later this will be replaced by true
 442      processor specific maps. */
 443   {
 444     int i;
 445     for (i = 0; i < MAX_NR_PROCESSORS; i++)
 446       {
 447         CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
 448       }
 449   }
 450 }
 451
 452
 453 STATIC_INLINE_SIM_CORE\
 454 (sim_core_mapping *)
 455 sim_core_find_mapping(sim_core_common *core,
 456                       sim_core_maps map,
 457                       address_word addr,
 458                       unsigned nr_bytes,
 459                       transfer_type transfer,
 460                       int abort, /*either 0 or 1 - hint to inline/-O */
 461                       sim_cpu *cpu, /* abort => cpu != NULL */
 462                       sim_cia cia)
 463 {
 464   sim_core_mapping *mapping = core->map[map].first;
 465   ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */
 466   ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
 467   ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */
 468   while (mapping != NULL)
 469     {
 470       if (addr >= mapping->base
 471           && (addr + (nr_bytes - 1)) <= mapping->bound)
 472         return mapping;
 473       mapping = mapping->next;
 474     }
 475   if (abort)
 476     {
 477       SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer,
 478                        sim_core_unmapped_signal);
 479     }
 480   return NULL;
 481 }
 482
 483
 484 STATIC_INLINE_SIM_CORE\
 485 (void *)
 486 sim_core_translate (sim_core_mapping *mapping,
 487                     address_word addr)
 488 {
 489   if (WITH_MODULO_MEMORY)
 490     return (void *)((unsigned8 *) mapping->buffer
 491                     + ((addr - mapping->base) & mapping->mask));
 492   else
 493     return (void *)((unsigned8 *) mapping->buffer
 494                     + addr - mapping->base);
 495 }
 496
 497
 498 EXTERN_SIM_CORE\
 499 (unsigned)
 500 sim_core_read_buffer (SIM_DESC sd,
 501                       sim_cpu *cpu,
 502                       sim_core_maps map,
 503                       void *buffer,
 504                       address_word addr,
 505                       unsigned len)
 506 {
 507   sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
 508   unsigned count = 0;
 509   while (count < len) {
 510     unsigned_word raddr = addr + count;
 511     sim_core_mapping *mapping =
 512       sim_core_find_mapping(core, map,
 513                             raddr, /*nr-bytes*/1,
 514                             read_transfer,
 515                             0 /*dont-abort*/, NULL, NULL_CIA);
 516     if (mapping == NULL)
 517       break;
 518 #if (WITH_DEVICES)
 519     if (mapping->device != NULL) {
 520       int nr_bytes = len - count;
 521       if (raddr + nr_bytes - 1> mapping->bound)
 522         nr_bytes = mapping->bound - raddr + 1;
 523       if (device_io_read_buffer(mapping->device,
 524                                 (unsigned_1*)buffer + count,
 525                                 mapping->space,
 526                                 raddr,
 527                                 nr_bytes) != nr_bytes)
 528         break;
 529       count += nr_bytes;
 530     }
 531     else
 532 #endif
 533       {
 534         ((unsigned_1*)buffer)[count] =
 535           *(unsigned_1*)sim_core_translate(mapping, raddr);
 536         count += 1;
 537       }
 538   }
 539   return count;
 540 }
 541
 542
 543 EXTERN_SIM_CORE\
 544 (unsigned)
 545 sim_core_write_buffer (SIM_DESC sd,
 546                        sim_cpu *cpu,
 547                        sim_core_maps map,
 548                        const void *buffer,
 549                        address_word addr,
 550                        unsigned len)
 551 {
 552   sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
 553   unsigned count = 0;
 554   while (count < len) {
 555     unsigned_word raddr = addr + count;
 556     sim_core_mapping *mapping =
 557       sim_core_find_mapping(core, map,
 558                             raddr, /*nr-bytes*/1,
 559                             write_transfer,
 560                             0 /*dont-abort*/, NULL, NULL_CIA);
 561     if (mapping == NULL)
 562       break;
 563 #if (WITH_DEVICES)
 564     if (WITH_CALLBACK_MEMORY
 565         && mapping->device != NULL) {
 566       int nr_bytes = len - count;
 567       if (raddr + nr_bytes - 1 > mapping->bound)
 568         nr_bytes = mapping->bound - raddr + 1;
 569       if (device_io_write_buffer(mapping->device,
 570                                  (unsigned_1*)buffer + count,
 571                                  mapping->space,
 572                                  raddr,
 573                                  nr_bytes) != nr_bytes)
 574         break;
 575       count += nr_bytes;
 576     }
 577     else
 578 #endif
 579       {
 580         *(unsigned_1*)sim_core_translate(mapping, raddr) =
 581           ((unsigned_1*)buffer)[count];
 582         count += 1;
 583       }
 584   }
 585   return count;
 586 }
 587
 588
 589 EXTERN_SIM_CORE\
 590 (void)
 591 sim_core_set_xor (SIM_DESC sd,
 592                   sim_cpu *cpu,
 593                   int is_xor)
 594 {
 595   /* set up the XOR map if required. */
 596   if (WITH_XOR_ENDIAN) {
 597     {
 598       sim_core *core = STATE_CORE (sd);
 599       sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL);
 600       if (cpu_core != NULL)
 601         {
 602           int i = 1;
 603           unsigned mask;
 604           if (is_xor)
 605             mask = WITH_XOR_ENDIAN - 1;
 606           else
 607             mask = 0;
 608           while (i - 1 < WITH_XOR_ENDIAN)
 609             {
 610               cpu_core->xor[i-1] = mask;
 611               mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
 612               i = (i << 1);
 613             }
 614         }
 615       else
 616         {
 617           if (is_xor)
 618             core->byte_xor = WITH_XOR_ENDIAN - 1;
 619           else
 620             core->byte_xor = 0;
 621         }
 622     }
 623   }
 624   else {
 625     if (is_xor)
 626       sim_engine_abort (sd, cpu, NULL_CIA,
 627                         "Attempted to enable xor-endian mode when permenantly disabled.");
 628   }
 629 }
 630
 631 STATIC_INLINE_SIM_CORE\
 632 (void)
 633 reverse_n (unsigned_1 *dest,
 634            const unsigned_1 *src,
 635            int nr_bytes)
 636 {
 637   int i;
 638   for (i = 0; i < nr_bytes; i++)
 639     {
 640       dest [nr_bytes - i - 1] = src [i];
 641     }
 642 }
 643
 644
 645 EXTERN_SIM_CORE\
 646 (unsigned)
 647 sim_core_xor_read_buffer (SIM_DESC sd,
 648                           sim_cpu *cpu,
 649                           sim_core_maps map,
 650                           void *buffer,
 651                           address_word addr,
 652                           unsigned nr_bytes)
 653 {
 654   address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
 655   if (!WITH_XOR_ENDIAN || !byte_xor)
 656     return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes);
 657   else
 658     /* only break up transfers when xor-endian is both selected and enabled */
 659     {
 660       unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
 661       unsigned nr_transfered = 0;
 662       address_word start = addr;
 663       unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
 664       address_word stop;
 665       /* initial and intermediate transfers are broken when they cross
 666          an XOR endian boundary */
 667       while (nr_transfered + nr_this_transfer < nr_bytes)
 668         /* initial/intermediate transfers */
 669         {
 670           /* since xor-endian is enabled stop^xor defines the start
 671              address of the transfer */
 672           stop = start + nr_this_transfer - 1;
 673           SIM_ASSERT (start <= stop);
 674           SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
 675           if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 676               != nr_this_transfer)
 677             return nr_transfered;
 678           reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
 679           nr_transfered += nr_this_transfer;
 680           nr_this_transfer = WITH_XOR_ENDIAN;
 681           start = stop + 1;
 682         }
 683       /* final transfer */
 684       nr_this_transfer = nr_bytes - nr_transfered;
 685       stop = start + nr_this_transfer - 1;
 686       SIM_ASSERT (stop == (addr + nr_bytes - 1));
 687       if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 688           != nr_this_transfer)
 689         return nr_transfered;
 690       reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
 691       return nr_bytes;
 692     }
 693 }
 694
 695
 696 EXTERN_SIM_CORE\
 697 (unsigned)
 698 sim_core_xor_write_buffer (SIM_DESC sd,
 699                            sim_cpu *cpu,
 700                            sim_core_maps map,
 701                            const void *buffer,
 702                            address_word addr,
 703                            unsigned nr_bytes)
 704 {
 705   address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
 706   if (!WITH_XOR_ENDIAN || !byte_xor)
 707     return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes);
 708   else
 709     /* only break up transfers when xor-endian is both selected and enabled */
 710     {
 711       unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */
 712       unsigned nr_transfered = 0;
 713       address_word start = addr;
 714       unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
 715       address_word stop;
 716       /* initial and intermediate transfers are broken when they cross
 717          an XOR endian boundary */
 718       while (nr_transfered + nr_this_transfer < nr_bytes)
 719         /* initial/intermediate transfers */
 720         {
 721           /* since xor-endian is enabled stop^xor defines the start
 722              address of the transfer */
 723           stop = start + nr_this_transfer - 1;
 724           SIM_ASSERT (start <= stop);
 725           SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
 726           reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
 727           if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 728               != nr_this_transfer)
 729             return nr_transfered;
 730           nr_transfered += nr_this_transfer;
 731           nr_this_transfer = WITH_XOR_ENDIAN;
 732           start = stop + 1;
 733         }
 734       /* final transfer */
 735       nr_this_transfer = nr_bytes - nr_transfered;
 736       stop = start + nr_this_transfer - 1;
 737       SIM_ASSERT (stop == (addr + nr_bytes - 1));
 738       reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
 739       if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 740           != nr_this_transfer)
 741         return nr_transfered;
 742       return nr_bytes;
 743     }
 744 }
 745
 746
 747
 748 /* define the read/write 1/2/4/8/16/word functions */
 749
 750 #define N 16
 751 #include "sim-n-core.h"
 752
 753 #define N 8
 754 #include "sim-n-core.h"
 755
 756 #define N 7
 757 #define M 8
 758 #include "sim-n-core.h"
 759
 760 #define N 6
 761 #define M 8
 762 #include "sim-n-core.h"
 763
 764 #define N 5
 765 #define M 8
 766 #include "sim-n-core.h"
 767
 768 #define N 4
 769 #include "sim-n-core.h"
 770
 771 #define N 3
 772 #define M 4
 773 #include "sim-n-core.h"
 774
 775 #define N 2
 776 #include "sim-n-core.h"
 777
 778 #define N 1
 779 #include "sim-n-core.h"
 780
 781 #endif