sim/common/sim-core.c

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 #ifndef _SIM_CORE_C_
  23 #define _SIM_CORE_C_
  24
  25 #include "libiberty.h"
  26 #include "sim-main.h"
  27 #include "sim-assert.h"
  28
  29 /* "core" module install handler.
  30
  31    This is called via sim_module_install to install the "core" subsystem
  32    into the simulator.  */
  33
  34 static MODULE_INIT_FN sim_core_init;
  35 static MODULE_UNINSTALL_FN sim_core_uninstall;
  36
  37 #if (WITH_DEVICES)
  38 /* TODO: create sim/common/device.h */
  39 void device_error (device *me, char* message, ...);
  40 int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
  41 int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
  42 #endif
  43
  44 EXTERN_SIM_CORE\
  45 (SIM_RC)
  46 sim_core_install (SIM_DESC sd)
  47 {
  48   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
  49
  50   /* establish the other handlers */
  51   sim_module_add_uninstall_fn (sd, sim_core_uninstall);
  52   sim_module_add_init_fn (sd, sim_core_init);
  53
  54   /* establish any initial data structures - none */
  55   return SIM_RC_OK;
  56 }
  57
  58
  59 /* Uninstall the "core" subsystem from the simulator.  */
  60
  61 STATIC_SIM_CORE\
  62 (void)
  63 sim_core_uninstall (SIM_DESC sd)
  64 {
  65   sim_core *core = STATE_CORE(sd);
  66   sim_core_maps map;
  67   /* blow away any mappings */
  68   for (map = 0; map < nr_sim_core_maps; map++) {
  69     sim_core_mapping *curr = core->common.map[map].first;
  70     while (curr != NULL) {
  71       sim_core_mapping *tbd = curr;
  72       curr = curr->next;
  73       if (tbd->free_buffer != NULL) {
  74         SIM_ASSERT(tbd->buffer != NULL);
  75         zfree(tbd->free_buffer);
  76       }
  77       zfree(tbd);
  78     }
  79     core->common.map[map].first = NULL;
  80   }
  81 }
  82
  83
  84 STATIC_SIM_CORE\
  85 (SIM_RC)
  86 sim_core_init (SIM_DESC sd)
  87 {
  88   /* Nothing to do */
  89   return SIM_RC_OK;
  90 }
  91
  92
  93
  94 #ifndef SIM_CORE_SIGNAL
  95 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  96 sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  97
  98 STATIC_SIM_CORE\
  99 (void)
 100 sim_core_signal (SIM_DESC sd,
 101                  sim_cpu *cpu,
 102                  sim_cia cia,
 103                  sim_core_maps map,
 104                  int nr_bytes,
 105                  address_word addr,
 106                  transfer_type transfer,
 107                  sim_core_signals sig)
 108 {
 109   const char *copy = (transfer == read_transfer ? "read" : "write");
 110   address_word ip = CIA_ADDR (cia);
 111   switch (sig)
 112     {
 113     case sim_core_unmapped_signal:
 114       sim_io_eprintf (sd, "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
 115                       nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
 116       sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGSEGV);
 117       break;
 118     case sim_core_unaligned_signal:
 119       sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
 120                       nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
 121       sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGBUS);
 122       break;
 123     default:
 124       sim_engine_abort (sd, cpu, cia,
 125                         "sim_core_signal - internal error - bad switch");
 126     }
 127 }
 128 #endif
 129
 130
 131 EXTERN_SIM_CORE\
 132 (const char *)
 133 sim_core_map_to_str (sim_core_maps map)
 134 {
 135   switch (map)
 136     {
 137     case sim_core_read_map: return "read";
 138     case sim_core_write_map: return "write";
 139     case sim_core_execute_map: return "exec";
 140     default: return "(invalid-map)";
 141     }
 142 }
 143
 144
 145 STATIC_SIM_CORE\
 146 (sim_core_mapping *)
 147 new_sim_core_mapping (SIM_DESC sd,
 148                       int level,
 149                       int space,
 150                       address_word addr,
 151                       address_word nr_bytes,
 152                       unsigned modulo,
 153                       device *device,
 154                       void *buffer,
 155                       void *free_buffer)
 156 {
 157   sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping);
 158   /* common */
 159   new_mapping->level = level;
 160   new_mapping->space = space;
 161   new_mapping->base = addr;
 162   new_mapping->nr_bytes = nr_bytes;
 163   new_mapping->bound = addr + (nr_bytes - 1);
 164   if (modulo == 0)
 165     new_mapping->mask = (unsigned) 0 - 1;
 166   else
 167     new_mapping->mask = modulo - 1;
 168   new_mapping->buffer = buffer;
 169   new_mapping->free_buffer = free_buffer;
 170   new_mapping->device = device;
 171   return new_mapping;
 172 }
 173
 174
 175 STATIC_SIM_CORE\
 176 (void)
 177 sim_core_map_attach (SIM_DESC sd,
 178                      sim_core_map *access_map,
 179                      int level,
 180                      int space,
 181                      address_word addr,
 182                      address_word nr_bytes,
 183                      unsigned modulo,
 184                      device *client, /*callback/default*/
 185                      void *buffer, /*raw_memory*/
 186                      void *free_buffer) /*raw_memory*/
 187 {
 188   /* find the insertion point for this additional mapping and then
 189      insert */
 190   sim_core_mapping *next_mapping;
 191   sim_core_mapping **last_mapping;
 192
 193   SIM_ASSERT ((client == NULL) != (buffer == NULL));
 194   SIM_ASSERT ((client == NULL) >= (free_buffer != NULL));
 195
 196   /* actually do occasionally get a zero size map */
 197   if (nr_bytes == 0)
 198     {
 199 #if (WITH_DEVICES)
 200       device_error(client, "called on sim_core_map_attach with size zero");
 201 #else
 202       sim_io_error (sd, "called on sim_core_map_attach with size zero");
 203 #endif
 204     }
 205
 206   /* find the insertion point (between last/next) */
 207   next_mapping = access_map->first;
 208   last_mapping = &access_map->first;
 209   while(next_mapping != NULL
 210         && (next_mapping->level < level
 211             || (next_mapping->level == level
 212                 && next_mapping->bound < addr)))
 213     {
 214       /* provided levels are the same */
 215       /* assert: next_mapping->base > all bases before next_mapping */
 216       /* assert: next_mapping->bound >= all bounds before next_mapping */
 217       last_mapping = &next_mapping->next;
 218       next_mapping = next_mapping->next;
 219     }
 220
 221   /* check insertion point correct */
 222   SIM_ASSERT (next_mapping == NULL || next_mapping->level >= level);
 223   if (next_mapping != NULL && next_mapping->level == level
 224       && next_mapping->base < (addr + (nr_bytes - 1)))
 225     {
 226 #if (WITH_DEVICES)
 227       device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
 228                     space,
 229                     (long) addr,
 230                     (long) nr_bytes,
 231                     (long) (addr + (nr_bytes - 1)),
 232                     next_mapping->space,
 233                     (long) next_mapping->base,
 234                     (long) next_mapping->bound,
 235                     (long) next_mapping->nr_bytes);
 236 #else
 237       sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
 238                     space,
 239                     (long) addr,
 240                     (long) nr_bytes,
 241                     (long) (addr + (nr_bytes - 1)),
 242                     next_mapping->space,
 243                     (long) next_mapping->base,
 244                     (long) next_mapping->bound,
 245                     (long) next_mapping->nr_bytes);
 246 #endif
 247   }
 248
 249   /* create/insert the new mapping */
 250   *last_mapping = new_sim_core_mapping(sd,
 251                                        level,
 252                                        space, addr, nr_bytes, modulo,
 253                                        client, buffer, free_buffer);
 254   (*last_mapping)->next = next_mapping;
 255 }
 256
 257 /* Attach memory or a memory mapped device to the simulator.
 258    See sim-core.h for a full description.  */
 259
 260 EXTERN_SIM_CORE\
 261 (void)
 262 sim_core_attach (SIM_DESC sd,
 263                  sim_cpu *cpu,
 264                  int level,
 265                  access_type access,
 266                  int space,
 267                  address_word addr,
 268                  address_word nr_bytes,
 269                  unsigned modulo,
 270                  device *client,
 271                  void *optional_buffer)
 272 {
 273   sim_core *memory = STATE_CORE(sd);
 274   sim_core_maps map;
 275   void *buffer;
 276   void *free_buffer;
 277
 278   /* check for for attempt to use unimplemented per-processor core map */
 279   if (cpu != NULL)
 280     sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported");
 281
 282   if ((access & access_read_write_exec) == 0
 283       || (access & ~access_read_write_exec) != 0)
 284     {
 285 #if (WITH_DEVICES)
 286       device_error(client, "invalid access for core attach");
 287 #else
 288       sim_io_error (sd, "invalid access for core attach");
 289 #endif
 290     }
 291
 292   /* verify modulo memory */
 293   if (!WITH_MODULO_MEMORY && modulo != 0)
 294     {
 295 #if (WITH_DEVICES)
 296       device_error (client, "sim_core_attach - internal error - modulo memory disabled");
 297 #else
 298       sim_io_error (sd, "sim_core_attach - internal error - modulo memory disabled");
 299 #endif
 300     }
 301   if (client != NULL && modulo != 0)
 302     {
 303 #if (WITH_DEVICES)
 304       device_error (client, "sim_core_attach - internal error - modulo and callback memory conflict");
 305 #else
 306       sim_io_error (sd, "sim_core_attach - internal error - modulo and callback memory conflict");
 307 #endif
 308     }
 309   if (modulo != 0)
 310     {
 311       unsigned mask = modulo - 1;
 312       /* any zero bits */
 313       while (mask >= sizeof (unsigned64)) /* minimum modulo */
 314         {
 315           if ((mask & 1) == 0)
 316             mask = 0;
 317           else
 318             mask >>= 1;
 319         }
 320       if (mask != sizeof (unsigned64) - 1)
 321         {
 322 #if (WITH_DEVICES)
 323           device_error (client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
 324 #else
 325           sim_io_error (sd, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
 326 #endif
 327         }
 328     }
 329
 330   /* verify consistency between device and buffer */
 331   if (client != NULL && optional_buffer != NULL)
 332     {
 333 #if (WITH_DEVICES)
 334       device_error (client, "sim_core_attach - internal error - conflicting buffer and attach arguments");
 335 #else
 336       sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments");
 337 #endif
 338     }
 339   if (client == NULL)
 340     {
 341       if (optional_buffer == NULL)
 342         {
 343           int padding = (addr % sizeof (unsigned64));
 344           unsigned int bytes = (modulo == 0 ? nr_bytes : modulo) + padding;
 345           free_buffer = xmalloc (bytes);
 346           /* #if WITH_DETERMINISTIC_SIMULATION? */
 347           memset (free_buffer, 0xa5, bytes);
 348           buffer = (char*) free_buffer + padding;
 349         }
 350       else
 351         {
 352           buffer = optional_buffer;
 353           free_buffer = NULL;
 354         }
 355     }
 356   else
 357     {
 358       /* a device */
 359       buffer = NULL;
 360       free_buffer = NULL;
 361     }
 362
 363   /* attach the region to all applicable access maps */
 364   for (map = 0;
 365        map < nr_sim_core_maps;
 366        map++)
 367     {
 368       switch (map)
 369         {
 370         case sim_core_read_map:
 371           if (access & access_read)
 372             sim_core_map_attach (sd, &memory->common.map[map],
 373                                  level, space, addr, nr_bytes, modulo,
 374                                  client, buffer, free_buffer);
 375           free_buffer = NULL;
 376           break;
 377         case sim_core_write_map:
 378           if (access & access_write)
 379             sim_core_map_attach (sd, &memory->common.map[map],
 380                                  level, space, addr, nr_bytes, modulo,
 381                                  client, buffer, free_buffer);
 382           free_buffer = NULL;
 383           break;
 384         case sim_core_execute_map:
 385           if (access & access_exec)
 386             sim_core_map_attach (sd, &memory->common.map[map],
 387                                  level, space, addr, nr_bytes, modulo,
 388                                  client, buffer, free_buffer);
 389           free_buffer = NULL;
 390           break;
 391         default:
 392           sim_io_error (sd, "sim_core_attach - internal error - bad switch");
 393           break;
 394         }
 395     }
 396
 397   /* Just copy this map to each of the processor specific data structures.
 398      FIXME - later this will be replaced by true processor specific
 399      maps. */
 400   {
 401     int i;
 402     for (i = 0; i < MAX_NR_PROCESSORS; i++)
 403       {
 404         CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
 405       }
 406   }
 407 }
 408
 409
 410 /* Remove any memory reference related to this address */
 411 STATIC_INLINE_SIM_CORE\
 412 (void)
 413 sim_core_map_detach (SIM_DESC sd,
 414                      sim_core_map *access_map,
 415                      int level,
 416                      int space,
 417                      address_word addr)
 418 {
 419   sim_core_mapping **entry;
 420   for (entry = &access_map->first;
 421        (*entry) != NULL;
 422        entry = &(*entry)->next)
 423     {
 424       if ((*entry)->base == addr
 425           && (*entry)->level == level
 426           && (*entry)->space == space)
 427         {
 428           sim_core_mapping *dead = (*entry);
 429           (*entry) = dead->next;
 430           if (dead->free_buffer != NULL)
 431             free (dead->free_buffer);
 432           zfree (dead);
 433           return;
 434         }
 435     }
 436 }
 437
 438 EXTERN_SIM_CORE\
 439 (void)
 440 sim_core_detach (SIM_DESC sd,
 441                  sim_cpu *cpu,
 442                  int level,
 443                  int address_space,
 444                  address_word addr)
 445 {
 446   sim_core *memory = STATE_CORE (sd);
 447   sim_core_maps map;
 448   for (map = 0; map < nr_sim_core_maps; map++)
 449     {
 450       sim_core_map_detach (sd, &memory->common.map[map],
 451                            level, address_space, addr);
 452     }
 453   /* Just copy this update to each of the processor specific data
 454      structures.  FIXME - later this will be replaced by true
 455      processor specific maps. */
 456   {
 457     int i;
 458     for (i = 0; i < MAX_NR_PROCESSORS; i++)
 459       {
 460         CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
 461       }
 462   }
 463 }
 464
 465
 466 STATIC_INLINE_SIM_CORE\
 467 (sim_core_mapping *)
 468 sim_core_find_mapping(sim_core_common *core,
 469                       sim_core_maps map,
 470                       address_word addr,
 471                       unsigned nr_bytes,
 472                       transfer_type transfer,
 473                       int abort, /*either 0 or 1 - hint to inline/-O */
 474                       sim_cpu *cpu, /* abort => cpu != NULL */
 475                       sim_cia cia)
 476 {
 477   sim_core_mapping *mapping = core->map[map].first;
 478   ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */
 479   ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
 480   ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */
 481   while (mapping != NULL)
 482     {
 483       if (addr >= mapping->base
 484           && (addr + (nr_bytes - 1)) <= mapping->bound)
 485         return mapping;
 486       mapping = mapping->next;
 487     }
 488   if (abort)
 489     {
 490       SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer,
 491                        sim_core_unmapped_signal);
 492     }
 493   return NULL;
 494 }
 495
 496
 497 STATIC_INLINE_SIM_CORE\
 498 (void *)
 499 sim_core_translate (sim_core_mapping *mapping,
 500                     address_word addr)
 501 {
 502   if (WITH_MODULO_MEMORY)
 503     return (void *)((unsigned8 *) mapping->buffer
 504                     + ((addr - mapping->base) & mapping->mask));
 505   else
 506     return (void *)((unsigned8 *) mapping->buffer
 507                     + addr - mapping->base);
 508 }
 509
 510
 511 EXTERN_SIM_CORE\
 512 (unsigned)
 513 sim_core_read_buffer (SIM_DESC sd,
 514                       sim_cpu *cpu,
 515                       sim_core_maps map,
 516                       void *buffer,
 517                       address_word addr,
 518                       unsigned len)
 519 {
 520   sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
 521   unsigned count = 0;
 522   while (count < len) {
 523     unsigned_word raddr = addr + count;
 524     sim_core_mapping *mapping =
 525       sim_core_find_mapping(core, map,
 526                             raddr, /*nr-bytes*/1,
 527                             read_transfer,
 528                             0 /*dont-abort*/, NULL, NULL_CIA);
 529     if (mapping == NULL)
 530       break;
 531 #if (WITH_DEVICES)
 532     if (mapping->device != NULL) {
 533       int nr_bytes = len - count;
 534       if (raddr + nr_bytes - 1> mapping->bound)
 535         nr_bytes = mapping->bound - raddr + 1;
 536       if (device_io_read_buffer(mapping->device,
 537                                 (unsigned_1*)buffer + count,
 538                                 mapping->space,
 539                                 raddr,
 540                                 nr_bytes,
 541                                 cpu,
 542                                 CIA_GET(cpu)) != nr_bytes)
 543         break;
 544       count += nr_bytes;
 545     }
 546     else
 547 #endif
 548       {
 549         ((unsigned_1*)buffer)[count] =
 550           *(unsigned_1*)sim_core_translate(mapping, raddr);
 551         count += 1;
 552       }
 553   }
 554   return count;
 555 }
 556
 557
 558 EXTERN_SIM_CORE\
 559 (unsigned)
 560 sim_core_write_buffer (SIM_DESC sd,
 561                        sim_cpu *cpu,
 562                        sim_core_maps map,
 563                        const void *buffer,
 564                        address_word addr,
 565                        unsigned len)
 566 {
 567   sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
 568   unsigned count = 0;
 569   while (count < len) {
 570     unsigned_word raddr = addr + count;
 571     sim_core_mapping *mapping =
 572       sim_core_find_mapping(core, map,
 573                             raddr, /*nr-bytes*/1,
 574                             write_transfer,
 575                             0 /*dont-abort*/, NULL, NULL_CIA);
 576     if (mapping == NULL)
 577       break;
 578 #if (WITH_DEVICES)
 579     if (WITH_CALLBACK_MEMORY
 580         && mapping->device != NULL) {
 581       int nr_bytes = len - count;
 582       if (raddr + nr_bytes - 1 > mapping->bound)
 583         nr_bytes = mapping->bound - raddr + 1;
 584       if (device_io_write_buffer(mapping->device,
 585                                  (unsigned_1*)buffer + count,
 586                                  mapping->space,
 587                                  raddr,
 588                                  nr_bytes,
 589                                  cpu,
 590                                  CIA_GET(cpu)) != nr_bytes)
 591         break;
 592       count += nr_bytes;
 593     }
 594     else
 595 #endif
 596       {
 597         *(unsigned_1*)sim_core_translate(mapping, raddr) =
 598           ((unsigned_1*)buffer)[count];
 599         count += 1;
 600       }
 601   }
 602   return count;
 603 }
 604
 605
 606 EXTERN_SIM_CORE\
 607 (void)
 608 sim_core_set_xor (SIM_DESC sd,
 609                   sim_cpu *cpu,
 610                   int is_xor)
 611 {
 612   /* set up the XOR map if required. */
 613   if (WITH_XOR_ENDIAN) {
 614     {
 615       sim_core *core = STATE_CORE (sd);
 616       sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL);
 617       if (cpu_core != NULL)
 618         {
 619           int i = 1;
 620           unsigned mask;
 621           if (is_xor)
 622             mask = WITH_XOR_ENDIAN - 1;
 623           else
 624             mask = 0;
 625           while (i - 1 < WITH_XOR_ENDIAN)
 626             {
 627               cpu_core->xor[i-1] = mask;
 628               mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
 629               i = (i << 1);
 630             }
 631         }
 632       else
 633         {
 634           if (is_xor)
 635             core->byte_xor = WITH_XOR_ENDIAN - 1;
 636           else
 637             core->byte_xor = 0;
 638         }
 639     }
 640   }
 641   else {
 642     if (is_xor)
 643       sim_engine_abort (sd, cpu, NULL_CIA,
 644                         "Attempted to enable xor-endian mode when permenantly disabled.");
 645   }
 646 }
 647
 648 STATIC_INLINE_SIM_CORE\
 649 (void)
 650 reverse_n (unsigned_1 *dest,
 651            const unsigned_1 *src,
 652            int nr_bytes)
 653 {
 654   int i;
 655   for (i = 0; i < nr_bytes; i++)
 656     {
 657       dest [nr_bytes - i - 1] = src [i];
 658     }
 659 }
 660
 661
 662 EXTERN_SIM_CORE\
 663 (unsigned)
 664 sim_core_xor_read_buffer (SIM_DESC sd,
 665                           sim_cpu *cpu,
 666                           sim_core_maps map,
 667                           void *buffer,
 668                           address_word addr,
 669                           unsigned nr_bytes)
 670 {
 671   address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
 672   if (!WITH_XOR_ENDIAN || !byte_xor)
 673     return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes);
 674   else
 675     /* only break up transfers when xor-endian is both selected and enabled */
 676     {
 677       unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
 678       unsigned nr_transfered = 0;
 679       address_word start = addr;
 680       unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
 681       address_word stop;
 682       /* initial and intermediate transfers are broken when they cross
 683          an XOR endian boundary */
 684       while (nr_transfered + nr_this_transfer < nr_bytes)
 685         /* initial/intermediate transfers */
 686         {
 687           /* since xor-endian is enabled stop^xor defines the start
 688              address of the transfer */
 689           stop = start + nr_this_transfer - 1;
 690           SIM_ASSERT (start <= stop);
 691           SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
 692           if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 693               != nr_this_transfer)
 694             return nr_transfered;
 695           reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
 696           nr_transfered += nr_this_transfer;
 697           nr_this_transfer = WITH_XOR_ENDIAN;
 698           start = stop + 1;
 699         }
 700       /* final transfer */
 701       nr_this_transfer = nr_bytes - nr_transfered;
 702       stop = start + nr_this_transfer - 1;
 703       SIM_ASSERT (stop == (addr + nr_bytes - 1));
 704       if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 705           != nr_this_transfer)
 706         return nr_transfered;
 707       reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
 708       return nr_bytes;
 709     }
 710 }
 711
 712
 713 EXTERN_SIM_CORE\
 714 (unsigned)
 715 sim_core_xor_write_buffer (SIM_DESC sd,
 716                            sim_cpu *cpu,
 717                            sim_core_maps map,
 718                            const void *buffer,
 719                            address_word addr,
 720                            unsigned nr_bytes)
 721 {
 722   address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
 723   if (!WITH_XOR_ENDIAN || !byte_xor)
 724     return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes);
 725   else
 726     /* only break up transfers when xor-endian is both selected and enabled */
 727     {
 728       unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */
 729       unsigned nr_transfered = 0;
 730       address_word start = addr;
 731       unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
 732       address_word stop;
 733       /* initial and intermediate transfers are broken when they cross
 734          an XOR endian boundary */
 735       while (nr_transfered + nr_this_transfer < nr_bytes)
 736         /* initial/intermediate transfers */
 737         {
 738           /* since xor-endian is enabled stop^xor defines the start
 739              address of the transfer */
 740           stop = start + nr_this_transfer - 1;
 741           SIM_ASSERT (start <= stop);
 742           SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
 743           reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
 744           if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 745               != nr_this_transfer)
 746             return nr_transfered;
 747           nr_transfered += nr_this_transfer;
 748           nr_this_transfer = WITH_XOR_ENDIAN;
 749           start = stop + 1;
 750         }
 751       /* final transfer */
 752       nr_this_transfer = nr_bytes - nr_transfered;
 753       stop = start + nr_this_transfer - 1;
 754       SIM_ASSERT (stop == (addr + nr_bytes - 1));
 755       reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
 756       if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 757           != nr_this_transfer)
 758         return nr_transfered;
 759       return nr_bytes;
 760     }
 761 }
 762
 763
 764
 765 /* define the read/write 1/2/4/8/16/word functions */
 766
 767 #define N 16
 768 #include "sim-n-core.h"
 769
 770 #define N 8
 771 #include "sim-n-core.h"
 772
 773 #define N 7
 774 #define M 8
 775 #include "sim-n-core.h"
 776
 777 #define N 6
 778 #define M 8
 779 #include "sim-n-core.h"
 780
 781 #define N 5
 782 #define M 8
 783 #include "sim-n-core.h"
 784
 785 #define N 4
 786 #include "sim-n-core.h"
 787
 788 #define N 3
 789 #define M 4
 790 #include "sim-n-core.h"
 791
 792 #define N 2
 793 #include "sim-n-core.h"
 794
 795 #define N 1
 796 #include "sim-n-core.h"
 797
 798 #endif