sim/common/sim-core.h

   1 /* The common simulator framework for GDB, the GNU Debugger.
   2
   3    Copyright 2002-2015 Free Software Foundation, Inc.
   4
   5    Contributed by Andrew Cagney and Red Hat.
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  21
  22
  23 #ifndef SIM_CORE_H
  24 #define SIM_CORE_H
  25
  26
  27 /* core signals (error conditions)
  28    Define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for
  29    details.  */
  30
  31 typedef enum {
  32   sim_core_unmapped_signal,
  33   sim_core_unaligned_signal,
  34   nr_sim_core_signals,
  35 } sim_core_signals;
  36
  37 /* Type of SIM_CORE_SIGNAL handler.  */
  38 typedef void (SIM_CORE_SIGNAL_FN)
  39      (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, unsigned map, int nr_bytes,
  40       address_word addr, transfer_type transfer, sim_core_signals sig);
  41
  42 extern SIM_CORE_SIGNAL_FN sim_core_signal;
  43
  44
  45 /* basic types */
  46
  47 typedef struct _sim_core_mapping sim_core_mapping;
  48 struct _sim_core_mapping {
  49   /* common */
  50   int level;
  51   int space;
  52   unsigned_word base;
  53   unsigned_word bound;
  54   unsigned_word nr_bytes;
  55   unsigned mask;
  56   /* memory map */
  57   void *free_buffer;
  58   void *buffer;
  59   /* callback map */
  60 #if (WITH_HW)
  61   struct hw *device;
  62 #else
  63   device *device;
  64 #endif
  65   /* tracing */
  66   int trace;
  67   /* growth */
  68   sim_core_mapping *next;
  69 };
  70
  71 typedef struct _sim_core_map sim_core_map;
  72 struct _sim_core_map {
  73   sim_core_mapping *first;
  74 };
  75
  76
  77 typedef struct _sim_core_common {
  78   sim_core_map map[nr_maps];
  79 } sim_core_common;
  80
  81
  82 /* Main core structure */
  83
  84 typedef struct _sim_core sim_core;
  85 struct _sim_core {
  86   sim_core_common common;
  87   address_word byte_xor; /* apply xor universally */
  88 };
  89
  90
  91 /* Per CPU distributed component of the core.  At present this is
  92    mostly a clone of the global core data structure. */
  93
  94 typedef struct _sim_cpu_core {
  95   sim_core_common common;
  96   address_word xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
  97 } sim_cpu_core;
  98
  99
 100 /* Install the "core" module.  */
 101
 102 extern SIM_RC sim_core_install (SIM_DESC sd);
 103
 104
 105
 106 /* Create a memory region within the core.
 107
 108    CPU - when non NULL, specifes the single processor that the memory
 109    space is to be attached to. (INIMPLEMENTED).
 110
 111    LEVEL - specifies the ordering of the memory region.  Lower regions
 112    are searched first.  Within a level, memory regions can not
 113    overlap.
 114
 115    MAPMASK - Bitmask specifying the memory maps that the region is to
 116    be attached to.  Typically the enums sim-basics.h:access_* are used.
 117
 118    ADDRESS_SPACE - For device regions, a MAP:ADDRESS pair is
 119    translated into ADDRESS_SPACE:OFFSET before being passed to the
 120    client device.
 121
 122    MODULO - Specifies that accesses to the region [ADDR .. ADDR+NR_BYTES)
 123    should be mapped onto the sub region [ADDR .. ADDR+MODULO).  The modulo
 124    value must be a power of two.
 125
 126    DEVICE - When non NULL, indicates that this is a callback memory
 127    space and specified device's memory callback handler should be
 128    called.
 129
 130    OPTIONAL_BUFFER - when non NULL, specifies the buffer to use for
 131    data read & written to the region.  Normally a more efficient
 132    internal structure is used.  It is assumed that buffer is allocated
 133    such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis
 134    (OPTIONAL_BUFFER % 8) == (ADDR % 8)).  It is defined to be a sub-optimal
 135    hook that allows clients to do nasty things that the interface doesn't
 136    accomodate. */
 137
 138 extern void sim_core_attach
 139 (SIM_DESC sd,
 140  sim_cpu *cpu,
 141  int level,
 142  unsigned mapmask,
 143  int address_space,
 144  address_word addr,
 145  address_word nr_bytes,
 146  unsigned modulo,
 147 #if (WITH_HW)
 148  struct hw *client,
 149 #else
 150  device *client,
 151 #endif
 152  void *optional_buffer);
 153
 154
 155 /* Delete a memory section within the core.
 156
 157  */
 158
 159 extern void sim_core_detach
 160 (SIM_DESC sd,
 161  sim_cpu *cpu,
 162  int level,
 163  int address_space,
 164  address_word addr);
 165
 166
 167 /* Variable sized read/write
 168
 169    Transfer a variable sized block of raw data between the host and
 170    target.  Should any problems occur, the number of bytes
 171    successfully transfered is returned.
 172
 173    No host/target byte endian conversion is performed.  No xor-endian
 174    conversion is performed.
 175
 176    If CPU argument, when non NULL, specifies the processor specific
 177    address map that is to be used in the transfer. */
 178
 179
 180 extern unsigned sim_core_read_buffer
 181 (SIM_DESC sd,
 182  sim_cpu *cpu,
 183  unsigned map,
 184  void *buffer,
 185  address_word addr,
 186  unsigned nr_bytes);
 187
 188 extern unsigned sim_core_write_buffer
 189 (SIM_DESC sd,
 190  sim_cpu *cpu,
 191  unsigned map,
 192  const void *buffer,
 193  address_word addr,
 194  unsigned nr_bytes);
 195
 196
 197
 198 /* Configure the core's XOR endian transfer mode.  Only applicable
 199    when WITH_XOR_ENDIAN is enabled.
 200
 201    Targets suporting XOR endian, shall notify the core of any changes
 202    in state via this call.
 203
 204    The CPU argument, when non NULL, specifes the single processor that
 205    the xor-endian configuration is to be applied to. */
 206
 207 extern void sim_core_set_xor
 208 (SIM_DESC sd,
 209  sim_cpu *cpu,
 210  int is_xor);
 211
 212
 213 /* XOR version of variable sized read/write.
 214
 215    Transfer a variable sized block of raw data between the host and
 216    target.  Should any problems occur, the number of bytes
 217    successfully transfered is returned.
 218
 219    No host/target byte endian conversion is performed.  If applicable
 220    (WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is*
 221    performed.
 222
 223    If CPU argument, when non NULL, specifies the processor specific
 224    address map that is to be used in the transfer. */
 225
 226 extern unsigned sim_core_xor_read_buffer
 227 (SIM_DESC sd,
 228  sim_cpu *cpu,
 229  unsigned map,
 230  void *buffer,
 231  address_word addr,
 232  unsigned nr_bytes);
 233
 234 extern unsigned sim_core_xor_write_buffer
 235 (SIM_DESC sd,
 236  sim_cpu *cpu,
 237  unsigned map,
 238  const void *buffer,
 239  address_word addr,
 240  unsigned nr_bytes);
 241
 242
 243 /* Translate an address based on a map.  */
 244
 245 extern void *sim_core_trans_addr
 246 (SIM_DESC sd,
 247  sim_cpu *cpu,
 248  unsigned map,
 249  address_word addr);
 250
 251
 252 /* Fixed sized, processor oriented, read/write.
 253
 254    Transfer a fixed amout of memory between the host and target.  The
 255    data transfered is translated from/to host to/from target byte
 256    order (including xor endian).  Should the transfer fail, the
 257    operation shall abort (no return).
 258
 259    ALIGNED assumes yhat the specified ADDRESS is correctly alligned
 260    for an N byte transfer (no alignment checks are made).  Passing an
 261    incorrectly aligned ADDRESS is erroneous.
 262
 263    UNALIGNED checks/modifies the ADDRESS according to the requirements
 264    of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being
 265    taken should the check fail.
 266
 267    MISSALIGNED transfers the data regardless.
 268
 269    Misaligned xor-endian accesses are broken into a sequence of
 270    transfers each <= WITH_XOR_ENDIAN bytes */
 271
 272
 273 #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \
 274 INLINE_SIM_CORE\
 275 (void) sim_core_write_##ALIGNMENT##_##N \
 276 (sim_cpu *cpu, \
 277  sim_cia cia, \
 278  unsigned map, \
 279  address_word addr, \
 280  unsigned_##M val);
 281
 282 DECLARE_SIM_CORE_WRITE_N(aligned,1,1)
 283 DECLARE_SIM_CORE_WRITE_N(aligned,2,2)
 284 DECLARE_SIM_CORE_WRITE_N(aligned,4,4)
 285 DECLARE_SIM_CORE_WRITE_N(aligned,8,8)
 286 DECLARE_SIM_CORE_WRITE_N(aligned,16,16)
 287
 288 #define sim_core_write_unaligned_1 sim_core_write_aligned_1
 289 DECLARE_SIM_CORE_WRITE_N(unaligned,2,2)
 290 DECLARE_SIM_CORE_WRITE_N(unaligned,4,4)
 291 DECLARE_SIM_CORE_WRITE_N(unaligned,8,8)
 292 DECLARE_SIM_CORE_WRITE_N(unaligned,16,16)
 293
 294 DECLARE_SIM_CORE_WRITE_N(misaligned,3,4)
 295 DECLARE_SIM_CORE_WRITE_N(misaligned,5,8)
 296 DECLARE_SIM_CORE_WRITE_N(misaligned,6,8)
 297 DECLARE_SIM_CORE_WRITE_N(misaligned,7,8)
 298
 299 #define sim_core_write_1 sim_core_write_aligned_1
 300 #define sim_core_write_2 sim_core_write_aligned_2
 301 #define sim_core_write_4 sim_core_write_aligned_4
 302 #define sim_core_write_8 sim_core_write_aligned_8
 303 #define sim_core_write_16 sim_core_write_aligned_16
 304
 305 #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE)
 306 #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE)
 307 #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE)
 308
 309 #undef DECLARE_SIM_CORE_WRITE_N
 310
 311
 312 #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \
 313 INLINE_SIM_CORE\
 314 (unsigned_##M) sim_core_read_##ALIGNMENT##_##N \
 315 (sim_cpu *cpu, \
 316  sim_cia cia, \
 317  unsigned map, \
 318  address_word addr);
 319
 320 DECLARE_SIM_CORE_READ_N(aligned,1,1)
 321 DECLARE_SIM_CORE_READ_N(aligned,2,2)
 322 DECLARE_SIM_CORE_READ_N(aligned,4,4)
 323 DECLARE_SIM_CORE_READ_N(aligned,8,8)
 324 DECLARE_SIM_CORE_READ_N(aligned,16,16)
 325
 326 #define sim_core_read_unaligned_1 sim_core_read_aligned_1
 327 DECLARE_SIM_CORE_READ_N(unaligned,2,2)
 328 DECLARE_SIM_CORE_READ_N(unaligned,4,4)
 329 DECLARE_SIM_CORE_READ_N(unaligned,8,8)
 330 DECLARE_SIM_CORE_READ_N(unaligned,16,16)
 331
 332 DECLARE_SIM_CORE_READ_N(misaligned,3,4)
 333 DECLARE_SIM_CORE_READ_N(misaligned,5,8)
 334 DECLARE_SIM_CORE_READ_N(misaligned,6,8)
 335 DECLARE_SIM_CORE_READ_N(misaligned,7,8)
 336
 337
 338 #define sim_core_read_1 sim_core_read_aligned_1
 339 #define sim_core_read_2 sim_core_read_aligned_2
 340 #define sim_core_read_4 sim_core_read_aligned_4
 341 #define sim_core_read_8 sim_core_read_aligned_8
 342 #define sim_core_read_16 sim_core_read_aligned_16
 343
 344 #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE)
 345 #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE)
 346 #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE)
 347
 348 #undef DECLARE_SIM_CORE_READ_N
 349
 350
 351 #if (WITH_DEVICES)
 352 /* TODO: create sim/common/device.h */
 353 /* These are defined with each particular cpu.  */
 354 void device_error (device *me, const char *message, ...) __attribute__((format (printf, 2, 3)));
 355 int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia);
 356 int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia);
 357 #endif
 358
 359
 360 #endif