1 /* This file is part of the program psim.
3 Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 /* core signals (error conditions) */
29 sim_core_unmapped_signal
,
30 sim_core_unaligned_signal
,
34 /* define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for
41 typedef struct _sim_core_mapping sim_core_mapping
;
42 struct _sim_core_mapping
{
48 unsigned_word nr_bytes
;
58 sim_core_mapping
*next
;
61 typedef struct _sim_core_map sim_core_map
;
62 struct _sim_core_map
{
63 sim_core_mapping
*first
;
74 typedef struct _sim_core_common
{
75 sim_core_map map
[nr_sim_core_maps
];
79 /* Main core structure */
81 typedef struct _sim_core sim_core
;
83 sim_core_common common
;
84 address_word byte_xor
; /* apply xor universally */
88 /* Per CPU distributed component of the core. At present this is
89 mostly a clone of the global core data structure. */
91 typedef struct _sim_cpu_core
{
92 sim_core_common common
;
93 address_word
xor[WITH_XOR_ENDIAN
+ 1]; /* +1 to avoid zero-sized array */
97 /* Install the "core" module. */
100 (SIM_RC
) sim_core_install (SIM_DESC sd
);
104 /* Create a memory space within the core.
106 CPU, when non NULL, specifes the single processor that the memory
107 space is to be attached to. (UNIMPLEMENTED).
109 LEVEL specifies the ordering of the memory region. Lower regions
110 are searched first. Within a level, memory regions can not
113 DEVICE, when non NULL, specifies a callback memory space.
114 (UNIMPLEMENTED, see the ppc simulator for an example).
116 MODULO, when the simulator has been configured WITH_MODULO support
117 and is greater than zero, specifies that accesses to the region
118 [ADDR .. ADDR+NR_BYTES) should be mapped onto the sub region [ADDR
119 .. ADDR+MODULO). The modulo value must be a power of two.
121 OPTIONAL_BUFFER, when non NULL, specifies the buffer to use for
122 data read & written to the region. Normally a more efficient
123 internal structure is used. It is assumed that buffer is allocated
124 such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis
125 (OPTIONAL_BUFFER % 8) == (ADDR % 8)). It is defined to be a sub-optimal
126 hook that allows clients to do nasty things that the interface doesn't
127 accomodate. ??? That seems unnecessarily restrictive. */
130 (void) sim_core_attach
137 address_word nr_bytes
,
140 void *optional_buffer
);
143 /* Utility to return the name of a map. */
146 (const char *) sim_core_map_to_str
150 /* Delete a memory space within the core.
155 (void) sim_core_detach
163 /* Variable sized read/write
165 Transfer a variable sized block of raw data between the host and
166 target. Should any problems occure, the number of bytes
167 successfully transfered is returned.
169 No host/target byte endian conversion is performed. No xor-endian
170 conversion is performed.
172 If CPU argument, when non NULL, specifies the processor specific
173 address map that is to be used in the transfer. */
177 (unsigned) sim_core_read_buffer
186 (unsigned) sim_core_write_buffer
196 /* Configure the core's XOR endian transfer mode. Only applicable
197 when WITH_XOR_ENDIAN is enabled.
199 Targets suporting XOR endian, shall notify the core of any changes
200 in state via this call.
202 The CPU argument, when non NULL, specifes the single processor that
203 the xor-endian configuration is to be applied to. */
206 (void) sim_core_set_xor\
212 /* XOR version of variable sized read/write.
214 Transfer a variable sized block of raw data between the host and
215 target. Should any problems occure, the number of bytes
216 successfully transfered is returned.
218 No host/target byte endian conversion is performed. If applicable
219 (WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is*
222 If CPU argument, when non NULL, specifies the processor specific
223 address map that is to be used in the transfer. */
226 (unsigned) sim_core_xor_read_buffer
235 (unsigned) sim_core_xor_write_buffer
245 /* Fixed sized, processor oriented, read/write.
247 Transfer a fixed amout of memory between the host and target. The
248 data transfered is translated from/to host to/from target byte
249 order (including xor endian). Should the transfer fail, the
250 operation shall abort (no return).
252 ALIGNED assumes yhat the specified ADDRESS is correctly alligned
253 for an N byte transfer (no alignment checks are made). Passing an
254 incorrectly aligned ADDRESS is erroneous.
256 UNALIGNED checks/modifies the ADDRESS according to the requirements
257 of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being
258 taken should the check fail.
260 MISSALIGNED transfers the data regardless.
262 Misaligned xor-endian accesses are broken into a sequence of
263 transfers each <= WITH_XOR_ENDIAN bytes */
266 #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \
268 (void) sim_core_write_##ALIGNMENT##_##N \
275 DECLARE_SIM_CORE_WRITE_N(aligned
,1,1)
276 DECLARE_SIM_CORE_WRITE_N(aligned
,2,2)
277 DECLARE_SIM_CORE_WRITE_N(aligned
,4,4)
278 DECLARE_SIM_CORE_WRITE_N(aligned
,8,8)
279 DECLARE_SIM_CORE_WRITE_N(aligned
,16,16)
281 #define sim_core_write_unaligned_1 sim_core_write_aligned_1
282 DECLARE_SIM_CORE_WRITE_N(unaligned
,2,2)
283 DECLARE_SIM_CORE_WRITE_N(unaligned
,4,4)
284 DECLARE_SIM_CORE_WRITE_N(unaligned
,8,8)
285 DECLARE_SIM_CORE_WRITE_N(unaligned
,16,16)
287 DECLARE_SIM_CORE_WRITE_N(misaligned
,3,4)
288 DECLARE_SIM_CORE_WRITE_N(misaligned
,5,8)
289 DECLARE_SIM_CORE_WRITE_N(misaligned
,6,8)
290 DECLARE_SIM_CORE_WRITE_N(misaligned
,7,8)
292 #define sim_core_write_1 sim_core_write_aligned_1
293 #define sim_core_write_2 sim_core_write_aligned_2
294 #define sim_core_write_4 sim_core_write_aligned_4
295 #define sim_core_write_8 sim_core_write_aligned_8
296 #define sim_core_write_16 sim_core_write_aligned_16
298 #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE)
299 #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE)
300 #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE)
302 #undef DECLARE_SIM_CORE_WRITE_N
305 #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \
307 (unsigned_##M) sim_core_read_##ALIGNMENT##_##N \
313 DECLARE_SIM_CORE_READ_N(aligned
,1,1)
314 DECLARE_SIM_CORE_READ_N(aligned
,2,2)
315 DECLARE_SIM_CORE_READ_N(aligned
,4,4)
316 DECLARE_SIM_CORE_READ_N(aligned
,8,8)
317 DECLARE_SIM_CORE_READ_N(aligned
,16,16)
319 #define sim_core_read_unaligned_1 sim_core_read_aligned_1
320 DECLARE_SIM_CORE_READ_N(unaligned
,2,2)
321 DECLARE_SIM_CORE_READ_N(unaligned
,4,4)
322 DECLARE_SIM_CORE_READ_N(unaligned
,8,8)
323 DECLARE_SIM_CORE_READ_N(unaligned
,16,16)
325 DECLARE_SIM_CORE_READ_N(misaligned
,3,4)
326 DECLARE_SIM_CORE_READ_N(misaligned
,5,8)
327 DECLARE_SIM_CORE_READ_N(misaligned
,6,8)
328 DECLARE_SIM_CORE_READ_N(misaligned
,7,8)
331 #define sim_core_read_1 sim_core_read_aligned_1
332 #define sim_core_read_2 sim_core_read_aligned_2
333 #define sim_core_read_4 sim_core_read_aligned_4
334 #define sim_core_read_8 sim_core_read_aligned_8
335 #define sim_core_read_16 sim_core_read_aligned_16
337 #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE)
338 #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE)
339 #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE)
341 #undef DECLARE_SIM_CORE_READ_N