1 /* This file is part of the program psim.
3 Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 #error "N must be #defined"
29 /* N: The number of bytes of data to transfer.
30 M: The number of bytes in the type used to transfer the data */
33 #error "N (nr bytes of data) must be <= M (nr of bytes in data type)"
39 /* NOTE: see end of file for #undef of these macros */
41 #define unsigned_M XCONCAT2(unsigned_,M)
43 #define T2H_M XCONCAT2(T2H_,M)
44 #define H2T_M XCONCAT2(H2T_,M)
45 #define SWAP_M XCONCAT2(SWAP_,M)
47 #define sim_core_read_aligned_N XCONCAT2(sim_core_read_aligned_,N)
48 #define sim_core_read_unaligned_N XCONCAT2(sim_core_read_unaligned_,N)
49 #define sim_core_read_misaligned_N XCONCAT2(sim_core_read_misaligned_,N)
50 #define sim_core_write_aligned_N XCONCAT2(sim_core_write_aligned_,N)
51 #define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N)
52 #define sim_core_write_misaligned_N XCONCAT2(sim_core_write_misaligned_,N)
53 #define sim_core_trace_M XCONCAT2(sim_core_trace_,M)
54 #define sim_core_dummy_M XCONCAT2(sim_core_dummy_,M)
58 /* dummy variable used as a return value when nothing else is
59 available and the compiler is complaining */
60 static unsigned_M sim_core_dummy_M
;
64 /* TAGS: sim_core_trace_1 sim_core_trace_2 */
65 /* TAGS: sim_core_trace_4 sim_core_trace_8 */
66 /* TAGS: sim_core_trace_16 */
70 sim_core_trace_M (sim_cpu
*cpu
,
79 const char *transfer
= (type
== read_transfer
? "read" : "write");
80 const char *direction
= (type
== read_transfer
? "->" : "<-");
82 if (TRACE_DEBUG_P (cpu
))
83 trace_printf (CPU_STATE (cpu
), cpu
, "sim-n-core.h:%d: ", line_nr
);
86 trace_printf (CPU_STATE (cpu
), cpu
,
87 "%s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx\n",
92 (unsigned long) V4_16 (val
, 0),
93 (unsigned long) V4_16 (val
, 1),
94 (unsigned long) V4_16 (val
, 2),
95 (unsigned long) V4_16 (val
, 3));
98 trace_printf (CPU_STATE (cpu
), cpu
,
99 "%s-%d %s:0x%08lx %s 0x%08lx%08lx\n",
102 (unsigned long) addr
,
104 (unsigned long) V4_8 (val
, 0),
105 (unsigned long) V4_8 (val
, 1));
108 trace_printf (CPU_STATE (cpu
), cpu
,
109 "%s-%d %s:0x%08lx %s 0x%08lx\n",
113 (unsigned long) addr
,
115 (unsigned long) val
);
118 trace_printf (CPU_STATE (cpu
), cpu
,
119 "%s-%d %s:0x%08lx %s 0x%04lx\n",
123 (unsigned long) addr
,
125 (unsigned long) val
);
128 trace_printf (CPU_STATE (cpu
), cpu
,
129 "%s-%d %s:0x%08lx %s 0x%02lx\n",
133 (unsigned long) addr
,
135 (unsigned long) val
);
141 /* TAGS: sim_core_read_aligned_1 sim_core_read_aligned_2 */
142 /* TAGS: sim_core_read_aligned_4 sim_core_read_aligned_8 */
143 /* TAGS: sim_core_read_aligned_16 */
146 INLINE_SIM_CORE(unsigned_M
)
147 sim_core_read_aligned_N(sim_cpu
*cpu
,
152 sim_cpu_core
*cpu_core
= CPU_CORE (cpu
);
153 sim_core_common
*core
= &cpu_core
->common
;
155 sim_core_mapping
*mapping
;
157 #if WITH_XOR_ENDIAN != 0
159 addr
= xaddr
^ cpu_core
->xor[(N
- 1) % WITH_XOR_ENDIAN
];
163 mapping
= sim_core_find_mapping (core
, map
, addr
, N
, read_transfer
, 1 /*abort*/, cpu
, cia
);
167 if (WITH_CALLBACK_MEMORY
&& mapping
->device
!= NULL
)
170 if (device_io_read_buffer (mapping
->device
, &data
, mapping
->space
, addr
, N
, CPU_STATE (cpu
), cpu
, cia
) != N
)
171 device_error (mapping
->device
, "internal error - %s - io_read_buffer should not fail",
172 XSTRING (sim_core_read_aligned_N
));
178 if (WITH_CALLBACK_MEMORY
&& mapping
->device
!= NULL
)
181 sim_cpu_hw_io_read_buffer (cpu
, cia
, mapping
->device
, &data
, mapping
->space
, addr
, N
);
186 val
= T2H_M (*(unsigned_M
*) sim_core_translate (mapping
, addr
));
189 PROFILE_COUNT_CORE (cpu
, addr
, N
, map
);
190 if (TRACE_P (cpu
, TRACE_CORE_IDX
))
191 sim_core_trace_M (cpu
, cia
, __LINE__
, read_transfer
, map
, addr
, val
, N
);
196 /* TAGS: sim_core_read_unaligned_1 sim_core_read_unaligned_2 */
197 /* TAGS: sim_core_read_unaligned_4 sim_core_read_unaligned_8 */
198 /* TAGS: sim_core_read_unaligned_16 */
200 #if (M == N && N > 1)
201 INLINE_SIM_CORE(unsigned_M
)
202 sim_core_read_unaligned_N(sim_cpu
*cpu
,
207 int alignment
= N
- 1;
208 /* if hardwired to forced alignment just do it */
209 if (WITH_ALIGNMENT
== FORCED_ALIGNMENT
)
210 return sim_core_read_aligned_N (cpu
, cia
, map
, addr
& ~alignment
);
211 else if ((addr
& alignment
) == 0)
212 return sim_core_read_aligned_N (cpu
, cia
, map
, addr
);
214 switch (CURRENT_ALIGNMENT
)
216 case STRICT_ALIGNMENT
:
217 SIM_CORE_SIGNAL (CPU_STATE (cpu
), cpu
, cia
, map
, N
, addr
,
218 read_transfer
, sim_core_unaligned_signal
);
219 case NONSTRICT_ALIGNMENT
:
222 if (sim_core_xor_read_buffer (CPU_STATE (cpu
), cpu
, map
, &val
, addr
, N
) != N
)
223 SIM_CORE_SIGNAL (CPU_STATE (cpu
), cpu
, cia
, map
, N
, addr
,
224 read_transfer
, sim_core_unaligned_signal
);
226 PROFILE_COUNT_CORE (cpu
, addr
, N
, map
);
227 if (TRACE_P (cpu
, TRACE_CORE_IDX
))
228 sim_core_trace_M (cpu
, cia
, __LINE__
, read_transfer
, map
, addr
, val
, N
);
231 case FORCED_ALIGNMENT
:
232 return sim_core_read_aligned_N (cpu
, cia
, map
, addr
& ~alignment
);
233 case MIXED_ALIGNMENT
:
234 sim_engine_abort (CPU_STATE (cpu
), cpu
, cia
,
235 "internal error - %s - mixed alignment",
236 XSTRING (sim_core_read_unaligned_N
));
238 sim_engine_abort (CPU_STATE (cpu
), cpu
, cia
,
239 "internal error - %s - bad switch",
240 XSTRING (sim_core_read_unaligned_N
));
241 /* to keep some compilers happy, we return a dummy */
242 return sim_core_dummy_M
;
247 /* TAGS: sim_core_read_misaligned_3 sim_core_read_misaligned_5 */
248 /* TAGS: sim_core_read_misaligned_6 sim_core_read_misaligned_7 */
251 INLINE_SIM_CORE(unsigned_M
)
252 sim_core_read_misaligned_N(sim_cpu
*cpu
,
258 if (sim_core_xor_read_buffer (CPU_STATE (cpu
), cpu
, map
, &val
, addr
, N
) != N
)
259 SIM_CORE_SIGNAL (CPU_STATE (cpu
), cpu
, cia
, map
, N
, addr
,
260 read_transfer
, sim_core_unaligned_signal
);
261 if (CURRENT_HOST_BYTE_ORDER
!= CURRENT_TARGET_BYTE_ORDER
)
263 if (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
)
265 PROFILE_COUNT_CORE (cpu
, addr
, N
, map
);
266 if (TRACE_P (cpu
, TRACE_CORE_IDX
))
267 sim_core_trace_M (cpu
, cia
, __LINE__
, read_transfer
, map
, addr
, val
, N
);
272 /* TAGS: sim_core_write_aligned_1 sim_core_write_aligned_2 */
273 /* TAGS: sim_core_write_aligned_4 sim_core_write_aligned_8 */
274 /* TAGS: sim_core_write_aligned_16 */
277 INLINE_SIM_CORE(void)
278 sim_core_write_aligned_N(sim_cpu
*cpu
,
284 sim_cpu_core
*cpu_core
= CPU_CORE (cpu
);
285 sim_core_common
*core
= &cpu_core
->common
;
286 sim_core_mapping
*mapping
;
288 #if WITH_XOR_ENDIAN != 0
290 addr
= xaddr
^ cpu_core
->xor[(N
- 1) % WITH_XOR_ENDIAN
];
294 mapping
= sim_core_find_mapping (core
, map
, addr
, N
, write_transfer
, 1 /*abort*/, cpu
, cia
);
298 if (WITH_CALLBACK_MEMORY
&& mapping
->device
!= NULL
)
300 unsigned_M data
= H2T_M (val
);
301 if (device_io_write_buffer (mapping
->device
, &data
, mapping
->space
, addr
, N
, CPU_STATE (cpu
), cpu
, cia
) != N
)
302 device_error (mapping
->device
, "internal error - %s - io_write_buffer should not fail",
303 XSTRING (sim_core_write_aligned_N
));
308 if (WITH_CALLBACK_MEMORY
&& mapping
->device
!= NULL
)
310 unsigned_M data
= H2T_M (val
);
311 sim_cpu_hw_io_write_buffer (cpu
, cia
, mapping
->device
, &data
, mapping
->space
, addr
, N
);
315 *(unsigned_M
*) sim_core_translate (mapping
, addr
) = H2T_M (val
);
318 PROFILE_COUNT_CORE (cpu
, addr
, N
, map
);
319 if (TRACE_P (cpu
, TRACE_CORE_IDX
))
320 sim_core_trace_M (cpu
, cia
, __LINE__
, write_transfer
, map
, addr
, val
, N
);
324 /* TAGS: sim_core_write_unaligned_1 sim_core_write_unaligned_2 */
325 /* TAGS: sim_core_write_unaligned_4 sim_core_write_unaligned_8 */
326 /* TAGS: sim_core_write_unaligned_16 */
328 #if (M == N && N > 1)
329 INLINE_SIM_CORE(void)
330 sim_core_write_unaligned_N(sim_cpu
*cpu
,
336 int alignment
= N
- 1;
337 /* if hardwired to forced alignment just do it */
338 if (WITH_ALIGNMENT
== FORCED_ALIGNMENT
)
339 sim_core_write_aligned_N (cpu
, cia
, map
, addr
& ~alignment
, val
);
340 else if ((addr
& alignment
) == 0)
341 sim_core_write_aligned_N (cpu
, cia
, map
, addr
, val
);
343 switch (CURRENT_ALIGNMENT
)
345 case STRICT_ALIGNMENT
:
346 SIM_CORE_SIGNAL (CPU_STATE (cpu
), cpu
, cia
, map
, N
, addr
,
347 write_transfer
, sim_core_unaligned_signal
);
349 case NONSTRICT_ALIGNMENT
:
351 unsigned_M data
= H2T_M (val
);
352 if (sim_core_xor_write_buffer (CPU_STATE (cpu
), cpu
, map
, &data
, addr
, N
) != N
)
353 SIM_CORE_SIGNAL (CPU_STATE (cpu
), cpu
, cia
, map
, N
, addr
,
354 write_transfer
, sim_core_unaligned_signal
);
355 PROFILE_COUNT_CORE (cpu
, addr
, N
, map
);
356 if (TRACE_P (cpu
, TRACE_CORE_IDX
))
357 sim_core_trace_M (cpu
, cia
, __LINE__
, write_transfer
, map
, addr
, val
, N
);
360 case FORCED_ALIGNMENT
:
361 sim_core_write_aligned_N (cpu
, cia
, map
, addr
& ~alignment
, val
);
363 case MIXED_ALIGNMENT
:
364 sim_engine_abort (CPU_STATE (cpu
), cpu
, cia
,
365 "internal error - %s - mixed alignment",
366 XSTRING (sim_core_write_unaligned_N
));
369 sim_engine_abort (CPU_STATE (cpu
), cpu
, cia
,
370 "internal error - %s - bad switch",
371 XSTRING (sim_core_write_unaligned_N
));
377 /* TAGS: sim_core_write_misaligned_3 sim_core_write_misaligned_5 */
378 /* TAGS: sim_core_write_misaligned_6 sim_core_write_misaligned_7 */
381 INLINE_SIM_CORE(void)
382 sim_core_write_misaligned_N(sim_cpu
*cpu
,
388 unsigned_M data
= val
;
389 if (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
)
390 data
<<= (M
- N
) * 8;
391 if (CURRENT_HOST_BYTE_ORDER
!= CURRENT_TARGET_BYTE_ORDER
)
392 data
= SWAP_M (data
);
393 if (sim_core_xor_write_buffer (CPU_STATE (cpu
), cpu
, map
, &data
, addr
, N
) != N
)
394 SIM_CORE_SIGNAL (CPU_STATE (cpu
), cpu
, cia
, map
, N
, addr
,
395 write_transfer
, sim_core_unaligned_signal
);
396 PROFILE_COUNT_CORE (cpu
, addr
, N
, map
);
397 if (TRACE_P (cpu
, TRACE_CORE_IDX
))
398 sim_core_trace_M (cpu
, cia
, __LINE__
, write_transfer
, map
, addr
, val
, N
);
403 /* NOTE: see start of file for #define of these macros */
408 #undef sim_core_read_aligned_N
409 #undef sim_core_read_unaligned_N
410 #undef sim_core_read_misaligned_N
411 #undef sim_core_write_aligned_N
412 #undef sim_core_write_unaligned_N
413 #undef sim_core_write_misaligned_N
414 #undef sim_core_trace_M
415 #undef sim_core_dummy_M