1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb/callback.h"
27 #include "opcode/cr16.h"
30 #define DEBUG_TRACE 0x00000001
31 #define DEBUG_VALUES 0x00000002
32 #define DEBUG_LINE_NUMBER 0x00000004
33 #define DEBUG_MEMSIZE 0x00000008
34 #define DEBUG_INSTRUCTION 0x00000010
35 #define DEBUG_TRAP 0x00000020
36 #define DEBUG_MEMORY 0x00000040
39 #define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
42 extern int cr16_debug
;
44 #include "gdb/remote-sim.h"
45 #include "sim-config.h"
46 #include "sim-types.h"
48 typedef unsigned8 uint8
;
50 typedef unsigned16 uint16
;
51 typedef signed16 int16
;
52 typedef unsigned32 uint32
;
53 typedef signed32 int32
;
54 typedef unsigned64 uint64
;
55 typedef signed64 int64
;
57 /* FIXME: CR16 defines */
59 typedef uint32 creg_t
;
71 operand_desc operands
[4];
76 INS_UNKNOWN
, /* unknown instruction */
89 extern unsigned long ins_type_counters
[ (int)INS_MAX
];
95 /* Write-back slots */
104 union slot_data data
;
105 union slot_data mask
;
110 #define SLOT (State.slot)
111 #define SLOT_NR (State.slot_nr)
112 #define SLOT_PEND_MASK(DEST, MSK, VAL) \
115 SLOT[SLOT_NR].dest = &(DEST); \
116 SLOT[SLOT_NR].size = sizeof (DEST); \
117 switch (sizeof (DEST)) \
120 SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
121 SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
124 SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
125 SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
128 SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
129 SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
132 SLOT_NR = (SLOT_NR + 1); \
135 #define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
136 #define SLOT_DISCARD() (SLOT_NR = 0)
137 #define SLOT_FLUSH() \
141 for (i = 0; i < SLOT_NR; i++) \
143 switch (SLOT[i].size) \
146 *(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \
147 *(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \
150 *(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \
151 *(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \
154 *(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \
155 *(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \
162 #define SLOT_DUMP() \
166 for (i = 0; i < SLOT_NR; i++) \
168 switch (SLOT[i].size) \
171 printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \
172 (long) SLOT[i].dest, \
173 (unsigned) SLOT[i].mask._1, \
174 (unsigned) SLOT[i].data._1); \
177 printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \
178 (long) SLOT[i].dest, \
179 (unsigned) SLOT[i].mask._2, \
180 (unsigned) SLOT[i].data._2); \
183 printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \
184 (long) SLOT[i].dest, \
185 (unsigned) SLOT[i].mask._4, \
186 (unsigned) SLOT[i].data._4); \
189 printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \
190 (long) SLOT[i].dest, \
191 (unsigned) (SLOT[i].mask._8 >> 32), \
192 (unsigned) SLOT[i].mask._8, \
193 (unsigned) (SLOT[i].data._8 >> 32), \
194 (unsigned) SLOT[i].data._8); \
201 /* cr16 memory: There are three separate cr16 memory regions IMEM,
202 UMEM and DMEM. The IMEM and DMEM are further broken down into
203 blocks (very like VM pages). */
207 IMAP_BLOCK_SIZE
= 0x2000000,
208 DMAP_BLOCK_SIZE
= 0x4000000
211 /* Implement the three memory regions using sparse arrays. Allocate
212 memory using ``segments''. A segment must be at least as large as
213 a BLOCK - ensures that an access that doesn't cross a block
214 boundary can't cross a segment boundary */
218 SEGMENT_SIZE
= 0x2000000, /* 128KB - MAX(IMAP_BLOCK_SIZE,DMAP_BLOCK_SIZE) */
219 IMEM_SEGMENTS
= 8, /* 1MB */
220 DMEM_SEGMENTS
= 8, /* 1MB */
221 UMEM_SEGMENTS
= 128 /* 16MB */
226 uint8
*insn
[IMEM_SEGMENTS
];
227 uint8
*data
[DMEM_SEGMENTS
];
228 uint8
*unif
[UMEM_SEGMENTS
];
234 creg_t regs
[16]; /* general-purpose registers */
235 #define GPR(N) (State.regs[(N)] + 0)
236 #define SET_GPR(N,VAL) (State.regs[(N)] = (VAL))
240 ((((uint16) State.regs[(N) + 1]) << 16) | (uint16) State.regs[(N)]) \
243 #define SET_GPR32(N,VAL) do { \
245 { SET_GPR (N + 1, (VAL) >> 16); SET_GPR (N, ((VAL) & 0xffff));} \
246 else { if ( N == 11) \
247 { SET_GPR (N + 1, ((GPR32 (12)) & 0xffff0000)|((VAL) >> 16)); \
248 SET_GPR (N, ((VAL) & 0xffff));} \
249 else SET_GPR (N, (VAL));} \
252 creg_t cregs
[16]; /* control registers */
253 #define CREG(N) (State.cregs[(N)] + 0)
254 #define SET_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 0)
255 #define SET_HW_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 1)
257 reg_t sp
[2]; /* holding area for SPI(0)/SPU(1) */
258 #define HELD_SP(N) (State.sp[(N)] + 0)
259 #define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
262 struct slot slot
[NR_SLOTS
];
274 /* NOTE: everything below this line is not reset by
275 sim_create_inferior() */
277 struct cr16_memory mem
;
279 enum _ins_type ins_type
;
284 extern host_callback
*cr16_callback
;
286 extern uint32 sign_flag
;
287 extern struct simops Simops
[];
288 extern asection
*text
;
289 extern bfd_vma text_start
;
290 extern bfd_vma text_end
;
291 extern bfd
*prog_bfd
;
322 #define PSR CREG (PSR_CR)
323 #define SET_PSR(VAL) SET_CREG (PSR_CR, (VAL))
324 #define SET_HW_PSR(VAL) SET_HW_CREG (PSR_CR, (VAL))
325 #define SET_PSR_BIT(MASK,VAL) move_to_cr (PSR_CR, ~((creg_t) MASK), (VAL) ? (MASK) : 0, 1)
327 #define PSR_SM ((PSR & PSR_SM_BIT) != 0)
328 #define SET_PSR_SM(VAL) SET_PSR_BIT (PSR_SM_BIT, (VAL))
330 #define PSR_I ((PSR & PSR_I_BIT) != 0)
331 #define SET_PSR_I(VAL) SET_PSR_BIT (PSR_I_BIT, (VAL))
333 #define PSR_DB ((PSR & PSR_DB_BIT) != 0)
334 #define SET_PSR_DB(VAL) SET_PSR_BIT (PSR_DB_BIT, (VAL))
336 #define PSR_P ((PSR & PSR_P_BIT) != 0)
337 #define SET_PSR_P(VAL) SET_PSR_BIT (PSR_P_BIT, (VAL))
339 #define PSR_E ((PSR & PSR_E_BIT) != 0)
340 #define SET_PSR_E(VAL) SET_PSR_BIT (PSR_E_BIT, (VAL))
342 #define PSR_N ((PSR & PSR_N_BIT) != 0)
343 #define SET_PSR_N(VAL) SET_PSR_BIT (PSR_N_BIT, (VAL))
345 #define PSR_Z ((PSR & PSR_Z_BIT) != 0)
346 #define SET_PSR_Z(VAL) SET_PSR_BIT (PSR_Z_BIT, (VAL))
348 #define PSR_F ((PSR & PSR_F_BIT) != 0)
349 #define SET_PSR_F(VAL) SET_PSR_BIT (PSR_F_BIT, (VAL))
351 #define PSR_U ((PSR & PSR_U_BIT) != 0)
352 #define SET_PSR_U(VAL) SET_PSR_BIT (PSR_U_BIT, (VAL))
354 #define PSR_L ((PSR & PSR_L_BIT) != 0)
355 #define SET_PSR_L(VAL) SET_PSR_BIT (PSR_L_BIT, (VAL))
357 #define PSR_T ((PSR & PSR_T_BIT) != 0)
358 #define SET_PSR_T(VAL) SET_PSR_BIT (PSR_T_BIT, (VAL))
360 #define PSR_C ((PSR & PSR_C_BIT) != 0)
361 #define SET_PSR_C(VAL) SET_PSR_BIT (PSR_C_BIT, (VAL))
363 /* See simopsc.:move_to_cr() for registers that can not be read-from
364 or assigned-to directly */
366 #define PC CREG (PC_CR)
367 #define SET_PC(VAL) SET_CREG (PC_CR, (VAL))
368 //#define SET_PC(VAL) (State.cregs[PC_CR] = (VAL))
370 #define BPSR CREG (BPSR_CR)
371 #define SET_BPSR(VAL) SET_CREG (BPSR_CR, (VAL))
373 #define BPC CREG (BPC_CR)
374 #define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))
376 #define DPSR CREG (DPSR_CR)
377 #define SET_DPSR(VAL) SET_CREG (DPSR_CR, (VAL))
379 #define DPC CREG (DPC_CR)
380 #define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))
382 #define RPT_C CREG (RPT_C_CR)
383 #define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))
385 #define RPT_S CREG (RPT_S_CR)
386 #define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))
388 #define RPT_E CREG (RPT_E_CR)
389 #define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))
391 #define MOD_S CREG (MOD_S_CR)
392 #define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))
394 #define MOD_E CREG (MOD_E_CR)
395 #define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))
397 #define IBA CREG (IBA_CR)
398 #define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))
401 #define SIG_CR16_STOP -1
402 #define SIG_CR16_EXIT -2
403 #define SIG_CR16_BUS -3
404 #define SIG_CR16_IAD -4
406 #define SEXT3(x) ((((x)&0x7)^(~3))+4)
408 /* sign-extend a 4-bit number */
409 #define SEXT4(x) ((((x)&0xf)^(~7))+8)
411 /* sign-extend an 8-bit number */
412 #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
414 /* sign-extend a 16-bit number */
415 #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
417 /* sign-extend a 24-bit number */
418 #define SEXT24(x) ((((x)&0xffffff)^(~0x7fffff))+0x800000)
420 /* sign-extend a 32-bit number */
421 #define SEXT32(x) ((((x)&0xffffffff)^(~0x7fffffff))+0x80000000)
423 extern uint8
*dmem_addr (uint32 offset
);
424 extern uint8
*imem_addr
PARAMS ((uint32
));
425 extern bfd_vma decode_pc
PARAMS ((void));
427 #define RB(x) (*(dmem_addr(x)))
428 #define SB(addr,data) ( RB(addr) = (data & 0xff))
430 #if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
431 #define ENDIAN_INLINE static __inline__
436 extern uint32 get_longword
PARAMS ((uint8
*));
437 extern uint16 get_word
PARAMS ((uint8
*));
438 extern int64 get_longlong
PARAMS ((uint8
*));
439 extern void write_word
PARAMS ((uint8
*addr
, uint16 data
));
440 extern void write_longword
PARAMS ((uint8
*addr
, uint32 data
));
441 extern void write_longlong
PARAMS ((uint8
*addr
, int64 data
));
444 #define SW(addr,data) write_word(dmem_addr(addr),data)
445 #define RW(x) get_word(dmem_addr(x))
446 #define SLW(addr,data) write_longword(dmem_addr(addr),data)
447 #define RLW(x) get_longword(dmem_addr(x))
448 #define READ_16(x) get_word(x)
449 #define WRITE_16(addr,data) write_word(addr,data)
450 #define READ_64(x) get_longlong(x)
451 #define WRITE_64(addr,data) write_longlong(addr,data)
453 #define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0)
455 #define RIE_VECTOR_START 0xffc2
456 #define AE_VECTOR_START 0xffc3
457 #define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */
458 #define DBT_VECTOR_START 0xffd4
459 #define SDBT_VECTOR_START 0xffd5
461 #define INT_VECTOR_START 0xFFFE00 /*maskable interrupt - mapped to ICU */
462 #define NMI_VECTOR_START 0xFFFF00 /*non-maskable interrupt;for observability*/
463 #define ISE_VECTOR_START 0xFFFC00 /*in-system emulation trap */
464 #define ADBG_VECTOR_START 0xFFFC02 /*alternate debug trap */
465 #define ATRC_VECTOR_START 0xFFFC0C /*alternate trace trap */
466 #define ABPT_VECTOR_START 0xFFFC0E /*alternate break point trap */
469 /* Scedule a store of VAL into cr[CR]. MASK indicates the bits in
470 cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) |
471 (VAL & ~MASK)). In addition, unless PSR_HW_P, a VAL intended for
472 PSR is masked for zero bits. */
474 extern creg_t
move_to_cr (int cr
, creg_t mask
, creg_t val
, int psw_hw_p
);
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