sim/cr16/interp.c

   1 /* Simulation code for the CR16 processor.
   2    Copyright (C) 2008-2015 Free Software Foundation, Inc.
   3    Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
   4
   5    This file is part of GDB, the GNU debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program. If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include <inttypes.h>
  22 #include <signal.h>
  23 #include <stdlib.h>
  24 #include <string.h>
  25 #include "bfd.h"
  26 #include "gdb/callback.h"
  27 #include "gdb/remote-sim.h"
  28
  29 #include "sim-main.h"
  30 #include "sim-options.h"
  31
  32 #include "gdb/sim-cr16.h"
  33 #include "gdb/signals.h"
  34 #include "opcode/cr16.h"
  35
  36 int cr16_debug;
  37
  38 host_callback *cr16_callback;
  39
  40 uint32 OP[4];
  41 uint32 sign_flag;
  42
  43 static struct hash_entry *lookup_hash (uint64 ins, int size);
  44 static void get_operands (operand_desc *s, uint64 mcode, int isize, int nops);
  45 extern void sim_set_profile (int n);
  46 extern void sim_set_profile_size (int n);
  47 static INLINE uint8 *map_memory (unsigned phys_addr);
  48
  49 #define MAX_HASH  16
  50
  51 struct hash_entry
  52 {
  53   struct hash_entry *next;
  54   uint32 opcode;
  55   uint32 mask;
  56   int format;
  57   int size;
  58   struct simops *ops;
  59 };
  60
  61 struct hash_entry hash_table[MAX_HASH+1];
  62
  63 INLINE static long
  64 hash(unsigned long long insn, int format)
  65 {
  66   unsigned int i = 4, tmp;
  67   if (format)
  68     {
  69       while ((insn >> i) != 0) i +=4;
  70
  71       return ((insn >> (i-4)) & 0xf); /* Use last 4 bits as hask key.  */
  72     }
  73   return ((insn & 0xF)); /* Use last 4 bits as hask key.  */
  74 }
  75
  76
  77 INLINE static struct hash_entry *
  78 lookup_hash (uint64 ins, int size)
  79 {
  80   uint32 mask;
  81   struct hash_entry *h;
  82
  83   h = &hash_table[hash(ins,1)];
  84
  85
  86   mask = (((1 << (32 - h->mask)) -1) << h->mask);
  87
  88  /* Adjuest mask for branch with 2 word instructions.  */
  89   if ((h->ops->mnimonic != NULL) &&
  90       ((streq(h->ops->mnimonic,"b") && h->size == 2)))
  91     mask = 0xff0f0000;
  92
  93
  94   while ((ins & mask) != (BIN(h->opcode, h->mask)))
  95     {
  96       if (h->next == NULL)
  97         {
  98           State.exception = SIGILL;
  99           State.pc_changed = 1; /* Don't increment the PC. */
 100           return NULL;
 101         }
 102       h = h->next;
 103
 104       mask = (((1 << (32 - h->mask)) -1) << h->mask);
 105      /* Adjuest mask for branch with 2 word instructions.  */
 106      if ((streq(h->ops->mnimonic,"b")) && h->size == 2)
 107        mask = 0xff0f0000;
 108
 109      }
 110    return (h);
 111 }
 112
 113 INLINE static void
 114 get_operands (operand_desc *s, uint64 ins, int isize, int nops)
 115 {
 116   uint32 i, opn = 0, start_bit = 0, op_type = 0;
 117   int32 op_size = 0, mask = 0;
 118
 119   if (isize == 1) /* Trunkcate the extra 16 bits of INS.  */
 120     ins = ins >> 16;
 121
 122   for (i=0; i < 4; ++i,++opn)
 123     {
 124       if (s[opn].op_type == dummy) break;
 125
 126       op_type = s[opn].op_type;
 127       start_bit = s[opn].shift;
 128       op_size = cr16_optab[op_type].bit_size;
 129
 130       switch (op_type)
 131         {
 132           case imm3: case imm4: case imm5: case imm6:
 133             {
 134              if (isize == 1)
 135                OP[i] = ((ins >> 4) & ((1 << op_size) -1));
 136              else
 137                OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));
 138
 139              if (OP[i] & ((long)1 << (op_size -1)))
 140                {
 141                  sign_flag = 1;
 142                  OP[i] = ~(OP[i]) + 1;
 143                }
 144              OP[i] = (unsigned long int)(OP[i] & (((long)1 << op_size) -1));
 145             }
 146             break;
 147
 148           case uimm3: case uimm3_1: case uimm4_1:
 149              switch (isize)
 150                {
 151               case 1:
 152                OP[i] = ((ins >> 4) & ((1 << op_size) -1)); break;
 153               case 2:
 154                OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));break;
 155               default: /* for case 3.  */
 156                OP[i] = ((ins >> (16 + start_bit)) & ((1 << op_size) -1)); break;
 157                break;
 158                }
 159             break;
 160
 161           case uimm4:
 162             switch (isize)
 163               {
 164               case 1:
 165                  if (start_bit == 20)
 166                    OP[i] = ((ins >> 4) & ((1 << op_size) -1));
 167                  else
 168                    OP[i] = (ins & ((1 << op_size) -1));
 169                  break;
 170               case 2:
 171                  OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
 172                  break;
 173               case 3:
 174                  OP[i] = ((ins >> (start_bit + 16)) & ((1 << op_size) -1));
 175                  break;
 176               default:
 177                  OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
 178                  break;
 179               }
 180             break;
 181
 182           case imm16: case uimm16:
 183             OP[i] = ins & 0xFFFF;
 184             break;
 185
 186           case uimm20: case imm20:
 187             OP[i] = ins & (((long)1 << op_size) - 1);
 188             break;
 189
 190           case imm32: case uimm32:
 191             OP[i] = ins & 0xFFFFFFFF;
 192             break;
 193
 194           case uimm5: break; /*NOT USED.  */
 195             OP[i] = ins & ((1 << op_size) - 1); break;
 196
 197           case disps5:
 198             OP[i] = (ins >> 4) & ((1 << 4) - 1);
 199             OP[i] = (OP[i] * 2) + 2;
 200             if (OP[i] & ((long)1 << 5))
 201               {
 202                 sign_flag = 1;
 203                 OP[i] = ~(OP[i]) + 1;
 204                 OP[i] = (unsigned long int)(OP[i] & 0x1F);
 205               }
 206             break;
 207
 208           case dispe9:
 209             OP[i] = ((((ins >> 8) & 0xf) << 4) | (ins & 0xf));
 210             OP[i] <<= 1;
 211             if (OP[i] & ((long)1 << 8))
 212               {
 213                 sign_flag = 1;
 214                 OP[i] = ~(OP[i]) + 1;
 215                 OP[i] = (unsigned long int)(OP[i] & 0xFF);
 216               }
 217             break;
 218
 219           case disps17:
 220             OP[i] = (ins & 0xFFFF);
 221             if (OP[i] & 1)
 222               {
 223                 OP[i] = (OP[i] & 0xFFFE);
 224                 sign_flag = 1;
 225                 OP[i] = ~(OP[i]) + 1;
 226                 OP[i] = (unsigned long int)(OP[i] & 0xFFFF);
 227               }
 228             break;
 229
 230           case disps25:
 231             if (isize == 2)
 232               OP[i] = (ins & 0xFFFFFF);
 233             else
 234               OP[i] = (ins & 0xFFFF) | (((ins >> 24) & 0xf) << 16) |
 235                       (((ins >> 16) & 0xf) << 20);
 236
 237             if (OP[i] & 1)
 238               {
 239                 OP[i] = (OP[i] & 0xFFFFFE);
 240                 sign_flag = 1;
 241                 OP[i] = ~(OP[i]) + 1;
 242                 OP[i] = (unsigned long int)(OP[i] & 0xFFFFFF);
 243               }
 244             break;
 245
 246           case abs20:
 247             if (isize == 3)
 248               OP[i] = (ins) & 0xFFFFF;
 249             else
 250               OP[i] = (ins >> start_bit) & 0xFFFFF;
 251             break;
 252           case abs24:
 253             if (isize == 3)
 254               OP[i] = ((ins & 0xFFFF) | (((ins >> 16) & 0xf) << 20)
 255                        | (((ins >> 24) & 0xf) << 16));
 256             else
 257               OP[i] = (ins >> 16) & 0xFFFFFF;
 258             break;
 259
 260           case rra:
 261           case rbase: break; /* NOT USED.  */
 262           case rbase_disps20:  case rbase_dispe20:
 263           case rpbase_disps20: case rpindex_disps20:
 264             OP[i] = ((((ins >> 24)&0xf) << 16)|((ins) & 0xFFFF));
 265             OP[++i] = (ins >> 16) & 0xF;     /* get 4 bit for reg.  */
 266             break;
 267           case rpbase_disps0:
 268             OP[i] = 0;                       /* 4 bit disp const.  */
 269             OP[++i] = (ins) & 0xF;           /* get 4 bit for reg.  */
 270             break;
 271           case rpbase_dispe4:
 272             OP[i] = ((ins >> 8) & 0xF) * 2;  /* 4 bit disp const.   */
 273             OP[++i] = (ins) & 0xF;           /* get 4 bit for reg.  */
 274             break;
 275           case rpbase_disps4:
 276             OP[i] = ((ins >> 8) & 0xF);      /* 4 bit disp const.  */
 277             OP[++i] = (ins) & 0xF;           /* get 4 bit for reg.  */
 278             break;
 279           case rpbase_disps16:
 280             OP[i] = (ins) & 0xFFFF;
 281             OP[++i] = (ins >> 16) & 0xF;     /* get 4 bit for reg.  */
 282             break;
 283           case rpindex_disps0:
 284             OP[i] = 0;
 285             OP[++i] = (ins >> 4) & 0xF;      /* get 4 bit for reg.  */
 286             OP[++i] = (ins >> 8) & 0x1;      /* get 1 bit for index-reg.  */
 287             break;
 288           case rpindex_disps14:
 289             OP[i] = (ins) & 0x3FFF;
 290             OP[++i] = (ins >> 14) & 0x1;     /* get 1 bit for index-reg.  */
 291             OP[++i] = (ins >> 16) & 0xF;     /* get 4 bit for reg.  */
 292           case rindex7_abs20:
 293           case rindex8_abs20:
 294             OP[i] = (ins) & 0xFFFFF;
 295             OP[++i] = (ins >> 24) & 0x1;     /* get 1 bit for index-reg.  */
 296             OP[++i] = (ins >> 20) & 0xF;     /* get 4 bit for reg.  */
 297             break;
 298           case regr: case regp: case pregr: case pregrp:
 299               switch(isize)
 300                 {
 301                   case 1:
 302                     if (start_bit == 20) OP[i] = (ins >> 4) & 0xF;
 303                     else if (start_bit == 16) OP[i] = ins & 0xF;
 304                     break;
 305                   case 2: OP[i] = (ins >>  start_bit) & 0xF; break;
 306                   case 3: OP[i] = (ins >> (start_bit + 16)) & 0xF; break;
 307                 }
 308                break;
 309           case cc:
 310             {
 311               if (isize == 1) OP[i] = (ins >> 4) & 0xF;
 312               else if (isize == 2)  OP[i] = (ins >> start_bit)  & 0xF;
 313               else  OP[i] = (ins >> (start_bit + 16)) & 0xF;
 314               break;
 315             }
 316           default: break;
 317         }
 318
 319       /* For ESC on uimm4_1 operand.  */
 320       if (op_type == uimm4_1)
 321         if (OP[i] == 9)
 322            OP[i] = -1;
 323
 324       /* For increment by 1.  */
 325       if ((op_type == pregr) || (op_type == pregrp))
 326           OP[i] += 1;
 327    }
 328   /* FIXME: for tracing, update values that need to be updated each
 329             instruction decode cycle */
 330   State.trace.psw = PSR;
 331 }
 332
 333 static int
 334 do_run (SIM_DESC sd, uint64 mcode)
 335 {
 336   host_callback *cr16_callback = STATE_CALLBACK (sd);
 337   struct simops *s= Simops;
 338   struct hash_entry *h;
 339   char func[12]="\0";
 340   uint8 *iaddr;
 341 #ifdef DEBUG
 342   if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
 343     (*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", mcode);
 344 #endif
 345
 346    h =  lookup_hash(mcode, 1);
 347
 348   if ((h == NULL) || (h->opcode == 0))
 349     return 0;
 350
 351    if (h->size == 3)
 352     {
 353       iaddr = imem_addr ((uint32)PC + 2);
 354        mcode = (mcode << 16) | get_longword( iaddr );
 355     }
 356
 357   /* Re-set OP list.  */
 358   OP[0] = OP[1] = OP[2] = OP[3] = sign_flag = 0;
 359
 360   /* for push/pop/pushrtn with RA instructions. */
 361   if ((h->format & REG_LIST) && (mcode & 0x800000))
 362     OP[2] = 1; /* Set 1 for RA operand.  */
 363
 364   /* numops == 0 means, no operands.  */
 365   if (((h->ops) != NULL) && (((h->ops)->numops) != 0))
 366     get_operands ((h->ops)->operands, mcode, h->size, (h->ops)->numops);
 367
 368   //State.ins_type = h->flags;
 369
 370   (h->ops->func)();
 371
 372   return h->size;
 373 }
 374
 375 static void
 376 sim_size (int power)
 377 {
 378   int i;
 379   for (i = 0; i < IMEM_SEGMENTS; i++)
 380     {
 381       if (State.mem.insn[i])
 382         free (State.mem.insn[i]);
 383     }
 384   for (i = 0; i < DMEM_SEGMENTS; i++)
 385     {
 386       if (State.mem.data[i])
 387         free (State.mem.data[i]);
 388     }
 389   for (i = 0; i < UMEM_SEGMENTS; i++)
 390     {
 391       if (State.mem.unif[i])
 392         free (State.mem.unif[i]);
 393     }
 394   /* Always allocate dmem segment 0.  This contains the IMAP and DMAP
 395      registers. */
 396   State.mem.data[0] = calloc (1, SEGMENT_SIZE);
 397 }
 398
 399 /* For tracing - leave info on last access around. */
 400 static char *last_segname = "invalid";
 401 static char *last_from = "invalid";
 402 static char *last_to = "invalid";
 403
 404 enum
 405   {
 406     IMAP0_OFFSET = 0xff00,
 407     DMAP0_OFFSET = 0xff08,
 408     DMAP2_SHADDOW = 0xff04,
 409     DMAP2_OFFSET = 0xff0c
 410   };
 411
 412 static unsigned long
 413 dmap_register (void *regcache, int reg_nr)
 414 {
 415   uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
 416                            + DMAP0_OFFSET + 2 * reg_nr);
 417   return READ_16 (raw);
 418 }
 419
 420 static unsigned long
 421 imap_register (void *regcache, int reg_nr)
 422 {
 423   uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
 424                            + IMAP0_OFFSET + 2 * reg_nr);
 425   return READ_16 (raw);
 426 }
 427
 428 /* Given a virtual address in the DMAP address space, translate it
 429    into a physical address. */
 430
 431 unsigned long
 432 sim_cr16_translate_dmap_addr (unsigned long offset,
 433                               int nr_bytes,
 434                               unsigned long *phys,
 435                               void *regcache,
 436                               unsigned long (*dmap_register) (void *regcache,
 437                                                               int reg_nr))
 438 {
 439   short map;
 440   int regno;
 441   last_from = "logical-data";
 442   if (offset >= DMAP_BLOCK_SIZE * SIM_CR16_NR_DMAP_REGS)
 443     {
 444       /* Logical address out side of data segments, not supported */
 445       return 0;
 446     }
 447   regno = (offset / DMAP_BLOCK_SIZE);
 448   offset = (offset % DMAP_BLOCK_SIZE);
 449
 450 #if 1
 451   if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE)
 452     {
 453       /* Don't cross a BLOCK boundary */
 454       nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE);
 455     }
 456   map = dmap_register (regcache, regno);
 457   if (regno == 3)
 458     {
 459       /* Always maps to data memory */
 460       int iospi = (offset / 0x1000) % 4;
 461       int iosp = (map >> (4 * (3 - iospi))) % 0x10;
 462       last_to = "io-space";
 463       *phys = (SIM_CR16_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset);
 464     }
 465   else
 466     {
 467       int sp = ((map & 0x3000) >> 12);
 468       int segno = (map & 0x3ff);
 469       switch (sp)
 470         {
 471         case 0: /* 00: Unified memory */
 472           *phys = SIM_CR16_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset;
 473           last_to = "unified";
 474           break;
 475         case 1: /* 01: Instruction Memory */
 476           *phys = SIM_CR16_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset;
 477           last_to = "chip-insn";
 478           break;
 479         case 2: /* 10: Internal data memory */
 480           *phys = SIM_CR16_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset;
 481           last_to = "chip-data";
 482           break;
 483         case 3: /* 11: Reserved */
 484           return 0;
 485         }
 486     }
 487 #endif
 488   return nr_bytes;
 489 }
 490
 491 /* Given a virtual address in the IMAP address space, translate it
 492    into a physical address. */
 493
 494 unsigned long
 495 sim_cr16_translate_imap_addr (unsigned long offset,
 496                               int nr_bytes,
 497                               unsigned long *phys,
 498                               void *regcache,
 499                               unsigned long (*imap_register) (void *regcache,
 500                                                               int reg_nr))
 501 {
 502   short map;
 503   int regno;
 504   int sp;
 505   int segno;
 506   last_from = "logical-insn";
 507   if (offset >= (IMAP_BLOCK_SIZE * SIM_CR16_NR_IMAP_REGS))
 508     {
 509       /* Logical address outside of IMAP segments, not supported */
 510       return 0;
 511     }
 512   regno = (offset / IMAP_BLOCK_SIZE);
 513   offset = (offset % IMAP_BLOCK_SIZE);
 514   if (offset + nr_bytes > IMAP_BLOCK_SIZE)
 515     {
 516       /* Don't cross a BLOCK boundary */
 517       nr_bytes = IMAP_BLOCK_SIZE - offset;
 518     }
 519   map = imap_register (regcache, regno);
 520   sp = (map & 0x3000) >> 12;
 521   segno = (map & 0x007f);
 522   switch (sp)
 523     {
 524     case 0: /* 00: unified memory */
 525       *phys = SIM_CR16_MEMORY_UNIFIED + (segno << 17) + offset;
 526       last_to = "unified";
 527       break;
 528     case 1: /* 01: instruction memory */
 529       *phys = SIM_CR16_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset;
 530       last_to = "chip-insn";
 531       break;
 532     case 2: /*10*/
 533       /* Reserved. */
 534       return 0;
 535     case 3: /* 11: for testing  - instruction memory */
 536       offset = (offset % 0x800);
 537       *phys = SIM_CR16_MEMORY_INSN + offset;
 538       if (offset + nr_bytes > 0x800)
 539         /* don't cross VM boundary */
 540         nr_bytes = 0x800 - offset;
 541       last_to = "test-insn";
 542       break;
 543     }
 544   return nr_bytes;
 545 }
 546
 547 unsigned long
 548 sim_cr16_translate_addr (unsigned long memaddr, int nr_bytes,
 549                          unsigned long *targ_addr, void *regcache,
 550                          unsigned long (*dmap_register) (void *regcache,
 551                                                          int reg_nr),
 552                          unsigned long (*imap_register) (void *regcache,
 553                                                          int reg_nr))
 554 {
 555   unsigned long phys;
 556   unsigned long seg;
 557   unsigned long off;
 558
 559   last_from = "unknown";
 560   last_to = "unknown";
 561
 562   seg = (memaddr >> 24);
 563   off = (memaddr & 0xffffffL);
 564
 565   switch (seg)
 566     {
 567     case 0x00:                        /* Physical unified memory */
 568       last_from = "phys-unified";
 569       last_to = "unified";
 570       phys = SIM_CR16_MEMORY_UNIFIED + off;
 571       if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
 572         nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
 573       break;
 574
 575     case 0x01:                        /* Physical instruction memory */
 576       last_from = "phys-insn";
 577       last_to = "chip-insn";
 578       phys = SIM_CR16_MEMORY_INSN + off;
 579       if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
 580         nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
 581       break;
 582
 583     case 0x02:                        /* Physical data memory segment */
 584       last_from = "phys-data";
 585       last_to = "chip-data";
 586       phys = SIM_CR16_MEMORY_DATA + off;
 587       if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
 588         nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
 589       break;
 590
 591     case 0x10:                        /* in logical data address segment */
 592       nr_bytes = sim_cr16_translate_dmap_addr (off, nr_bytes, &phys, regcache,
 593                                                dmap_register);
 594       break;
 595
 596     case 0x11:                        /* in logical instruction address segment */
 597       nr_bytes = sim_cr16_translate_imap_addr (off, nr_bytes, &phys, regcache,
 598                                                imap_register);
 599       break;
 600
 601     default:
 602       return 0;
 603     }
 604
 605   *targ_addr = phys;
 606   return nr_bytes;
 607 }
 608
 609 /* Return a pointer into the raw buffer designated by phys_addr.  It
 610    is assumed that the client has already ensured that the access
 611    isn't going to cross a segment boundary. */
 612
 613 uint8 *
 614 map_memory (unsigned phys_addr)
 615 {
 616   uint8 **memory;
 617   uint8 *raw;
 618   unsigned offset;
 619   int segment = ((phys_addr >> 24) & 0xff);
 620
 621   switch (segment)
 622     {
 623
 624     case 0x00: /* Unified memory */
 625       {
 626         memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS];
 627         last_segname = "umem";
 628         break;
 629       }
 630
 631     case 0x01: /* On-chip insn memory */
 632       {
 633         memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS];
 634         last_segname = "imem";
 635         break;
 636       }
 637
 638     case 0x02: /* On-chip data memory */
 639       {
 640         if ((phys_addr & 0xff00) == 0xff00)
 641           {
 642             phys_addr = (phys_addr & 0xffff);
 643             if (phys_addr == DMAP2_SHADDOW)
 644               {
 645                 phys_addr = DMAP2_OFFSET;
 646                 last_segname = "dmap";
 647               }
 648             else
 649               last_segname = "reg";
 650           }
 651         else
 652           last_segname = "dmem";
 653         memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS];
 654         break;
 655       }
 656
 657     default:
 658       /* OOPS! */
 659       last_segname = "scrap";
 660       return State.mem.fault;
 661     }
 662
 663   if (*memory == NULL)
 664     {
 665       *memory = calloc (1, SEGMENT_SIZE);
 666       if (*memory == NULL)
 667         {
 668           (*cr16_callback->printf_filtered) (cr16_callback, "Malloc failed.\n");
 669           return State.mem.fault;
 670         }
 671     }
 672
 673   offset = (phys_addr % SEGMENT_SIZE);
 674   raw = *memory + offset;
 675   return raw;
 676 }
 677
 678 /* Transfer data to/from simulated memory.  Since a bug in either the
 679    simulated program or in gdb or the simulator itself may cause a
 680    bogus address to be passed in, we need to do some sanity checking
 681    on addresses to make sure they are within bounds.  When an address
 682    fails the bounds check, treat it as a zero length read/write rather
 683    than aborting the entire run. */
 684
 685 static int
 686 xfer_mem (SIM_DESC sd, SIM_ADDR virt,
 687           unsigned char *buffer,
 688           int size,
 689           int write_p)
 690 {
 691   host_callback *cr16_callback = STATE_CALLBACK (sd);
 692   uint8 *memory;
 693   unsigned long phys;
 694   int phys_size;
 695   phys_size = sim_cr16_translate_addr (virt, size, &phys, NULL,
 696                                        dmap_register, imap_register);
 697   if (phys_size == 0)
 698     return 0;
 699
 700   memory = map_memory (phys);
 701
 702 #ifdef DEBUG
 703   if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
 704     {
 705       (*cr16_callback->printf_filtered)
 706         (cr16_callback,
 707          "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
 708              (write_p ? "write" : "read"),
 709          phys_size, virt, last_from,
 710          phys, last_to,
 711          (long) memory, last_segname);
 712     }
 713 #endif
 714
 715   if (write_p)
 716     {
 717       memcpy (memory, buffer, phys_size);
 718     }
 719   else
 720     {
 721       memcpy (buffer, memory, phys_size);
 722     }
 723
 724   return phys_size;
 725 }
 726
 727
 728 int
 729 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
 730 {
 731   /* FIXME: this should be performing a virtual transfer */
 732   return xfer_mem (sd, addr, buffer, size, 1);
 733 }
 734
 735 int
 736 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
 737 {
 738   /* FIXME: this should be performing a virtual transfer */
 739   return xfer_mem (sd, addr, buffer, size, 0);
 740 }
 741
 742 static void
 743 free_state (SIM_DESC sd)
 744 {
 745   if (STATE_MODULES (sd) != NULL)
 746     sim_module_uninstall (sd);
 747   sim_cpu_free_all (sd);
 748   sim_state_free (sd);
 749 }
 750
 751 SIM_DESC trace_sd = NULL;
 752
 753 SIM_DESC
 754 sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, struct bfd *abfd, char **argv)
 755 {
 756   struct simops *s;
 757   struct hash_entry *h;
 758   static int init_p = 0;
 759   char **p;
 760   int i;
 761   SIM_DESC sd = sim_state_alloc (kind, cb);
 762   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 763
 764   /* The cpu data is kept in a separately allocated chunk of memory.  */
 765   if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
 766     {
 767       free_state (sd);
 768       return 0;
 769     }
 770
 771   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
 772     {
 773       free_state (sd);
 774       return 0;
 775     }
 776
 777   /* getopt will print the error message so we just have to exit if this fails.
 778      FIXME: Hmmm...  in the case of gdb we need getopt to call
 779      print_filtered.  */
 780   if (sim_parse_args (sd, argv) != SIM_RC_OK)
 781     {
 782       free_state (sd);
 783       return 0;
 784     }
 785
 786   /* Check for/establish the a reference program image.  */
 787   if (sim_analyze_program (sd,
 788                            (STATE_PROG_ARGV (sd) != NULL
 789                             ? *STATE_PROG_ARGV (sd)
 790                             : NULL), abfd) != SIM_RC_OK)
 791     {
 792       free_state (sd);
 793       return 0;
 794     }
 795
 796   /* Configure/verify the target byte order and other runtime
 797      configuration options.  */
 798   if (sim_config (sd) != SIM_RC_OK)
 799     {
 800       sim_module_uninstall (sd);
 801       return 0;
 802     }
 803
 804   if (sim_post_argv_init (sd) != SIM_RC_OK)
 805     {
 806       /* Uninstall the modules to avoid memory leaks,
 807          file descriptor leaks, etc.  */
 808       sim_module_uninstall (sd);
 809       return 0;
 810     }
 811
 812   trace_sd = sd;
 813   cr16_callback = cb;
 814
 815   /* put all the opcodes in the hash table.  */
 816   if (!init_p++)
 817     {
 818       for (s = Simops; s->func; s++)
 819         {
 820           switch(32 - s->mask)
 821             {
 822             case 0x4:
 823                h = &hash_table[hash(s->opcode, 0)];
 824                break;
 825
 826             case 0x7:
 827                if (((s->opcode << 1) >> 4) != 0)
 828                   h = &hash_table[hash((s->opcode << 1) >> 4, 0)];
 829                else
 830                   h = &hash_table[hash((s->opcode << 1), 0)];
 831                break;
 832
 833             case 0x8:
 834                if ((s->opcode >> 4) != 0)
 835                   h = &hash_table[hash(s->opcode >> 4, 0)];
 836                else
 837                   h = &hash_table[hash(s->opcode, 0)];
 838                break;
 839
 840             case 0x9:
 841                if (((s->opcode  >> 1) >> 4) != 0)
 842                  h = &hash_table[hash((s->opcode >>1) >> 4, 0)];
 843                else
 844                  h = &hash_table[hash((s->opcode >> 1), 0)];
 845                break;
 846
 847             case 0xa:
 848                if ((s->opcode >> 8) != 0)
 849                  h = &hash_table[hash(s->opcode >> 8, 0)];
 850                else if ((s->opcode >> 4) != 0)
 851                  h = &hash_table[hash(s->opcode >> 4, 0)];
 852                else
 853                  h = &hash_table[hash(s->opcode, 0)];
 854                break;
 855
 856             case 0xc:
 857                if ((s->opcode >> 8) != 0)
 858                  h = &hash_table[hash(s->opcode >> 8, 0)];
 859                else if ((s->opcode >> 4) != 0)
 860                  h = &hash_table[hash(s->opcode >> 4, 0)];
 861                else
 862                  h = &hash_table[hash(s->opcode, 0)];
 863                break;
 864
 865             case 0xd:
 866                if (((s->opcode >> 1) >> 8) != 0)
 867                  h = &hash_table[hash((s->opcode >>1) >> 8, 0)];
 868                else if (((s->opcode >> 1) >> 4) != 0)
 869                  h = &hash_table[hash((s->opcode >>1) >> 4, 0)];
 870                else
 871                  h = &hash_table[hash((s->opcode >>1), 0)];
 872                break;
 873
 874             case 0x10:
 875                if ((s->opcode >> 0xc) != 0)
 876                  h = &hash_table[hash(s->opcode >> 12, 0)];
 877                else if ((s->opcode >> 8) != 0)
 878                  h = &hash_table[hash(s->opcode >> 8, 0)];
 879                else if ((s->opcode >> 4) != 0)
 880                  h = &hash_table[hash(s->opcode >> 4, 0)];
 881                else
 882                  h = &hash_table[hash(s->opcode, 0)];
 883                break;
 884
 885             case 0x14:
 886                if ((s->opcode >> 16) != 0)
 887                  h = &hash_table[hash(s->opcode >> 16, 0)];
 888                else if ((s->opcode >> 12) != 0)
 889                  h = &hash_table[hash(s->opcode >> 12, 0)];
 890                else if ((s->opcode >> 8) != 0)
 891                  h = &hash_table[hash(s->opcode >> 8, 0)];
 892                else if ((s->opcode >> 4) != 0)
 893                  h = &hash_table[hash(s->opcode >> 4, 0)];
 894                else
 895                  h = &hash_table[hash(s->opcode, 0)];
 896                break;
 897             default:
 898               break;
 899             }
 900
 901           /* go to the last entry in the chain.  */
 902           while (h->next)
 903             h = h->next;
 904
 905           if (h->ops)
 906             {
 907               h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry));
 908               if (!h->next)
 909                 perror ("malloc failure");
 910
 911               h = h->next;
 912             }
 913           h->ops = s;
 914           h->mask = s->mask;
 915           h->opcode = s->opcode;
 916           h->format = s->format;
 917           h->size = s->size;
 918         }
 919     }
 920
 921   /* reset the processor state */
 922   if (!State.mem.data[0])
 923     sim_size (1);
 924   sim_create_inferior ((SIM_DESC) 1, NULL, NULL, NULL);
 925
 926   return sd;
 927 }
 928
 929
 930 void
 931 sim_close (SIM_DESC sd, int quitting)
 932 {
 933   /* Nothing to do.  */
 934 }
 935
 936 uint8 *
 937 dmem_addr (uint32 offset)
 938 {
 939   unsigned long phys;
 940   uint8 *mem;
 941   int phys_size;
 942
 943   /* Note: DMEM address range is 0..0x10000. Calling code can compute
 944      things like ``0xfffe + 0x0e60 == 0x10e5d''.  Since offset's type
 945      is uint16 this is modulo'ed onto 0x0e5d. */
 946
 947   phys_size = sim_cr16_translate_dmap_addr (offset, 1, &phys, NULL,
 948                                             dmap_register);
 949   if (phys_size == 0)
 950     {
 951       mem = State.mem.fault;
 952     }
 953   else
 954     mem = map_memory (phys);
 955 #ifdef DEBUG
 956   if ((cr16_debug & DEBUG_MEMORY))
 957     {
 958       (*cr16_callback->printf_filtered)
 959         (cr16_callback,
 960          "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
 961          offset, last_from,
 962          phys, phys_size, last_to,
 963          (long) mem, last_segname);
 964     }
 965 #endif
 966   return mem;
 967 }
 968
 969 uint8 *
 970 imem_addr (uint32 offset)
 971 {
 972   unsigned long phys;
 973   uint8 *mem;
 974   int phys_size = sim_cr16_translate_imap_addr (offset, 1, &phys, NULL,
 975                                                 imap_register);
 976   if (phys_size == 0)
 977     {
 978       return State.mem.fault;
 979     }
 980   mem = map_memory (phys);
 981 #ifdef DEBUG
 982   if ((cr16_debug & DEBUG_MEMORY))
 983     {
 984       (*cr16_callback->printf_filtered)
 985         (cr16_callback,
 986          "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
 987          offset, last_from,
 988          phys, phys_size, last_to,
 989          (long) mem, last_segname);
 990     }
 991 #endif
 992   return mem;
 993 }
 994
 995 static int stop_simulator = 0;
 996
 997 int
 998 sim_stop (SIM_DESC sd)
 999 {
1000   stop_simulator = 1;
1001   return 1;
1002 }
1003
1004
1005 /* Run (or resume) the program.  */
1006 void
1007 sim_resume (SIM_DESC sd, int step, int siggnal)
1008 {
1009   uint32 curr_ins_size = 0;
1010   uint64 mcode = 0;
1011   uint8 *iaddr;
1012
1013 #ifdef DEBUG
1014 //  (*cr16_callback->printf_filtered) (cr16_callback, "sim_resume (%d,%d)  PC=0x%x\n",step,siggnal,PC);
1015 #endif
1016
1017   State.exception = 0;
1018   if (step)
1019     sim_stop (sd);
1020
1021   switch (siggnal)
1022     {
1023     case 0:
1024       break;
1025 #ifdef SIGBUS
1026     case SIGBUS:
1027 #endif
1028     case SIGSEGV:
1029       SET_PC (PC);
1030       SET_PSR (PSR);
1031       JMP (AE_VECTOR_START);
1032       SLOT_FLUSH ();
1033       break;
1034     case SIGILL:
1035       SET_PC (PC);
1036       SET_PSR (PSR);
1037       SET_HW_PSR ((PSR & (PSR_C_BIT)));
1038       JMP (RIE_VECTOR_START);
1039       SLOT_FLUSH ();
1040       break;
1041     default:
1042       /* just ignore it */
1043       break;
1044     }
1045
1046   do
1047     {
1048       iaddr = imem_addr ((uint32)PC);
1049       if (iaddr == State.mem.fault)
1050         {
1051 #ifdef SIGBUS
1052           State.exception = SIGBUS;
1053 #else
1054           State.exception = SIGSEGV;
1055 #endif
1056           break;
1057         }
1058
1059       mcode = get_longword( iaddr );
1060
1061       State.pc_changed = 0;
1062
1063       curr_ins_size = do_run(sd, mcode);
1064
1065 #if CR16_DEBUG
1066  (*cr16_callback->printf_filtered) (cr16_callback, "INS: PC=0x%X, mcode=0x%X\n",PC,mcode);
1067 #endif
1068
1069       if (!State.pc_changed)
1070         {
1071           if (curr_ins_size == 0)
1072            {
1073              State.exception = SIG_CR16_EXIT; /* exit trap */
1074              break;
1075            }
1076           else
1077            SET_PC (PC + (curr_ins_size * 2)); /* For word instructions.  */
1078         }
1079
1080 #if 0
1081       /* Check for a breakpoint trap on this instruction.  This
1082          overrides any pending branches or loops */
1083       if (PSR_DB && PC == DBS)
1084         {
1085           SET_BPC (PC);
1086           SET_BPSR (PSR);
1087           SET_PC (SDBT_VECTOR_START);
1088         }
1089 #endif
1090
1091       /* Writeback all the DATA / PC changes */
1092       SLOT_FLUSH ();
1093     }
1094   while ( !State.exception && !stop_simulator);
1095
1096   if (step && !State.exception)
1097     State.exception = SIGTRAP;
1098 }
1099
1100 SIM_RC
1101 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
1102 {
1103   bfd_vma start_address;
1104
1105   /* reset all state information */
1106   memset (&State.regs, 0, (uintptr_t)&State.mem - (uintptr_t)&State.regs);
1107
1108   /* There was a hack here to copy the values of argc and argv into r0
1109      and r1.  The values were also saved into some high memory that
1110      won't be overwritten by the stack (0x7C00).  The reason for doing
1111      this was to allow the 'run' program to accept arguments.  Without
1112      the hack, this is not possible anymore.  If the simulator is run
1113      from the debugger, arguments cannot be passed in, so this makes
1114      no difference.  */
1115
1116   /* set PC */
1117   if (abfd != NULL)
1118     start_address = bfd_get_start_address (abfd);
1119   else
1120     start_address = 0x0;
1121 #ifdef DEBUG
1122   if (cr16_debug)
1123     (*cr16_callback->printf_filtered) (cr16_callback, "sim_create_inferior:  PC=0x%lx\n", (long) start_address);
1124 #endif
1125   SET_CREG (PC_CR, start_address);
1126
1127   SLOT_FLUSH ();
1128   return SIM_RC_OK;
1129 }
1130
1131 void
1132 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
1133 {
1134 /*   (*cr16_callback->printf_filtered) (cr16_callback, "sim_stop_reason:  PC=0x%x\n",PC<<2); */
1135
1136   switch (State.exception)
1137     {
1138     case SIG_CR16_STOP:                        /* stop instruction */
1139       *reason = sim_stopped;
1140       *sigrc = 0;
1141       break;
1142
1143     case SIG_CR16_EXIT:                        /* exit trap */
1144       *reason = sim_exited;
1145       *sigrc = GPR (2);
1146       break;
1147
1148     case SIG_CR16_BUS:
1149       *reason = sim_stopped;
1150       *sigrc = GDB_SIGNAL_BUS;
1151       break;
1152 //
1153 //    case SIG_CR16_IAD:
1154 //      *reason = sim_stopped;
1155 //      *sigrc = GDB_SIGNAL_IAD;
1156 //      break;
1157
1158     default:                                /* some signal */
1159       *reason = sim_stopped;
1160       if (stop_simulator && !State.exception)
1161         *sigrc = GDB_SIGNAL_INT;
1162       else
1163         *sigrc = State.exception;
1164       break;
1165     }
1166
1167   stop_simulator = 0;
1168 }
1169
1170 int
1171 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1172 {
1173   int size;
1174   switch ((enum sim_cr16_regs) rn)
1175     {
1176     case SIM_CR16_R0_REGNUM:
1177     case SIM_CR16_R1_REGNUM:
1178     case SIM_CR16_R2_REGNUM:
1179     case SIM_CR16_R3_REGNUM:
1180     case SIM_CR16_R4_REGNUM:
1181     case SIM_CR16_R5_REGNUM:
1182     case SIM_CR16_R6_REGNUM:
1183     case SIM_CR16_R7_REGNUM:
1184     case SIM_CR16_R8_REGNUM:
1185     case SIM_CR16_R9_REGNUM:
1186     case SIM_CR16_R10_REGNUM:
1187     case SIM_CR16_R11_REGNUM:
1188       WRITE_16 (memory, GPR (rn - SIM_CR16_R0_REGNUM));
1189       size = 2;
1190       break;
1191     case SIM_CR16_R12_REGNUM:
1192     case SIM_CR16_R13_REGNUM:
1193     case SIM_CR16_R14_REGNUM:
1194     case SIM_CR16_R15_REGNUM:
1195       //WRITE_32 (memory, GPR (rn - SIM_CR16_R0_REGNUM));
1196       write_longword (memory, GPR (rn - SIM_CR16_R0_REGNUM));
1197       size = 4;
1198       break;
1199     case SIM_CR16_PC_REGNUM:
1200     case SIM_CR16_ISP_REGNUM:
1201     case SIM_CR16_USP_REGNUM:
1202     case SIM_CR16_INTBASE_REGNUM:
1203     case SIM_CR16_PSR_REGNUM:
1204     case SIM_CR16_CFG_REGNUM:
1205     case SIM_CR16_DBS_REGNUM:
1206     case SIM_CR16_DCR_REGNUM:
1207     case SIM_CR16_DSR_REGNUM:
1208     case SIM_CR16_CAR0_REGNUM:
1209     case SIM_CR16_CAR1_REGNUM:
1210       //WRITE_32 (memory, CREG (rn - SIM_CR16_PC_REGNUM));
1211       write_longword (memory, CREG (rn - SIM_CR16_PC_REGNUM));
1212       size = 4;
1213       break;
1214     default:
1215       size = 0;
1216       break;
1217     }
1218   return size;
1219 }
1220
1221 int
1222 sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1223 {
1224   int size;
1225   switch ((enum sim_cr16_regs) rn)
1226     {
1227     case SIM_CR16_R0_REGNUM:
1228     case SIM_CR16_R1_REGNUM:
1229     case SIM_CR16_R2_REGNUM:
1230     case SIM_CR16_R3_REGNUM:
1231     case SIM_CR16_R4_REGNUM:
1232     case SIM_CR16_R5_REGNUM:
1233     case SIM_CR16_R6_REGNUM:
1234     case SIM_CR16_R7_REGNUM:
1235     case SIM_CR16_R8_REGNUM:
1236     case SIM_CR16_R9_REGNUM:
1237     case SIM_CR16_R10_REGNUM:
1238     case SIM_CR16_R11_REGNUM:
1239       SET_GPR (rn - SIM_CR16_R0_REGNUM, READ_16 (memory));
1240       size = 2;
1241       break;
1242     case SIM_CR16_R12_REGNUM:
1243     case SIM_CR16_R13_REGNUM:
1244     case SIM_CR16_R14_REGNUM:
1245     case SIM_CR16_R15_REGNUM:
1246       SET_GPR32 (rn - SIM_CR16_R0_REGNUM, get_longword (memory));
1247       size = 4;
1248       break;
1249     case SIM_CR16_PC_REGNUM:
1250     case SIM_CR16_ISP_REGNUM:
1251     case SIM_CR16_USP_REGNUM:
1252     case SIM_CR16_INTBASE_REGNUM:
1253     case SIM_CR16_PSR_REGNUM:
1254     case SIM_CR16_CFG_REGNUM:
1255     case SIM_CR16_DBS_REGNUM:
1256     case SIM_CR16_DCR_REGNUM:
1257     case SIM_CR16_DSR_REGNUM:
1258     case SIM_CR16_CAR0_REGNUM:
1259     case SIM_CR16_CAR1_REGNUM:
1260       SET_CREG (rn - SIM_CR16_PC_REGNUM, get_longword (memory));
1261       size = 4;
1262       break;
1263     default:
1264       size = 0;
1265       break;
1266     }
1267   SLOT_FLUSH ();
1268   return size;
1269 }