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[deliverable/binutils-gdb.git] / sim / cr16 / simops.c
1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008-2015 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20
21 #include "config.h"
22
23 #include <signal.h>
24 #include <errno.h>
25 #include <sys/types.h>
26 #include <sys/stat.h>
27 #ifdef HAVE_UNISTD_H
28 #include <unistd.h>
29 #endif
30 #ifdef HAVE_STRING_H
31 #include <string.h>
32 #endif
33 #ifdef HAVE_TIME_H
34 #include <time.h>
35 #endif
36 #ifdef HAVE_SYS_TIME_H
37 #include <sys/time.h>
38 #endif
39
40 #include "sim-main.h"
41 #include "simops.h"
42 #include "targ-vals.h"
43
44 #ifdef TARGET_SYS_utime
45 #include <utime.h>
46 #endif
47 #ifdef TARGET_SYS_wait
48 #include <sys/wait.h>
49 #endif
50
51 enum op_types {
52 OP_VOID,
53 OP_CONSTANT3,
54 OP_UCONSTANT3,
55 OP_CONSTANT4,
56 OP_CONSTANT4_1,
57 OP_CONSTANT5,
58 OP_CONSTANT6,
59 OP_CONSTANT16,
60 OP_UCONSTANT16,
61 OP_CONSTANT20,
62 OP_UCONSTANT20,
63 OP_CONSTANT32,
64 OP_UCONSTANT32,
65 OP_MEMREF,
66 OP_MEMREF2,
67 OP_MEMREF3,
68
69 OP_DISP5,
70 OP_DISP17,
71 OP_DISP25,
72 OP_DISPE9,
73 //OP_ABS20,
74 OP_ABS20_OUTPUT,
75 //OP_ABS24,
76 OP_ABS24_OUTPUT,
77
78 OP_R_BASE_DISPS16,
79 OP_R_BASE_DISP20,
80 OP_R_BASE_DISPS20,
81 OP_R_BASE_DISPE20,
82
83 OP_RP_BASE_DISPE0,
84 OP_RP_BASE_DISP4,
85 OP_RP_BASE_DISPE4,
86 OP_RP_BASE_DISP14,
87 OP_RP_BASE_DISP16,
88 OP_RP_BASE_DISP20,
89 OP_RP_BASE_DISPS20,
90 OP_RP_BASE_DISPE20,
91
92 OP_R_INDEX7_ABS20,
93 OP_R_INDEX8_ABS20,
94
95 OP_RP_INDEX_DISP0,
96 OP_RP_INDEX_DISP14,
97 OP_RP_INDEX_DISP20,
98 OP_RP_INDEX_DISPS20,
99
100 OP_REG,
101 OP_REGP,
102 OP_PROC_REG,
103 OP_PROC_REGP,
104 OP_COND,
105 OP_RA
106 };
107
108
109 enum {
110 PSR_MASK = (PSR_I_BIT
111 | PSR_P_BIT
112 | PSR_E_BIT
113 | PSR_N_BIT
114 | PSR_Z_BIT
115 | PSR_F_BIT
116 | PSR_U_BIT
117 | PSR_L_BIT
118 | PSR_T_BIT
119 | PSR_C_BIT),
120 /* The following bits in the PSR _can't_ be set by instructions such
121 as mvtc. */
122 PSR_HW_MASK = (PSR_MASK)
123 };
124
125 /* cond Code Condition True State
126 * EQ Equal Z flag is 1
127 * NE Not Equal Z flag is 0
128 * CS Carry Set C flag is 1
129 * CC Carry Clear C flag is 0
130 * HI Higher L flag is 1
131 * LS Lower or Same L flag is 0
132 * GT Greater Than N flag is 1
133 * LE Less Than or Equal To N flag is 0
134 * FS Flag Set F flag is 1
135 * FC Flag Clear F flag is 0
136 * LO Lower Z and L flags are 0
137 * HS Higher or Same Z or L flag is 1
138 * LT Less Than Z and N flags are 0
139 * GE Greater Than or Equal To Z or N flag is 1. */
140
141 static int cond_stat(int cc)
142 {
143 switch (cc)
144 {
145 case 0: return PSR_Z; break;
146 case 1: return !PSR_Z; break;
147 case 2: return PSR_C; break;
148 case 3: return !PSR_C; break;
149 case 4: return PSR_L; break;
150 case 5: return !PSR_L; break;
151 case 6: return PSR_N; break;
152 case 7: return !PSR_N; break;
153 case 8: return PSR_F; break;
154 case 9: return !PSR_F; break;
155 case 10: return !PSR_Z && !PSR_L; break;
156 case 11: return PSR_Z || PSR_L; break;
157 case 12: return !PSR_Z && !PSR_N; break;
158 case 13: return PSR_Z || PSR_N; break;
159 case 14: return 1; break; /*ALWAYS. */
160 default:
161 // case NEVER: return false; break;
162 //case NO_COND_CODE:
163 //panic("Shouldn't have NO_COND_CODE in an actual instruction!");
164 return 0; break;
165 }
166 return 0;
167 }
168
169
170 creg_t
171 move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, creg_t mask, creg_t val, int psw_hw_p)
172 {
173 /* A MASK bit is set when the corresponding bit in the CR should
174 be left alone. */
175 /* This assumes that (VAL & MASK) == 0. */
176 switch (cr)
177 {
178 case PSR_CR:
179 if (psw_hw_p)
180 val &= PSR_HW_MASK;
181 #if 0
182 else
183 val &= PSR_MASK;
184 (*cr16_callback->printf_filtered)
185 (cr16_callback,
186 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC);
187 State.exception = SIGILL;
188 #endif
189 /* keep an up-to-date psw around for tracing. */
190 State.trace.psw = (State.trace.psw & mask) | val;
191 break;
192 default:
193 break;
194 }
195 /* only issue an update if the register is being changed. */
196 if ((State.cregs[cr] & ~mask) != val)
197 SLOT_PEND_MASK (State.cregs[cr], mask, val);
198
199 return val;
200 }
201
202 #ifdef DEBUG
203 static void trace_input_func (SIM_DESC sd,
204 const char *name,
205 enum op_types in1,
206 enum op_types in2,
207 enum op_types in3);
208
209 #define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
210
211 #ifndef SIZE_INSTRUCTION
212 #define SIZE_INSTRUCTION 8
213 #endif
214
215 #ifndef SIZE_OPERANDS
216 #define SIZE_OPERANDS 18
217 #endif
218
219 #ifndef SIZE_VALUES
220 #define SIZE_VALUES 13
221 #endif
222
223 #ifndef SIZE_LOCATION
224 #define SIZE_LOCATION 20
225 #endif
226
227 #ifndef SIZE_PC
228 #define SIZE_PC 4
229 #endif
230
231 #ifndef SIZE_LINE_NUMBER
232 #define SIZE_LINE_NUMBER 2
233 #endif
234
235 static void
236 trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
237 {
238 char *comma;
239 enum op_types in[3];
240 int i;
241 char buf[1024];
242 char *p;
243 long tmp;
244 char *type;
245 const char *filename;
246 const char *functionname;
247 unsigned int linenumber;
248 bfd_vma byte_pc;
249
250 if ((cr16_debug & DEBUG_TRACE) == 0)
251 return;
252
253 switch (State.ins_type)
254 {
255 default:
256 case INS_UNKNOWN: type = " ?"; break;
257 }
258
259 if ((cr16_debug & DEBUG_LINE_NUMBER) == 0)
260 (*cr16_callback->printf_filtered) (cr16_callback,
261 "0x%.*x %s: %-*s ",
262 SIZE_PC, (unsigned)PC,
263 type,
264 SIZE_INSTRUCTION, name);
265
266 else
267 {
268 buf[0] = '\0';
269 byte_pc = PC;
270 if (STATE_TEXT_SECTION (sd)
271 && byte_pc >= STATE_TEXT_START (sd)
272 && byte_pc < STATE_TEXT_END (sd))
273 {
274 filename = (const char *)0;
275 functionname = (const char *)0;
276 linenumber = 0;
277 if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
278 STATE_TEXT_SECTION (sd),
279 (struct bfd_symbol **)0,
280 byte_pc - STATE_TEXT_START (sd),
281 &filename, &functionname, &linenumber))
282 {
283 p = buf;
284 if (linenumber)
285 {
286 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
287 p += strlen (p);
288 }
289 else
290 {
291 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
292 p += SIZE_LINE_NUMBER+2;
293 }
294
295 if (functionname)
296 {
297 sprintf (p, "%s ", functionname);
298 p += strlen (p);
299 }
300 else if (filename)
301 {
302 char *q = strrchr (filename, '/');
303 sprintf (p, "%s ", (q) ? q+1 : filename);
304 p += strlen (p);
305 }
306
307 if (*p == ' ')
308 *p = '\0';
309 }
310 }
311
312 (*cr16_callback->printf_filtered) (cr16_callback,
313 "0x%.*x %s: %-*.*s %-*s ",
314 SIZE_PC, (unsigned)PC,
315 type,
316 SIZE_LOCATION, SIZE_LOCATION, buf,
317 SIZE_INSTRUCTION, name);
318 }
319
320 in[0] = in1;
321 in[1] = in2;
322 in[2] = in3;
323 comma = "";
324 p = buf;
325 for (i = 0; i < 3; i++)
326 {
327 switch (in[i])
328 {
329 case OP_VOID:
330 break;
331
332 case OP_REG:
333 case OP_REGP:
334 sprintf (p, "%sr%d", comma, OP[i]);
335 p += strlen (p);
336 comma = ",";
337 break;
338
339 case OP_PROC_REG:
340 sprintf (p, "%scr%d", comma, OP[i]);
341 p += strlen (p);
342 comma = ",";
343 break;
344
345 case OP_CONSTANT16:
346 sprintf (p, "%s%d", comma, OP[i]);
347 p += strlen (p);
348 comma = ",";
349 break;
350
351 case OP_CONSTANT4:
352 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
353 p += strlen (p);
354 comma = ",";
355 break;
356
357 case OP_CONSTANT3:
358 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
359 p += strlen (p);
360 comma = ",";
361 break;
362
363 case OP_MEMREF:
364 sprintf (p, "%s@r%d", comma, OP[i]);
365 p += strlen (p);
366 comma = ",";
367 break;
368
369 case OP_MEMREF2:
370 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
371 p += strlen (p);
372 comma = ",";
373 break;
374
375 case OP_MEMREF3:
376 sprintf (p, "%s@%d", comma, OP[i]);
377 p += strlen (p);
378 comma = ",";
379 break;
380 }
381 }
382
383 if ((cr16_debug & DEBUG_VALUES) == 0)
384 {
385 *p++ = '\n';
386 *p = '\0';
387 (*cr16_callback->printf_filtered) (cr16_callback, "%s", buf);
388 }
389 else
390 {
391 *p = '\0';
392 (*cr16_callback->printf_filtered) (cr16_callback, "%-*s", SIZE_OPERANDS, buf);
393
394 p = buf;
395 for (i = 0; i < 3; i++)
396 {
397 buf[0] = '\0';
398 switch (in[i])
399 {
400 case OP_VOID:
401 (*cr16_callback->printf_filtered) (cr16_callback, "%*s", SIZE_VALUES, "");
402 break;
403
404 case OP_REG:
405 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
406 (uint16) GPR (OP[i]));
407 break;
408
409 case OP_REGP:
410 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
411 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
412 break;
413
414 case OP_PROC_REG:
415 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
416 (uint16) CREG (OP[i]));
417 break;
418
419 case OP_CONSTANT16:
420 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
421 (uint16)OP[i]);
422 break;
423
424 case OP_CONSTANT4:
425 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
426 (uint16)SEXT4(OP[i]));
427 break;
428
429 case OP_CONSTANT3:
430 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
431 (uint16)SEXT3(OP[i]));
432 break;
433
434 case OP_MEMREF2:
435 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
436 (uint16)OP[i]);
437 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
438 (uint16)GPR (OP[i + 1]));
439 i++;
440 break;
441 }
442 }
443 }
444
445 (*cr16_callback->flush_stdout) (cr16_callback);
446 }
447
448 static void
449 do_trace_output_flush (SIM_DESC sd)
450 {
451 (*cr16_callback->flush_stdout) (cr16_callback);
452 }
453
454 static void
455 do_trace_output_finish (SIM_DESC sd)
456 {
457 (*cr16_callback->printf_filtered) (cr16_callback,
458 " F0=%d F1=%d C=%d\n",
459 (State.trace.psw & PSR_F_BIT) != 0,
460 (State.trace.psw & PSR_F_BIT) != 0,
461 (State.trace.psw & PSR_C_BIT) != 0);
462 (*cr16_callback->flush_stdout) (cr16_callback);
463 }
464
465 #if 0
466 static void
467 trace_output_40 (SIM_DESC sd, uint64 val)
468 {
469 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
470 {
471 (*cr16_callback->printf_filtered) (cr16_callback,
472 " :: %*s0x%.2x%.8lx",
473 SIZE_VALUES - 12,
474 "",
475 ((int)(val >> 32) & 0xff),
476 ((unsigned long) val) & 0xffffffff);
477 do_trace_output_finish ();
478 }
479 }
480 #endif
481
482 static void
483 trace_output_32 (SIM_DESC sd, uint32 val)
484 {
485 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
486 {
487 (*cr16_callback->printf_filtered) (cr16_callback,
488 " :: %*s0x%.8x",
489 SIZE_VALUES - 10,
490 "",
491 (int) val);
492 do_trace_output_finish (sd);
493 }
494 }
495
496 static void
497 trace_output_16 (SIM_DESC sd, uint16 val)
498 {
499 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
500 {
501 (*cr16_callback->printf_filtered) (cr16_callback,
502 " :: %*s0x%.4x",
503 SIZE_VALUES - 6,
504 "",
505 (int) val);
506 do_trace_output_finish (sd);
507 }
508 }
509
510 static void
511 trace_output_void (SIM_DESC sd)
512 {
513 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
514 {
515 (*cr16_callback->printf_filtered) (cr16_callback, "\n");
516 do_trace_output_flush (sd);
517 }
518 }
519
520 static void
521 trace_output_flag (SIM_DESC sd)
522 {
523 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
524 {
525 (*cr16_callback->printf_filtered) (cr16_callback,
526 " :: %*s",
527 SIZE_VALUES,
528 "");
529 do_trace_output_finish (sd);
530 }
531 }
532
533
534
535
536 #else
537 #define trace_input(NAME, IN1, IN2, IN3)
538 #define trace_output(RESULT)
539 #endif
540
541 /* addub. */
542 void
543 OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
544 {
545 uint8 tmp;
546 uint8 a = OP[0] & 0xff;
547 uint16 b = (GPR (OP[1])) & 0xff;
548 trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
549 tmp = (a + b) & 0xff;
550 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
551 trace_output_16 (sd, tmp);
552 }
553
554 /* addub. */
555 void
556 OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
557 {
558 uint16 tmp;
559 uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
560 trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
561 tmp = (a + b) & 0xff;
562 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
563 trace_output_16 (sd, tmp);
564 }
565
566 /* addub. */
567 void
568 OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
569 {
570 uint8 a = (GPR (OP[0])) & 0xff;
571 uint8 b = (GPR (OP[1])) & 0xff;
572 uint16 tmp = (a + b) & 0xff;
573 trace_input ("addub", OP_REG, OP_REG, OP_VOID);
574 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
575 trace_output_16 (sd, tmp);
576 }
577
578 /* adduw. */
579 void
580 OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
581 {
582 uint16 a = OP[0];
583 uint16 b = GPR (OP[1]);
584 uint16 tmp = (a + b);
585 trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
586 SET_GPR (OP[1], tmp);
587 trace_output_16 (sd, tmp);
588 }
589
590 /* adduw. */
591 void
592 OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
593 {
594 uint16 a = OP[0];
595 uint16 b = GPR (OP[1]);
596 uint16 tmp = (a + b);
597 trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
598 SET_GPR (OP[1], tmp);
599 trace_output_16 (sd, tmp);
600 }
601
602 /* adduw. */
603 void
604 OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
605 {
606 uint16 a = GPR (OP[0]);
607 uint16 b = GPR (OP[1]);
608 uint16 tmp = (a + b);
609 trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
610 SET_GPR (OP[1], tmp);
611 trace_output_16 (sd, tmp);
612 }
613
614 /* addb. */
615 void
616 OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
617 {
618 uint8 a = OP[0];
619 uint8 b = (GPR (OP[1]) & 0xff);
620 uint16 tmp = (a + b) & 0xff;
621 trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
622 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
623 SET_PSR_C (tmp > 0xFF);
624 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
625 trace_output_16 (sd, tmp);
626 }
627
628 /* addb. */
629 void
630 OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
631 {
632 uint8 a = (OP[0]) & 0xff;
633 uint8 b = (GPR (OP[1]) & 0xff);
634 uint16 tmp = (a + b) & 0xff;
635 trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
636 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
637 SET_PSR_C (tmp > 0xFF);
638 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
639 trace_output_16 (sd, tmp);
640 }
641
642 /* addb. */
643 void
644 OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
645 {
646 uint8 a = (GPR (OP[0]) & 0xff);
647 uint8 b = (GPR (OP[1]) & 0xff);
648 uint16 tmp = (a + b) & 0xff;
649 trace_input ("addb", OP_REG, OP_REG, OP_VOID);
650 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
651 SET_PSR_C (tmp > 0xFF);
652 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
653 trace_output_16 (sd, tmp);
654 }
655
656 /* addw. */
657 void
658 OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
659 {
660 int16 a = OP[0];
661 uint16 tmp, b = GPR (OP[1]);
662 tmp = (a + b);
663 trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
664 SET_GPR (OP[1], tmp);
665 SET_PSR_C (tmp > 0xFFFF);
666 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
667 trace_output_16 (sd, tmp);
668 }
669
670 /* addw. */
671 void
672 OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
673 {
674 int16 a = OP[0];
675 uint16 tmp, b = GPR (OP[1]);
676 tmp = (a + b);
677 trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
678 SET_GPR (OP[1], tmp);
679 SET_PSR_C (tmp > 0xFFFF);
680 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
681 trace_output_16 (sd, tmp);
682 }
683
684 /* addw. */
685 void
686 OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
687 {
688 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
689 trace_input ("addw", OP_REG, OP_REG, OP_VOID);
690 tmp = (a + b);
691 SET_GPR (OP[1], tmp);
692 SET_PSR_C (tmp > 0xFFFF);
693 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
694 trace_output_16 (sd, tmp);
695 }
696
697 /* addcb. */
698 void
699 OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
700 {
701 uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
702 trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
703 tmp = (a + b + PSR_C) & 0xff;
704 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
705 SET_PSR_C (tmp > 0xFF);
706 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
707 trace_output_16 (sd, tmp);
708 }
709
710 /* addcb. */
711 void
712 OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
713 {
714 int8 a = OP[0] & 0xff;
715 uint8 b = (GPR (OP[1])) & 0xff;
716 uint8 tmp = (a + b + PSR_C) & 0xff;
717 trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
718 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
719 SET_PSR_C (tmp > 0xFF);
720 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
721 trace_output_16 (sd, tmp);
722 }
723
724 /* addcb. */
725 void
726 OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
727 {
728 uint8 a = (GPR (OP[0])) & 0xff;
729 uint8 b = (GPR (OP[1])) & 0xff;
730 uint8 tmp = (a + b + PSR_C) & 0xff;
731 trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
732 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
733 SET_PSR_C (tmp > 0xFF);
734 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
735 trace_output_16 (sd, tmp);
736 }
737
738 /* addcw. */
739 void
740 OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
741 {
742 uint16 a = OP[0];
743 uint16 b = GPR (OP[1]);
744 uint16 tmp = (a + b + PSR_C);
745 trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
746 SET_GPR (OP[1], tmp);
747 SET_PSR_C (tmp > 0xFFFF);
748 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
749 trace_output_16 (sd, tmp);
750 }
751
752 /* addcw. */
753 void
754 OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
755 {
756 int16 a = OP[0];
757 uint16 b = GPR (OP[1]);
758 uint16 tmp = (a + b + PSR_C);
759 trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
760 SET_GPR (OP[1], tmp);
761 SET_PSR_C (tmp > 0xFFFF);
762 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
763 trace_output_16 (sd, tmp);
764 }
765
766 /* addcw. */
767 void
768 OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
769 {
770 uint16 a = GPR (OP[1]);
771 uint16 b = GPR (OP[1]);
772 uint16 tmp = (a + b + PSR_C);
773 trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
774 SET_GPR (OP[1], tmp);
775 SET_PSR_C (tmp > 0xFFFF);
776 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
777 trace_output_16 (sd, tmp);
778 }
779
780 /* addd. */
781 void
782 OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
783 {
784 int16 a = (OP[0]);
785 uint32 b = GPR32 (OP[1]);
786 uint32 tmp = (a + b);
787 trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
788 SET_GPR32 (OP[1], tmp);
789 SET_PSR_C (tmp > 0xFFFFFFFF);
790 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
791 trace_output_32 (sd, tmp);
792 }
793
794 /* addd. */
795 void
796 OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
797 {
798 int32 a = (SEXT16(OP[0]));
799 uint32 b = GPR32 (OP[1]);
800 uint32 tmp = (a + b);
801 trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
802 SET_GPR32 (OP[1], tmp);
803 SET_PSR_C (tmp > 0xFFFFFFFF);
804 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
805 trace_output_32 (sd, tmp);
806 }
807
808 /* addd. */
809 void
810 OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
811 {
812 uint32 a = GPR32 (OP[0]);
813 uint32 b = GPR32 (OP[1]);
814 uint32 tmp = (a + b);
815 trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
816 SET_GPR32 (OP[1], tmp);
817 trace_output_32 (sd, tmp);
818 SET_PSR_C (tmp > 0xFFFFFFFF);
819 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
820 }
821
822 /* addd. */
823 void
824 OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
825 {
826 uint32 a = OP[0];
827 uint32 b = GPR32 (OP[1]);
828 uint32 tmp;
829 trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
830 tmp = (a + b);
831 SET_GPR32 (OP[1], tmp);
832 SET_PSR_C (tmp > 0xFFFFFFFF);
833 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
834 trace_output_32 (sd, tmp);
835 }
836
837 /* addd. */
838 void
839 OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
840 {
841 int32 a = OP[0];
842 uint32 b = GPR32 (OP[1]);
843 uint32 tmp;
844 trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
845 tmp = (a + b);
846 SET_GPR32 (OP[1], tmp);
847 SET_PSR_C (tmp > 0xFFFFFFFF);
848 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
849 trace_output_32 (sd, tmp);
850 }
851
852 /* andb. */
853 void
854 OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
855 {
856 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
857 trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
858 tmp = a & b;
859 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
860 trace_output_16 (sd, tmp);
861 }
862
863 /* andb. */
864 void
865 OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
866 {
867 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
868 trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
869 tmp = a & b;
870 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
871 trace_output_16 (sd, tmp);
872 }
873
874 /* andb. */
875 void
876 OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
877 {
878 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
879 trace_input ("andb", OP_REG, OP_REG, OP_VOID);
880 tmp = a & b;
881 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
882 trace_output_16 (sd, tmp);
883 }
884
885 /* andw. */
886 void
887 OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
888 {
889 uint16 tmp, a = OP[0], b = GPR (OP[1]);
890 trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
891 tmp = a & b;
892 SET_GPR (OP[1], tmp);
893 trace_output_16 (sd, tmp);
894 }
895
896 /* andw. */
897 void
898 OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
899 {
900 uint16 tmp, a = OP[0], b = GPR (OP[1]);
901 trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
902 tmp = a & b;
903 SET_GPR (OP[1], tmp);
904 trace_output_16 (sd, tmp);
905 }
906
907 /* andw. */
908 void
909 OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
910 {
911 uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]);
912 trace_input ("andw", OP_REG, OP_REG, OP_VOID);
913 tmp = a & b;
914 SET_GPR (OP[1], tmp);
915 trace_output_16 (sd, tmp);
916 }
917
918 /* andd. */
919 void
920 OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
921 {
922 uint32 tmp, a = OP[0], b = GPR32 (OP[1]);
923 trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
924 tmp = a & b;
925 SET_GPR32 (OP[1], tmp);
926 trace_output_32 (sd, tmp);
927 }
928
929 /* andd. */
930 void
931 OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
932 {
933 uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
934 trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
935 tmp = a & b;
936 SET_GPR32 (OP[1], tmp);
937 trace_output_32 (sd, tmp);
938 }
939
940 /* ord. */
941 void
942 OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
943 {
944 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
945 trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
946 tmp = a | b;
947 SET_GPR32 (OP[1], tmp);
948 trace_output_32 (sd, tmp);
949 }
950
951 /* ord. */
952 void
953 OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
954 {
955 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
956 trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
957 tmp = a | b;
958 SET_GPR32 (OP[1], tmp);
959 trace_output_32 (sd, tmp);
960 }
961
962 /* xord. */
963 void
964 OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
965 {
966 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
967 trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
968 tmp = a ^ b;
969 SET_GPR32 (OP[1], tmp);
970 trace_output_32 (sd, tmp);
971 }
972
973 /* xord. */
974 void
975 OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
976 {
977 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
978 trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
979 tmp = a ^ b;
980 SET_GPR32 (OP[1], tmp);
981 trace_output_32 (sd, tmp);
982 }
983
984
985 /* b. */
986 void
987 OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
988 {
989 uint32 tmp = 0, cc = cond_stat (OP[0]);
990 trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
991 if (cc)
992 {
993 if (sign_flag)
994 tmp = (PC - (OP[1]));
995 else
996 tmp = (PC + (OP[1]));
997 /* If the resulting PC value is less than 0x00_0000 or greater
998 than 0xFF_FFFF, this instruction causes an IAD trap.*/
999
1000 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1001 {
1002 State.exception = SIG_CR16_BUS;
1003 State.pc_changed = 1; /* Don't increment the PC. */
1004 trace_output_void (sd);
1005 return;
1006 }
1007 else
1008 JMP (tmp);
1009 }
1010 sign_flag = 0; /* Reset sign_flag. */
1011 trace_output_32 (sd, tmp);
1012 }
1013
1014 /* b. */
1015 void
1016 OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
1017 {
1018 uint32 tmp = 0, cc = cond_stat (OP[0]);
1019 trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
1020 if (cc)
1021 {
1022 if (sign_flag)
1023 tmp = (PC - OP[1]);
1024 else
1025 tmp = (PC + OP[1]);
1026 /* If the resulting PC value is less than 0x00_0000 or greater
1027 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1028
1029 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1030 {
1031 State.exception = SIG_CR16_BUS;
1032 State.pc_changed = 1; /* Don't increment the PC. */
1033 trace_output_void (sd);
1034 return;
1035 }
1036 else
1037 JMP (tmp);
1038 }
1039 sign_flag = 0; /* Reset sign_flag. */
1040 trace_output_32 (sd, tmp);
1041 }
1042
1043 /* b. */
1044 void
1045 OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
1046 {
1047 uint32 tmp = 0, cc = cond_stat (OP[0]);
1048 trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
1049 if (cc)
1050 {
1051 if (sign_flag)
1052 tmp = (PC - (OP[1]));
1053 else
1054 tmp = (PC + (OP[1]));
1055 /* If the resulting PC value is less than 0x00_0000 or greater
1056 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1057
1058 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1059 {
1060 State.exception = SIG_CR16_BUS;
1061 State.pc_changed = 1; /* Don't increment the PC. */
1062 trace_output_void (sd);
1063 return;
1064 }
1065 else
1066 JMP (tmp);
1067 }
1068 sign_flag = 0; /* Reset sign_flag. */
1069 trace_output_32 (sd, tmp);
1070 }
1071
1072 /* bal. */
1073 void
1074 OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
1075 {
1076 uint32 tmp;
1077 trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
1078 tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
1079 SET_GPR32 (14, tmp);
1080 if (sign_flag)
1081 tmp = (PC - (OP[1]));
1082 else
1083 tmp = (PC + (OP[1]));
1084
1085 /* If the resulting PC value is less than 0x00_0000 or greater
1086 than 0xFF_FFFF, this instruction causes an IAD trap. */
1087
1088 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1089 {
1090 State.exception = SIG_CR16_BUS;
1091 State.pc_changed = 1; /* Don't increment the PC. */
1092 trace_output_void (sd);
1093 return;
1094 }
1095 else
1096 JMP (tmp);
1097 sign_flag = 0; /* Reset sign_flag. */
1098 trace_output_32 (sd, tmp);
1099 }
1100
1101
1102 /* bal. */
1103 void
1104 OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
1105 {
1106 uint32 tmp;
1107 trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
1108 tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
1109 SET_GPR32 (OP[0], tmp);
1110 if (sign_flag)
1111 tmp = ((PC) - (OP[1]));
1112 else
1113 tmp = ((PC) + (OP[1]));
1114 /* If the resulting PC value is less than 0x00_0000 or greater
1115 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1116
1117 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1118 {
1119 State.exception = SIG_CR16_BUS;
1120 State.pc_changed = 1; /* Don't increment the PC. */
1121 trace_output_void (sd);
1122 return;
1123 }
1124 else
1125 JMP (tmp);
1126 sign_flag = 0; /* Reset sign_flag. */
1127 trace_output_32 (sd, tmp);
1128 }
1129
1130 /* jal. */
1131 void
1132 OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
1133 {
1134 uint32 tmp;
1135 trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
1136 SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
1137 tmp = GPR32 (OP[1]);
1138 tmp = SEXT24(tmp << 1);
1139 /* If the resulting PC value is less than 0x00_0000 or greater
1140 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1141
1142 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1143 {
1144 State.exception = SIG_CR16_BUS;
1145 State.pc_changed = 1; /* Don't increment the PC. */
1146 trace_output_void (sd);
1147 return;
1148 }
1149 else
1150 JMP (tmp);
1151
1152 trace_output_32 (sd, tmp);
1153 }
1154
1155
1156 /* jal. */
1157 void
1158 OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
1159 {
1160 uint32 tmp;
1161 trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
1162 SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
1163 tmp = GPR32 (OP[0]);
1164 tmp = SEXT24(tmp << 1);
1165 /* If the resulting PC value is less than 0x00_0000 or greater
1166 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1167
1168 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1169 {
1170 State.exception = SIG_CR16_BUS;
1171 State.pc_changed = 1; /* Don't increment the PC. */
1172 trace_output_void (sd);
1173 return;
1174 }
1175 else
1176 JMP (tmp);
1177
1178 trace_output_32 (sd, tmp);
1179 }
1180
1181
1182 /* beq0b. */
1183 void
1184 OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
1185 {
1186 uint32 addr;
1187 uint8 a = (GPR (OP[0]) & 0xFF);
1188 trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
1189 addr = OP[1];
1190 if (a == 0)
1191 {
1192 if (sign_flag)
1193 addr = (PC - OP[1]);
1194 else
1195 addr = (PC + OP[1]);
1196
1197 JMP (addr);
1198 }
1199 sign_flag = 0; /* Reset sign_flag. */
1200 trace_output_void (sd);
1201 }
1202
1203 /* bne0b. */
1204 void
1205 OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
1206 {
1207 uint32 addr;
1208 uint8 a = (GPR (OP[0]) & 0xFF);
1209 trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
1210 addr = OP[1];
1211 if (a != 0)
1212 {
1213 if (sign_flag)
1214 addr = (PC - OP[1]);
1215 else
1216 addr = (PC + OP[1]);
1217
1218 JMP (addr);
1219 }
1220 sign_flag = 0; /* Reset sign_flag. */
1221 trace_output_void (sd);
1222 }
1223
1224 /* beq0w. */
1225 void
1226 OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
1227 {
1228 uint32 addr;
1229 uint16 a = GPR (OP[0]);
1230 trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
1231 addr = OP[1];
1232 if (a == 0)
1233 {
1234 if (sign_flag)
1235 addr = (PC - OP[1]);
1236 else
1237 addr = (PC + OP[1]);
1238
1239 JMP (addr);
1240 }
1241 sign_flag = 0; /* Reset sign_flag. */
1242 trace_output_void (sd);
1243 }
1244
1245 /* bne0w. */
1246 void
1247 OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
1248 {
1249 uint32 addr;
1250 uint16 a = GPR (OP[0]);
1251 trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
1252 addr = OP[1];
1253 if (a != 0)
1254 {
1255 if (sign_flag)
1256 addr = (PC - OP[1]);
1257 else
1258 addr = (PC + OP[1]);
1259
1260 JMP (addr);
1261 }
1262 sign_flag = 0; /* Reset sign_flag. */
1263 trace_output_void (sd);
1264 }
1265
1266
1267 /* jeq. */
1268 void
1269 OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
1270 {
1271 uint32 tmp = 0;
1272 trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
1273 if ((PSR_Z) == 1)
1274 {
1275 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1276 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1277 }
1278 trace_output_32 (sd, tmp);
1279 }
1280
1281 /* jne. */
1282 void
1283 OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
1284 {
1285 uint32 tmp = 0;
1286 trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
1287 if ((PSR_Z) == 0)
1288 {
1289 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1290 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1291 }
1292 trace_output_32 (sd, tmp);
1293 }
1294
1295 /* jcs. */
1296 void
1297 OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
1298 {
1299 uint32 tmp = 0;
1300 trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
1301 if ((PSR_C) == 1)
1302 {
1303 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1304 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1305 }
1306 trace_output_32 (sd, tmp);
1307 }
1308
1309 /* jcc. */
1310 void
1311 OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
1312 {
1313 uint32 tmp = 0;
1314 trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
1315 if ((PSR_C) == 0)
1316 {
1317 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1318 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1319 }
1320 trace_output_32 (sd, tmp);
1321 }
1322
1323 /* jhi. */
1324 void
1325 OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
1326 {
1327 uint32 tmp = 0;
1328 trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
1329 if ((PSR_L) == 1)
1330 {
1331 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1332 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1333 }
1334 trace_output_32 (sd, tmp);
1335 }
1336
1337 /* jls. */
1338 void
1339 OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
1340 {
1341 uint32 tmp = 0;
1342 trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
1343 if ((PSR_L) == 0)
1344 {
1345 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1346 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1347 }
1348 trace_output_32 (sd, tmp);
1349 }
1350
1351 /* jgt. */
1352 void
1353 OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
1354 {
1355 uint32 tmp = 0;
1356 trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
1357 if ((PSR_N) == 1)
1358 {
1359 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1360 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1361 }
1362 trace_output_32 (sd, tmp);
1363 }
1364
1365 /* jle. */
1366 void
1367 OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
1368 {
1369 uint32 tmp = 0;
1370 trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
1371 if ((PSR_N) == 0)
1372 {
1373 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1374 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1375 }
1376 trace_output_32 (sd, tmp);
1377 }
1378
1379
1380 /* jfs. */
1381 void
1382 OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
1383 {
1384 uint32 tmp = 0;
1385 trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
1386 if ((PSR_F) == 1)
1387 {
1388 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1389 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1390 }
1391 trace_output_32 (sd, tmp);
1392 }
1393
1394 /* jfc. */
1395 void
1396 OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
1397 {
1398 uint32 tmp = 0;
1399 trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
1400 if ((PSR_F) == 0)
1401 {
1402 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1403 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1404 }
1405 trace_output_32 (sd, tmp);
1406 }
1407
1408 /* jlo. */
1409 void
1410 OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
1411 {
1412 uint32 tmp = 0;
1413 trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
1414 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1415 {
1416 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1417 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1418 }
1419 trace_output_32 (sd, tmp);
1420 }
1421
1422 /* jhs. */
1423 void
1424 OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
1425 {
1426 uint32 tmp = 0;
1427 trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
1428 if (((PSR_Z) == 1) | ((PSR_L) == 1))
1429 {
1430 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1431 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1432 }
1433 trace_output_32 (sd, tmp);
1434 }
1435
1436 /* jlt. */
1437 void
1438 OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
1439 {
1440 uint32 tmp = 0;
1441 trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
1442 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1443 {
1444 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1445 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1446 }
1447 trace_output_32 (sd, tmp);
1448 }
1449
1450 /* jge. */
1451 void
1452 OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
1453 {
1454 uint32 tmp = 0;
1455 trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
1456 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1457 {
1458 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1459 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1460 }
1461 trace_output_32 (sd, tmp);
1462 }
1463
1464 /* jump. */
1465 void
1466 OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
1467 {
1468 uint32 tmp;
1469 trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
1470 tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
1471 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1472 trace_output_32 (sd, tmp);
1473 }
1474
1475 /* jusr. */
1476 void
1477 OP_AF_C (SIM_DESC sd, SIM_CPU *cpu)
1478 {
1479 uint32 tmp;
1480 trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
1481 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1482 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1483 SET_PSR_U(1);
1484 trace_output_32 (sd, tmp);
1485 }
1486
1487 /* seq. */
1488 void
1489 OP_80_C (SIM_DESC sd, SIM_CPU *cpu)
1490 {
1491 trace_input ("seq", OP_REG, OP_VOID, OP_VOID);
1492 if ((PSR_Z) == 1)
1493 SET_GPR (OP[0], 1);
1494 else
1495 SET_GPR (OP[0], 0);
1496 trace_output_void (sd);
1497 }
1498 /* sne. */
1499 void
1500 OP_81_C (SIM_DESC sd, SIM_CPU *cpu)
1501 {
1502 trace_input ("sne", OP_REG, OP_VOID, OP_VOID);
1503 if ((PSR_Z) == 0)
1504 SET_GPR (OP[0], 1);
1505 else
1506 SET_GPR (OP[0], 0);
1507 trace_output_void (sd);
1508 }
1509
1510 /* scs. */
1511 void
1512 OP_82_C (SIM_DESC sd, SIM_CPU *cpu)
1513 {
1514 trace_input ("scs", OP_REG, OP_VOID, OP_VOID);
1515 if ((PSR_C) == 1)
1516 SET_GPR (OP[0], 1);
1517 else
1518 SET_GPR (OP[0], 0);
1519 trace_output_void (sd);
1520 }
1521
1522 /* scc. */
1523 void
1524 OP_83_C (SIM_DESC sd, SIM_CPU *cpu)
1525 {
1526 trace_input ("scc", OP_REG, OP_VOID, OP_VOID);
1527 if ((PSR_C) == 0)
1528 SET_GPR (OP[0], 1);
1529 else
1530 SET_GPR (OP[0], 0);
1531 trace_output_void (sd);
1532 }
1533
1534 /* shi. */
1535 void
1536 OP_84_C (SIM_DESC sd, SIM_CPU *cpu)
1537 {
1538 trace_input ("shi", OP_REG, OP_VOID, OP_VOID);
1539 if ((PSR_L) == 1)
1540 SET_GPR (OP[0], 1);
1541 else
1542 SET_GPR (OP[0], 0);
1543 trace_output_void (sd);
1544 }
1545
1546 /* sls. */
1547 void
1548 OP_85_C (SIM_DESC sd, SIM_CPU *cpu)
1549 {
1550 trace_input ("sls", OP_REG, OP_VOID, OP_VOID);
1551 if ((PSR_L) == 0)
1552 SET_GPR (OP[0], 1);
1553 else
1554 SET_GPR (OP[0], 0);
1555 trace_output_void (sd);
1556 }
1557
1558 /* sgt. */
1559 void
1560 OP_86_C (SIM_DESC sd, SIM_CPU *cpu)
1561 {
1562 trace_input ("sgt", OP_REG, OP_VOID, OP_VOID);
1563 if ((PSR_N) == 1)
1564 SET_GPR (OP[0], 1);
1565 else
1566 SET_GPR (OP[0], 0);
1567 trace_output_void (sd);
1568 }
1569
1570 /* sle. */
1571 void
1572 OP_87_C (SIM_DESC sd, SIM_CPU *cpu)
1573 {
1574 trace_input ("sle", OP_REG, OP_VOID, OP_VOID);
1575 if ((PSR_N) == 0)
1576 SET_GPR (OP[0], 1);
1577 else
1578 SET_GPR (OP[0], 0);
1579 trace_output_void (sd);
1580 }
1581
1582 /* sfs. */
1583 void
1584 OP_88_C (SIM_DESC sd, SIM_CPU *cpu)
1585 {
1586 trace_input ("sfs", OP_REG, OP_VOID, OP_VOID);
1587 if ((PSR_F) == 1)
1588 SET_GPR (OP[0], 1);
1589 else
1590 SET_GPR (OP[0], 0);
1591 trace_output_void (sd);
1592 }
1593
1594 /* sfc. */
1595 void
1596 OP_89_C (SIM_DESC sd, SIM_CPU *cpu)
1597 {
1598 trace_input ("sfc", OP_REG, OP_VOID, OP_VOID);
1599 if ((PSR_F) == 0)
1600 SET_GPR (OP[0], 1);
1601 else
1602 SET_GPR (OP[0], 0);
1603 trace_output_void (sd);
1604 }
1605
1606
1607 /* slo. */
1608 void
1609 OP_8A_C (SIM_DESC sd, SIM_CPU *cpu)
1610 {
1611 trace_input ("slo", OP_REG, OP_VOID, OP_VOID);
1612 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1613 SET_GPR (OP[0], 1);
1614 else
1615 SET_GPR (OP[0], 0);
1616 trace_output_void (sd);
1617 }
1618
1619 /* shs. */
1620 void
1621 OP_8B_C (SIM_DESC sd, SIM_CPU *cpu)
1622 {
1623 trace_input ("shs", OP_REG, OP_VOID, OP_VOID);
1624 if ( ((PSR_Z) == 1) | ((PSR_L) == 1))
1625 SET_GPR (OP[0], 1);
1626 else
1627 SET_GPR (OP[0], 0);
1628 trace_output_void (sd);
1629 }
1630
1631 /* slt. */
1632 void
1633 OP_8C_C (SIM_DESC sd, SIM_CPU *cpu)
1634 {
1635 trace_input ("slt", OP_REG, OP_VOID, OP_VOID);
1636 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1637 SET_GPR (OP[0], 1);
1638 else
1639 SET_GPR (OP[0], 0);
1640 trace_output_void (sd);
1641 }
1642
1643 /* sge. */
1644 void
1645 OP_8D_C (SIM_DESC sd, SIM_CPU *cpu)
1646 {
1647 trace_input ("sge", OP_REG, OP_VOID, OP_VOID);
1648 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1649 SET_GPR (OP[0], 1);
1650 else
1651 SET_GPR (OP[0], 0);
1652 trace_output_void (sd);
1653 }
1654
1655 /* cbitb. */
1656 void
1657 OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
1658 {
1659 uint8 a = OP[0] & 0xff;
1660 uint32 addr = OP[1], tmp;
1661 trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1662 tmp = RB (addr);
1663 SET_PSR_F (tmp & (1 << a));
1664 tmp = tmp & ~(1 << a);
1665 SB (addr, tmp);
1666 trace_output_32 (sd, tmp);
1667 }
1668
1669 /* cbitb. */
1670 void
1671 OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
1672 {
1673 uint8 a = OP[0] & 0xff;
1674 uint32 addr = OP[1], tmp;
1675 trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1676 tmp = RB (addr);
1677 SET_PSR_F (tmp & (1 << a));
1678 tmp = tmp & ~(1 << a);
1679 SB (addr, tmp);
1680 trace_output_32 (sd, tmp);
1681 }
1682
1683 /* cbitb. */
1684 void
1685 OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
1686 {
1687 uint8 a = (OP[0]) & 0xff;
1688 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1689 trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1690 tmp = RB (addr);
1691 SET_PSR_F (tmp & (1 << a));
1692 tmp = tmp & ~(1 << a);
1693 SB (addr, tmp);
1694 trace_output_32 (sd, addr);
1695 }
1696
1697 /* cbitb. */
1698 void
1699 OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
1700 {
1701 uint8 a = (OP[0]) & 0xff;
1702 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1703 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1704 tmp = RB (addr);
1705 SET_PSR_F (tmp & (1 << a));
1706 tmp = tmp & ~(1 << a);
1707 SB (addr, tmp);
1708 trace_output_32 (sd, addr);
1709 }
1710
1711 /* cbitb. */
1712 void
1713 OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
1714 {
1715 uint8 a = (OP[0]) & 0xff;
1716 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1717 trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1718 tmp = RB (addr);
1719 SET_PSR_F (tmp & (1 << a));
1720 tmp = tmp & ~(1 << a);
1721 SB (addr, tmp);
1722 trace_output_32 (sd, addr);
1723 }
1724
1725 /* cbitb. */
1726 void
1727 OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
1728 {
1729 uint8 a = (OP[0]) & 0xff;
1730 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1731 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1732 tmp = RB (addr);
1733 SET_PSR_F (tmp & (1 << a));
1734 tmp = tmp & ~(1 << a);
1735 SB (addr, tmp);
1736 trace_output_32 (sd, addr);
1737 }
1738
1739 /* cbitb. */
1740 void
1741 OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
1742 {
1743 uint8 a = (OP[0]) & 0xff;
1744 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1745 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1746 tmp = RB (addr);
1747 SET_PSR_F (tmp & (1 << a));
1748 tmp = tmp & ~(1 << a);
1749 SB (addr, tmp);
1750 trace_output_32 (sd, addr);
1751
1752 }
1753
1754 /* cbitb. */
1755 void
1756 OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
1757 {
1758 uint8 a = (OP[0]) & 0xff;
1759 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1760 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1761 tmp = RB (addr);
1762 SET_PSR_F (tmp & (1 << a));
1763 tmp = tmp & ~(1 << a);
1764 SB (addr, tmp);
1765 trace_output_32 (sd, addr);
1766 }
1767
1768 /* cbitb. */
1769 void
1770 OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
1771 {
1772 uint8 a = (OP[0]) & 0xff;
1773 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1774 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1775 tmp = RB (addr);
1776 SET_PSR_F (tmp & (1 << a));
1777 tmp = tmp & ~(1 << a);
1778 SB (addr, tmp);
1779 trace_output_32 (sd, addr);
1780 }
1781
1782
1783 /* cbitw. */
1784 void
1785 OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
1786 {
1787 uint16 a = OP[0];
1788 uint32 addr = OP[1], tmp;
1789 trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1790 tmp = RW (addr);
1791 SET_PSR_F (tmp & (1 << a));
1792 tmp = tmp & ~(1 << a);
1793 SW (addr, tmp);
1794 trace_output_32 (sd, tmp);
1795 }
1796
1797 /* cbitw. */
1798 void
1799 OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
1800 {
1801 uint16 a = OP[0];
1802 uint32 addr = OP[1], tmp;
1803 trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1804 tmp = RW (addr);
1805 SET_PSR_F (tmp & (1 << a));
1806 tmp = tmp & ~(1 << a);
1807 SW (addr, tmp);
1808 trace_output_32 (sd, tmp);
1809 }
1810
1811 /* cbitw. */
1812 void
1813 OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
1814 {
1815 uint32 addr;
1816 uint16 a = (OP[0]), tmp;
1817 trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
1818
1819 if (OP[1] == 0)
1820 addr = (GPR32 (12)) + OP[2];
1821 else
1822 addr = (GPR32 (13)) + OP[2];
1823
1824 tmp = RW (addr);
1825 SET_PSR_F (tmp & (1 << a));
1826 tmp = tmp & ~(1 << a);
1827 SW (addr, tmp);
1828 trace_output_32 (sd, addr);
1829
1830 }
1831
1832 /* cbitw. */
1833 void
1834 OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
1835 {
1836 uint16 a = (OP[0]);
1837 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1838 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1839 tmp = RW (addr);
1840 SET_PSR_F (tmp & (1 << a));
1841 tmp = tmp & ~(1 << a);
1842 SW (addr, tmp);
1843 trace_output_32 (sd, addr);
1844 }
1845
1846 /* cbitw. */
1847 void
1848 OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
1849 {
1850 uint16 a = (OP[0]);
1851 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1852 trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1853 tmp = RW (addr);
1854 SET_PSR_F (tmp & (1 << a));
1855 tmp = tmp & ~(1 << a);
1856 SW (addr, tmp);
1857 trace_output_32 (sd, addr);
1858 }
1859
1860
1861 /* cbitw. */
1862 void
1863 OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
1864 {
1865 uint16 a = (OP[0]);
1866 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1867 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1868 tmp = RW (addr);
1869 SET_PSR_F (tmp & (1 << a));
1870 tmp = tmp & ~(1 << a);
1871 SW (addr, tmp);
1872 trace_output_32 (sd, addr);
1873 }
1874
1875 /* cbitw. */
1876 void
1877 OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
1878 {
1879 uint16 a = (OP[0]);
1880 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1881 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1882 tmp = RW (addr);
1883 SET_PSR_F (tmp & (1 << a));
1884 tmp = tmp & ~(1 << a);
1885 SW (addr, tmp);
1886 trace_output_32 (sd, addr);
1887 }
1888
1889
1890 /* cbitw. */
1891 void
1892 OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
1893 {
1894 uint16 a = (OP[0]);
1895 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1896 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1897 tmp = RW (addr);
1898 SET_PSR_F (tmp & (1 << a));
1899 tmp = tmp & ~(1 << a);
1900 SW (addr, tmp);
1901 trace_output_32 (sd, addr);
1902 }
1903
1904 /* cbitw. */
1905 void
1906 OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
1907 {
1908 uint16 a = (OP[0]);
1909 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1910 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1911 tmp = RW (addr);
1912 SET_PSR_F (tmp & (1 << a));
1913 tmp = tmp & ~(1 << a);
1914 SW (addr, tmp);
1915 trace_output_32 (sd, addr);
1916 }
1917
1918 /* sbitb. */
1919 void
1920 OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
1921 {
1922 uint8 a = OP[0] & 0xff;
1923 uint32 addr = OP[1], tmp;
1924 trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1925 tmp = RB (addr);
1926 SET_PSR_F (tmp & (1 << a));
1927 tmp = tmp | (1 << a);
1928 SB (addr, tmp);
1929 trace_output_32 (sd, tmp);
1930 }
1931
1932 /* sbitb. */
1933 void
1934 OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
1935 {
1936 uint8 a = OP[0] & 0xff;
1937 uint32 addr = OP[1], tmp;
1938 trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1939 tmp = RB (addr);
1940 SET_PSR_F (tmp & (1 << a));
1941 tmp = tmp | (1 << a);
1942 SB (addr, tmp);
1943 trace_output_32 (sd, tmp);
1944 }
1945
1946 /* sbitb. */
1947 void
1948 OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
1949 {
1950 uint8 a = OP[0] & 0xff;
1951 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1952 trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1953 tmp = RB (addr);
1954 SET_PSR_F (tmp & (1 << a));
1955 tmp = tmp | (1 << a);
1956 SB (addr, tmp);
1957 trace_output_32 (sd, tmp);
1958 }
1959
1960 /* sbitb. */
1961 void
1962 OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
1963 {
1964 uint8 a = OP[0] & 0xff;
1965 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1966 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1967 tmp = RB (addr);
1968 SET_PSR_F (tmp & (1 << a));
1969 tmp = tmp | (1 << a);
1970 SB (addr, tmp);
1971 trace_output_32 (sd, tmp);
1972 }
1973
1974 /* sbitb. */
1975 void
1976 OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
1977 {
1978 uint8 a = OP[0] & 0xff;
1979 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1980 trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1981 tmp = RB (addr);
1982 SET_PSR_F (tmp & (1 << a));
1983 tmp = tmp | (1 << a);
1984 SB (addr, tmp);
1985 trace_output_32 (sd, tmp);
1986 }
1987
1988
1989 /* sbitb. */
1990 void
1991 OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
1992 {
1993 uint8 a = OP[0] & 0xff;
1994 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1995 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1996 tmp = RB (addr);
1997 SET_PSR_F (tmp & (1 << a));
1998 tmp = tmp | (1 << a);
1999 SB (addr, tmp);
2000 trace_output_32 (sd, tmp);
2001 }
2002
2003 /* sbitb. */
2004 void
2005 OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
2006 {
2007 uint8 a = OP[0] & 0xff;
2008 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2009 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2010 tmp = RB (addr);
2011 SET_PSR_F (tmp & (1 << a));
2012 tmp = tmp | (1 << a);
2013 SB (addr, tmp);
2014 trace_output_32 (sd, tmp);
2015 }
2016
2017
2018 /* sbitb. */
2019 void
2020 OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
2021 {
2022 uint8 a = OP[0] & 0xff;
2023 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2024 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2025 tmp = RB (addr);
2026 SET_PSR_F (tmp & (1 << a));
2027 tmp = tmp | (1 << a);
2028 SB (addr, tmp);
2029 trace_output_32 (sd, tmp);
2030 }
2031
2032
2033 /* sbitb. */
2034 void
2035 OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
2036 {
2037 uint8 a = OP[0] & 0xff;
2038 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2039 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2040 tmp = RB (addr);
2041 SET_PSR_F (tmp & (1 << a));
2042 tmp = tmp | (1 << a);
2043 SB (addr, tmp);
2044 trace_output_32 (sd, tmp);
2045 }
2046
2047
2048 /* sbitw. */
2049 void
2050 OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
2051 {
2052 uint16 a = OP[0];
2053 uint32 addr = OP[1], tmp;
2054 trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2055 tmp = RW (addr);
2056 SET_PSR_F (tmp & (1 << a));
2057 tmp = tmp | (1 << a);
2058 SW (addr, tmp);
2059 trace_output_32 (sd, tmp);
2060 }
2061
2062 /* sbitw. */
2063 void
2064 OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
2065 {
2066 uint16 a = OP[0];
2067 uint32 addr = OP[1], tmp;
2068 trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2069 tmp = RW (addr);
2070 SET_PSR_F (tmp & (1 << a));
2071 tmp = tmp | (1 << a);
2072 SW (addr, tmp);
2073 trace_output_32 (sd, tmp);
2074 }
2075
2076 /* sbitw. */
2077 void
2078 OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
2079 {
2080 uint32 addr;
2081 uint16 a = (OP[0]), tmp;
2082 trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2083
2084 if (OP[1] == 0)
2085 addr = (GPR32 (12)) + OP[2];
2086 else
2087 addr = (GPR32 (13)) + OP[2];
2088
2089 tmp = RW (addr);
2090 SET_PSR_F (tmp & (1 << a));
2091 tmp = tmp | (1 << a);
2092 SW (addr, tmp);
2093 trace_output_32 (sd, addr);
2094 }
2095
2096 /* sbitw. */
2097 void
2098 OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
2099 {
2100 uint16 a = (OP[0]);
2101 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2102 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2103 tmp = RW (addr);
2104 SET_PSR_F (tmp & (1 << a));
2105 tmp = tmp | (1 << a);
2106 SW (addr, tmp);
2107 trace_output_32 (sd, addr);
2108 }
2109
2110 /* sbitw. */
2111 void
2112 OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
2113 {
2114 uint16 a = (OP[0]);
2115 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2116 trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2117 tmp = RW (addr);
2118 SET_PSR_F (tmp & (1 << a));
2119 tmp = tmp | (1 << a);
2120 SW (addr, tmp);
2121 trace_output_32 (sd, addr);
2122 }
2123
2124 /* sbitw. */
2125 void
2126 OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
2127 {
2128 uint16 a = (OP[0]);
2129 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2130 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2131 tmp = RW (addr);
2132 SET_PSR_F (tmp & (1 << a));
2133 tmp = tmp | (1 << a);
2134 SW (addr, tmp);
2135 trace_output_32 (sd, addr);
2136 }
2137
2138 /* sbitw. */
2139 void
2140 OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
2141 {
2142 uint16 a = (OP[0]);
2143 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2144 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2145 tmp = RW (addr);
2146 SET_PSR_F (tmp & (1 << a));
2147 tmp = tmp | (1 << a);
2148 SW (addr, tmp);
2149 trace_output_32 (sd, addr);
2150 }
2151
2152 /* sbitw. */
2153 void
2154 OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
2155 {
2156 uint16 a = (OP[0]);
2157 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2158 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2159 tmp = RW (addr);
2160 SET_PSR_F (tmp & (1 << a));
2161 tmp = tmp | (1 << a);
2162 SW (addr, tmp);
2163 trace_output_32 (sd, addr);
2164 }
2165
2166 /* sbitw. */
2167 void
2168 OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
2169 {
2170 uint16 a = (OP[0]);
2171 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2172 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2173 tmp = RW (addr);
2174 SET_PSR_F (tmp & (1 << a));
2175 tmp = tmp | (1 << a);
2176 SW (addr, tmp);
2177 trace_output_32 (sd, addr);
2178 }
2179
2180
2181 /* tbitb. */
2182 void
2183 OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
2184 {
2185 uint8 a = OP[0] & 0xff;
2186 uint32 addr = OP[1], tmp;
2187 trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2188 tmp = RB (addr);
2189 SET_PSR_F (tmp & (1 << a));
2190 trace_output_32 (sd, tmp);
2191 }
2192
2193 /* tbitb. */
2194 void
2195 OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
2196 {
2197 uint8 a = OP[0] & 0xff;
2198 uint32 addr = OP[1], tmp;
2199 trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2200 tmp = RB (addr);
2201 SET_PSR_F (tmp & (1 << a));
2202 trace_output_32 (sd, tmp);
2203 }
2204
2205 /* tbitb. */
2206 void
2207 OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
2208 {
2209 uint8 a = (OP[0]) & 0xff;
2210 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2211 trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
2212 tmp = RB (addr);
2213 SET_PSR_F (tmp & (1 << a));
2214 trace_output_32 (sd, addr);
2215 }
2216
2217 /* tbitb. */
2218 void
2219 OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
2220 {
2221 uint8 a = (OP[0]) & 0xff;
2222 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2223 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2224 tmp = RB (addr);
2225 SET_PSR_F (tmp & (1 << a));
2226 trace_output_32 (sd, addr);
2227 }
2228
2229 /* tbitb. */
2230 void
2231 OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
2232 {
2233 uint8 a = (OP[0]) & 0xff;
2234 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2235 trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2236 tmp = RB (addr);
2237 SET_PSR_F (tmp & (1 << a));
2238 trace_output_32 (sd, addr);
2239 }
2240
2241 /* tbitb. */
2242 void
2243 OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
2244 {
2245 uint8 a = (OP[0]) & 0xff;
2246 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2247 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2248 tmp = RB (addr);
2249 SET_PSR_F (tmp & (1 << a));
2250 trace_output_32 (sd, addr);
2251 }
2252
2253 /* tbitb. */
2254 void
2255 OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
2256 {
2257 uint8 a = (OP[0]) & 0xff;
2258 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2259 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2260 tmp = RB (addr);
2261 SET_PSR_F (tmp & (1 << a));
2262 trace_output_32 (sd, addr);
2263 }
2264
2265 /* tbitb. */
2266 void
2267 OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
2268 {
2269 uint8 a = (OP[0]) & 0xff;
2270 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2271 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2272 tmp = RB (addr);
2273 SET_PSR_F (tmp & (1 << a));
2274 trace_output_32 (sd, addr);
2275 }
2276
2277 /* tbitb. */
2278 void
2279 OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
2280 {
2281 uint8 a = (OP[0]) & 0xff;
2282 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2283 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2284 tmp = RB (addr);
2285 SET_PSR_F (tmp & (1 << a));
2286 trace_output_32 (sd, addr);
2287 }
2288
2289
2290 /* tbitw. */
2291 void
2292 OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
2293 {
2294 uint16 a = OP[0];
2295 uint32 addr = OP[1], tmp;
2296 trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2297 tmp = RW (addr);
2298 SET_PSR_F (tmp & (1 << a));
2299 trace_output_32 (sd, tmp);
2300 }
2301
2302 /* tbitw. */
2303 void
2304 OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
2305 {
2306 uint16 a = OP[0];
2307 uint32 addr = OP[1], tmp;
2308 trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2309 tmp = RW (addr);
2310 SET_PSR_F (tmp & (1 << a));
2311 trace_output_32 (sd, tmp);
2312 }
2313
2314
2315 /* tbitw. */
2316 void
2317 OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
2318 {
2319 uint32 addr;
2320 uint16 a = (OP[0]), tmp;
2321 trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2322
2323 if (OP[1] == 0)
2324 addr = (GPR32 (12)) + OP[2];
2325 else
2326 addr = (GPR32 (13)) + OP[2];
2327
2328 tmp = RW (addr);
2329 SET_PSR_F (tmp & (1 << a));
2330 trace_output_32 (sd, addr);
2331 }
2332
2333 /* tbitw. */
2334 void
2335 OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
2336 {
2337 uint16 a = (OP[0]);
2338 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2339 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2340 tmp = RW (addr);
2341 SET_PSR_F (tmp & (1 << a));
2342 trace_output_32 (sd, addr);
2343 }
2344
2345 /* tbitw. */
2346 void
2347 OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
2348 {
2349 uint16 a = (OP[0]);
2350 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2351 trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2352 tmp = RW (addr);
2353 SET_PSR_F (tmp & (1 << a));
2354 trace_output_32 (sd, addr);
2355 }
2356
2357 /* tbitw. */
2358 void
2359 OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
2360 {
2361 uint16 a = (OP[0]);
2362 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2363 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2364 tmp = RW (addr);
2365 SET_PSR_F (tmp & (1 << a));
2366 trace_output_32 (sd, addr);
2367 }
2368
2369 /* tbitw. */
2370 void
2371 OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
2372 {
2373 uint16 a = (OP[0]);
2374 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2375 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2376 tmp = RW (addr);
2377 SET_PSR_F (tmp & (1 << a));
2378 trace_output_32 (sd, addr);
2379 }
2380
2381 /* tbitw. */
2382 void
2383 OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
2384 {
2385 uint16 a = (OP[0]);
2386 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2387 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2388 tmp = RW (addr);
2389 SET_PSR_F (tmp & (1 << a));
2390 trace_output_32 (sd, addr);
2391 }
2392
2393
2394 /* tbitw. */
2395 void
2396 OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
2397 {
2398 uint16 a = (OP[0]);
2399 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2400 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2401 tmp = RW (addr);
2402 SET_PSR_F (tmp & (1 << a));
2403 trace_output_32 (sd, addr);
2404 }
2405
2406
2407 /* tbit. */
2408 void
2409 OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
2410 {
2411 uint16 a = OP[0];
2412 uint16 b = (GPR (OP[1]));
2413 trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
2414 SET_PSR_F (b & (1 << a));
2415 trace_output_16 (sd, b);
2416 }
2417
2418 /* tbit. */
2419 void
2420 OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
2421 {
2422 uint16 a = GPR (OP[0]);
2423 uint16 b = (GPR (OP[1]));
2424 trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
2425 SET_PSR_F (b & (1 << a));
2426 trace_output_16 (sd, b);
2427 }
2428
2429
2430 /* cmpb. */
2431 void
2432 OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
2433 {
2434 uint8 a = (OP[0]) & 0xFF;
2435 uint8 b = (GPR (OP[1])) & 0xFF;
2436 trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
2437 SET_PSR_Z (a == b);
2438 SET_PSR_N ((int8)a > (int8)b);
2439 SET_PSR_L (a > b);
2440 trace_output_flag (sd);
2441 }
2442
2443 /* cmpb. */
2444 void
2445 OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
2446 {
2447 uint8 a = (OP[0]) & 0xFF;
2448 uint8 b = (GPR (OP[1])) & 0xFF;
2449 trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
2450 SET_PSR_Z (a == b);
2451 SET_PSR_N ((int8)a > (int8)b);
2452 SET_PSR_L (a > b);
2453 trace_output_flag (sd);
2454 }
2455
2456 /* cmpb. */
2457 void
2458 OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
2459 {
2460 uint8 a = (GPR (OP[0])) & 0xFF;
2461 uint8 b = (GPR (OP[1])) & 0xFF;
2462 trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
2463 SET_PSR_Z (a == b);
2464 SET_PSR_N ((int8)a > (int8)b);
2465 SET_PSR_L (a > b);
2466 trace_output_flag (sd);
2467 }
2468
2469 /* cmpw. */
2470 void
2471 OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
2472 {
2473 uint16 a = (OP[0]);
2474 uint16 b = GPR (OP[1]);
2475 trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
2476 SET_PSR_Z (a == b);
2477 SET_PSR_N ((int16)a > (int16)b);
2478 SET_PSR_L (a > b);
2479 trace_output_flag (sd);
2480 }
2481
2482 /* cmpw. */
2483 void
2484 OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
2485 {
2486 uint16 a = (OP[0]);
2487 uint16 b = GPR (OP[1]);
2488 trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
2489 SET_PSR_Z (a == b);
2490 SET_PSR_N ((int16)a > (int16)b);
2491 SET_PSR_L (a > b);
2492 trace_output_flag (sd);
2493 }
2494
2495 /* cmpw. */
2496 void
2497 OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
2498 {
2499 uint16 a = GPR (OP[0]) ;
2500 uint16 b = GPR (OP[1]) ;
2501 trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
2502 SET_PSR_Z (a == b);
2503 SET_PSR_N ((int16)a > (int16)b);
2504 SET_PSR_L (a > b);
2505 trace_output_flag (sd);
2506 }
2507
2508 /* cmpd. */
2509 void
2510 OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
2511 {
2512 uint32 a = (OP[0]);
2513 uint32 b = GPR32 (OP[1]);
2514 trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
2515 SET_PSR_Z (a == b);
2516 SET_PSR_N ((int32)a > (int32)b);
2517 SET_PSR_L (a > b);
2518 trace_output_flag (sd);
2519 }
2520
2521 /* cmpd. */
2522 void
2523 OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
2524 {
2525 uint32 a = (SEXT16(OP[0]));
2526 uint32 b = GPR32 (OP[1]);
2527 trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
2528 SET_PSR_Z (a == b);
2529 SET_PSR_N ((int32)a > (int32)b);
2530 SET_PSR_L (a > b);
2531 trace_output_flag (sd);
2532 }
2533
2534 /* cmpd. */
2535 void
2536 OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
2537 {
2538 uint32 a = GPR32 (OP[0]) ;
2539 uint32 b = GPR32 (OP[1]) ;
2540 trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
2541 SET_PSR_Z (a == b);
2542 SET_PSR_N ((int32)a > (int32)b);
2543 SET_PSR_L (a > b);
2544 trace_output_flag (sd);
2545 }
2546
2547 /* cmpd. */
2548 void
2549 OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
2550 {
2551 uint32 a = (OP[0]);
2552 uint32 b = GPR32 (OP[1]);
2553 trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
2554 SET_PSR_Z (a == b);
2555 SET_PSR_N ((int32)a > (int32)b);
2556 SET_PSR_L (a > b);
2557 trace_output_flag (sd);
2558 }
2559
2560
2561 /* movb. */
2562 void
2563 OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
2564 {
2565 uint8 tmp = OP[0] & 0xFF;
2566 uint16 a = (GPR (OP[1])) & 0xFF00;
2567 trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
2568 SET_GPR (OP[1], (a | tmp));
2569 trace_output_16 (sd, tmp);
2570 }
2571
2572 /* movb. */
2573 void
2574 OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
2575 {
2576 uint8 tmp = OP[0] & 0xFF;
2577 uint16 a = (GPR (OP[1])) & 0xFF00;
2578 trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
2579 SET_GPR (OP[1], (a | tmp));
2580 trace_output_16 (sd, tmp);
2581 }
2582
2583 /* movb. */
2584 void
2585 OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
2586 {
2587 uint8 tmp = (GPR (OP[0])) & 0xFF;
2588 uint16 a = (GPR (OP[1])) & 0xFF00;
2589 trace_input ("movb", OP_REG, OP_REG, OP_VOID);
2590 SET_GPR (OP[1], (a | tmp));
2591 trace_output_16 (sd, tmp);
2592 }
2593
2594 /* movw. */
2595 void
2596 OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
2597 {
2598 uint16 tmp = OP[0];
2599 trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
2600 SET_GPR (OP[1], (tmp & 0xffff));
2601 trace_output_16 (sd, tmp);
2602 }
2603
2604 /* movw. */
2605 void
2606 OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
2607 {
2608 int16 tmp = OP[0];
2609 trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
2610 SET_GPR (OP[1], (tmp & 0xffff));
2611 trace_output_16 (sd, tmp);
2612 }
2613
2614 /* movw. */
2615 void
2616 OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
2617 {
2618 uint16 tmp = GPR (OP[0]);
2619 uint32 a = GPR32 (OP[1]);
2620 trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
2621 a = (a & 0xffff0000) | tmp;
2622 SET_GPR32 (OP[1], a);
2623 trace_output_16 (sd, tmp);
2624 }
2625
2626 /* movxb. */
2627 void
2628 OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
2629 {
2630 uint8 tmp = (GPR (OP[0])) & 0xFF;
2631 trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
2632 SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
2633 trace_output_16 (sd, tmp);
2634 }
2635
2636 /* movzb. */
2637 void
2638 OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
2639 {
2640 uint8 tmp = (GPR (OP[0])) & 0xFF;
2641 trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
2642 SET_GPR (OP[1], tmp);
2643 trace_output_16 (sd, tmp);
2644 }
2645
2646 /* movxw. */
2647 void
2648 OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
2649 {
2650 uint16 tmp = GPR (OP[0]);
2651 trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
2652 SET_GPR32 (OP[1], SEXT16(tmp));
2653 trace_output_16 (sd, tmp);
2654 }
2655
2656 /* movzw. */
2657 void
2658 OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
2659 {
2660 uint16 tmp = GPR (OP[0]);
2661 trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
2662 SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
2663 trace_output_16 (sd, tmp);
2664 }
2665
2666 /* movd. */
2667 void
2668 OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
2669 {
2670 int32 tmp = OP[0];
2671 trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
2672 SET_GPR32 (OP[1], tmp);
2673 trace_output_32 (sd, tmp);
2674 }
2675
2676 /* movd. */
2677 void
2678 OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
2679 {
2680 int32 tmp = SEXT16(OP[0]);
2681 trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
2682 SET_GPR32 (OP[1], tmp);
2683 trace_output_32 (sd, tmp);
2684 }
2685
2686 /* movd. */
2687 void
2688 OP_55_8 (SIM_DESC sd, SIM_CPU *cpu)
2689 {
2690 uint32 tmp = GPR32 (OP[0]);
2691 trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
2692 SET_GPR32 (OP[1], tmp);
2693 trace_output_32 (sd, tmp);
2694 }
2695
2696 /* movd. */
2697 void
2698 OP_5_8 (SIM_DESC sd, SIM_CPU *cpu)
2699 {
2700 uint32 tmp = OP[0];
2701 trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
2702 SET_GPR32 (OP[1], tmp);
2703 trace_output_32 (sd, tmp);
2704 }
2705
2706 /* movd. */
2707 void
2708 OP_7_C (SIM_DESC sd, SIM_CPU *cpu)
2709 {
2710 int32 tmp = OP[0];
2711 trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
2712 SET_GPR32 (OP[1], tmp);
2713 trace_output_32 (sd, tmp);
2714 }
2715
2716 /* loadm. */
2717 void
2718 OP_14_D (SIM_DESC sd, SIM_CPU *cpu)
2719 {
2720 uint32 addr = GPR (0);
2721 uint16 count = OP[0], reg = 2, tmp;
2722 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2723 if ((addr & 1))
2724 {
2725 State.exception = SIG_CR16_BUS;
2726 State.pc_changed = 1; /* Don't increment the PC. */
2727 trace_output_void (sd);
2728 return;
2729 }
2730
2731 while (count)
2732 {
2733 tmp = RW (addr);
2734 SET_GPR (reg, tmp);
2735 addr +=2;
2736 --count;
2737 reg++;
2738 if (reg == 6) reg = 8;
2739 };
2740
2741 SET_GPR (0, addr);
2742 trace_output_void (sd);
2743 }
2744
2745
2746 /* loadmp. */
2747 void
2748 OP_15_D (SIM_DESC sd, SIM_CPU *cpu)
2749 {
2750 uint32 addr = GPR32 (0);
2751 uint16 count = OP[0], reg = 2, tmp;
2752 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2753 if ((addr & 1))
2754 {
2755 State.exception = SIG_CR16_BUS;
2756 State.pc_changed = 1; /* Don't increment the PC. */
2757 trace_output_void (sd);
2758 return;
2759 }
2760
2761 while (count)
2762 {
2763 tmp = RW (addr);
2764 SET_GPR (reg, tmp);
2765 addr +=2;
2766 --count;
2767 reg++;
2768 if (reg == 6) reg = 8;
2769 };
2770
2771 SET_GPR32 (0, addr);
2772 trace_output_void (sd);
2773 }
2774
2775
2776 /* loadb. */
2777 void
2778 OP_88_8 (SIM_DESC sd, SIM_CPU *cpu)
2779 {
2780 /* loadb ABS20, REG
2781 * ADDR = zext24(abs20) | remap (ie 0xF00000)
2782 * REG = [ADDR]
2783 * NOTE: remap is
2784 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2785 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2786 * by the core to 16M-64k to 16M. */
2787
2788 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2789 uint32 addr = OP[0];
2790 trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
2791 if (addr > 0xEFFFF) addr |= 0xF00000;
2792 tmp = (RB (addr));
2793 SET_GPR (OP[1], (a | tmp));
2794 trace_output_16 (sd, tmp);
2795 }
2796
2797 /* loadb. */
2798 void
2799 OP_127_14 (SIM_DESC sd, SIM_CPU *cpu)
2800 {
2801 /* loadb ABS24, REG
2802 * ADDR = abs24
2803 * REGR = [ADDR]. */
2804
2805 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2806 uint32 addr = OP[0];
2807 trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
2808 tmp = (RB (addr));
2809 SET_GPR (OP[1], (a | tmp));
2810 trace_output_16 (sd, tmp);
2811 }
2812
2813 /* loadb. */
2814 void
2815 OP_45_7 (SIM_DESC sd, SIM_CPU *cpu)
2816 {
2817 /* loadb [Rindex]ABS20 REG
2818 * ADDR = Rindex + zext24(disp20)
2819 * REGR = [ADDR]. */
2820
2821 uint32 addr;
2822 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2823 trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
2824
2825 if (OP[0] == 0)
2826 addr = (GPR32 (12)) + OP[1];
2827 else
2828 addr = (GPR32 (13)) + OP[1];
2829
2830 tmp = (RB (addr));
2831 SET_GPR (OP[2], (a | tmp));
2832 trace_output_16 (sd, tmp);
2833 }
2834
2835
2836 /* loadb. */
2837 void
2838 OP_B_4 (SIM_DESC sd, SIM_CPU *cpu)
2839 {
2840 /* loadb DIPS4(REGP) REG
2841 * ADDR = RPBASE + zext24(DISP4)
2842 * REG = [ADDR]. */
2843 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2844 uint32 addr = (GPR32 (OP[1])) + OP[0];
2845 trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
2846 tmp = (RB (addr));
2847 SET_GPR (OP[2], (a | tmp));
2848 trace_output_16 (sd, tmp);
2849 }
2850
2851 /* loadb. */
2852 void
2853 OP_BE_8 (SIM_DESC sd, SIM_CPU *cpu)
2854 {
2855 /* loadb [Rindex]disp0(RPbasex) REG
2856 * ADDR = Rpbasex + Rindex
2857 * REGR = [ADDR] */
2858
2859 uint32 addr;
2860 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2861 trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
2862
2863 addr = (GPR32 (OP[2])) + OP[1];
2864
2865 if (OP[0] == 0)
2866 addr = (GPR32 (12)) + addr;
2867 else
2868 addr = (GPR32 (13)) + addr;
2869
2870 tmp = (RB (addr));
2871 SET_GPR (OP[3], (a | tmp));
2872 trace_output_16 (sd, tmp);
2873 }
2874
2875 /* loadb. */
2876 void
2877 OP_219_A (SIM_DESC sd, SIM_CPU *cpu)
2878 {
2879 /* loadb [Rindex]disp14(RPbasex) REG
2880 * ADDR = Rpbasex + Rindex + zext24(disp14)
2881 * REGR = [ADDR] */
2882
2883 uint32 addr;
2884 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2885
2886 addr = (GPR32 (OP[2])) + OP[1];
2887
2888 if (OP[0] == 0)
2889 addr = (GPR32 (12)) + addr;
2890 else
2891 addr = (GPR32 (13)) + addr;
2892
2893 trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
2894 tmp = (RB (addr));
2895 SET_GPR (OP[3], (a | tmp));
2896 trace_output_16 (sd, tmp);
2897 }
2898
2899
2900 /* loadb. */
2901 void
2902 OP_184_14 (SIM_DESC sd, SIM_CPU *cpu)
2903 {
2904 /* loadb DISPE20(REG) REG
2905 * zext24(Rbase) + zext24(dispe20)
2906 * REG = [ADDR] */
2907
2908 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2909 uint32 addr = OP[0] + (GPR (OP[1]));
2910 trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
2911 tmp = (RB (addr));
2912 SET_GPR (OP[2], (a | tmp));
2913 trace_output_16 (sd, tmp);
2914 }
2915
2916 /* loadb. */
2917 void
2918 OP_124_14 (SIM_DESC sd, SIM_CPU *cpu)
2919 {
2920 /* loadb DISP20(REG) REG
2921 * ADDR = zext24(Rbase) + zext24(disp20)
2922 * REG = [ADDR] */
2923
2924 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2925 uint32 addr = OP[0] + (GPR (OP[1]));
2926 trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
2927 tmp = (RB (addr));
2928 SET_GPR (OP[2], (a | tmp));
2929 trace_output_16 (sd, tmp);
2930 }
2931
2932 /* loadb. */
2933 void
2934 OP_BF_8 (SIM_DESC sd, SIM_CPU *cpu)
2935 {
2936 /* loadb disp16(REGP) REG
2937 * ADDR = RPbase + zext24(disp16)
2938 * REGR = [ADDR] */
2939
2940 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2941 uint32 addr = (GPR32 (OP[1])) + OP[0];
2942 trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
2943 tmp = (RB (addr));
2944 SET_GPR (OP[2], (a | tmp));
2945 trace_output_16 (sd, tmp);
2946 }
2947
2948 /* loadb. */
2949 void
2950 OP_125_14 (SIM_DESC sd, SIM_CPU *cpu)
2951 {
2952 /* loadb disp20(REGP) REG
2953 * ADDR = RPbase + zext24(disp20)
2954 * REGR = [ADDR] */
2955 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2956 uint32 addr = (GPR32 (OP[1])) + OP[0];
2957 trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
2958 tmp = (RB (addr));
2959 SET_GPR (OP[2], (a | tmp));
2960 trace_output_16 (sd, tmp);
2961 }
2962
2963
2964 /* loadb. */
2965 void
2966 OP_185_14 (SIM_DESC sd, SIM_CPU *cpu)
2967 {
2968 /* loadb -disp20(REGP) REG
2969 * ADDR = RPbase + zext24(-disp20)
2970 * REGR = [ADDR] */
2971 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2972 uint32 addr = (GPR32 (OP[1])) + OP[1];
2973 trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
2974 tmp = (RB (addr));
2975 SET_GPR (OP[2], (a | tmp));
2976 trace_output_16 (sd, tmp);
2977 }
2978
2979 /* loadb. */
2980 void
2981 OP_126_14 (SIM_DESC sd, SIM_CPU *cpu)
2982 {
2983 /* loadb [Rindex]disp20(RPbasexb) REG
2984 * ADDR = RPbasex + Rindex + zext24(disp20)
2985 * REGR = [ADDR] */
2986
2987 uint32 addr;
2988 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2989 trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
2990
2991 addr = (GPR32 (OP[2])) + OP[1];
2992
2993 if (OP[0] == 0)
2994 addr = (GPR32 (12)) + addr;
2995 else
2996 addr = (GPR32 (13)) + addr;
2997
2998 tmp = (RB (addr));
2999 SET_GPR (OP[3], (a | tmp));
3000 trace_output_16 (sd, tmp);
3001 }
3002
3003
3004 /* loadw. */
3005 void
3006 OP_89_8 (SIM_DESC sd, SIM_CPU *cpu)
3007 {
3008 /* loadw ABS20, REG
3009 * ADDR = zext24(abs20) | remap
3010 * REGR = [ADDR]
3011 * NOTE: remap is
3012 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3013 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3014 * by the core to 16M-64k to 16M. */
3015
3016 uint16 tmp;
3017 uint32 addr = OP[0];
3018 trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
3019 if (addr > 0xEFFFF) addr |= 0xF00000;
3020 tmp = (RW (addr));
3021 SET_GPR (OP[1], tmp);
3022 trace_output_16 (sd, tmp);
3023 }
3024
3025
3026 /* loadw. */
3027 void
3028 OP_12F_14 (SIM_DESC sd, SIM_CPU *cpu)
3029 {
3030 /* loadw ABS24, REG
3031 * ADDR = abs24
3032 * REGR = [ADDR] */
3033 uint16 tmp;
3034 uint32 addr = OP[0];
3035 trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
3036 tmp = (RW (addr));
3037 SET_GPR (OP[1], tmp);
3038 trace_output_16 (sd, tmp);
3039 }
3040
3041 /* loadw. */
3042 void
3043 OP_47_7 (SIM_DESC sd, SIM_CPU *cpu)
3044 {
3045 /* loadw [Rindex]ABS20 REG
3046 * ADDR = Rindex + zext24(disp20)
3047 * REGR = [ADDR] */
3048
3049 uint32 addr;
3050 uint16 tmp;
3051 trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
3052
3053 if (OP[0] == 0)
3054 addr = (GPR32 (12)) + OP[1];
3055 else
3056 addr = (GPR32 (13)) + OP[1];
3057
3058 tmp = (RW (addr));
3059 SET_GPR (OP[2], tmp);
3060 trace_output_16 (sd, tmp);
3061 }
3062
3063
3064 /* loadw. */
3065 void
3066 OP_9_4 (SIM_DESC sd, SIM_CPU *cpu)
3067 {
3068 /* loadw DIPS4(REGP) REGP
3069 * ADDR = RPBASE + zext24(DISP4)
3070 * REGP = [ADDR]. */
3071 uint16 tmp;
3072 uint32 addr, a;
3073 trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
3074 addr = (GPR32 (OP[1])) + OP[0];
3075 tmp = (RW (addr));
3076 if (OP[2] > 11)
3077 {
3078 a = (GPR32 (OP[2])) & 0xffff0000;
3079 SET_GPR32 (OP[2], (a | tmp));
3080 }
3081 else
3082 SET_GPR (OP[2], tmp);
3083
3084 trace_output_16 (sd, tmp);
3085 }
3086
3087
3088 /* loadw. */
3089 void
3090 OP_9E_8 (SIM_DESC sd, SIM_CPU *cpu)
3091 {
3092 /* loadw [Rindex]disp0(RPbasex) REG
3093 * ADDR = Rpbasex + Rindex
3094 * REGR = [ADDR] */
3095
3096 uint32 addr;
3097 uint16 tmp;
3098 trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
3099
3100 addr = (GPR32 (OP[2])) + OP[1];
3101
3102 if (OP[0] == 0)
3103 addr = (GPR32 (12)) + addr;
3104 else
3105 addr = (GPR32 (13)) + addr;
3106
3107 tmp = RW (addr);
3108 SET_GPR (OP[3], tmp);
3109 trace_output_16 (sd, tmp);
3110 }
3111
3112
3113 /* loadw. */
3114 void
3115 OP_21B_A (SIM_DESC sd, SIM_CPU *cpu)
3116 {
3117 /* loadw [Rindex]disp14(RPbasex) REG
3118 * ADDR = Rpbasex + Rindex + zext24(disp14)
3119 * REGR = [ADDR] */
3120
3121 uint32 addr;
3122 uint16 tmp;
3123 trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
3124 addr = (GPR32 (OP[2])) + OP[1];
3125
3126 if (OP[0] == 0)
3127 addr = (GPR32 (12)) + addr;
3128 else
3129 addr = (GPR32 (13)) + addr;
3130
3131 tmp = (RW (addr));
3132 SET_GPR (OP[3], tmp);
3133 trace_output_16 (sd, tmp);
3134 }
3135
3136 /* loadw. */
3137 void
3138 OP_18C_14 (SIM_DESC sd, SIM_CPU *cpu)
3139 {
3140 /* loadw dispe20(REG) REGP
3141 * REGP = [DISPE20+[REG]] */
3142
3143 uint16 tmp;
3144 uint32 addr, a;
3145 trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3146 addr = OP[0] + (GPR (OP[1]));
3147 tmp = (RW (addr));
3148 if (OP[2] > 11)
3149 {
3150 a = (GPR32 (OP[2])) & 0xffff0000;
3151 SET_GPR32 (OP[2], (a | tmp));
3152 }
3153 else
3154 SET_GPR (OP[2], tmp);
3155
3156 trace_output_16 (sd, tmp);
3157 }
3158
3159
3160 /* loadw. */
3161 void
3162 OP_12C_14 (SIM_DESC sd, SIM_CPU *cpu)
3163 {
3164 /* loadw DISP20(REG) REGP
3165 * ADDR = zext24(Rbase) + zext24(disp20)
3166 * REGP = [ADDR] */
3167
3168 uint16 tmp;
3169 uint32 addr, a;
3170 trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3171 addr = OP[0] + (GPR (OP[1]));
3172 tmp = (RW (addr));
3173 if (OP[2] > 11)
3174 {
3175 a = (GPR32 (OP[2])) & 0xffff0000;
3176 SET_GPR32 (OP[2], (a | tmp));
3177 }
3178 else
3179 SET_GPR (OP[2], tmp);
3180
3181 trace_output_16 (sd, tmp);
3182 }
3183
3184 /* loadw. */
3185 void
3186 OP_9F_8 (SIM_DESC sd, SIM_CPU *cpu)
3187 {
3188 /* loadw disp16(REGP) REGP
3189 * ADDR = RPbase + zext24(disp16)
3190 * REGP = [ADDR] */
3191 uint16 tmp;
3192 uint32 addr, a;
3193 trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3194 addr = (GPR32 (OP[1])) + OP[0];
3195 tmp = (RW (addr));
3196 if (OP[2] > 11)
3197 {
3198 a = (GPR32 (OP[2])) & 0xffff0000;
3199 SET_GPR32 (OP[2], (a | tmp));
3200 }
3201 else
3202 SET_GPR (OP[2], tmp);
3203
3204 trace_output_16 (sd, tmp);
3205 }
3206
3207 /* loadw. */
3208 void
3209 OP_12D_14 (SIM_DESC sd, SIM_CPU *cpu)
3210 {
3211 /* loadw disp20(REGP) REGP
3212 * ADDR = RPbase + zext24(disp20)
3213 * REGP = [ADDR] */
3214 uint16 tmp;
3215 uint32 addr, a;
3216 trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
3217 addr = (GPR32 (OP[1])) + OP[0];
3218 tmp = (RW (addr));
3219 if (OP[2] > 11)
3220 {
3221 a = (GPR32 (OP[2])) & 0xffff0000;
3222 SET_GPR32 (OP[2], (a | tmp));
3223 }
3224 else
3225 SET_GPR (OP[2], tmp);
3226
3227 trace_output_16 (sd, tmp);
3228 }
3229
3230 /* loadw. */
3231 void
3232 OP_18D_14 (SIM_DESC sd, SIM_CPU *cpu)
3233 {
3234 /* loadw -disp20(REGP) REG
3235 * ADDR = RPbase + zext24(-disp20)
3236 * REGR = [ADDR] */
3237
3238 uint16 tmp;
3239 uint32 addr, a;
3240 trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
3241 addr = (GPR32 (OP[1])) + OP[0];
3242 tmp = (RB (addr));
3243 if (OP[2] > 11)
3244 {
3245 a = (GPR32 (OP[2])) & 0xffff0000;
3246 SET_GPR32 (OP[2], (a | tmp));
3247 }
3248 else
3249 SET_GPR (OP[2], tmp);
3250
3251 trace_output_16 (sd, tmp);
3252 }
3253
3254
3255 /* loadw. */
3256 void
3257 OP_12E_14 (SIM_DESC sd, SIM_CPU *cpu)
3258 {
3259 /* loadw [Rindex]disp20(RPbasexb) REG
3260 * ADDR = RPbasex + Rindex + zext24(disp20)
3261 * REGR = [ADDR] */
3262
3263 uint32 addr;
3264 uint16 tmp;
3265 trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
3266
3267 if (OP[0] == 0)
3268 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3269 else
3270 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3271
3272 tmp = (RW (addr));
3273 SET_GPR (OP[3], tmp);
3274 trace_output_16 (sd, tmp);
3275 }
3276
3277
3278 /* loadd. */
3279 void
3280 OP_87_8 (SIM_DESC sd, SIM_CPU *cpu)
3281 {
3282 /* loadd ABS20, REGP
3283 * ADDR = zext24(abs20) | remap
3284 * REGP = [ADDR]
3285 * NOTE: remap is
3286 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3287 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3288 * by the core to 16M-64k to 16M. */
3289
3290 uint32 addr, tmp;
3291 addr = OP[0];
3292 trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
3293 if (addr > 0xEFFFF) addr |= 0xF00000;
3294 tmp = RLW (addr);
3295 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3296 SET_GPR32 (OP[1], tmp);
3297 trace_output_32 (sd, tmp);
3298 }
3299
3300 /* loadd. */
3301 void
3302 OP_12B_14 (SIM_DESC sd, SIM_CPU *cpu)
3303 {
3304 /* loadd ABS24, REGP
3305 * ADDR = abs24
3306 * REGP = [ADDR] */
3307
3308 uint32 addr = OP[0];
3309 uint32 tmp;
3310 trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
3311 tmp = RLW (addr);
3312 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3313 SET_GPR32 (OP[1],tmp);
3314 trace_output_32 (sd, tmp);
3315 }
3316
3317
3318 /* loadd. */
3319 void
3320 OP_46_7 (SIM_DESC sd, SIM_CPU *cpu)
3321 {
3322 /* loadd [Rindex]ABS20 REGP
3323 * ADDR = Rindex + zext24(disp20)
3324 * REGP = [ADDR] */
3325
3326 uint32 addr, tmp;
3327 trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
3328
3329 if (OP[0] == 0)
3330 addr = (GPR32 (12)) + OP[1];
3331 else
3332 addr = (GPR32 (13)) + OP[1];
3333
3334 tmp = RLW (addr);
3335 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3336 SET_GPR32 (OP[2], tmp);
3337 trace_output_32 (sd, tmp);
3338 }
3339
3340
3341 /* loadd. */
3342 void
3343 OP_A_4 (SIM_DESC sd, SIM_CPU *cpu)
3344 {
3345 /* loadd dips4(regp) REGP
3346 * ADDR = Rpbase + zext24(disp4)
3347 * REGP = [ADDR] */
3348
3349 uint32 tmp, addr = (GPR32 (OP[1])) + OP[0];
3350 trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
3351 tmp = RLW (addr);
3352 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3353 SET_GPR32 (OP[2], tmp);
3354 trace_output_32 (sd, tmp);
3355 }
3356
3357
3358 /* loadd. */
3359 void
3360 OP_AE_8 (SIM_DESC sd, SIM_CPU *cpu)
3361 {
3362 /* loadd [Rindex]disp0(RPbasex) REGP
3363 * ADDR = Rpbasex + Rindex
3364 * REGP = [ADDR] */
3365
3366 uint32 addr, tmp;
3367 trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
3368
3369 if (OP[0] == 0)
3370 addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1];
3371 else
3372 addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1];
3373
3374 tmp = RLW (addr);
3375 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3376 SET_GPR32 (OP[3], tmp);
3377 trace_output_32 (sd, tmp);
3378 }
3379
3380
3381 /* loadd. */
3382 void
3383 OP_21A_A (SIM_DESC sd, SIM_CPU *cpu)
3384 {
3385 /* loadd [Rindex]disp14(RPbasex) REGP
3386 * ADDR = Rpbasex + Rindex + zext24(disp14)
3387 * REGR = [ADDR] */
3388
3389 uint32 addr, tmp;
3390 trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
3391
3392 if (OP[0] == 0)
3393 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3394 else
3395 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3396
3397 tmp = RLW (addr);
3398 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3399 SET_GPR (OP[3],tmp);
3400 trace_output_32 (sd, tmp);
3401 }
3402
3403
3404 /* loadd. */
3405 void
3406 OP_188_14 (SIM_DESC sd, SIM_CPU *cpu)
3407 {
3408 /* loadd dispe20(REG) REG
3409 * zext24(Rbase) + zext24(dispe20)
3410 * REG = [ADDR] */
3411
3412 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3413 trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3414 tmp = RLW (addr);
3415 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3416 SET_GPR32 (OP[2], tmp);
3417 trace_output_32 (sd, tmp);
3418 }
3419
3420
3421 /* loadd. */
3422 void
3423 OP_128_14 (SIM_DESC sd, SIM_CPU *cpu)
3424 {
3425 /* loadd DISP20(REG) REG
3426 * ADDR = zext24(Rbase) + zext24(disp20)
3427 * REG = [ADDR] */
3428
3429 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3430 trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3431 tmp = RLW (addr);
3432 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3433 SET_GPR32 (OP[2], tmp);
3434 trace_output_32 (sd, tmp);
3435 }
3436
3437 /* loadd. */
3438 void
3439 OP_AF_8 (SIM_DESC sd, SIM_CPU *cpu)
3440 {
3441 /* loadd disp16(REGP) REGP
3442 * ADDR = RPbase + zext24(disp16)
3443 * REGR = [ADDR] */
3444 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3445 trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3446 tmp = RLW (addr);
3447 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3448 SET_GPR32 (OP[2], tmp);
3449 trace_output_32 (sd, tmp);
3450 }
3451
3452
3453 /* loadd. */
3454 void
3455 OP_129_14 (SIM_DESC sd, SIM_CPU *cpu)
3456 {
3457 /* loadd disp20(REGP) REGP
3458 * ADDR = RPbase + zext24(disp20)
3459 * REGP = [ADDR] */
3460 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3461 trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
3462 tmp = RLW (addr);
3463 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3464 SET_GPR32 (OP[2], tmp);
3465 trace_output_32 (sd, tmp);
3466 }
3467
3468 /* loadd. */
3469 void
3470 OP_189_14 (SIM_DESC sd, SIM_CPU *cpu)
3471 {
3472 /* loadd -disp20(REGP) REGP
3473 * ADDR = RPbase + zext24(-disp20)
3474 * REGP = [ADDR] */
3475
3476 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3477 trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
3478 tmp = RLW (addr);
3479 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3480 SET_GPR32 (OP[2], tmp);
3481 trace_output_32 (sd, tmp);
3482 }
3483
3484 /* loadd. */
3485 void
3486 OP_12A_14 (SIM_DESC sd, SIM_CPU *cpu)
3487 {
3488 /* loadd [Rindex]disp20(RPbasexb) REGP
3489 * ADDR = RPbasex + Rindex + zext24(disp20)
3490 * REGP = [ADDR] */
3491
3492 uint32 addr, tmp;
3493 trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
3494
3495 if (OP[0] == 0)
3496 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3497 else
3498 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3499
3500 tmp = RLW (addr);
3501 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3502 SET_GPR32 (OP[3], tmp);
3503 trace_output_32 (sd, tmp);
3504 }
3505
3506
3507 /* storb. */
3508 void
3509 OP_C8_8 (SIM_DESC sd, SIM_CPU *cpu)
3510 {
3511 /* storb REG, ABS20
3512 * ADDR = zext24(abs20) | remap
3513 * [ADDR] = REGR
3514 * NOTE: remap is
3515 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3516 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3517 * by the core to 16M-64k to 16M. */
3518
3519 uint8 a = ((GPR (OP[0])) & 0xff);
3520 uint32 addr = OP[1];
3521 trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3522 SB (addr, a);
3523 trace_output_32 (sd, addr);
3524 }
3525
3526 /* storb. */
3527 void
3528 OP_137_14 (SIM_DESC sd, SIM_CPU *cpu)
3529 {
3530 /* storb REG, ABS24
3531 * ADDR = abs24
3532 * [ADDR] = REGR. */
3533
3534 uint8 a = ((GPR (OP[0])) & 0xff);
3535 uint32 addr = OP[1];
3536 trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3537 SB (addr, a);
3538 trace_output_32 (sd, addr);
3539 }
3540
3541 /* storb. */
3542 void
3543 OP_65_7 (SIM_DESC sd, SIM_CPU *cpu)
3544 {
3545 /* storb REG, [Rindex]ABS20
3546 * ADDR = Rindex + zext24(disp20)
3547 * [ADDR] = REGR */
3548
3549 uint32 addr;
3550 uint8 a = ((GPR (OP[0])) & 0xff);
3551 trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3552
3553 if (OP[1] == 0)
3554 addr = (GPR32 (12)) + OP[2];
3555 else
3556 addr = (GPR32 (13)) + OP[2];
3557
3558 SB (addr, a);
3559 trace_output_32 (sd, addr);
3560 }
3561
3562 /* storb. */
3563 void
3564 OP_F_4 (SIM_DESC sd, SIM_CPU *cpu)
3565 {
3566 /* storb REG, DIPS4(REGP)
3567 * ADDR = RPBASE + zext24(DISP4)
3568 * [ADDR] = REG. */
3569
3570 uint16 a = ((GPR (OP[0])) & 0xff);
3571 uint32 addr = (GPR32 (OP[2])) + OP[1];
3572 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
3573 SB (addr, a);
3574 trace_output_32 (sd, addr);
3575 }
3576
3577 /* storb. */
3578 void
3579 OP_FE_8 (SIM_DESC sd, SIM_CPU *cpu)
3580 {
3581 /* storb [Rindex]disp0(RPbasex) REG
3582 * ADDR = Rpbasex + Rindex
3583 * [ADDR] = REGR */
3584
3585 uint32 addr;
3586 uint8 a = ((GPR (OP[0])) & 0xff);
3587 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3588
3589 if (OP[1] == 0)
3590 addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2];
3591 else
3592 addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2];
3593
3594 SB (addr, a);
3595 trace_output_32 (sd, addr);
3596 }
3597
3598 /* storb. */
3599 void
3600 OP_319_A (SIM_DESC sd, SIM_CPU *cpu)
3601 {
3602 /* storb REG, [Rindex]disp14(RPbasex)
3603 * ADDR = Rpbasex + Rindex + zext24(disp14)
3604 * [ADDR] = REGR */
3605
3606 uint8 a = ((GPR (OP[0])) & 0xff);
3607 uint32 addr = (GPR32 (OP[2])) + OP[1];
3608 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3609 SB (addr, a);
3610 trace_output_32 (sd, addr);
3611 }
3612
3613 /* storb. */
3614 void
3615 OP_194_14 (SIM_DESC sd, SIM_CPU *cpu)
3616 {
3617 /* storb REG, DISPE20(REG)
3618 * zext24(Rbase) + zext24(dispe20)
3619 * [ADDR] = REG */
3620
3621 uint8 a = ((GPR (OP[0])) & 0xff);
3622 uint32 addr = OP[1] + (GPR (OP[2]));
3623 trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
3624 SB (addr, a);
3625 trace_output_32 (sd, addr);
3626 }
3627
3628 /* storb. */
3629 void
3630 OP_134_14 (SIM_DESC sd, SIM_CPU *cpu)
3631 {
3632 /* storb REG, DISP20(REG)
3633 * ADDR = zext24(Rbase) + zext24(disp20)
3634 * [ADDR] = REG */
3635
3636 uint8 a = (GPR (OP[0]) & 0xff);
3637 uint32 addr = OP[1] + (GPR (OP[2]));
3638 trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3639 SB (addr, a);
3640 trace_output_32 (sd, addr);
3641 }
3642
3643 /* storb. */
3644 void
3645 OP_FF_8 (SIM_DESC sd, SIM_CPU *cpu)
3646 {
3647 /* storb REG, disp16(REGP)
3648 * ADDR = RPbase + zext24(disp16)
3649 * [ADDR] = REGP */
3650
3651 uint8 a = ((GPR (OP[0])) & 0xff);
3652 uint32 addr = (GPR32 (OP[2])) + OP[1];
3653 trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3654 SB (addr, a);
3655 trace_output_32 (sd, addr);
3656 }
3657
3658 /* storb. */
3659 void
3660 OP_135_14 (SIM_DESC sd, SIM_CPU *cpu)
3661 {
3662 /* storb REG, disp20(REGP)
3663 * ADDR = RPbase + zext24(disp20)
3664 * [ADDR] = REGP */
3665
3666 uint8 a = ((GPR (OP[0])) & 0xff);
3667 uint32 addr = (GPR32 (OP[2])) + OP[1];
3668 trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3669 SB (addr, a);
3670 trace_output_32 (sd, addr);
3671 }
3672
3673 /* storb. */
3674 void
3675 OP_195_14 (SIM_DESC sd, SIM_CPU *cpu)
3676 {
3677 /* storb REG, -disp20(REGP)
3678 * ADDR = RPbase + zext24(-disp20)
3679 * [ADDR] = REGP */
3680
3681 uint8 a = (GPR (OP[0]) & 0xff);
3682 uint32 addr = (GPR32 (OP[2])) + OP[1];
3683 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3684 SB (addr, a);
3685 trace_output_32 (sd, addr);
3686 }
3687
3688 /* storb. */
3689 void
3690 OP_136_14 (SIM_DESC sd, SIM_CPU *cpu)
3691 {
3692 /* storb REG, [Rindex]disp20(RPbase)
3693 * ADDR = RPbasex + Rindex + zext24(disp20)
3694 * [ADDR] = REGP */
3695
3696 uint8 a = (GPR (OP[0])) & 0xff;
3697 uint32 addr = (GPR32 (OP[2])) + OP[1];
3698 trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3699 SB (addr, a);
3700 trace_output_32 (sd, addr);
3701 }
3702
3703 /* STR_IMM instructions. */
3704 /* storb . */
3705 void
3706 OP_81_8 (SIM_DESC sd, SIM_CPU *cpu)
3707 {
3708 uint8 a = (OP[0]) & 0xff;
3709 uint32 addr = OP[1];
3710 trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3711 SB (addr, a);
3712 trace_output_32 (sd, addr);
3713 }
3714
3715 /* storb. */
3716 void
3717 OP_123_14 (SIM_DESC sd, SIM_CPU *cpu)
3718 {
3719 uint8 a = (OP[0]) & 0xff;
3720 uint32 addr = OP[1];
3721 trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3722 SB (addr, a);
3723 trace_output_32 (sd, addr);
3724 }
3725
3726 /* storb. */
3727 void
3728 OP_42_7 (SIM_DESC sd, SIM_CPU *cpu)
3729 {
3730 uint32 addr;
3731 uint8 a = (OP[0]) & 0xff;
3732 trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3733
3734 if (OP[1] == 0)
3735 addr = (GPR32 (12)) + OP[2];
3736 else
3737 addr = (GPR32 (13)) + OP[2];
3738
3739 SB (addr, a);
3740 trace_output_32 (sd, addr);
3741 }
3742
3743 /* storb. */
3744 void
3745 OP_218_A (SIM_DESC sd, SIM_CPU *cpu)
3746 {
3747 uint8 a = (OP[0]) & 0xff;
3748 uint32 addr = (GPR32 (OP[2])) + OP[1];
3749 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3750 SB (addr, a);
3751 trace_output_32 (sd, addr);
3752 }
3753
3754 /* storb. */
3755 void
3756 OP_82_8 (SIM_DESC sd, SIM_CPU *cpu)
3757 {
3758 uint8 a = (OP[0]) & 0xff;
3759 uint32 addr = (GPR32 (OP[2])) + OP[1];
3760 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
3761 SB (addr, a);
3762 trace_output_32 (sd, addr);
3763 }
3764
3765 /* storb. */
3766 void
3767 OP_120_14 (SIM_DESC sd, SIM_CPU *cpu)
3768 {
3769 uint8 a = (OP[0]) & 0xff;
3770 uint32 addr = (GPR (OP[2])) + OP[1];
3771 trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
3772 SB (addr, a);
3773 trace_output_32 (sd, addr);
3774 }
3775
3776 /* storb. */
3777 void
3778 OP_83_8 (SIM_DESC sd, SIM_CPU *cpu)
3779 {
3780 uint8 a = (OP[0]) & 0xff;
3781 uint32 addr = (GPR32 (OP[2])) + OP[1];
3782 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
3783 SB (addr, a);
3784 trace_output_32 (sd, addr);
3785 }
3786
3787 /* storb. */
3788 void
3789 OP_121_14 (SIM_DESC sd, SIM_CPU *cpu)
3790 {
3791 uint8 a = (OP[0]) & 0xff;
3792 uint32 addr = (GPR32 (OP[2])) + OP[1];
3793 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
3794 SB (addr, a);
3795 trace_output_32 (sd, addr);
3796 }
3797
3798 /* storb. */
3799 void
3800 OP_122_14 (SIM_DESC sd, SIM_CPU *cpu)
3801 {
3802 uint8 a = (OP[0]) & 0xff;
3803 uint32 addr = (GPR32 (OP[2])) + OP[1];
3804 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
3805 SB (addr, a);
3806 trace_output_32 (sd, addr);
3807 }
3808 /* endif for STR_IMM. */
3809
3810 /* storw . */
3811 void
3812 OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu)
3813 {
3814 uint16 a = GPR (OP[0]);
3815 uint32 addr = OP[1];
3816 trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3817 SW (addr, a);
3818 trace_output_32 (sd, addr);
3819 }
3820
3821 /* storw. */
3822 void
3823 OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu)
3824 {
3825 uint16 a = GPR (OP[0]);
3826 uint32 addr = OP[1];
3827 trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3828 SW (addr, a);
3829 trace_output_32 (sd, addr);
3830 }
3831
3832 /* storw. */
3833 void
3834 OP_67_7 (SIM_DESC sd, SIM_CPU *cpu)
3835 {
3836 uint32 addr;
3837 uint16 a = GPR (OP[0]);
3838 trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3839
3840 if (OP[1] == 0)
3841 addr = (GPR32 (12)) + OP[2];
3842 else
3843 addr = (GPR32 (13)) + OP[2];
3844
3845 SW (addr, a);
3846 trace_output_32 (sd, addr);
3847 }
3848
3849
3850 /* storw. */
3851 void
3852 OP_D_4 (SIM_DESC sd, SIM_CPU *cpu)
3853 {
3854 uint16 a = (GPR (OP[0]));
3855 uint32 addr = (GPR32 (OP[2])) + OP[1];
3856 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
3857 SW (addr, a);
3858 trace_output_32 (sd, addr);
3859 }
3860
3861 /* storw. */
3862 void
3863 OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu)
3864 {
3865 uint16 a = GPR (OP[0]);
3866 uint32 addr = (GPR32 (OP[2])) + OP[1];
3867 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3868 SW (addr, a);
3869 trace_output_32 (sd, addr);
3870 }
3871
3872 /* storw. */
3873 void
3874 OP_31B_A (SIM_DESC sd, SIM_CPU *cpu)
3875 {
3876 uint16 a = GPR (OP[0]);
3877 uint32 addr = (GPR32 (OP[2])) + OP[1];
3878 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3879 SW (addr, a);
3880 trace_output_32 (sd, addr);
3881 }
3882
3883 /* storw. */
3884 void
3885 OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu)
3886 {
3887 uint16 a = (GPR (OP[0]));
3888 uint32 addr = (GPR32 (OP[2])) + OP[1];
3889 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
3890 SW (addr, a);
3891 trace_output_32 (sd, addr);
3892 }
3893
3894 /* storw. */
3895 void
3896 OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu)
3897 {
3898 uint16 a = (GPR (OP[0]));
3899 uint32 addr = (GPR (OP[2])) + OP[1];
3900 trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3901 SW (addr, a);
3902 trace_output_32 (sd, addr);
3903 }
3904
3905 /* storw. */
3906 void
3907 OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu)
3908 {
3909 uint16 a = (GPR (OP[0]));
3910 uint32 addr = (GPR32 (OP[2])) + OP[1];
3911 trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3912 SW (addr, a);
3913 trace_output_32 (sd, addr);
3914 }
3915
3916 /* storw. */
3917 void
3918 OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu)
3919 {
3920 uint16 a = (GPR (OP[0]));
3921 uint32 addr = (GPR32 (OP[2])) + OP[1];
3922 trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3923 SW (addr, a);
3924 trace_output_32 (sd, addr);
3925 }
3926
3927 /* storw. */
3928 void
3929 OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu)
3930 {
3931 uint16 a = (GPR (OP[0]));
3932 uint32 addr = (GPR32 (OP[2])) + OP[1];
3933 trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3934 SW (addr, a);
3935 trace_output_32 (sd, addr);
3936 }
3937
3938 /* storw. */
3939 void
3940 OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu)
3941 {
3942 uint16 a = (GPR (OP[0]));
3943 uint32 addr = (GPR32 (OP[2])) + OP[1];
3944 trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3945 SW (addr, a);
3946 trace_output_32 (sd, addr);
3947 }
3948
3949 /* STORE-w IMM instruction *****/
3950 /* storw . */
3951 void
3952 OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu)
3953 {
3954 uint16 a = OP[0];
3955 uint32 addr = OP[1];
3956 trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3957 SW (addr, a);
3958 trace_output_32 (sd, addr);
3959 }
3960
3961 /* storw. */
3962 void
3963 OP_133_14 (SIM_DESC sd, SIM_CPU *cpu)
3964 {
3965 uint16 a = OP[0];
3966 uint32 addr = OP[1];
3967 trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3968 SW (addr, a);
3969 trace_output_32 (sd, addr);
3970 }
3971
3972 /* storw. */
3973 void
3974 OP_62_7 (SIM_DESC sd, SIM_CPU *cpu)
3975 {
3976 uint32 addr;
3977 uint16 a = OP[0];
3978 trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3979
3980 if (OP[1] == 0)
3981 addr = (GPR32 (12)) + OP[2];
3982 else
3983 addr = (GPR32 (13)) + OP[2];
3984
3985 SW (addr, a);
3986 trace_output_32 (sd, addr);
3987 }
3988
3989 /* storw. */
3990 void
3991 OP_318_A (SIM_DESC sd, SIM_CPU *cpu)
3992 {
3993 uint16 a = OP[0];
3994 uint32 addr = (GPR32 (OP[2])) + OP[1];
3995 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3996 SW (addr, a);
3997 trace_output_32 (sd, addr);
3998 }
3999
4000 /* storw. */
4001 void
4002 OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu)
4003 {
4004 uint16 a = OP[0];
4005 uint32 addr = (GPR32 (OP[2])) + OP[1];
4006 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
4007 SW (addr, a);
4008 trace_output_32 (sd, addr);
4009 }
4010
4011 /* storw. */
4012 void
4013 OP_130_14 (SIM_DESC sd, SIM_CPU *cpu)
4014 {
4015 uint16 a = OP[0];
4016 uint32 addr = (GPR32 (OP[2])) + OP[1];
4017 trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
4018 SW (addr, a);
4019 trace_output_32 (sd, addr);
4020 }
4021
4022 /* storw. */
4023 void
4024 OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu)
4025 {
4026 uint16 a = OP[0];
4027 uint32 addr = (GPR32 (OP[2])) + OP[1];
4028 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
4029 SW (addr, a);
4030 trace_output_32 (sd, addr);
4031 }
4032
4033
4034 /* storw. */
4035 void
4036 OP_131_14 (SIM_DESC sd, SIM_CPU *cpu)
4037 {
4038 uint16 a = OP[0];
4039 uint32 addr = (GPR32 (OP[2])) + OP[1];
4040 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
4041 SW (addr, a);
4042 trace_output_32 (sd, addr);
4043 }
4044
4045 /* storw. */
4046 void
4047 OP_132_14 (SIM_DESC sd, SIM_CPU *cpu)
4048 {
4049 uint16 a = OP[0];
4050 uint32 addr = (GPR32 (OP[2])) + OP[1];
4051 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
4052 SW (addr, a);
4053 trace_output_32 (sd, addr);
4054 }
4055
4056
4057 /* stord. */
4058 void
4059 OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu)
4060 {
4061 uint32 a = GPR32 (OP[0]);
4062 uint32 addr = OP[1];
4063 trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
4064 SLW (addr, a);
4065 trace_output_32 (sd, addr);
4066 }
4067
4068 /* stord. */
4069 void
4070 OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu)
4071 {
4072 uint32 a = GPR32 (OP[0]);
4073 uint32 addr = OP[1];
4074 trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
4075 SLW (addr, a);
4076 trace_output_32 (sd, addr);
4077 }
4078
4079 /* stord. */
4080 void
4081 OP_66_7 (SIM_DESC sd, SIM_CPU *cpu)
4082 {
4083 uint32 addr, a = GPR32 (OP[0]);
4084 trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
4085
4086 if (OP[1] == 0)
4087 addr = (GPR32 (12)) + OP[2];
4088 else
4089 addr = (GPR32 (13)) + OP[2];
4090
4091 SLW (addr, a);
4092 trace_output_32 (sd, addr);
4093 }
4094
4095 /* stord. */
4096 void
4097 OP_E_4 (SIM_DESC sd, SIM_CPU *cpu)
4098 {
4099 uint32 a = GPR32 (OP[0]);
4100 uint32 addr = (GPR32 (OP[2])) + OP[1];
4101 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
4102 SLW (addr, a);
4103 trace_output_32 (sd, addr);
4104 }
4105
4106 /* stord. */
4107 void
4108 OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu)
4109 {
4110 uint32 a = GPR32 (OP[0]);
4111 uint32 addr = (GPR32 (OP[2])) + OP[1];
4112 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
4113 SLW (addr, a);
4114 trace_output_32 (sd, addr);
4115 }
4116
4117 /* stord. */
4118 void
4119 OP_31A_A (SIM_DESC sd, SIM_CPU *cpu)
4120 {
4121 uint32 a = GPR32 (OP[0]);
4122 uint32 addr = (GPR32 (OP[2])) + OP[1];
4123 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
4124 SLW (addr, a);
4125 trace_output_32 (sd, addr);
4126 }
4127
4128 /* stord. */
4129 void
4130 OP_198_14 (SIM_DESC sd, SIM_CPU *cpu)
4131 {
4132 uint32 a = GPR32 (OP[0]);
4133 uint32 addr = (GPR32 (OP[2])) + OP[1];
4134 trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
4135 SLW (addr, a);
4136 trace_output_32 (sd, addr);
4137 }
4138
4139 /* stord. */
4140 void
4141 OP_138_14 (SIM_DESC sd, SIM_CPU *cpu)
4142 {
4143 uint32 a = GPR32 (OP[0]);
4144 uint32 addr = (GPR32 (OP[2])) + OP[1];
4145 trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
4146 SLW (addr, a);
4147 trace_output_32 (sd, addr);
4148 }
4149
4150 /* stord. */
4151 void
4152 OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu)
4153 {
4154 uint32 a = GPR32 (OP[0]);
4155 uint32 addr = (GPR32 (OP[2])) + OP[1];
4156 trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
4157 SLW (addr, a);
4158 trace_output_32 (sd, addr);
4159 }
4160
4161 /* stord. */
4162 void
4163 OP_139_14 (SIM_DESC sd, SIM_CPU *cpu)
4164 {
4165 uint32 a = GPR32 (OP[0]);
4166 uint32 addr = (GPR32 (OP[2])) + OP[1];
4167 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
4168 SLW (addr, a);
4169 trace_output_32 (sd, addr);
4170 }
4171
4172 /* stord. */
4173 void
4174 OP_199_14 (SIM_DESC sd, SIM_CPU *cpu)
4175 {
4176 uint32 a = GPR32 (OP[0]);
4177 uint32 addr = (GPR32 (OP[2])) + OP[1];
4178 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
4179 SLW (addr, a);
4180 trace_output_32 (sd, addr);
4181 }
4182
4183 /* stord. */
4184 void
4185 OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu)
4186 {
4187 uint32 a = GPR32 (OP[0]);
4188 uint32 addr = (GPR32 (OP[2])) + OP[1];
4189 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
4190 SLW (addr, a);
4191 trace_output_32 (sd, addr);
4192 }
4193
4194 /* macqu. */
4195 void
4196 OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu)
4197 {
4198 int32 tmp;
4199 int16 src1, src2;
4200 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4201 src1 = GPR (OP[0]);
4202 src2 = GPR (OP[1]);
4203 tmp = src1 * src2;
4204 /*REVISIT FOR SATURATION and Q FORMAT. */
4205 SET_GPR32 (OP[2], tmp);
4206 trace_output_32 (sd, tmp);
4207 }
4208
4209 /* macuw. */
4210 void
4211 OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu)
4212 {
4213 uint32 tmp;
4214 uint16 src1, src2;
4215 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4216 src1 = GPR (OP[0]);
4217 src2 = GPR (OP[1]);
4218 tmp = src1 * src2;
4219 /*REVISIT FOR SATURATION. */
4220 SET_GPR32 (OP[2], tmp);
4221 trace_output_32 (sd, tmp);
4222 }
4223
4224 /* macsw. */
4225 void
4226 OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu)
4227 {
4228 int32 tmp;
4229 int16 src1, src2;
4230 trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
4231 src1 = GPR (OP[0]);
4232 src2 = GPR (OP[1]);
4233 tmp = src1 * src2;
4234 /*REVISIT FOR SATURATION. */
4235 SET_GPR32 (OP[2], tmp);
4236 trace_output_32 (sd, tmp);
4237 }
4238
4239
4240 /* mulb. */
4241 void
4242 OP_64_8 (SIM_DESC sd, SIM_CPU *cpu)
4243 {
4244 int16 tmp;
4245 int8 a = (OP[0]) & 0xff;
4246 int8 b = (GPR (OP[1])) & 0xff;
4247 trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
4248 tmp = (a * b) & 0xff;
4249 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4250 trace_output_16 (sd, tmp);
4251 }
4252
4253 /* mulb. */
4254 void
4255 OP_64B_C (SIM_DESC sd, SIM_CPU *cpu)
4256 {
4257 int16 tmp;
4258 int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4259 trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
4260 tmp = (a * b) & 0xff;
4261 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4262 trace_output_16 (sd, tmp);
4263 }
4264
4265
4266 /* mulb. */
4267 void
4268 OP_65_8 (SIM_DESC sd, SIM_CPU *cpu)
4269 {
4270 int16 tmp;
4271 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4272 trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
4273 tmp = (a * b) & 0xff;
4274 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4275 trace_output_16 (sd, tmp);
4276 }
4277
4278
4279 /* mulw. */
4280 void
4281 OP_66_8 (SIM_DESC sd, SIM_CPU *cpu)
4282 {
4283 int32 tmp;
4284 uint16 a = OP[0];
4285 int16 b = (GPR (OP[1]));
4286 trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
4287 tmp = (a * b) & 0xffff;
4288 SET_GPR (OP[1], tmp);
4289 trace_output_32 (sd, tmp);
4290 }
4291
4292 /* mulw. */
4293 void
4294 OP_66B_C (SIM_DESC sd, SIM_CPU *cpu)
4295 {
4296 int32 tmp;
4297 int16 a = OP[0], b = (GPR (OP[1]));
4298 trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
4299 tmp = (a * b) & 0xffff;
4300 SET_GPR (OP[1], tmp);
4301 trace_output_32 (sd, tmp);
4302 }
4303
4304
4305 /* mulw. */
4306 void
4307 OP_67_8 (SIM_DESC sd, SIM_CPU *cpu)
4308 {
4309 int32 tmp;
4310 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4311 trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
4312 tmp = (a * b) & 0xffff;
4313 SET_GPR (OP[1], tmp);
4314 trace_output_32 (sd, tmp);
4315 }
4316
4317
4318 /* mulsb. */
4319 void
4320 OP_B_8 (SIM_DESC sd, SIM_CPU *cpu)
4321 {
4322 int16 tmp;
4323 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4324 trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
4325 tmp = a * b;
4326 SET_GPR (OP[1], tmp);
4327 trace_output_32 (sd, tmp);
4328 }
4329
4330 /* mulsw. */
4331 void
4332 OP_62_8 (SIM_DESC sd, SIM_CPU *cpu)
4333 {
4334 int32 tmp;
4335 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4336 trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
4337 tmp = a * b;
4338 SET_GPR32 (OP[1], tmp);
4339 trace_output_32 (sd, tmp);
4340 }
4341
4342 /* muluw. */
4343 void
4344 OP_63_8 (SIM_DESC sd, SIM_CPU *cpu)
4345 {
4346 uint32 tmp;
4347 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4348 trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
4349 tmp = a * b;
4350 SET_GPR32 (OP[1], tmp);
4351 trace_output_32 (sd, tmp);
4352 }
4353
4354
4355 /* nop. */
4356 void
4357 OP_2C00_10 (SIM_DESC sd, SIM_CPU *cpu)
4358 {
4359 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
4360
4361 #if 0
4362 State.exception = SIGTRAP;
4363 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
4364 switch (State.ins_type)
4365 {
4366 default:
4367 ins_type_counters[ (int)INS_UNKNOWN ]++;
4368 break;
4369
4370 }
4371
4372 #endif
4373 trace_output_void (sd);
4374 }
4375
4376
4377 /* orb. */
4378 void
4379 OP_24_8 (SIM_DESC sd, SIM_CPU *cpu)
4380 {
4381 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4382 trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
4383 tmp = a | b;
4384 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4385 trace_output_16 (sd, tmp);
4386 }
4387
4388 /* orb. */
4389 void
4390 OP_24B_C (SIM_DESC sd, SIM_CPU *cpu)
4391 {
4392 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4393 trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
4394 tmp = a | b;
4395 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4396 trace_output_16 (sd, tmp);
4397 }
4398
4399 /* orb. */
4400 void
4401 OP_25_8 (SIM_DESC sd, SIM_CPU *cpu)
4402 {
4403 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4404 trace_input ("orb", OP_REG, OP_REG, OP_VOID);
4405 tmp = a | b;
4406 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4407 trace_output_16 (sd, tmp);
4408 }
4409
4410 /* orw. */
4411 void
4412 OP_26_8 (SIM_DESC sd, SIM_CPU *cpu)
4413 {
4414 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4415 trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
4416 tmp = a | b;
4417 SET_GPR (OP[1], tmp);
4418 trace_output_16 (sd, tmp);
4419 }
4420
4421
4422 /* orw. */
4423 void
4424 OP_26B_C (SIM_DESC sd, SIM_CPU *cpu)
4425 {
4426 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4427 trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
4428 tmp = a | b;
4429 SET_GPR (OP[1], tmp);
4430 trace_output_16 (sd, tmp);
4431 }
4432
4433 /* orw. */
4434 void
4435 OP_27_8 (SIM_DESC sd, SIM_CPU *cpu)
4436 {
4437 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
4438 trace_input ("orw", OP_REG, OP_REG, OP_VOID);
4439 tmp = a | b;
4440 SET_GPR (OP[1], tmp);
4441 trace_output_16 (sd, tmp);
4442 }
4443
4444
4445 /* lshb. */
4446 void
4447 OP_13_9 (SIM_DESC sd, SIM_CPU *cpu)
4448 {
4449 uint16 a = OP[0];
4450 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4451 trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
4452 /* A positive count specifies a shift to the left;
4453 * A negative count specifies a shift to the right. */
4454 if (sign_flag)
4455 tmp = b >> a;
4456 else
4457 tmp = b << a;
4458
4459 sign_flag = 0; /* Reset sign_flag. */
4460
4461 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4462 trace_output_16 (sd, tmp);
4463 }
4464
4465 /* lshb. */
4466 void
4467 OP_44_8 (SIM_DESC sd, SIM_CPU *cpu)
4468 {
4469 uint16 a = (GPR (OP[0])) & 0xff;
4470 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4471 trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
4472 if (a & ((long)1 << 3))
4473 {
4474 sign_flag = 1;
4475 a = ~(a) + 1;
4476 }
4477 a = (unsigned int) (a & 0x7);
4478
4479 /* A positive count specifies a shift to the left;
4480 * A negative count specifies a shift to the right. */
4481 if (sign_flag)
4482 tmp = b >> a;
4483 else
4484 tmp = b << a;
4485
4486 sign_flag = 0; /* Reset sign_flag. */
4487 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4488 trace_output_16 (sd, tmp);
4489 }
4490
4491 /* lshw. */
4492 void
4493 OP_46_8 (SIM_DESC sd, SIM_CPU *cpu)
4494 {
4495 uint16 tmp, b = GPR (OP[1]);
4496 int16 a = GPR (OP[0]);
4497 trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
4498 if (a & ((long)1 << 4))
4499 {
4500 sign_flag = 1;
4501 a = ~(a) + 1;
4502 }
4503 a = (unsigned int) (a & 0xf);
4504
4505 /* A positive count specifies a shift to the left;
4506 * A negative count specifies a shift to the right. */
4507 if (sign_flag)
4508 tmp = b >> a;
4509 else
4510 tmp = b << a;
4511
4512 sign_flag = 0; /* Reset sign_flag. */
4513 SET_GPR (OP[1], (tmp & 0xffff));
4514 trace_output_16 (sd, tmp);
4515 }
4516
4517 /* lshw. */
4518 void
4519 OP_49_8 (SIM_DESC sd, SIM_CPU *cpu)
4520 {
4521 uint16 tmp, b = GPR (OP[1]);
4522 uint16 a = OP[0];
4523 trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
4524 /* A positive count specifies a shift to the left;
4525 * A negative count specifies a shift to the right. */
4526 if (sign_flag)
4527 tmp = b >> a;
4528 else
4529 tmp = b << a;
4530
4531 sign_flag = 0; /* Reset sign_flag. */
4532 SET_GPR (OP[1], (tmp & 0xffff));
4533 trace_output_16 (sd, tmp);
4534 }
4535
4536 /* lshd. */
4537 void
4538 OP_25_7 (SIM_DESC sd, SIM_CPU *cpu)
4539 {
4540 uint32 tmp, b = GPR32 (OP[1]);
4541 uint16 a = OP[0];
4542 trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
4543 /* A positive count specifies a shift to the left;
4544 * A negative count specifies a shift to the right. */
4545 if (sign_flag)
4546 tmp = b >> a;
4547 else
4548 tmp = b << a;
4549
4550 sign_flag = 0; /* Reset sign flag. */
4551
4552 SET_GPR32 (OP[1], tmp);
4553 trace_output_32 (sd, tmp);
4554 }
4555
4556 /* lshd. */
4557 void
4558 OP_47_8 (SIM_DESC sd, SIM_CPU *cpu)
4559 {
4560 uint32 tmp, b = GPR32 (OP[1]);
4561 uint16 a = GPR (OP[0]);
4562 trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
4563 if (a & ((long)1 << 5))
4564 {
4565 sign_flag = 1;
4566 a = ~(a) + 1;
4567 }
4568 a = (unsigned int) (a & 0x1f);
4569 /* A positive count specifies a shift to the left;
4570 * A negative count specifies a shift to the right. */
4571 if (sign_flag)
4572 tmp = b >> a;
4573 else
4574 tmp = b << a;
4575
4576 sign_flag = 0; /* Reset sign flag. */
4577
4578 SET_GPR32 (OP[1], tmp);
4579 trace_output_32 (sd, tmp);
4580 }
4581
4582 /* ashub. */
4583 void
4584 OP_80_9 (SIM_DESC sd, SIM_CPU *cpu)
4585 {
4586 uint16 a = OP[0];
4587 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4588 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4589 /* A positive count specifies a shift to the left;
4590 * A negative count specifies a shift to the right. */
4591 if (sign_flag)
4592 tmp = b >> a;
4593 else
4594 tmp = b << a;
4595
4596 sign_flag = 0; /* Reset sign flag. */
4597
4598 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00)));
4599 trace_output_16 (sd, tmp);
4600 }
4601
4602 /* ashub. */
4603 void
4604 OP_81_9 (SIM_DESC sd, SIM_CPU *cpu)
4605 {
4606 uint16 a = OP[0];
4607 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4608 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4609 /* A positive count specifies a shift to the left;
4610 * A negative count specifies a shift to the right. */
4611 if (sign_flag)
4612 tmp = b >> a;
4613 else
4614 tmp = b << a;
4615
4616 sign_flag = 0; /* Reset sign flag. */
4617
4618 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4619 trace_output_16 (sd, tmp);
4620 }
4621
4622
4623 /* ashub. */
4624 void
4625 OP_41_8 (SIM_DESC sd, SIM_CPU *cpu)
4626 {
4627 int16 a = (GPR (OP[0]));
4628 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4629 trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
4630
4631 if (a & ((long)1 << 3))
4632 {
4633 sign_flag = 1;
4634 a = ~(a) + 1;
4635 }
4636 a = (unsigned int) (a & 0x7);
4637
4638 /* A positive count specifies a shift to the left;
4639 * A negative count specifies a shift to the right. */
4640 if (sign_flag)
4641 tmp = b >> a;
4642 else
4643 tmp = b << a;
4644
4645 sign_flag = 0; /* Reset sign flag. */
4646
4647 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4648 trace_output_16 (sd, tmp);
4649 }
4650
4651
4652 /* ashuw. */
4653 void
4654 OP_42_8 (SIM_DESC sd, SIM_CPU *cpu)
4655 {
4656 int16 tmp, b = GPR (OP[1]);
4657 uint16 a = OP[0];
4658 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4659 /* A positive count specifies a shift to the left;
4660 * A negative count specifies a shift to the right. */
4661 if (sign_flag)
4662 tmp = b >> a;
4663 else
4664 tmp = b << a;
4665
4666 sign_flag = 0; /* Reset sign flag. */
4667
4668 SET_GPR (OP[1], (tmp & 0xffff));
4669 trace_output_16 (sd, tmp);
4670 }
4671
4672 /* ashuw. */
4673 void
4674 OP_43_8 (SIM_DESC sd, SIM_CPU *cpu)
4675 {
4676 int16 tmp, b = GPR (OP[1]);
4677 uint16 a = OP[0];
4678 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4679 /* A positive count specifies a shift to the left;
4680 * A negative count specifies a shift to the right. */
4681 if (sign_flag)
4682 tmp = b >> a;
4683 else
4684 tmp = b << a;
4685
4686 sign_flag = 0; /* Reset sign flag. */
4687 SET_GPR (OP[1], (tmp & 0xffff));
4688 trace_output_16 (sd, tmp);
4689 }
4690
4691 /* ashuw. */
4692 void
4693 OP_45_8 (SIM_DESC sd, SIM_CPU *cpu)
4694 {
4695 int16 tmp;
4696 int16 a = GPR (OP[0]), b = GPR (OP[1]);
4697 trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
4698
4699 if (a & ((long)1 << 4))
4700 {
4701 sign_flag = 1;
4702 a = ~(a) + 1;
4703 }
4704 a = (unsigned int) (a & 0xf);
4705 /* A positive count specifies a shift to the left;
4706 * A negative count specifies a shift to the right. */
4707
4708 if (sign_flag)
4709 tmp = b >> a;
4710 else
4711 tmp = b << a;
4712
4713 sign_flag = 0; /* Reset sign flag. */
4714 SET_GPR (OP[1], (tmp & 0xffff));
4715 trace_output_16 (sd, tmp);
4716 }
4717
4718 /* ashud. */
4719 void
4720 OP_26_7 (SIM_DESC sd, SIM_CPU *cpu)
4721 {
4722 int32 tmp,b = GPR32 (OP[1]);
4723 uint32 a = OP[0];
4724 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4725 /* A positive count specifies a shift to the left;
4726 * A negative count specifies a shift to the right. */
4727 if (sign_flag)
4728 tmp = b >> a;
4729 else
4730 tmp = b << a;
4731
4732 sign_flag = 0; /* Reset sign flag. */
4733 SET_GPR32 (OP[1], tmp);
4734 trace_output_32 (sd, tmp);
4735 }
4736
4737 /* ashud. */
4738 void
4739 OP_27_7 (SIM_DESC sd, SIM_CPU *cpu)
4740 {
4741 int32 tmp;
4742 int32 a = OP[0], b = GPR32 (OP[1]);
4743 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4744 /* A positive count specifies a shift to the left;
4745 * A negative count specifies a shift to the right. */
4746 if (sign_flag)
4747 tmp = b >> a;
4748 else
4749 tmp = b << a;
4750
4751 sign_flag = 0; /* Reset sign flag. */
4752 SET_GPR32 (OP[1], tmp);
4753 trace_output_32 (sd, tmp);
4754 }
4755
4756 /* ashud. */
4757 void
4758 OP_48_8 (SIM_DESC sd, SIM_CPU *cpu)
4759 {
4760 int32 tmp;
4761 int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]);
4762 trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
4763
4764 if (a & ((long)1 << 5))
4765 {
4766 sign_flag = 1;
4767 a = ~(a) + 1;
4768 }
4769 a = (unsigned int) (a & 0x1f);
4770 /* A positive count specifies a shift to the left;
4771 * A negative count specifies a shift to the right. */
4772 if (sign_flag)
4773 tmp = b >> a;
4774 else
4775 tmp = b << a;
4776
4777 sign_flag = 0; /* Reset sign flag. */
4778 SET_GPR32 (OP[1], tmp);
4779 trace_output_32 (sd, tmp);
4780 }
4781
4782
4783 /* storm. */
4784 void
4785 OP_16_D (SIM_DESC sd, SIM_CPU *cpu)
4786 {
4787 uint32 addr = GPR (1);
4788 uint16 count = OP[0], reg = 2;
4789 trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
4790 if ((addr & 1))
4791 {
4792 State.exception = SIG_CR16_BUS;
4793 State.pc_changed = 1; /* Don't increment the PC. */
4794 trace_output_void (sd);
4795 return;
4796 }
4797
4798 while (count)
4799 {
4800 SW (addr, (GPR (reg)));
4801 addr +=2;
4802 --count;
4803 reg++;
4804 if (reg == 6) reg = 8;
4805 };
4806
4807 SET_GPR (1, addr);
4808
4809 trace_output_void (sd);
4810 }
4811
4812
4813 /* stormp. */
4814 void
4815 OP_17_D (SIM_DESC sd, SIM_CPU *cpu)
4816 {
4817 uint32 addr = GPR32 (6);
4818 uint16 count = OP[0], reg = 2;
4819 trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
4820 if ((addr & 1))
4821 {
4822 State.exception = SIG_CR16_BUS;
4823 State.pc_changed = 1; /* Don't increment the PC. */
4824 trace_output_void (sd);
4825 return;
4826 }
4827
4828 while (count)
4829 {
4830 SW (addr, (GPR (reg)));
4831 addr +=2;
4832 --count;
4833 reg++;
4834 if (reg == 6) reg = 8;
4835 };
4836
4837 SET_GPR32 (6, addr);
4838 trace_output_void (sd);
4839 }
4840
4841 /* subb. */
4842 void
4843 OP_38_8 (SIM_DESC sd, SIM_CPU *cpu)
4844 {
4845 uint8 a = OP[0];
4846 uint8 b = (GPR (OP[1])) & 0xff;
4847 uint16 tmp = (~a + 1 + b) & 0xff;
4848 trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
4849 /* see ../common/sim-alu.h for a more extensive discussion on how to
4850 compute the carry/overflow bits. */
4851 SET_PSR_C (tmp > 0xff);
4852 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4853 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4854 trace_output_16 (sd, tmp);
4855 }
4856
4857 /* subb. */
4858 void
4859 OP_38B_C (SIM_DESC sd, SIM_CPU *cpu)
4860 {
4861 uint8 a = OP[0] & 0xFF;
4862 uint8 b = (GPR (OP[1])) & 0xFF;
4863 uint16 tmp = (~a + 1 + b) & 0xFF;
4864 trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
4865 /* see ../common/sim-alu.h for a more extensive discussion on how to
4866 compute the carry/overflow bits. */
4867 SET_PSR_C (tmp > 0xff);
4868 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4869 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4870 trace_output_16 (sd, tmp);
4871 }
4872
4873 /* subb. */
4874 void
4875 OP_39_8 (SIM_DESC sd, SIM_CPU *cpu)
4876 {
4877 uint8 a = (GPR (OP[0])) & 0xFF;
4878 uint8 b = (GPR (OP[1])) & 0xFF;
4879 uint16 tmp = (~a + 1 + b) & 0xff;
4880 trace_input ("subb", OP_REG, OP_REG, OP_VOID);
4881 /* see ../common/sim-alu.h for a more extensive discussion on how to
4882 compute the carry/overflow bits. */
4883 SET_PSR_C (tmp > 0xff);
4884 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4885 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4886 trace_output_16 (sd, tmp);
4887 }
4888
4889 /* subw. */
4890 void
4891 OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu)
4892 {
4893 uint16 a = OP[0];
4894 uint16 b = GPR (OP[1]);
4895 uint16 tmp = (~a + 1 + b);
4896 trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
4897 /* see ../common/sim-alu.h for a more extensive discussion on how to
4898 compute the carry/overflow bits. */
4899 SET_PSR_C (tmp > 0xffff);
4900 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4901 SET_GPR (OP[1], tmp);
4902 trace_output_16 (sd, tmp);
4903 }
4904
4905 /* subw. */
4906 void
4907 OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu)
4908 {
4909 uint16 a = OP[0];
4910 uint16 b = GPR (OP[1]);
4911 uint32 tmp = (~a + 1 + b);
4912 trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
4913 /* see ../common/sim-alu.h for a more extensive discussion on how to
4914 compute the carry/overflow bits. */
4915 SET_PSR_C (tmp > 0xffff);
4916 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4917 SET_GPR (OP[1], tmp & 0xffff);
4918 trace_output_16 (sd, tmp);
4919 }
4920
4921 /* subw. */
4922 void
4923 OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu)
4924 {
4925 uint16 a = GPR (OP[0]);
4926 uint16 b = GPR (OP[1]);
4927 uint32 tmp = (~a + 1 + b);
4928 trace_input ("subw", OP_REG, OP_REG, OP_VOID);
4929 /* see ../common/sim-alu.h for a more extensive discussion on how to
4930 compute the carry/overflow bits. */
4931 SET_PSR_C (tmp > 0xffff);
4932 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4933 SET_GPR (OP[1], tmp & 0xffff);
4934 trace_output_16 (sd, tmp);
4935 }
4936
4937 /* subcb. */
4938 void
4939 OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu)
4940 {
4941 uint8 a = OP[0];
4942 uint8 b = (GPR (OP[1])) & 0xff;
4943 //uint16 tmp1 = a + 1;
4944 uint16 tmp1 = a + (PSR_C);
4945 uint16 tmp = (~tmp1 + 1 + b);
4946 trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
4947 /* see ../common/sim-alu.h for a more extensive discussion on how to
4948 compute the carry/overflow bits. */
4949 SET_PSR_C (tmp > 0xff);
4950 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4951 SET_GPR (OP[1], tmp);
4952 trace_output_16 (sd, tmp);
4953 }
4954
4955 /* subcb. */
4956 void
4957 OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu)
4958 {
4959 uint16 a = OP[0];
4960 uint16 b = (GPR (OP[1])) & 0xff;
4961 //uint16 tmp1 = a + 1;
4962 uint16 tmp1 = a + (PSR_C);
4963 uint16 tmp = (~tmp1 + 1 + b);
4964 trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
4965 /* see ../common/sim-alu.h for a more extensive discussion on how to
4966 compute the carry/overflow bits. */
4967 SET_PSR_C (tmp > 0xff);
4968 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4969 SET_GPR (OP[1], tmp);
4970 trace_output_16 (sd, tmp);
4971 }
4972
4973 /* subcb. */
4974 void
4975 OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu)
4976 {
4977 uint16 a = (GPR (OP[0])) & 0xff;
4978 uint16 b = (GPR (OP[1])) & 0xff;
4979 uint16 tmp1 = a + (PSR_C);
4980 uint16 tmp = (~tmp1 + 1 + b);
4981 trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
4982 /* see ../common/sim-alu.h for a more extensive discussion on how to
4983 compute the carry/overflow bits. */
4984 SET_PSR_C (tmp > 0xff);
4985 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4986 SET_GPR (OP[1], tmp);
4987 trace_output_16 (sd, tmp);
4988 }
4989
4990 /* subcw. */
4991 void
4992 OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu)
4993 {
4994 uint16 a = OP[0], b = (GPR (OP[1]));
4995 uint16 tmp1 = a + (PSR_C);
4996 uint16 tmp = (~tmp1 + 1 + b);
4997 trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
4998 /* see ../common/sim-alu.h for a more extensive discussion on how to
4999 compute the carry/overflow bits. */
5000 SET_PSR_C (tmp > 0xffff);
5001 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5002 SET_GPR (OP[1], tmp);
5003 trace_output_16 (sd, tmp);
5004 }
5005
5006 /* subcw. */
5007 void
5008 OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu)
5009 {
5010 int16 a = OP[0];
5011 uint16 b = GPR (OP[1]);
5012 uint16 tmp1 = a + (PSR_C);
5013 uint16 tmp = (~tmp1 + 1 + b);
5014 trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
5015 /* see ../common/sim-alu.h for a more extensive discussion on how to
5016 compute the carry/overflow bits. */
5017 SET_PSR_C (tmp > 0xffff);
5018 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5019 SET_GPR (OP[1], tmp);
5020 trace_output_16 (sd, tmp);
5021 }
5022
5023 /* subcw. */
5024 void
5025 OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu)
5026 {
5027 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
5028 uint16 tmp1 = a + (PSR_C);
5029 uint16 tmp = (~tmp1 + 1 + b);
5030 trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
5031 /* see ../common/sim-alu.h for a more extensive discussion on how to
5032 compute the carry/overflow bits. */
5033 SET_PSR_C (tmp > 0xffff);
5034 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5035 SET_GPR (OP[1], tmp);
5036 trace_output_16 (sd, tmp);
5037 }
5038
5039 /* subd. */
5040 void
5041 OP_3_C (SIM_DESC sd, SIM_CPU *cpu)
5042 {
5043 int32 a = OP[0];
5044 uint32 b = GPR32 (OP[1]);
5045 uint32 tmp = (~a + 1 + b);
5046 trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
5047 /* see ../common/sim-alu.h for a more extensive discussion on how to
5048 compute the carry/overflow bits. */
5049 SET_PSR_C (tmp > 0xffffffff);
5050 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5051 ((b & 0x80000000) != (tmp & 0x80000000)));
5052 SET_GPR32 (OP[1], tmp);
5053 trace_output_32 (sd, tmp);
5054 }
5055
5056 /* subd. */
5057 void
5058 OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu)
5059 {
5060 uint32 a = GPR32 (OP[0]);
5061 uint32 b = GPR32 (OP[1]);
5062 uint32 tmp = (~a + 1 + b);
5063 trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
5064 /* see ../common/sim-alu.h for a more extensive discussion on how to
5065 compute the carry/overflow bits. */
5066 SET_PSR_C (tmp > 0xffffffff);
5067 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5068 ((b & 0x80000000) != (tmp & 0x80000000)));
5069 SET_GPR32 (OP[1], tmp);
5070 trace_output_32 (sd, tmp);
5071 }
5072
5073 /* excp. */
5074 void
5075 OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
5076 {
5077 uint32 tmp;
5078 uint16 a;
5079 trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
5080 switch (OP[0])
5081 {
5082 default:
5083 #if (DEBUG & DEBUG_TRAP) == 0
5084 {
5085 #if 0
5086 uint16 vec = OP[0] + TRAP_VECTOR_START;
5087 SET_BPC (PC + 1);
5088 SET_BPSR (PSR);
5089 SET_PSR (PSR & PSR_SM_BIT);
5090 JMP (vec);
5091 break;
5092 #endif
5093 }
5094 #else /* if debugging use trap to print registers */
5095 {
5096 int i;
5097 static int first_time = 1;
5098
5099 if (first_time)
5100 {
5101 first_time = 0;
5102 (*cr16_callback->printf_filtered) (cr16_callback, "Trap # PC ");
5103 for (i = 0; i < 16; i++)
5104 (*cr16_callback->printf_filtered) (cr16_callback, " %sr%d", (i > 9) ? "" : " ", i);
5105 (*cr16_callback->printf_filtered) (cr16_callback, " a0 a1 f0 f1 c\n");
5106 }
5107
5108 (*cr16_callback->printf_filtered) (cr16_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
5109
5110 for (i = 0; i < 16; i++)
5111 (*cr16_callback->printf_filtered) (cr16_callback, " %.4x", (int) GPR (i));
5112
5113 for (i = 0; i < 2; i++)
5114 (*cr16_callback->printf_filtered) (cr16_callback, " %.2x%.8lx",
5115 ((int)(ACC (i) >> 32) & 0xff),
5116 ((unsigned long) ACC (i)) & 0xffffffff);
5117
5118 (*cr16_callback->printf_filtered) (cr16_callback, " %d %d %d\n",
5119 PSR_F != 0, PSR_F != 0, PSR_C != 0);
5120 (*cr16_callback->flush_stdout) (cr16_callback);
5121 break;
5122 }
5123 #endif
5124 case 8: /* new system call trap */
5125 /* Trap 8 is used for simulating low-level I/O */
5126 {
5127 unsigned32 result = 0;
5128 errno = 0;
5129
5130 /* Registers passed to trap 0. */
5131
5132 #define FUNC GPR (0) /* function number. */
5133 #define PARM1 GPR (2) /* optional parm 1. */
5134 #define PARM2 GPR (3) /* optional parm 2. */
5135 #define PARM3 GPR (4) /* optional parm 3. */
5136 #define PARM4 GPR (5) /* optional parm 4. */
5137
5138 /* Registers set by trap 0 */
5139
5140 #define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0)
5141 #define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0)
5142 #define RETERR(X) SET_GPR (4, (X)) /* return error code. */
5143
5144 /* Turn a pointer in a register into a pointer into real memory. */
5145
5146 #define MEMPTR(x) sim_core_trans_addr (sd, cpu, read_map, x)
5147
5148 switch (FUNC)
5149 {
5150 #if !defined(__GO32__) && !defined(_WIN32)
5151 #ifdef TARGET_SYS_fork
5152 case TARGET_SYS_fork:
5153 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
5154 RETVAL (fork ());
5155 trace_output_16 (sd, result);
5156 break;
5157 #endif
5158
5159 #define getpid() 47
5160 case TARGET_SYS_getpid:
5161 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5162 RETVAL (getpid ());
5163 trace_output_16 (sd, result);
5164 break;
5165
5166 case TARGET_SYS_kill:
5167 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5168 if (PARM1 == getpid ())
5169 {
5170 trace_output_void (sd);
5171 State.exception = PARM2;
5172 }
5173 else
5174 {
5175 int os_sig = -1;
5176 switch (PARM2)
5177 {
5178 #ifdef SIGHUP
5179 case 1: os_sig = SIGHUP; break;
5180 #endif
5181 #ifdef SIGINT
5182 case 2: os_sig = SIGINT; break;
5183 #endif
5184 #ifdef SIGQUIT
5185 case 3: os_sig = SIGQUIT; break;
5186 #endif
5187 #ifdef SIGILL
5188 case 4: os_sig = SIGILL; break;
5189 #endif
5190 #ifdef SIGTRAP
5191 case 5: os_sig = SIGTRAP; break;
5192 #endif
5193 #ifdef SIGABRT
5194 case 6: os_sig = SIGABRT; break;
5195 #elif defined(SIGIOT)
5196 case 6: os_sig = SIGIOT; break;
5197 #endif
5198 #ifdef SIGEMT
5199 case 7: os_sig = SIGEMT; break;
5200 #endif
5201 #ifdef SIGFPE
5202 case 8: os_sig = SIGFPE; break;
5203 #endif
5204 #ifdef SIGKILL
5205 case 9: os_sig = SIGKILL; break;
5206 #endif
5207 #ifdef SIGBUS
5208 case 10: os_sig = SIGBUS; break;
5209 #endif
5210 #ifdef SIGSEGV
5211 case 11: os_sig = SIGSEGV; break;
5212 #endif
5213 #ifdef SIGSYS
5214 case 12: os_sig = SIGSYS; break;
5215 #endif
5216 #ifdef SIGPIPE
5217 case 13: os_sig = SIGPIPE; break;
5218 #endif
5219 #ifdef SIGALRM
5220 case 14: os_sig = SIGALRM; break;
5221 #endif
5222 #ifdef SIGTERM
5223 case 15: os_sig = SIGTERM; break;
5224 #endif
5225 #ifdef SIGURG
5226 case 16: os_sig = SIGURG; break;
5227 #endif
5228 #ifdef SIGSTOP
5229 case 17: os_sig = SIGSTOP; break;
5230 #endif
5231 #ifdef SIGTSTP
5232 case 18: os_sig = SIGTSTP; break;
5233 #endif
5234 #ifdef SIGCONT
5235 case 19: os_sig = SIGCONT; break;
5236 #endif
5237 #ifdef SIGCHLD
5238 case 20: os_sig = SIGCHLD; break;
5239 #elif defined(SIGCLD)
5240 case 20: os_sig = SIGCLD; break;
5241 #endif
5242 #ifdef SIGTTIN
5243 case 21: os_sig = SIGTTIN; break;
5244 #endif
5245 #ifdef SIGTTOU
5246 case 22: os_sig = SIGTTOU; break;
5247 #endif
5248 #ifdef SIGIO
5249 case 23: os_sig = SIGIO; break;
5250 #elif defined (SIGPOLL)
5251 case 23: os_sig = SIGPOLL; break;
5252 #endif
5253 #ifdef SIGXCPU
5254 case 24: os_sig = SIGXCPU; break;
5255 #endif
5256 #ifdef SIGXFSZ
5257 case 25: os_sig = SIGXFSZ; break;
5258 #endif
5259 #ifdef SIGVTALRM
5260 case 26: os_sig = SIGVTALRM; break;
5261 #endif
5262 #ifdef SIGPROF
5263 case 27: os_sig = SIGPROF; break;
5264 #endif
5265 #ifdef SIGWINCH
5266 case 28: os_sig = SIGWINCH; break;
5267 #endif
5268 #ifdef SIGLOST
5269 case 29: os_sig = SIGLOST; break;
5270 #endif
5271 #ifdef SIGUSR1
5272 case 30: os_sig = SIGUSR1; break;
5273 #endif
5274 #ifdef SIGUSR2
5275 case 31: os_sig = SIGUSR2; break;
5276 #endif
5277 }
5278
5279 if (os_sig == -1)
5280 {
5281 trace_output_void (sd);
5282 (*cr16_callback->printf_filtered) (cr16_callback, "Unknown signal %d\n", PARM2);
5283 (*cr16_callback->flush_stdout) (cr16_callback);
5284 State.exception = SIGILL;
5285 }
5286 else
5287 {
5288 RETVAL (kill (PARM1, PARM2));
5289 trace_output_16 (sd, result);
5290 }
5291 }
5292 break;
5293
5294 #ifdef TARGET_SYS_execve
5295 case TARGET_SYS_execve:
5296 trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID);
5297 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3),
5298 (char **)MEMPTR (PARM4)));
5299 trace_output_16 (sd, result);
5300 break;
5301 #endif
5302
5303 #ifdef TARGET_SYS_execv
5304 case TARGET_SYS_execv:
5305 trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID);
5306 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
5307 trace_output_16 (sd, result);
5308 break;
5309 #endif
5310
5311 #ifdef TARGET_SYS_pipe
5312 case TARGET_SYS_pipe:
5313 {
5314 reg_t buf;
5315 int host_fd[2];
5316
5317 trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID);
5318 buf = PARM1;
5319 RETVAL (pipe (host_fd));
5320 SW (buf, host_fd[0]);
5321 buf += sizeof(uint16);
5322 SW (buf, host_fd[1]);
5323 trace_output_16 (sd, result);
5324 }
5325 break;
5326 #endif
5327
5328 #ifdef TARGET_SYS_wait
5329 case TARGET_SYS_wait:
5330 {
5331 int status;
5332 trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID);
5333 RETVAL (wait (&status));
5334 if (PARM1)
5335 SW (PARM1, status);
5336 trace_output_16 (sd, result);
5337 }
5338 break;
5339 #endif
5340 #else
5341 case TARGET_SYS_getpid:
5342 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5343 RETVAL (1);
5344 trace_output_16 (sd, result);
5345 break;
5346
5347 case TARGET_SYS_kill:
5348 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5349 trace_output_void (sd);
5350 State.exception = PARM2;
5351 break;
5352 #endif
5353
5354 case TARGET_SYS_read:
5355 trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG);
5356 RETVAL (cr16_callback->read (cr16_callback, PARM1,
5357 MEMPTR (((unsigned long)PARM3 << 16)
5358 |((unsigned long)PARM2)), PARM4));
5359 trace_output_16 (sd, result);
5360 break;
5361
5362 case TARGET_SYS_write:
5363 trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG);
5364 RETVAL ((int)cr16_callback->write (cr16_callback, PARM1,
5365 MEMPTR (((unsigned long)PARM3 << 16) | PARM2), PARM4));
5366 trace_output_16 (sd, result);
5367 break;
5368
5369 case TARGET_SYS_lseek:
5370 trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG);
5371 RETVAL32 (cr16_callback->lseek (cr16_callback, PARM1,
5372 ((((long) PARM3) << 16) | PARM2),
5373 PARM4));
5374 trace_output_32 (sd, result);
5375 break;
5376
5377 case TARGET_SYS_close:
5378 trace_input ("<close>", OP_REG, OP_VOID, OP_VOID);
5379 RETVAL (cr16_callback->close (cr16_callback, PARM1));
5380 trace_output_16 (sd, result);
5381 break;
5382
5383 case TARGET_SYS_open:
5384 trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID);
5385 RETVAL32 (cr16_callback->open (cr16_callback,
5386 MEMPTR ((((unsigned long)PARM2)<<16)|PARM1),
5387 PARM3));
5388 trace_output_32 (sd, result);
5389 break;
5390
5391 #ifdef TARGET_SYS_rename
5392 case TARGET_SYS_rename:
5393 trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID);
5394 RETVAL (cr16_callback->rename (cr16_callback,
5395 MEMPTR ((((unsigned long)PARM2)<<16) |PARM1),
5396 MEMPTR ((((unsigned long)PARM4)<<16) |PARM3)));
5397 trace_output_16 (sd, result);
5398 break;
5399 #endif
5400
5401 case 0x408: /* REVISIT: Added a dummy getenv call. */
5402 trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID);
5403 RETVAL32 (0);
5404 trace_output_32 (sd, result);
5405 break;
5406
5407 case TARGET_SYS_exit:
5408 trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID);
5409 State.exception = SIG_CR16_EXIT;
5410 trace_output_void (sd);
5411 break;
5412
5413 case TARGET_SYS_unlink:
5414 trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID);
5415 RETVAL (cr16_callback->unlink (cr16_callback,
5416 MEMPTR (((unsigned long)PARM2<<16)|PARM1)));
5417 trace_output_16 (sd, result);
5418 break;
5419
5420
5421 #ifdef TARGET_SYS_stat
5422 case TARGET_SYS_stat:
5423 trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID);
5424 /* stat system call. */
5425 {
5426 struct stat host_stat;
5427 reg_t buf;
5428
5429 RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat));
5430
5431 buf = PARM2;
5432
5433 /* The hard-coded offsets and sizes were determined by using
5434 * the CR16 compiler on a test program that used struct stat.
5435 */
5436 SW (buf, host_stat.st_dev);
5437 SW (buf+2, host_stat.st_ino);
5438 SW (buf+4, host_stat.st_mode);
5439 SW (buf+6, host_stat.st_nlink);
5440 SW (buf+8, host_stat.st_uid);
5441 SW (buf+10, host_stat.st_gid);
5442 SW (buf+12, host_stat.st_rdev);
5443 SLW (buf+16, host_stat.st_size);
5444 SLW (buf+20, host_stat.st_atime);
5445 SLW (buf+28, host_stat.st_mtime);
5446 SLW (buf+36, host_stat.st_ctime);
5447 }
5448 trace_output_16 (sd, result);
5449 break;
5450 #endif
5451
5452 #ifdef TARGET_SYS_chown
5453 case TARGET_SYS_chown:
5454 trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID);
5455 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
5456 trace_output_16 (sd, result);
5457 break;
5458 #endif
5459
5460 case TARGET_SYS_chmod:
5461 trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID);
5462 RETVAL (chmod (MEMPTR (PARM1), PARM2));
5463 trace_output_16 (sd, result);
5464 break;
5465
5466 #ifdef TARGET_SYS_utime
5467 case TARGET_SYS_utime:
5468 trace_input ("<utime>", OP_REG, OP_REG, OP_REG);
5469 /* Cast the second argument to void *, to avoid type mismatch
5470 if a prototype is present. */
5471 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
5472 trace_output_16 (sd, result);
5473 break;
5474 #endif
5475
5476 #ifdef TARGET_SYS_time
5477 case TARGET_SYS_time:
5478 trace_input ("<time>", OP_VOID, OP_VOID, OP_REG);
5479 RETVAL32 (time (NULL));
5480 trace_output_32 (sd, result);
5481 break;
5482 #endif
5483
5484 default:
5485 a = OP[0];
5486 switch (a)
5487 {
5488 case TRAP_BREAKPOINT:
5489 State.exception = SIGTRAP;
5490 tmp = (PC);
5491 JMP(tmp);
5492 trace_output_void (sd);
5493 break;
5494 case SIGTRAP: /* supervisor call ? */
5495 State.exception = SIG_CR16_EXIT;
5496 trace_output_void (sd);
5497 break;
5498 default:
5499 cr16_callback->error (cr16_callback, "Unknown syscall %d", FUNC);
5500 break;
5501 }
5502 }
5503 if ((uint16) result == (uint16) -1)
5504 RETERR (cr16_callback->get_errno(cr16_callback));
5505 else
5506 RETERR (0);
5507 break;
5508 }
5509 }
5510 }
5511
5512
5513 /* push. */
5514 void
5515 OP_3_9 (SIM_DESC sd, SIM_CPU *cpu)
5516 {
5517 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5518 uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
5519 trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
5520
5521 for (; i < a; ++i)
5522 {
5523 if ((b+i) <= 11)
5524 {
5525 SW (sp_addr, (GPR (b+i)));
5526 sp_addr +=2;
5527 }
5528 else
5529 {
5530 if (is_regp == 0)
5531 tmp = (GPR32 (b+i));
5532 else
5533 tmp = (GPR32 (b+i-1));
5534
5535 if ((a-i) > 1)
5536 {
5537 SLW (sp_addr, tmp);
5538 sp_addr +=4;
5539 }
5540 else
5541 {
5542 SW (sp_addr, tmp);
5543 sp_addr +=2;
5544 }
5545 ++i;
5546 is_regp = 1;
5547 }
5548 }
5549
5550 sp_addr +=4;
5551
5552 /* Store RA address. */
5553 tmp = (GPR32 (14));
5554 SLW(sp_addr,tmp);
5555
5556 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5557 SET_GPR32 (15, sp_addr); /* Update SP address. */
5558
5559 trace_output_void (sd);
5560 }
5561
5562 /* push. */
5563 void
5564 OP_1_8 (SIM_DESC sd, SIM_CPU *cpu)
5565 {
5566 uint32 sp_addr, tmp, is_regp = 0;
5567 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5568 trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
5569
5570 if (c == 1)
5571 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5572 else
5573 sp_addr = (GPR32 (15)) - (a * 2);
5574
5575 for (; i < a; ++i)
5576 {
5577 if ((b+i) <= 11)
5578 {
5579 SW (sp_addr, (GPR (b+i)));
5580 sp_addr +=2;
5581 }
5582 else
5583 {
5584 if (is_regp == 0)
5585 tmp = (GPR32 (b+i));
5586 else
5587 tmp = (GPR32 (b+i-1));
5588
5589 if ((a-i) > 1)
5590 {
5591 SLW (sp_addr, tmp);
5592 sp_addr +=4;
5593 }
5594 else
5595 {
5596 SW (sp_addr, tmp);
5597 sp_addr +=2;
5598 }
5599 ++i;
5600 is_regp = 1;
5601 }
5602 }
5603
5604 if (c == 1)
5605 {
5606 /* Store RA address. */
5607 tmp = (GPR32 (14));
5608 SLW(sp_addr,tmp);
5609 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5610 }
5611 else
5612 sp_addr = (GPR32 (15)) - (a * 2);
5613
5614 SET_GPR32 (15, sp_addr); /* Update SP address. */
5615
5616 trace_output_void (sd);
5617 }
5618
5619
5620 /* push. */
5621 void
5622 OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu)
5623 {
5624 uint32 sp_addr = (GPR32 (15)), tmp;
5625 trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
5626 tmp = (GPR32 (14));
5627 SLW(sp_addr-4,tmp); /* Store RA address. */
5628 SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */
5629 trace_output_void (sd);
5630 }
5631
5632
5633 /* pop. */
5634 void
5635 OP_5_9 (SIM_DESC sd, SIM_CPU *cpu)
5636 {
5637 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5638 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
5639 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
5640
5641 for (; i < a; ++i)
5642 {
5643 if ((b+i) <= 11)
5644 {
5645 SET_GPR ((b+i), RW(sp_addr));
5646 sp_addr +=2;
5647 }
5648 else
5649 {
5650 if ((a-i) > 1)
5651 {
5652 tmp = RLW(sp_addr);
5653 sp_addr +=4;
5654 }
5655 else
5656 {
5657 tmp = RW(sp_addr);
5658 sp_addr +=2;
5659
5660 if (is_regp == 0)
5661 tmp = (tmp << 16) | (GPR32 (b+i));
5662 else
5663 tmp = (tmp << 16) | (GPR32 (b+i-1));
5664 }
5665
5666 if (is_regp == 0)
5667 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)
5668 | ((tmp >> 16) & 0xffff)));
5669 else
5670 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)
5671 | ((tmp >> 16) & 0xffff)));
5672
5673 ++i;
5674 is_regp = 1;
5675 }
5676 }
5677
5678 tmp = RLW(sp_addr); /* store RA also. */
5679 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5680
5681 SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */
5682
5683 trace_output_void (sd);
5684 }
5685
5686 /* pop. */
5687 void
5688 OP_2_8 (SIM_DESC sd, SIM_CPU *cpu)
5689 {
5690 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5691 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;
5692 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
5693
5694 for (; i < a; ++i)
5695 {
5696 if ((b+i) <= 11)
5697 {
5698 SET_GPR ((b+i), RW(sp_addr));
5699 sp_addr +=2;
5700 }
5701 else
5702 {
5703 if ((a-i) > 1)
5704 {
5705 tmp = RLW(sp_addr);
5706 sp_addr +=4;
5707 }
5708 else
5709 {
5710 tmp = RW(sp_addr);
5711 sp_addr +=2;
5712
5713 if (is_regp == 0)
5714 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i));
5715 else
5716 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1));
5717 }
5718
5719 if (is_regp == 0)
5720 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5721 else
5722 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5723 ++i;
5724 is_regp = 1;
5725 }
5726 }
5727
5728 if (c == 1)
5729 {
5730 tmp = RLW(sp_addr); /* Store RA Reg. */
5731 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5732 sp_addr +=4;
5733 }
5734
5735 SET_GPR32 (15, sp_addr); /* Update SP address. */
5736
5737 trace_output_void (sd);
5738 }
5739
5740 /* pop. */
5741 void
5742 OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu)
5743 {
5744 uint32 sp_addr = GPR32 (15);
5745 uint32 tmp;
5746 trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
5747
5748 tmp = RLW(sp_addr);
5749 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5750 SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */
5751
5752 trace_output_void (sd);
5753 }
5754
5755 /* popret. */
5756 void
5757 OP_7_9 (SIM_DESC sd, SIM_CPU *cpu)
5758 {
5759 uint16 a = OP[0], b = OP[1];
5760 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
5761 OP_5_9 (sd, cpu);
5762 JMP(((GPR32(14)) << 1) & 0xffffff);
5763
5764 trace_output_void (sd);
5765 }
5766
5767 /* popret. */
5768 void
5769 OP_3_8 (SIM_DESC sd, SIM_CPU *cpu)
5770 {
5771 uint16 a = OP[0], b = OP[1];
5772 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
5773 OP_2_8 (sd, cpu);
5774 JMP(((GPR32(14)) << 1) & 0xffffff);
5775
5776 trace_output_void (sd);
5777 }
5778
5779 /* popret. */
5780 void
5781 OP_31E_10 (SIM_DESC sd, SIM_CPU *cpu)
5782 {
5783 uint32 tmp;
5784 trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
5785 OP_21E_10 (sd, cpu);
5786 tmp = (((GPR32(14)) << 1) & 0xffffff);
5787 /* If the resulting PC value is less than 0x00_0000 or greater
5788 than 0xFF_FFFF, this instruction causes an IAD trap.*/
5789
5790 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
5791 {
5792 State.exception = SIG_CR16_BUS;
5793 State.pc_changed = 1; /* Don't increment the PC. */
5794 trace_output_void (sd);
5795 return;
5796 }
5797 else
5798 JMP (tmp);
5799
5800 trace_output_32 (sd, tmp);
5801 }
5802
5803
5804 /* cinv[i]. */
5805 void
5806 OP_A_10 (SIM_DESC sd, SIM_CPU *cpu)
5807 {
5808 trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID);
5809 SET_PSR_I (1);
5810 trace_output_void (sd);
5811 }
5812
5813 /* cinv[i,u]. */
5814 void
5815 OP_B_10 (SIM_DESC sd, SIM_CPU *cpu)
5816 {
5817 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5818 SET_PSR_I (1);
5819 trace_output_void (sd);
5820 }
5821
5822 /* cinv[d]. */
5823 void
5824 OP_C_10 (SIM_DESC sd, SIM_CPU *cpu)
5825 {
5826 trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID);
5827 SET_PSR_I (1);
5828 trace_output_void (sd);
5829 }
5830
5831 /* cinv[d,u]. */
5832 void
5833 OP_D_10 (SIM_DESC sd, SIM_CPU *cpu)
5834 {
5835 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5836 SET_PSR_I (1);
5837 trace_output_void (sd);
5838 }
5839
5840 /* cinv[d,i]. */
5841 void
5842 OP_E_10 (SIM_DESC sd, SIM_CPU *cpu)
5843 {
5844 trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID);
5845 SET_PSR_I (1);
5846 trace_output_void (sd);
5847 }
5848
5849 /* cinv[d,i,u]. */
5850 void
5851 OP_F_10 (SIM_DESC sd, SIM_CPU *cpu)
5852 {
5853 trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID);
5854 SET_PSR_I (1);
5855 trace_output_void (sd);
5856 }
5857
5858 /* retx. */
5859 void
5860 OP_3_10 (SIM_DESC sd, SIM_CPU *cpu)
5861 {
5862 trace_input ("retx", OP_VOID, OP_VOID, OP_VOID);
5863 SET_PSR_I (1);
5864 trace_output_void (sd);
5865 }
5866
5867 /* di. */
5868 void
5869 OP_4_10 (SIM_DESC sd, SIM_CPU *cpu)
5870 {
5871 trace_input ("di", OP_VOID, OP_VOID, OP_VOID);
5872 SET_PSR_I (1);
5873 trace_output_void (sd);
5874 }
5875
5876 /* ei. */
5877 void
5878 OP_5_10 (SIM_DESC sd, SIM_CPU *cpu)
5879 {
5880 trace_input ("ei", OP_VOID, OP_VOID, OP_VOID);
5881 SET_PSR_I (1);
5882 trace_output_void (sd);
5883 }
5884
5885 /* wait. */
5886 void
5887 OP_6_10 (SIM_DESC sd, SIM_CPU *cpu)
5888 {
5889 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
5890 State.exception = SIGTRAP;
5891 trace_output_void (sd);
5892 }
5893
5894 /* ewait. */
5895 void
5896 OP_7_10 (SIM_DESC sd, SIM_CPU *cpu)
5897 {
5898 trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID);
5899 SET_PSR_I (1);
5900 trace_output_void (sd);
5901 }
5902
5903 /* xorb. */
5904 void
5905 OP_28_8 (SIM_DESC sd, SIM_CPU *cpu)
5906 {
5907 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5908 trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
5909 tmp = a ^ b;
5910 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5911 trace_output_16 (sd, tmp);
5912 }
5913
5914 /* xorb. */
5915 void
5916 OP_28B_C (SIM_DESC sd, SIM_CPU *cpu)
5917 {
5918 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5919 trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
5920 tmp = a ^ b;
5921 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5922 trace_output_16 (sd, tmp);
5923 }
5924
5925 /* xorb. */
5926 void
5927 OP_29_8 (SIM_DESC sd, SIM_CPU *cpu)
5928 {
5929 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
5930 trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
5931 tmp = a ^ b;
5932 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5933 trace_output_16 (sd, tmp);
5934 }
5935
5936 /* xorw. */
5937 void
5938 OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu)
5939 {
5940 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5941 trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
5942 tmp = a ^ b;
5943 SET_GPR (OP[1], tmp);
5944 trace_output_16 (sd, tmp);
5945 }
5946
5947 /* xorw. */
5948 void
5949 OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu)
5950 {
5951 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5952 trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
5953 tmp = a ^ b;
5954 SET_GPR (OP[1], tmp);
5955 trace_output_16 (sd, tmp);
5956 }
5957
5958 /* xorw. */
5959 void
5960 OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu)
5961 {
5962 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
5963 trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
5964 tmp = a ^ b;
5965 SET_GPR (OP[1], tmp);
5966 trace_output_16 (sd, tmp);
5967 }
5968
5969 /*REVISIT FOR LPR/SPR . */
5970
5971 /* lpr. */
5972 void
5973 OP_140_14 (SIM_DESC sd, SIM_CPU *cpu)
5974 {
5975 uint16 a = GPR (OP[0]);
5976 trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
5977 SET_CREG (OP[1], a);
5978 trace_output_16 (sd, a);
5979 }
5980
5981 /* lprd. */
5982 void
5983 OP_141_14 (SIM_DESC sd, SIM_CPU *cpu)
5984 {
5985 uint32 a = GPR32 (OP[0]);
5986 trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
5987 SET_CREG (OP[1], a);
5988 trace_output_flag (sd);
5989 }
5990
5991 /* spr. */
5992 void
5993 OP_142_14 (SIM_DESC sd, SIM_CPU *cpu)
5994 {
5995 uint16 a = CREG (OP[0]);
5996 trace_input ("spr", OP_REG, OP_REG, OP_VOID);
5997 SET_GPR (OP[1], a);
5998 trace_output_16 (sd, a);
5999 }
6000
6001 /* sprd. */
6002 void
6003 OP_143_14 (SIM_DESC sd, SIM_CPU *cpu)
6004 {
6005 uint32 a = CREG (OP[0]);
6006 trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
6007 SET_GPR32 (OP[1], a);
6008 trace_output_32 (sd, a);
6009 }
6010
6011 /* null. */
6012 void
6013 OP_0_20 (SIM_DESC sd, SIM_CPU *cpu)
6014 {
6015 trace_input ("null", OP_VOID, OP_VOID, OP_VOID);
6016 State.exception = SIG_CR16_STOP;
6017 }
GDB Binutils - Deliverables
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