db595f1849b4492f3a5e8b7df46344092f39c029
1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008-2015 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include <sys/types.h>
36 #ifdef HAVE_SYS_TIME_H
42 #include "targ-vals.h"
44 #ifdef TARGET_SYS_utime
47 #ifdef TARGET_SYS_wait
110 PSR_MASK
= (PSR_I_BIT
120 /* The following bits in the PSR _can't_ be set by instructions such
122 PSR_HW_MASK
= (PSR_MASK
)
125 /* cond Code Condition True State
126 * EQ Equal Z flag is 1
127 * NE Not Equal Z flag is 0
128 * CS Carry Set C flag is 1
129 * CC Carry Clear C flag is 0
130 * HI Higher L flag is 1
131 * LS Lower or Same L flag is 0
132 * GT Greater Than N flag is 1
133 * LE Less Than or Equal To N flag is 0
134 * FS Flag Set F flag is 1
135 * FC Flag Clear F flag is 0
136 * LO Lower Z and L flags are 0
137 * HS Higher or Same Z or L flag is 1
138 * LT Less Than Z and N flags are 0
139 * GE Greater Than or Equal To Z or N flag is 1. */
141 static int cond_stat(int cc
)
145 case 0: return PSR_Z
; break;
146 case 1: return !PSR_Z
; break;
147 case 2: return PSR_C
; break;
148 case 3: return !PSR_C
; break;
149 case 4: return PSR_L
; break;
150 case 5: return !PSR_L
; break;
151 case 6: return PSR_N
; break;
152 case 7: return !PSR_N
; break;
153 case 8: return PSR_F
; break;
154 case 9: return !PSR_F
; break;
155 case 10: return !PSR_Z
&& !PSR_L
; break;
156 case 11: return PSR_Z
|| PSR_L
; break;
157 case 12: return !PSR_Z
&& !PSR_N
; break;
158 case 13: return PSR_Z
|| PSR_N
; break;
159 case 14: return 1; break; /*ALWAYS. */
161 // case NEVER: return false; break;
163 //panic("Shouldn't have NO_COND_CODE in an actual instruction!");
171 move_to_cr (SIM_DESC sd
, SIM_CPU
*cpu
, int cr
, creg_t mask
, creg_t val
, int psw_hw_p
)
173 /* A MASK bit is set when the corresponding bit in the CR should
175 /* This assumes that (VAL & MASK) == 0. */
184 (*cr16_callback
->printf_filtered
)
186 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC
);
187 State
.exception
= SIGILL
;
189 /* keep an up-to-date psw around for tracing. */
190 State
.trace
.psw
= (State
.trace
.psw
& mask
) | val
;
195 /* only issue an update if the register is being changed. */
196 if ((State
.cregs
[cr
] & ~mask
) != val
)
197 SLOT_PEND_MASK (State
.cregs
[cr
], mask
, val
);
203 static void trace_input_func (SIM_DESC sd
,
209 #define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
211 #ifndef SIZE_INSTRUCTION
212 #define SIZE_INSTRUCTION 8
215 #ifndef SIZE_OPERANDS
216 #define SIZE_OPERANDS 18
220 #define SIZE_VALUES 13
223 #ifndef SIZE_LOCATION
224 #define SIZE_LOCATION 20
231 #ifndef SIZE_LINE_NUMBER
232 #define SIZE_LINE_NUMBER 2
236 trace_input_func (SIM_DESC sd
, const char *name
, enum op_types in1
, enum op_types in2
, enum op_types in3
)
245 const char *filename
;
246 const char *functionname
;
247 unsigned int linenumber
;
250 if ((cr16_debug
& DEBUG_TRACE
) == 0)
253 switch (State
.ins_type
)
256 case INS_UNKNOWN
: type
= " ?"; break;
259 if ((cr16_debug
& DEBUG_LINE_NUMBER
) == 0)
260 (*cr16_callback
->printf_filtered
) (cr16_callback
,
262 SIZE_PC
, (unsigned)PC
,
264 SIZE_INSTRUCTION
, name
);
270 if (STATE_TEXT_SECTION (sd
)
271 && byte_pc
>= STATE_TEXT_START (sd
)
272 && byte_pc
< STATE_TEXT_END (sd
))
274 filename
= (const char *)0;
275 functionname
= (const char *)0;
277 if (bfd_find_nearest_line (STATE_PROG_BFD (sd
),
278 STATE_TEXT_SECTION (sd
),
279 (struct bfd_symbol
**)0,
280 byte_pc
- STATE_TEXT_START (sd
),
281 &filename
, &functionname
, &linenumber
))
286 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
291 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
292 p
+= SIZE_LINE_NUMBER
+2;
297 sprintf (p
, "%s ", functionname
);
302 char *q
= strrchr (filename
, '/');
303 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
312 (*cr16_callback
->printf_filtered
) (cr16_callback
,
313 "0x%.*x %s: %-*.*s %-*s ",
314 SIZE_PC
, (unsigned)PC
,
316 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
317 SIZE_INSTRUCTION
, name
);
325 for (i
= 0; i
< 3; i
++)
334 sprintf (p
, "%sr%d", comma
, OP
[i
]);
340 sprintf (p
, "%scr%d", comma
, OP
[i
]);
346 sprintf (p
, "%s%d", comma
, OP
[i
]);
352 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
358 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
364 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
370 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
376 sprintf (p
, "%s@%d", comma
, OP
[i
]);
383 if ((cr16_debug
& DEBUG_VALUES
) == 0)
387 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%s", buf
);
392 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%-*s", SIZE_OPERANDS
, buf
);
395 for (i
= 0; i
< 3; i
++)
401 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s", SIZE_VALUES
, "");
405 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
406 (uint16
) GPR (OP
[i
]));
410 tmp
= (long)((((uint32
) GPR (OP
[i
])) << 16) | ((uint32
) GPR (OP
[i
] + 1)));
411 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
415 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
416 (uint16
) CREG (OP
[i
]));
420 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
425 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
426 (uint16
)SEXT4(OP
[i
]));
430 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
431 (uint16
)SEXT3(OP
[i
]));
435 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
437 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
438 (uint16
)GPR (OP
[i
+ 1]));
445 (*cr16_callback
->flush_stdout
) (cr16_callback
);
449 do_trace_output_flush (SIM_DESC sd
)
451 (*cr16_callback
->flush_stdout
) (cr16_callback
);
455 do_trace_output_finish (SIM_DESC sd
)
457 (*cr16_callback
->printf_filtered
) (cr16_callback
,
458 " F0=%d F1=%d C=%d\n",
459 (State
.trace
.psw
& PSR_F_BIT
) != 0,
460 (State
.trace
.psw
& PSR_F_BIT
) != 0,
461 (State
.trace
.psw
& PSR_C_BIT
) != 0);
462 (*cr16_callback
->flush_stdout
) (cr16_callback
);
467 trace_output_40 (SIM_DESC sd
, uint64 val
)
469 if ((cr16_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
471 (*cr16_callback
->printf_filtered
) (cr16_callback
,
472 " :: %*s0x%.2x%.8lx",
475 ((int)(val
>> 32) & 0xff),
476 ((unsigned long) val
) & 0xffffffff);
477 do_trace_output_finish ();
483 trace_output_32 (SIM_DESC sd
, uint32 val
)
485 if ((cr16_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
487 (*cr16_callback
->printf_filtered
) (cr16_callback
,
492 do_trace_output_finish (sd
);
497 trace_output_16 (SIM_DESC sd
, uint16 val
)
499 if ((cr16_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
501 (*cr16_callback
->printf_filtered
) (cr16_callback
,
506 do_trace_output_finish (sd
);
511 trace_output_void (SIM_DESC sd
)
513 if ((cr16_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
515 (*cr16_callback
->printf_filtered
) (cr16_callback
, "\n");
516 do_trace_output_flush (sd
);
521 trace_output_flag (SIM_DESC sd
)
523 if ((cr16_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
525 (*cr16_callback
->printf_filtered
) (cr16_callback
,
529 do_trace_output_finish (sd
);
537 #define trace_input(NAME, IN1, IN2, IN3)
538 #define trace_output(RESULT)
543 OP_2C_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
546 uint8 a
= OP
[0] & 0xff;
547 uint16 b
= (GPR (OP
[1])) & 0xff;
548 trace_input ("addub", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
549 tmp
= (a
+ b
) & 0xff;
550 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
551 trace_output_16 (sd
, tmp
);
556 OP_2CB_C (SIM_DESC sd
, SIM_CPU
*cpu
)
559 uint8 a
= ((OP
[0]) & 0xff), b
= (GPR (OP
[1])) & 0xff;
560 trace_input ("addub", OP_CONSTANT16
, OP_REG
, OP_VOID
);
561 tmp
= (a
+ b
) & 0xff;
562 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
563 trace_output_16 (sd
, tmp
);
568 OP_2D_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
570 uint8 a
= (GPR (OP
[0])) & 0xff;
571 uint8 b
= (GPR (OP
[1])) & 0xff;
572 uint16 tmp
= (a
+ b
) & 0xff;
573 trace_input ("addub", OP_REG
, OP_REG
, OP_VOID
);
574 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
575 trace_output_16 (sd
, tmp
);
580 OP_2E_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
583 uint16 b
= GPR (OP
[1]);
584 uint16 tmp
= (a
+ b
);
585 trace_input ("adduw", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
586 SET_GPR (OP
[1], tmp
);
587 trace_output_16 (sd
, tmp
);
592 OP_2EB_C (SIM_DESC sd
, SIM_CPU
*cpu
)
595 uint16 b
= GPR (OP
[1]);
596 uint16 tmp
= (a
+ b
);
597 trace_input ("adduw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
598 SET_GPR (OP
[1], tmp
);
599 trace_output_16 (sd
, tmp
);
604 OP_2F_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
606 uint16 a
= GPR (OP
[0]);
607 uint16 b
= GPR (OP
[1]);
608 uint16 tmp
= (a
+ b
);
609 trace_input ("adduw", OP_REG
, OP_REG
, OP_VOID
);
610 SET_GPR (OP
[1], tmp
);
611 trace_output_16 (sd
, tmp
);
616 OP_30_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
619 uint8 b
= (GPR (OP
[1]) & 0xff);
620 uint16 tmp
= (a
+ b
) & 0xff;
621 trace_input ("addb", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
622 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
623 SET_PSR_C (tmp
> 0xFF);
624 SET_PSR_F (((a
& 0x80) == (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
625 trace_output_16 (sd
, tmp
);
630 OP_30B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
632 uint8 a
= (OP
[0]) & 0xff;
633 uint8 b
= (GPR (OP
[1]) & 0xff);
634 uint16 tmp
= (a
+ b
) & 0xff;
635 trace_input ("addb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
636 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
637 SET_PSR_C (tmp
> 0xFF);
638 SET_PSR_F (((a
& 0x80) == (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
639 trace_output_16 (sd
, tmp
);
644 OP_31_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
646 uint8 a
= (GPR (OP
[0]) & 0xff);
647 uint8 b
= (GPR (OP
[1]) & 0xff);
648 uint16 tmp
= (a
+ b
) & 0xff;
649 trace_input ("addb", OP_REG
, OP_REG
, OP_VOID
);
650 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
651 SET_PSR_C (tmp
> 0xFF);
652 SET_PSR_F (((a
& 0x80) == (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
653 trace_output_16 (sd
, tmp
);
658 OP_32_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
661 uint16 tmp
, b
= GPR (OP
[1]);
663 trace_input ("addw", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
664 SET_GPR (OP
[1], tmp
);
665 SET_PSR_C (tmp
> 0xFFFF);
666 SET_PSR_F (((a
& 0x8000) == (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
667 trace_output_16 (sd
, tmp
);
672 OP_32B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
675 uint16 tmp
, b
= GPR (OP
[1]);
677 trace_input ("addw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
678 SET_GPR (OP
[1], tmp
);
679 SET_PSR_C (tmp
> 0xFFFF);
680 SET_PSR_F (((a
& 0x8000) == (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
681 trace_output_16 (sd
, tmp
);
686 OP_33_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
688 uint16 tmp
, a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
689 trace_input ("addw", OP_REG
, OP_REG
, OP_VOID
);
691 SET_GPR (OP
[1], tmp
);
692 SET_PSR_C (tmp
> 0xFFFF);
693 SET_PSR_F (((a
& 0x8000) == (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
694 trace_output_16 (sd
, tmp
);
699 OP_34_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
701 uint8 tmp
, a
= OP
[0] & 0xff, b
= (GPR (OP
[1])) & 0xff;
702 trace_input ("addcb", OP_CONSTANT4_1
, OP_REG
, OP_REG
);
703 tmp
= (a
+ b
+ PSR_C
) & 0xff;
704 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
705 SET_PSR_C (tmp
> 0xFF);
706 SET_PSR_F (((a
& 0x80) == (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
707 trace_output_16 (sd
, tmp
);
712 OP_34B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
714 int8 a
= OP
[0] & 0xff;
715 uint8 b
= (GPR (OP
[1])) & 0xff;
716 uint8 tmp
= (a
+ b
+ PSR_C
) & 0xff;
717 trace_input ("addcb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
718 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
719 SET_PSR_C (tmp
> 0xFF);
720 SET_PSR_F (((a
& 0x80) == (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
721 trace_output_16 (sd
, tmp
);
726 OP_35_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
728 uint8 a
= (GPR (OP
[0])) & 0xff;
729 uint8 b
= (GPR (OP
[1])) & 0xff;
730 uint8 tmp
= (a
+ b
+ PSR_C
) & 0xff;
731 trace_input ("addcb", OP_REG
, OP_REG
, OP_VOID
);
732 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
733 SET_PSR_C (tmp
> 0xFF);
734 SET_PSR_F (((a
& 0x80) == (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
735 trace_output_16 (sd
, tmp
);
740 OP_36_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
743 uint16 b
= GPR (OP
[1]);
744 uint16 tmp
= (a
+ b
+ PSR_C
);
745 trace_input ("addcw", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
746 SET_GPR (OP
[1], tmp
);
747 SET_PSR_C (tmp
> 0xFFFF);
748 SET_PSR_F (((a
& 0x8000) == (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
749 trace_output_16 (sd
, tmp
);
754 OP_36B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
757 uint16 b
= GPR (OP
[1]);
758 uint16 tmp
= (a
+ b
+ PSR_C
);
759 trace_input ("addcw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
760 SET_GPR (OP
[1], tmp
);
761 SET_PSR_C (tmp
> 0xFFFF);
762 SET_PSR_F (((a
& 0x8000) == (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
763 trace_output_16 (sd
, tmp
);
768 OP_37_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
770 uint16 a
= GPR (OP
[1]);
771 uint16 b
= GPR (OP
[1]);
772 uint16 tmp
= (a
+ b
+ PSR_C
);
773 trace_input ("addcw", OP_REG
, OP_REG
, OP_VOID
);
774 SET_GPR (OP
[1], tmp
);
775 SET_PSR_C (tmp
> 0xFFFF);
776 SET_PSR_F (((a
& 0x8000) == (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
777 trace_output_16 (sd
, tmp
);
782 OP_60_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
785 uint32 b
= GPR32 (OP
[1]);
786 uint32 tmp
= (a
+ b
);
787 trace_input ("addd", OP_CONSTANT4_1
, OP_REGP
, OP_VOID
);
788 SET_GPR32 (OP
[1], tmp
);
789 SET_PSR_C (tmp
> 0xFFFFFFFF);
790 SET_PSR_F (((a
& 0x80000000) == (b
& 0x80000000)) && ((b
& 0x80000000) != (tmp
& 0x80000000)));
791 trace_output_32 (sd
, tmp
);
796 OP_60B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
798 int32 a
= (SEXT16(OP
[0]));
799 uint32 b
= GPR32 (OP
[1]);
800 uint32 tmp
= (a
+ b
);
801 trace_input ("addd", OP_CONSTANT16
, OP_REGP
, OP_VOID
);
802 SET_GPR32 (OP
[1], tmp
);
803 SET_PSR_C (tmp
> 0xFFFFFFFF);
804 SET_PSR_F (((a
& 0x80000000) == (b
& 0x80000000)) && ((b
& 0x80000000) != (tmp
& 0x80000000)));
805 trace_output_32 (sd
, tmp
);
810 OP_61_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
812 uint32 a
= GPR32 (OP
[0]);
813 uint32 b
= GPR32 (OP
[1]);
814 uint32 tmp
= (a
+ b
);
815 trace_input ("addd", OP_REGP
, OP_REGP
, OP_VOID
);
816 SET_GPR32 (OP
[1], tmp
);
817 trace_output_32 (sd
, tmp
);
818 SET_PSR_C (tmp
> 0xFFFFFFFF);
819 SET_PSR_F (((a
& 0x80000000) == (b
& 0x80000000)) && ((b
& 0x80000000) != (tmp
& 0x80000000)));
824 OP_4_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
827 uint32 b
= GPR32 (OP
[1]);
829 trace_input ("addd", OP_CONSTANT20
, OP_REGP
, OP_VOID
);
831 SET_GPR32 (OP
[1], tmp
);
832 SET_PSR_C (tmp
> 0xFFFFFFFF);
833 SET_PSR_F (((a
& 0x80000000) == (b
& 0x80000000)) && ((b
& 0x80000000) != (tmp
& 0x80000000)));
834 trace_output_32 (sd
, tmp
);
839 OP_2_C (SIM_DESC sd
, SIM_CPU
*cpu
)
842 uint32 b
= GPR32 (OP
[1]);
844 trace_input ("addd", OP_CONSTANT32
, OP_REGP
, OP_VOID
);
846 SET_GPR32 (OP
[1], tmp
);
847 SET_PSR_C (tmp
> 0xFFFFFFFF);
848 SET_PSR_F (((a
& 0x80000000) == (b
& 0x80000000)) && ((b
& 0x80000000) != (tmp
& 0x80000000)));
849 trace_output_32 (sd
, tmp
);
854 OP_20_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
856 uint8 tmp
, a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
857 trace_input ("andb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
859 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
860 trace_output_16 (sd
, tmp
);
865 OP_20B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
867 uint8 tmp
, a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
868 trace_input ("andb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
870 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
871 trace_output_16 (sd
, tmp
);
876 OP_21_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
878 uint8 tmp
, a
= (GPR (OP
[0])) & 0xff, b
= (GPR (OP
[1])) & 0xff;
879 trace_input ("andb", OP_REG
, OP_REG
, OP_VOID
);
881 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
882 trace_output_16 (sd
, tmp
);
887 OP_22_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
889 uint16 tmp
, a
= OP
[0], b
= GPR (OP
[1]);
890 trace_input ("andw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
892 SET_GPR (OP
[1], tmp
);
893 trace_output_16 (sd
, tmp
);
898 OP_22B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
900 uint16 tmp
, a
= OP
[0], b
= GPR (OP
[1]);
901 trace_input ("andw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
903 SET_GPR (OP
[1], tmp
);
904 trace_output_16 (sd
, tmp
);
909 OP_23_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
911 uint16 tmp
, a
= GPR (OP
[0]), b
= GPR (OP
[1]);
912 trace_input ("andw", OP_REG
, OP_REG
, OP_VOID
);
914 SET_GPR (OP
[1], tmp
);
915 trace_output_16 (sd
, tmp
);
920 OP_4_C (SIM_DESC sd
, SIM_CPU
*cpu
)
922 uint32 tmp
, a
= OP
[0], b
= GPR32 (OP
[1]);
923 trace_input ("andd", OP_CONSTANT32
, OP_REGP
, OP_VOID
);
925 SET_GPR32 (OP
[1], tmp
);
926 trace_output_32 (sd
, tmp
);
931 OP_14B_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
933 uint32 tmp
, a
= (GPR32 (OP
[0])), b
= (GPR32 (OP
[1]));
934 trace_input ("andd", OP_REGP
, OP_REGP
, OP_VOID
);
936 SET_GPR32 (OP
[1], tmp
);
937 trace_output_32 (sd
, tmp
);
942 OP_5_C (SIM_DESC sd
, SIM_CPU
*cpu
)
944 uint32 tmp
, a
= (OP
[0]), b
= GPR32 (OP
[1]);
945 trace_input ("ord", OP_CONSTANT32
, OP_REG
, OP_VOID
);
947 SET_GPR32 (OP
[1], tmp
);
948 trace_output_32 (sd
, tmp
);
953 OP_149_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
955 uint32 tmp
, a
= GPR32 (OP
[0]), b
= GPR32 (OP
[1]);
956 trace_input ("ord", OP_REGP
, OP_REGP
, OP_VOID
);
958 SET_GPR32 (OP
[1], tmp
);
959 trace_output_32 (sd
, tmp
);
964 OP_6_C (SIM_DESC sd
, SIM_CPU
*cpu
)
966 uint32 tmp
, a
= (OP
[0]), b
= GPR32 (OP
[1]);
967 trace_input ("xord", OP_CONSTANT32
, OP_REG
, OP_VOID
);
969 SET_GPR32 (OP
[1], tmp
);
970 trace_output_32 (sd
, tmp
);
975 OP_14A_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
977 uint32 tmp
, a
= GPR32 (OP
[0]), b
= GPR32 (OP
[1]);
978 trace_input ("xord", OP_REGP
, OP_REGP
, OP_VOID
);
980 SET_GPR32 (OP
[1], tmp
);
981 trace_output_32 (sd
, tmp
);
987 OP_1_4 (SIM_DESC sd
, SIM_CPU
*cpu
)
989 uint32 tmp
= 0, cc
= cond_stat (OP
[0]);
990 trace_input ("b", OP_CONSTANT4
, OP_DISPE9
, OP_VOID
);
994 tmp
= (PC
- (OP
[1]));
996 tmp
= (PC
+ (OP
[1]));
997 /* If the resulting PC value is less than 0x00_0000 or greater
998 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1000 if ((tmp
< 0x000000) || (tmp
> 0xFFFFFF))
1002 State
.exception
= SIG_CR16_BUS
;
1003 State
.pc_changed
= 1; /* Don't increment the PC. */
1004 trace_output_void (sd
);
1010 sign_flag
= 0; /* Reset sign_flag. */
1011 trace_output_32 (sd
, tmp
);
1016 OP_18_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
1018 uint32 tmp
= 0, cc
= cond_stat (OP
[0]);
1019 trace_input ("b", OP_CONSTANT4
, OP_DISP17
, OP_VOID
);
1026 /* If the resulting PC value is less than 0x00_0000 or greater
1027 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1029 if ((tmp
< 0x000000) || (tmp
> 0xFFFFFF))
1031 State
.exception
= SIG_CR16_BUS
;
1032 State
.pc_changed
= 1; /* Don't increment the PC. */
1033 trace_output_void (sd
);
1039 sign_flag
= 0; /* Reset sign_flag. */
1040 trace_output_32 (sd
, tmp
);
1045 OP_10_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
1047 uint32 tmp
= 0, cc
= cond_stat (OP
[0]);
1048 trace_input ("b", OP_CONSTANT4
, OP_DISP25
, OP_VOID
);
1052 tmp
= (PC
- (OP
[1]));
1054 tmp
= (PC
+ (OP
[1]));
1055 /* If the resulting PC value is less than 0x00_0000 or greater
1056 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1058 if ((tmp
< 0x000000) || (tmp
> 0xFFFFFF))
1060 State
.exception
= SIG_CR16_BUS
;
1061 State
.pc_changed
= 1; /* Don't increment the PC. */
1062 trace_output_void (sd
);
1068 sign_flag
= 0; /* Reset sign_flag. */
1069 trace_output_32 (sd
, tmp
);
1074 OP_C0_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
1077 trace_input ("bal", OP_REG
, OP_DISP17
, OP_VOID
);
1078 tmp
= ((PC
+ 4) >> 1); /* Store PC in RA register. */
1079 SET_GPR32 (14, tmp
);
1081 tmp
= (PC
- (OP
[1]));
1083 tmp
= (PC
+ (OP
[1]));
1085 /* If the resulting PC value is less than 0x00_0000 or greater
1086 than 0xFF_FFFF, this instruction causes an IAD trap. */
1088 if ((tmp
< 0x000000) || (tmp
> 0xFFFFFF))
1090 State
.exception
= SIG_CR16_BUS
;
1091 State
.pc_changed
= 1; /* Don't increment the PC. */
1092 trace_output_void (sd
);
1097 sign_flag
= 0; /* Reset sign_flag. */
1098 trace_output_32 (sd
, tmp
);
1104 OP_102_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
1107 trace_input ("bal", OP_REGP
, OP_DISP25
, OP_VOID
);
1108 tmp
= (((PC
) + 4) >> 1); /* Store PC in reg pair. */
1109 SET_GPR32 (OP
[0], tmp
);
1111 tmp
= ((PC
) - (OP
[1]));
1113 tmp
= ((PC
) + (OP
[1]));
1114 /* If the resulting PC value is less than 0x00_0000 or greater
1115 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1117 if ((tmp
< 0x000000) || (tmp
> 0xFFFFFF))
1119 State
.exception
= SIG_CR16_BUS
;
1120 State
.pc_changed
= 1; /* Don't increment the PC. */
1121 trace_output_void (sd
);
1126 sign_flag
= 0; /* Reset sign_flag. */
1127 trace_output_32 (sd
, tmp
);
1132 OP_148_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
1135 trace_input ("jal", OP_REGP
, OP_REGP
, OP_VOID
);
1136 SET_GPR32 (OP
[0], (((PC
) + 4) >> 1)); /* Store next PC in RA */
1137 tmp
= GPR32 (OP
[1]);
1138 tmp
= SEXT24(tmp
<< 1);
1139 /* If the resulting PC value is less than 0x00_0000 or greater
1140 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1142 if ((tmp
< 0x0) || (tmp
> 0xFFFFFF))
1144 State
.exception
= SIG_CR16_BUS
;
1145 State
.pc_changed
= 1; /* Don't increment the PC. */
1146 trace_output_void (sd
);
1152 trace_output_32 (sd
, tmp
);
1158 OP_D_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1161 trace_input ("jal", OP_REGP
, OP_VOID
, OP_VOID
);
1162 SET_GPR32 (14, (((PC
) + 2) >> 1)); /* Store next PC in RA */
1163 tmp
= GPR32 (OP
[0]);
1164 tmp
= SEXT24(tmp
<< 1);
1165 /* If the resulting PC value is less than 0x00_0000 or greater
1166 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1168 if ((tmp
< 0x0) || (tmp
> 0xFFFFFF))
1170 State
.exception
= SIG_CR16_BUS
;
1171 State
.pc_changed
= 1; /* Don't increment the PC. */
1172 trace_output_void (sd
);
1178 trace_output_32 (sd
, tmp
);
1184 OP_C_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
1187 uint8 a
= (GPR (OP
[0]) & 0xFF);
1188 trace_input ("beq0b", OP_REG
, OP_DISP5
, OP_VOID
);
1193 addr
= (PC
- OP
[1]);
1195 addr
= (PC
+ OP
[1]);
1199 sign_flag
= 0; /* Reset sign_flag. */
1200 trace_output_void (sd
);
1205 OP_D_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
1208 uint8 a
= (GPR (OP
[0]) & 0xFF);
1209 trace_input ("bne0b", OP_REG
, OP_DISP5
, OP_VOID
);
1214 addr
= (PC
- OP
[1]);
1216 addr
= (PC
+ OP
[1]);
1220 sign_flag
= 0; /* Reset sign_flag. */
1221 trace_output_void (sd
);
1226 OP_E_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
1229 uint16 a
= GPR (OP
[0]);
1230 trace_input ("beq0w", OP_REG
, OP_DISP5
, OP_VOID
);
1235 addr
= (PC
- OP
[1]);
1237 addr
= (PC
+ OP
[1]);
1241 sign_flag
= 0; /* Reset sign_flag. */
1242 trace_output_void (sd
);
1247 OP_F_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
1250 uint16 a
= GPR (OP
[0]);
1251 trace_input ("bne0w", OP_REG
, OP_DISP5
, OP_VOID
);
1256 addr
= (PC
- OP
[1]);
1258 addr
= (PC
+ OP
[1]);
1262 sign_flag
= 0; /* Reset sign_flag. */
1263 trace_output_void (sd
);
1269 OP_A0_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1272 trace_input ("jeq", OP_REGP
, OP_VOID
, OP_VOID
);
1275 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1276 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1278 trace_output_32 (sd
, tmp
);
1283 OP_A1_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1286 trace_input ("jne", OP_REGP
, OP_VOID
, OP_VOID
);
1289 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1290 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1292 trace_output_32 (sd
, tmp
);
1297 OP_A2_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1300 trace_input ("jcs", OP_REGP
, OP_VOID
, OP_VOID
);
1303 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1304 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1306 trace_output_32 (sd
, tmp
);
1311 OP_A3_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1314 trace_input ("jcc", OP_REGP
, OP_VOID
, OP_VOID
);
1317 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1318 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1320 trace_output_32 (sd
, tmp
);
1325 OP_A4_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1328 trace_input ("jhi", OP_REGP
, OP_VOID
, OP_VOID
);
1331 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1332 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1334 trace_output_32 (sd
, tmp
);
1339 OP_A5_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1342 trace_input ("jls", OP_REGP
, OP_VOID
, OP_VOID
);
1345 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1346 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1348 trace_output_32 (sd
, tmp
);
1353 OP_A6_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1356 trace_input ("jgt", OP_REGP
, OP_VOID
, OP_VOID
);
1359 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1360 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1362 trace_output_32 (sd
, tmp
);
1367 OP_A7_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1370 trace_input ("jle", OP_REGP
, OP_VOID
, OP_VOID
);
1373 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1374 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1376 trace_output_32 (sd
, tmp
);
1382 OP_A8_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1385 trace_input ("jfs", OP_REGP
, OP_VOID
, OP_VOID
);
1388 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1389 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1391 trace_output_32 (sd
, tmp
);
1396 OP_A9_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1399 trace_input ("jfc", OP_REGP
, OP_VOID
, OP_VOID
);
1402 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1403 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1405 trace_output_32 (sd
, tmp
);
1410 OP_AA_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1413 trace_input ("jlo", OP_REGP
, OP_VOID
, OP_VOID
);
1414 if (((PSR_Z
) == 0) & ((PSR_L
) == 0))
1416 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1417 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1419 trace_output_32 (sd
, tmp
);
1424 OP_AB_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1427 trace_input ("jhs", OP_REGP
, OP_VOID
, OP_VOID
);
1428 if (((PSR_Z
) == 1) | ((PSR_L
) == 1))
1430 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1431 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1433 trace_output_32 (sd
, tmp
);
1438 OP_AC_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1441 trace_input ("jlt", OP_REGP
, OP_VOID
, OP_VOID
);
1442 if (((PSR_Z
) == 0) & ((PSR_N
) == 0))
1444 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1445 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1447 trace_output_32 (sd
, tmp
);
1452 OP_AD_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1455 trace_input ("jge", OP_REGP
, OP_VOID
, OP_VOID
);
1456 if (((PSR_Z
) == 1) | ((PSR_N
) == 1))
1458 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1459 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1461 trace_output_32 (sd
, tmp
);
1466 OP_AE_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1469 trace_input ("jump", OP_REGP
, OP_VOID
, OP_VOID
);
1470 tmp
= GPR32 (OP
[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
1471 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1472 trace_output_32 (sd
, tmp
);
1477 OP_AF_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1480 trace_input ("jusr", OP_REGP
, OP_VOID
, OP_VOID
);
1481 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1482 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1484 trace_output_32 (sd
, tmp
);
1489 OP_80_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1491 trace_input ("seq", OP_REG
, OP_VOID
, OP_VOID
);
1496 trace_output_void (sd
);
1500 OP_81_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1502 trace_input ("sne", OP_REG
, OP_VOID
, OP_VOID
);
1507 trace_output_void (sd
);
1512 OP_82_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1514 trace_input ("scs", OP_REG
, OP_VOID
, OP_VOID
);
1519 trace_output_void (sd
);
1524 OP_83_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1526 trace_input ("scc", OP_REG
, OP_VOID
, OP_VOID
);
1531 trace_output_void (sd
);
1536 OP_84_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1538 trace_input ("shi", OP_REG
, OP_VOID
, OP_VOID
);
1543 trace_output_void (sd
);
1548 OP_85_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1550 trace_input ("sls", OP_REG
, OP_VOID
, OP_VOID
);
1555 trace_output_void (sd
);
1560 OP_86_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1562 trace_input ("sgt", OP_REG
, OP_VOID
, OP_VOID
);
1567 trace_output_void (sd
);
1572 OP_87_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1574 trace_input ("sle", OP_REG
, OP_VOID
, OP_VOID
);
1579 trace_output_void (sd
);
1584 OP_88_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1586 trace_input ("sfs", OP_REG
, OP_VOID
, OP_VOID
);
1591 trace_output_void (sd
);
1596 OP_89_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1598 trace_input ("sfc", OP_REG
, OP_VOID
, OP_VOID
);
1603 trace_output_void (sd
);
1609 OP_8A_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1611 trace_input ("slo", OP_REG
, OP_VOID
, OP_VOID
);
1612 if (((PSR_Z
) == 0) & ((PSR_L
) == 0))
1616 trace_output_void (sd
);
1621 OP_8B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1623 trace_input ("shs", OP_REG
, OP_VOID
, OP_VOID
);
1624 if ( ((PSR_Z
) == 1) | ((PSR_L
) == 1))
1628 trace_output_void (sd
);
1633 OP_8C_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1635 trace_input ("slt", OP_REG
, OP_VOID
, OP_VOID
);
1636 if (((PSR_Z
) == 0) & ((PSR_N
) == 0))
1640 trace_output_void (sd
);
1645 OP_8D_C (SIM_DESC sd
, SIM_CPU
*cpu
)
1647 trace_input ("sge", OP_REG
, OP_VOID
, OP_VOID
);
1648 if (((PSR_Z
) == 1) | ((PSR_N
) == 1))
1652 trace_output_void (sd
);
1657 OP_D7_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
1659 uint8 a
= OP
[0] & 0xff;
1660 uint32 addr
= OP
[1], tmp
;
1661 trace_input ("cbitb", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
1663 SET_PSR_F (tmp
& (1 << a
));
1664 tmp
= tmp
& ~(1 << a
);
1666 trace_output_32 (sd
, tmp
);
1671 OP_107_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
1673 uint8 a
= OP
[0] & 0xff;
1674 uint32 addr
= OP
[1], tmp
;
1675 trace_input ("cbitb", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
1677 SET_PSR_F (tmp
& (1 << a
));
1678 tmp
= tmp
& ~(1 << a
);
1680 trace_output_32 (sd
, tmp
);
1685 OP_68_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
1687 uint8 a
= (OP
[0]) & 0xff;
1688 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
1689 trace_input ("cbitb", OP_CONSTANT4
, OP_R_INDEX7_ABS20
, OP_VOID
);
1691 SET_PSR_F (tmp
& (1 << a
));
1692 tmp
= tmp
& ~(1 << a
);
1694 trace_output_32 (sd
, addr
);
1699 OP_1AA_A (SIM_DESC sd
, SIM_CPU
*cpu
)
1701 uint8 a
= (OP
[0]) & 0xff;
1702 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1703 trace_input ("cbitb", OP_CONSTANT4
, OP_RP_INDEX_DISP14
, OP_VOID
);
1705 SET_PSR_F (tmp
& (1 << a
));
1706 tmp
= tmp
& ~(1 << a
);
1708 trace_output_32 (sd
, addr
);
1713 OP_104_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
1715 uint8 a
= (OP
[0]) & 0xff;
1716 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
1717 trace_input ("cbitb", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
1719 SET_PSR_F (tmp
& (1 << a
));
1720 tmp
= tmp
& ~(1 << a
);
1722 trace_output_32 (sd
, addr
);
1727 OP_D4_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
1729 uint8 a
= (OP
[0]) & 0xff;
1730 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1731 trace_input ("cbitb", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
1733 SET_PSR_F (tmp
& (1 << a
));
1734 tmp
= tmp
& ~(1 << a
);
1736 trace_output_32 (sd
, addr
);
1741 OP_D6_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
1743 uint8 a
= (OP
[0]) & 0xff;
1744 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1745 trace_input ("cbitb", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
1747 SET_PSR_F (tmp
& (1 << a
));
1748 tmp
= tmp
& ~(1 << a
);
1750 trace_output_32 (sd
, addr
);
1756 OP_105_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
1758 uint8 a
= (OP
[0]) & 0xff;
1759 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1760 trace_input ("cbitb", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
1762 SET_PSR_F (tmp
& (1 << a
));
1763 tmp
= tmp
& ~(1 << a
);
1765 trace_output_32 (sd
, addr
);
1770 OP_106_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
1772 uint8 a
= (OP
[0]) & 0xff;
1773 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1774 trace_input ("cbitb", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
1776 SET_PSR_F (tmp
& (1 << a
));
1777 tmp
= tmp
& ~(1 << a
);
1779 trace_output_32 (sd
, addr
);
1785 OP_6F_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
1788 uint32 addr
= OP
[1], tmp
;
1789 trace_input ("cbitw", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
1791 SET_PSR_F (tmp
& (1 << a
));
1792 tmp
= tmp
& ~(1 << a
);
1794 trace_output_32 (sd
, tmp
);
1799 OP_117_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
1802 uint32 addr
= OP
[1], tmp
;
1803 trace_input ("cbitw", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
1805 SET_PSR_F (tmp
& (1 << a
));
1806 tmp
= tmp
& ~(1 << a
);
1808 trace_output_32 (sd
, tmp
);
1813 OP_36_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
1816 uint16 a
= (OP
[0]), tmp
;
1817 trace_input ("cbitw", OP_CONSTANT4
, OP_R_INDEX8_ABS20
, OP_VOID
);
1820 addr
= (GPR32 (12)) + OP
[2];
1822 addr
= (GPR32 (13)) + OP
[2];
1825 SET_PSR_F (tmp
& (1 << a
));
1826 tmp
= tmp
& ~(1 << a
);
1828 trace_output_32 (sd
, addr
);
1834 OP_1AB_A (SIM_DESC sd
, SIM_CPU
*cpu
)
1837 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1838 trace_input ("cbitw", OP_CONSTANT4
, OP_RP_INDEX_DISP14
, OP_VOID
);
1840 SET_PSR_F (tmp
& (1 << a
));
1841 tmp
= tmp
& ~(1 << a
);
1843 trace_output_32 (sd
, addr
);
1848 OP_114_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
1851 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
1852 trace_input ("cbitw", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
1854 SET_PSR_F (tmp
& (1 << a
));
1855 tmp
= tmp
& ~(1 << a
);
1857 trace_output_32 (sd
, addr
);
1863 OP_6E_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
1866 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1867 trace_input ("cbitw", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
1869 SET_PSR_F (tmp
& (1 << a
));
1870 tmp
= tmp
& ~(1 << a
);
1872 trace_output_32 (sd
, addr
);
1877 OP_69_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
1880 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1881 trace_input ("cbitw", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
1883 SET_PSR_F (tmp
& (1 << a
));
1884 tmp
= tmp
& ~(1 << a
);
1886 trace_output_32 (sd
, addr
);
1892 OP_115_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
1895 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1896 trace_input ("cbitw", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
1898 SET_PSR_F (tmp
& (1 << a
));
1899 tmp
= tmp
& ~(1 << a
);
1901 trace_output_32 (sd
, addr
);
1906 OP_116_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
1909 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1910 trace_input ("cbitw", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
1912 SET_PSR_F (tmp
& (1 << a
));
1913 tmp
= tmp
& ~(1 << a
);
1915 trace_output_32 (sd
, addr
);
1920 OP_E7_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
1922 uint8 a
= OP
[0] & 0xff;
1923 uint32 addr
= OP
[1], tmp
;
1924 trace_input ("sbitb", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
1926 SET_PSR_F (tmp
& (1 << a
));
1927 tmp
= tmp
| (1 << a
);
1929 trace_output_32 (sd
, tmp
);
1934 OP_10B_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
1936 uint8 a
= OP
[0] & 0xff;
1937 uint32 addr
= OP
[1], tmp
;
1938 trace_input ("sbitb", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
1940 SET_PSR_F (tmp
& (1 << a
));
1941 tmp
= tmp
| (1 << a
);
1943 trace_output_32 (sd
, tmp
);
1948 OP_70_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
1950 uint8 a
= OP
[0] & 0xff;
1951 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
1952 trace_input ("sbitb", OP_CONSTANT4
, OP_R_INDEX7_ABS20
, OP_VOID
);
1954 SET_PSR_F (tmp
& (1 << a
));
1955 tmp
= tmp
| (1 << a
);
1957 trace_output_32 (sd
, tmp
);
1962 OP_1CA_A (SIM_DESC sd
, SIM_CPU
*cpu
)
1964 uint8 a
= OP
[0] & 0xff;
1965 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1966 trace_input ("sbitb", OP_CONSTANT4
, OP_RP_INDEX_DISP14
, OP_VOID
);
1968 SET_PSR_F (tmp
& (1 << a
));
1969 tmp
= tmp
| (1 << a
);
1971 trace_output_32 (sd
, tmp
);
1976 OP_108_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
1978 uint8 a
= OP
[0] & 0xff;
1979 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
1980 trace_input ("sbitb", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
1982 SET_PSR_F (tmp
& (1 << a
));
1983 tmp
= tmp
| (1 << a
);
1985 trace_output_32 (sd
, tmp
);
1991 OP_E4_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
1993 uint8 a
= OP
[0] & 0xff;
1994 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1995 trace_input ("sbitb", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
1997 SET_PSR_F (tmp
& (1 << a
));
1998 tmp
= tmp
| (1 << a
);
2000 trace_output_32 (sd
, tmp
);
2005 OP_E6_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
2007 uint8 a
= OP
[0] & 0xff;
2008 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2009 trace_input ("sbitb", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
2011 SET_PSR_F (tmp
& (1 << a
));
2012 tmp
= tmp
| (1 << a
);
2014 trace_output_32 (sd
, tmp
);
2020 OP_109_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2022 uint8 a
= OP
[0] & 0xff;
2023 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2024 trace_input ("sbitb", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
2026 SET_PSR_F (tmp
& (1 << a
));
2027 tmp
= tmp
| (1 << a
);
2029 trace_output_32 (sd
, tmp
);
2035 OP_10A_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2037 uint8 a
= OP
[0] & 0xff;
2038 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2039 trace_input ("sbitb", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
2041 SET_PSR_F (tmp
& (1 << a
));
2042 tmp
= tmp
| (1 << a
);
2044 trace_output_32 (sd
, tmp
);
2050 OP_77_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2053 uint32 addr
= OP
[1], tmp
;
2054 trace_input ("sbitw", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
2056 SET_PSR_F (tmp
& (1 << a
));
2057 tmp
= tmp
| (1 << a
);
2059 trace_output_32 (sd
, tmp
);
2064 OP_11B_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2067 uint32 addr
= OP
[1], tmp
;
2068 trace_input ("sbitw", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
2070 SET_PSR_F (tmp
& (1 << a
));
2071 tmp
= tmp
| (1 << a
);
2073 trace_output_32 (sd
, tmp
);
2078 OP_3A_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
2081 uint16 a
= (OP
[0]), tmp
;
2082 trace_input ("sbitw", OP_CONSTANT4
, OP_R_INDEX8_ABS20
, OP_VOID
);
2085 addr
= (GPR32 (12)) + OP
[2];
2087 addr
= (GPR32 (13)) + OP
[2];
2090 SET_PSR_F (tmp
& (1 << a
));
2091 tmp
= tmp
| (1 << a
);
2093 trace_output_32 (sd
, addr
);
2098 OP_1CB_A (SIM_DESC sd
, SIM_CPU
*cpu
)
2101 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2102 trace_input ("sbitw", OP_CONSTANT4
, OP_RP_INDEX_DISP14
, OP_VOID
);
2104 SET_PSR_F (tmp
& (1 << a
));
2105 tmp
= tmp
| (1 << a
);
2107 trace_output_32 (sd
, addr
);
2112 OP_118_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2115 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
2116 trace_input ("sbitw", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
2118 SET_PSR_F (tmp
& (1 << a
));
2119 tmp
= tmp
| (1 << a
);
2121 trace_output_32 (sd
, addr
);
2126 OP_76_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2129 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2130 trace_input ("sbitw", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
2132 SET_PSR_F (tmp
& (1 << a
));
2133 tmp
= tmp
| (1 << a
);
2135 trace_output_32 (sd
, addr
);
2140 OP_71_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2143 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2144 trace_input ("sbitw", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
2146 SET_PSR_F (tmp
& (1 << a
));
2147 tmp
= tmp
| (1 << a
);
2149 trace_output_32 (sd
, addr
);
2154 OP_119_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2157 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2158 trace_input ("sbitw", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
2160 SET_PSR_F (tmp
& (1 << a
));
2161 tmp
= tmp
| (1 << a
);
2163 trace_output_32 (sd
, addr
);
2168 OP_11A_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2171 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2172 trace_input ("sbitw", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
2174 SET_PSR_F (tmp
& (1 << a
));
2175 tmp
= tmp
| (1 << a
);
2177 trace_output_32 (sd
, addr
);
2183 OP_F7_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
2185 uint8 a
= OP
[0] & 0xff;
2186 uint32 addr
= OP
[1], tmp
;
2187 trace_input ("tbitb", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
2189 SET_PSR_F (tmp
& (1 << a
));
2190 trace_output_32 (sd
, tmp
);
2195 OP_10F_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2197 uint8 a
= OP
[0] & 0xff;
2198 uint32 addr
= OP
[1], tmp
;
2199 trace_input ("tbitb", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
2201 SET_PSR_F (tmp
& (1 << a
));
2202 trace_output_32 (sd
, tmp
);
2207 OP_78_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2209 uint8 a
= (OP
[0]) & 0xff;
2210 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
2211 trace_input ("tbitb", OP_CONSTANT4
, OP_R_INDEX7_ABS20
, OP_VOID
);
2213 SET_PSR_F (tmp
& (1 << a
));
2214 trace_output_32 (sd
, addr
);
2219 OP_1EA_A (SIM_DESC sd
, SIM_CPU
*cpu
)
2221 uint8 a
= (OP
[0]) & 0xff;
2222 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2223 trace_input ("tbitb", OP_CONSTANT4
, OP_RP_INDEX_DISP14
, OP_VOID
);
2225 SET_PSR_F (tmp
& (1 << a
));
2226 trace_output_32 (sd
, addr
);
2231 OP_10C_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2233 uint8 a
= (OP
[0]) & 0xff;
2234 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
2235 trace_input ("tbitb", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
2237 SET_PSR_F (tmp
& (1 << a
));
2238 trace_output_32 (sd
, addr
);
2243 OP_F4_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
2245 uint8 a
= (OP
[0]) & 0xff;
2246 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2247 trace_input ("tbitb", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
2249 SET_PSR_F (tmp
& (1 << a
));
2250 trace_output_32 (sd
, addr
);
2255 OP_F6_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
2257 uint8 a
= (OP
[0]) & 0xff;
2258 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2259 trace_input ("tbitb", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
2261 SET_PSR_F (tmp
& (1 << a
));
2262 trace_output_32 (sd
, addr
);
2267 OP_10D_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2269 uint8 a
= (OP
[0]) & 0xff;
2270 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2271 trace_input ("tbitb", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
2273 SET_PSR_F (tmp
& (1 << a
));
2274 trace_output_32 (sd
, addr
);
2279 OP_10E_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2281 uint8 a
= (OP
[0]) & 0xff;
2282 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2283 trace_input ("tbitb", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
2285 SET_PSR_F (tmp
& (1 << a
));
2286 trace_output_32 (sd
, addr
);
2292 OP_7F_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2295 uint32 addr
= OP
[1], tmp
;
2296 trace_input ("tbitw", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
2298 SET_PSR_F (tmp
& (1 << a
));
2299 trace_output_32 (sd
, tmp
);
2304 OP_11F_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2307 uint32 addr
= OP
[1], tmp
;
2308 trace_input ("tbitw", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
2310 SET_PSR_F (tmp
& (1 << a
));
2311 trace_output_32 (sd
, tmp
);
2317 OP_3E_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
2320 uint16 a
= (OP
[0]), tmp
;
2321 trace_input ("tbitw", OP_CONSTANT4
, OP_R_INDEX8_ABS20
, OP_VOID
);
2324 addr
= (GPR32 (12)) + OP
[2];
2326 addr
= (GPR32 (13)) + OP
[2];
2329 SET_PSR_F (tmp
& (1 << a
));
2330 trace_output_32 (sd
, addr
);
2335 OP_1EB_A (SIM_DESC sd
, SIM_CPU
*cpu
)
2338 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2339 trace_input ("tbitw", OP_CONSTANT4
, OP_RP_INDEX_DISP14
, OP_VOID
);
2341 SET_PSR_F (tmp
& (1 << a
));
2342 trace_output_32 (sd
, addr
);
2347 OP_11C_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2350 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
2351 trace_input ("tbitw", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
2353 SET_PSR_F (tmp
& (1 << a
));
2354 trace_output_32 (sd
, addr
);
2359 OP_7E_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2362 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2363 trace_input ("tbitw", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
2365 SET_PSR_F (tmp
& (1 << a
));
2366 trace_output_32 (sd
, addr
);
2371 OP_79_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2374 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2375 trace_input ("tbitw", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
2377 SET_PSR_F (tmp
& (1 << a
));
2378 trace_output_32 (sd
, addr
);
2383 OP_11D_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2386 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2387 trace_input ("tbitw", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
2389 SET_PSR_F (tmp
& (1 << a
));
2390 trace_output_32 (sd
, addr
);
2396 OP_11E_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2399 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2400 trace_input ("tbitw", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
2402 SET_PSR_F (tmp
& (1 << a
));
2403 trace_output_32 (sd
, addr
);
2409 OP_6_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2412 uint16 b
= (GPR (OP
[1]));
2413 trace_input ("tbit", OP_CONSTANT4
, OP_REG
, OP_VOID
);
2414 SET_PSR_F (b
& (1 << a
));
2415 trace_output_16 (sd
, b
);
2420 OP_7_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2422 uint16 a
= GPR (OP
[0]);
2423 uint16 b
= (GPR (OP
[1]));
2424 trace_input ("tbit", OP_REG
, OP_REG
, OP_VOID
);
2425 SET_PSR_F (b
& (1 << a
));
2426 trace_output_16 (sd
, b
);
2432 OP_50_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2434 uint8 a
= (OP
[0]) & 0xFF;
2435 uint8 b
= (GPR (OP
[1])) & 0xFF;
2436 trace_input ("cmpb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
2438 SET_PSR_N ((int8
)a
> (int8
)b
);
2440 trace_output_flag (sd
);
2445 OP_50B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
2447 uint8 a
= (OP
[0]) & 0xFF;
2448 uint8 b
= (GPR (OP
[1])) & 0xFF;
2449 trace_input ("cmpb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
2451 SET_PSR_N ((int8
)a
> (int8
)b
);
2453 trace_output_flag (sd
);
2458 OP_51_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2460 uint8 a
= (GPR (OP
[0])) & 0xFF;
2461 uint8 b
= (GPR (OP
[1])) & 0xFF;
2462 trace_input ("cmpb", OP_REG
, OP_REG
, OP_VOID
);
2464 SET_PSR_N ((int8
)a
> (int8
)b
);
2466 trace_output_flag (sd
);
2471 OP_52_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2474 uint16 b
= GPR (OP
[1]);
2475 trace_input ("cmpw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
2477 SET_PSR_N ((int16
)a
> (int16
)b
);
2479 trace_output_flag (sd
);
2484 OP_52B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
2487 uint16 b
= GPR (OP
[1]);
2488 trace_input ("cmpw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
2490 SET_PSR_N ((int16
)a
> (int16
)b
);
2492 trace_output_flag (sd
);
2497 OP_53_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2499 uint16 a
= GPR (OP
[0]) ;
2500 uint16 b
= GPR (OP
[1]) ;
2501 trace_input ("cmpw", OP_REG
, OP_REG
, OP_VOID
);
2503 SET_PSR_N ((int16
)a
> (int16
)b
);
2505 trace_output_flag (sd
);
2510 OP_56_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2513 uint32 b
= GPR32 (OP
[1]);
2514 trace_input ("cmpd", OP_CONSTANT4
, OP_REGP
, OP_VOID
);
2516 SET_PSR_N ((int32
)a
> (int32
)b
);
2518 trace_output_flag (sd
);
2523 OP_56B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
2525 uint32 a
= (SEXT16(OP
[0]));
2526 uint32 b
= GPR32 (OP
[1]);
2527 trace_input ("cmpd", OP_CONSTANT16
, OP_REGP
, OP_VOID
);
2529 SET_PSR_N ((int32
)a
> (int32
)b
);
2531 trace_output_flag (sd
);
2536 OP_57_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2538 uint32 a
= GPR32 (OP
[0]) ;
2539 uint32 b
= GPR32 (OP
[1]) ;
2540 trace_input ("cmpd", OP_REGP
, OP_REGP
, OP_VOID
);
2542 SET_PSR_N ((int32
)a
> (int32
)b
);
2544 trace_output_flag (sd
);
2549 OP_9_C (SIM_DESC sd
, SIM_CPU
*cpu
)
2552 uint32 b
= GPR32 (OP
[1]);
2553 trace_input ("cmpd", OP_CONSTANT32
, OP_REGP
, OP_VOID
);
2555 SET_PSR_N ((int32
)a
> (int32
)b
);
2557 trace_output_flag (sd
);
2563 OP_58_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2565 uint8 tmp
= OP
[0] & 0xFF;
2566 uint16 a
= (GPR (OP
[1])) & 0xFF00;
2567 trace_input ("movb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
2568 SET_GPR (OP
[1], (a
| tmp
));
2569 trace_output_16 (sd
, tmp
);
2574 OP_58B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
2576 uint8 tmp
= OP
[0] & 0xFF;
2577 uint16 a
= (GPR (OP
[1])) & 0xFF00;
2578 trace_input ("movb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
2579 SET_GPR (OP
[1], (a
| tmp
));
2580 trace_output_16 (sd
, tmp
);
2585 OP_59_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2587 uint8 tmp
= (GPR (OP
[0])) & 0xFF;
2588 uint16 a
= (GPR (OP
[1])) & 0xFF00;
2589 trace_input ("movb", OP_REG
, OP_REG
, OP_VOID
);
2590 SET_GPR (OP
[1], (a
| tmp
));
2591 trace_output_16 (sd
, tmp
);
2596 OP_5A_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2599 trace_input ("movw", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
2600 SET_GPR (OP
[1], (tmp
& 0xffff));
2601 trace_output_16 (sd
, tmp
);
2606 OP_5AB_C (SIM_DESC sd
, SIM_CPU
*cpu
)
2609 trace_input ("movw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
2610 SET_GPR (OP
[1], (tmp
& 0xffff));
2611 trace_output_16 (sd
, tmp
);
2616 OP_5B_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2618 uint16 tmp
= GPR (OP
[0]);
2619 uint32 a
= GPR32 (OP
[1]);
2620 trace_input ("movw", OP_REG
, OP_REGP
, OP_VOID
);
2621 a
= (a
& 0xffff0000) | tmp
;
2622 SET_GPR32 (OP
[1], a
);
2623 trace_output_16 (sd
, tmp
);
2628 OP_5C_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2630 uint8 tmp
= (GPR (OP
[0])) & 0xFF;
2631 trace_input ("movxb", OP_REG
, OP_REG
, OP_VOID
);
2632 SET_GPR (OP
[1], ((SEXT8(tmp
)) & 0xffff));
2633 trace_output_16 (sd
, tmp
);
2638 OP_5D_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2640 uint8 tmp
= (GPR (OP
[0])) & 0xFF;
2641 trace_input ("movzb", OP_REG
, OP_REG
, OP_VOID
);
2642 SET_GPR (OP
[1], tmp
);
2643 trace_output_16 (sd
, tmp
);
2648 OP_5E_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2650 uint16 tmp
= GPR (OP
[0]);
2651 trace_input ("movxw", OP_REG
, OP_REGP
, OP_VOID
);
2652 SET_GPR32 (OP
[1], SEXT16(tmp
));
2653 trace_output_16 (sd
, tmp
);
2658 OP_5F_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2660 uint16 tmp
= GPR (OP
[0]);
2661 trace_input ("movzw", OP_REG
, OP_REGP
, OP_VOID
);
2662 SET_GPR32 (OP
[1], (tmp
& 0x0000FFFF));
2663 trace_output_16 (sd
, tmp
);
2668 OP_54_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2671 trace_input ("movd", OP_CONSTANT4
, OP_REGP
, OP_VOID
);
2672 SET_GPR32 (OP
[1], tmp
);
2673 trace_output_32 (sd
, tmp
);
2678 OP_54B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
2680 int32 tmp
= SEXT16(OP
[0]);
2681 trace_input ("movd", OP_CONSTANT16
, OP_REGP
, OP_VOID
);
2682 SET_GPR32 (OP
[1], tmp
);
2683 trace_output_32 (sd
, tmp
);
2688 OP_55_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2690 uint32 tmp
= GPR32 (OP
[0]);
2691 trace_input ("movd", OP_REGP
, OP_REGP
, OP_VOID
);
2692 SET_GPR32 (OP
[1], tmp
);
2693 trace_output_32 (sd
, tmp
);
2698 OP_5_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2701 trace_input ("movd", OP_CONSTANT20
, OP_REGP
, OP_VOID
);
2702 SET_GPR32 (OP
[1], tmp
);
2703 trace_output_32 (sd
, tmp
);
2708 OP_7_C (SIM_DESC sd
, SIM_CPU
*cpu
)
2711 trace_input ("movd", OP_CONSTANT32
, OP_REGP
, OP_VOID
);
2712 SET_GPR32 (OP
[1], tmp
);
2713 trace_output_32 (sd
, tmp
);
2718 OP_14_D (SIM_DESC sd
, SIM_CPU
*cpu
)
2720 uint32 addr
= GPR (0);
2721 uint16 count
= OP
[0], reg
= 2, tmp
;
2722 trace_input ("loadm", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
2725 State
.exception
= SIG_CR16_BUS
;
2726 State
.pc_changed
= 1; /* Don't increment the PC. */
2727 trace_output_void (sd
);
2738 if (reg
== 6) reg
= 8;
2742 trace_output_void (sd
);
2748 OP_15_D (SIM_DESC sd
, SIM_CPU
*cpu
)
2750 uint32 addr
= GPR32 (0);
2751 uint16 count
= OP
[0], reg
= 2, tmp
;
2752 trace_input ("loadm", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
2755 State
.exception
= SIG_CR16_BUS
;
2756 State
.pc_changed
= 1; /* Don't increment the PC. */
2757 trace_output_void (sd
);
2768 if (reg
== 6) reg
= 8;
2771 SET_GPR32 (0, addr
);
2772 trace_output_void (sd
);
2778 OP_88_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2781 * ADDR = zext24(abs20) | remap (ie 0xF00000)
2784 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2785 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2786 * by the core to 16M-64k to 16M. */
2788 uint16 tmp
, a
= (GPR (OP
[1])) & 0xFF00;
2789 uint32 addr
= OP
[0];
2790 trace_input ("loadb", OP_ABS20
, OP_REG
, OP_VOID
);
2791 if (addr
> 0xEFFFF) addr
|= 0xF00000;
2793 SET_GPR (OP
[1], (a
| tmp
));
2794 trace_output_16 (sd
, tmp
);
2799 OP_127_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2805 uint16 tmp
, a
= (GPR (OP
[1])) & 0xFF00;
2806 uint32 addr
= OP
[0];
2807 trace_input ("loadb", OP_ABS24
, OP_REG
, OP_VOID
);
2809 SET_GPR (OP
[1], (a
| tmp
));
2810 trace_output_16 (sd
, tmp
);
2815 OP_45_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
2817 /* loadb [Rindex]ABS20 REG
2818 * ADDR = Rindex + zext24(disp20)
2822 uint16 tmp
, a
= (GPR (OP
[2])) & 0xFF00;
2823 trace_input ("loadb", OP_R_INDEX8_ABS20
, OP_REG
, OP_VOID
);
2826 addr
= (GPR32 (12)) + OP
[1];
2828 addr
= (GPR32 (13)) + OP
[1];
2831 SET_GPR (OP
[2], (a
| tmp
));
2832 trace_output_16 (sd
, tmp
);
2838 OP_B_4 (SIM_DESC sd
, SIM_CPU
*cpu
)
2840 /* loadb DIPS4(REGP) REG
2841 * ADDR = RPBASE + zext24(DISP4)
2843 uint16 tmp
, a
= (GPR (OP
[2])) & 0xFF00;
2844 uint32 addr
= (GPR32 (OP
[1])) + OP
[0];
2845 trace_input ("loadb", OP_RP_BASE_DISP4
, OP_REG
, OP_VOID
);
2847 SET_GPR (OP
[2], (a
| tmp
));
2848 trace_output_16 (sd
, tmp
);
2853 OP_BE_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2855 /* loadb [Rindex]disp0(RPbasex) REG
2856 * ADDR = Rpbasex + Rindex
2860 uint16 tmp
, a
= (GPR (OP
[3])) & 0xFF00;
2861 trace_input ("loadb", OP_RP_INDEX_DISP0
, OP_REG
, OP_VOID
);
2863 addr
= (GPR32 (OP
[2])) + OP
[1];
2866 addr
= (GPR32 (12)) + addr
;
2868 addr
= (GPR32 (13)) + addr
;
2871 SET_GPR (OP
[3], (a
| tmp
));
2872 trace_output_16 (sd
, tmp
);
2877 OP_219_A (SIM_DESC sd
, SIM_CPU
*cpu
)
2879 /* loadb [Rindex]disp14(RPbasex) REG
2880 * ADDR = Rpbasex + Rindex + zext24(disp14)
2884 uint16 tmp
, a
= (GPR (OP
[3])) & 0xFF00;
2886 addr
= (GPR32 (OP
[2])) + OP
[1];
2889 addr
= (GPR32 (12)) + addr
;
2891 addr
= (GPR32 (13)) + addr
;
2893 trace_input ("loadb", OP_RP_INDEX_DISP14
, OP_REG
, OP_VOID
);
2895 SET_GPR (OP
[3], (a
| tmp
));
2896 trace_output_16 (sd
, tmp
);
2902 OP_184_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2904 /* loadb DISPE20(REG) REG
2905 * zext24(Rbase) + zext24(dispe20)
2908 uint16 tmp
,a
= (GPR (OP
[2])) & 0xFF00;
2909 uint32 addr
= OP
[0] + (GPR (OP
[1]));
2910 trace_input ("loadb", OP_R_BASE_DISPE20
, OP_REG
, OP_VOID
);
2912 SET_GPR (OP
[2], (a
| tmp
));
2913 trace_output_16 (sd
, tmp
);
2918 OP_124_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2920 /* loadb DISP20(REG) REG
2921 * ADDR = zext24(Rbase) + zext24(disp20)
2924 uint16 tmp
,a
= (GPR (OP
[2])) & 0xFF00;
2925 uint32 addr
= OP
[0] + (GPR (OP
[1]));
2926 trace_input ("loadb", OP_R_BASE_DISP20
, OP_REG
, OP_VOID
);
2928 SET_GPR (OP
[2], (a
| tmp
));
2929 trace_output_16 (sd
, tmp
);
2934 OP_BF_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
2936 /* loadb disp16(REGP) REG
2937 * ADDR = RPbase + zext24(disp16)
2940 uint16 tmp
,a
= (GPR (OP
[2])) & 0xFF00;
2941 uint32 addr
= (GPR32 (OP
[1])) + OP
[0];
2942 trace_input ("loadb", OP_RP_BASE_DISP16
, OP_REG
, OP_VOID
);
2944 SET_GPR (OP
[2], (a
| tmp
));
2945 trace_output_16 (sd
, tmp
);
2950 OP_125_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2952 /* loadb disp20(REGP) REG
2953 * ADDR = RPbase + zext24(disp20)
2955 uint16 tmp
,a
= (GPR (OP
[2])) & 0xFF00;
2956 uint32 addr
= (GPR32 (OP
[1])) + OP
[0];
2957 trace_input ("loadb", OP_RP_BASE_DISP20
, OP_REG
, OP_VOID
);
2959 SET_GPR (OP
[2], (a
| tmp
));
2960 trace_output_16 (sd
, tmp
);
2966 OP_185_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2968 /* loadb -disp20(REGP) REG
2969 * ADDR = RPbase + zext24(-disp20)
2971 uint16 tmp
,a
= (GPR (OP
[2])) & 0xFF00;
2972 uint32 addr
= (GPR32 (OP
[1])) + OP
[1];
2973 trace_input ("loadb", OP_RP_BASE_DISPE20
, OP_REG
, OP_VOID
);
2975 SET_GPR (OP
[2], (a
| tmp
));
2976 trace_output_16 (sd
, tmp
);
2981 OP_126_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
2983 /* loadb [Rindex]disp20(RPbasexb) REG
2984 * ADDR = RPbasex + Rindex + zext24(disp20)
2988 uint16 tmp
, a
= (GPR (OP
[3])) & 0xFF00;
2989 trace_input ("loadb", OP_RP_INDEX_DISP20
, OP_REG
, OP_VOID
);
2991 addr
= (GPR32 (OP
[2])) + OP
[1];
2994 addr
= (GPR32 (12)) + addr
;
2996 addr
= (GPR32 (13)) + addr
;
2999 SET_GPR (OP
[3], (a
| tmp
));
3000 trace_output_16 (sd
, tmp
);
3006 OP_89_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3009 * ADDR = zext24(abs20) | remap
3012 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3013 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3014 * by the core to 16M-64k to 16M. */
3017 uint32 addr
= OP
[0];
3018 trace_input ("loadw", OP_ABS20
, OP_REG
, OP_VOID
);
3019 if (addr
> 0xEFFFF) addr
|= 0xF00000;
3021 SET_GPR (OP
[1], tmp
);
3022 trace_output_16 (sd
, tmp
);
3028 OP_12F_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3034 uint32 addr
= OP
[0];
3035 trace_input ("loadw", OP_ABS24
, OP_REG
, OP_VOID
);
3037 SET_GPR (OP
[1], tmp
);
3038 trace_output_16 (sd
, tmp
);
3043 OP_47_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
3045 /* loadw [Rindex]ABS20 REG
3046 * ADDR = Rindex + zext24(disp20)
3051 trace_input ("loadw", OP_R_INDEX8_ABS20
, OP_REG
, OP_VOID
);
3054 addr
= (GPR32 (12)) + OP
[1];
3056 addr
= (GPR32 (13)) + OP
[1];
3059 SET_GPR (OP
[2], tmp
);
3060 trace_output_16 (sd
, tmp
);
3066 OP_9_4 (SIM_DESC sd
, SIM_CPU
*cpu
)
3068 /* loadw DIPS4(REGP) REGP
3069 * ADDR = RPBASE + zext24(DISP4)
3073 trace_input ("loadw", OP_RP_BASE_DISP4
, OP_REG
, OP_VOID
);
3074 addr
= (GPR32 (OP
[1])) + OP
[0];
3078 a
= (GPR32 (OP
[2])) & 0xffff0000;
3079 SET_GPR32 (OP
[2], (a
| tmp
));
3082 SET_GPR (OP
[2], tmp
);
3084 trace_output_16 (sd
, tmp
);
3090 OP_9E_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3092 /* loadw [Rindex]disp0(RPbasex) REG
3093 * ADDR = Rpbasex + Rindex
3098 trace_input ("loadw", OP_RP_INDEX_DISP0
, OP_REG
, OP_VOID
);
3100 addr
= (GPR32 (OP
[2])) + OP
[1];
3103 addr
= (GPR32 (12)) + addr
;
3105 addr
= (GPR32 (13)) + addr
;
3108 SET_GPR (OP
[3], tmp
);
3109 trace_output_16 (sd
, tmp
);
3115 OP_21B_A (SIM_DESC sd
, SIM_CPU
*cpu
)
3117 /* loadw [Rindex]disp14(RPbasex) REG
3118 * ADDR = Rpbasex + Rindex + zext24(disp14)
3123 trace_input ("loadw", OP_RP_INDEX_DISP14
, OP_REG
, OP_VOID
);
3124 addr
= (GPR32 (OP
[2])) + OP
[1];
3127 addr
= (GPR32 (12)) + addr
;
3129 addr
= (GPR32 (13)) + addr
;
3132 SET_GPR (OP
[3], tmp
);
3133 trace_output_16 (sd
, tmp
);
3138 OP_18C_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3140 /* loadw dispe20(REG) REGP
3141 * REGP = [DISPE20+[REG]] */
3145 trace_input ("loadw", OP_R_BASE_DISPE20
, OP_REGP
, OP_VOID
);
3146 addr
= OP
[0] + (GPR (OP
[1]));
3150 a
= (GPR32 (OP
[2])) & 0xffff0000;
3151 SET_GPR32 (OP
[2], (a
| tmp
));
3154 SET_GPR (OP
[2], tmp
);
3156 trace_output_16 (sd
, tmp
);
3162 OP_12C_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3164 /* loadw DISP20(REG) REGP
3165 * ADDR = zext24(Rbase) + zext24(disp20)
3170 trace_input ("loadw", OP_R_BASE_DISP20
, OP_REGP
, OP_VOID
);
3171 addr
= OP
[0] + (GPR (OP
[1]));
3175 a
= (GPR32 (OP
[2])) & 0xffff0000;
3176 SET_GPR32 (OP
[2], (a
| tmp
));
3179 SET_GPR (OP
[2], tmp
);
3181 trace_output_16 (sd
, tmp
);
3186 OP_9F_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3188 /* loadw disp16(REGP) REGP
3189 * ADDR = RPbase + zext24(disp16)
3193 trace_input ("loadw", OP_RP_BASE_DISP16
, OP_REGP
, OP_VOID
);
3194 addr
= (GPR32 (OP
[1])) + OP
[0];
3198 a
= (GPR32 (OP
[2])) & 0xffff0000;
3199 SET_GPR32 (OP
[2], (a
| tmp
));
3202 SET_GPR (OP
[2], tmp
);
3204 trace_output_16 (sd
, tmp
);
3209 OP_12D_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3211 /* loadw disp20(REGP) REGP
3212 * ADDR = RPbase + zext24(disp20)
3216 trace_input ("loadw", OP_RP_BASE_DISP20
, OP_REG
, OP_VOID
);
3217 addr
= (GPR32 (OP
[1])) + OP
[0];
3221 a
= (GPR32 (OP
[2])) & 0xffff0000;
3222 SET_GPR32 (OP
[2], (a
| tmp
));
3225 SET_GPR (OP
[2], tmp
);
3227 trace_output_16 (sd
, tmp
);
3232 OP_18D_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3234 /* loadw -disp20(REGP) REG
3235 * ADDR = RPbase + zext24(-disp20)
3240 trace_input ("loadw", OP_RP_BASE_DISPE20
, OP_REG
, OP_VOID
);
3241 addr
= (GPR32 (OP
[1])) + OP
[0];
3245 a
= (GPR32 (OP
[2])) & 0xffff0000;
3246 SET_GPR32 (OP
[2], (a
| tmp
));
3249 SET_GPR (OP
[2], tmp
);
3251 trace_output_16 (sd
, tmp
);
3257 OP_12E_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3259 /* loadw [Rindex]disp20(RPbasexb) REG
3260 * ADDR = RPbasex + Rindex + zext24(disp20)
3265 trace_input ("loadw", OP_RP_INDEX_DISP20
, OP_REG
, OP_VOID
);
3268 addr
= (GPR32 (12)) + OP
[1] + (GPR32 (OP
[2]));
3270 addr
= (GPR32 (13)) + OP
[1] + (GPR32 (OP
[2]));
3273 SET_GPR (OP
[3], tmp
);
3274 trace_output_16 (sd
, tmp
);
3280 OP_87_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3282 /* loadd ABS20, REGP
3283 * ADDR = zext24(abs20) | remap
3286 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3287 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3288 * by the core to 16M-64k to 16M. */
3292 trace_input ("loadd", OP_ABS20
, OP_REGP
, OP_VOID
);
3293 if (addr
> 0xEFFFF) addr
|= 0xF00000;
3295 tmp
= ((tmp
<< 16) & 0xffff)| ((tmp
>> 16) & 0xffff);
3296 SET_GPR32 (OP
[1], tmp
);
3297 trace_output_32 (sd
, tmp
);
3302 OP_12B_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3304 /* loadd ABS24, REGP
3308 uint32 addr
= OP
[0];
3310 trace_input ("loadd", OP_ABS24
, OP_REGP
, OP_VOID
);
3312 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3313 SET_GPR32 (OP
[1],tmp
);
3314 trace_output_32 (sd
, tmp
);
3320 OP_46_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
3322 /* loadd [Rindex]ABS20 REGP
3323 * ADDR = Rindex + zext24(disp20)
3327 trace_input ("loadd", OP_R_INDEX8_ABS20
, OP_REGP
, OP_VOID
);
3330 addr
= (GPR32 (12)) + OP
[1];
3332 addr
= (GPR32 (13)) + OP
[1];
3335 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3336 SET_GPR32 (OP
[2], tmp
);
3337 trace_output_32 (sd
, tmp
);
3343 OP_A_4 (SIM_DESC sd
, SIM_CPU
*cpu
)
3345 /* loadd dips4(regp) REGP
3346 * ADDR = Rpbase + zext24(disp4)
3349 uint32 tmp
, addr
= (GPR32 (OP
[1])) + OP
[0];
3350 trace_input ("loadd", OP_RP_BASE_DISP4
, OP_REGP
, OP_VOID
);
3352 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3353 SET_GPR32 (OP
[2], tmp
);
3354 trace_output_32 (sd
, tmp
);
3360 OP_AE_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3362 /* loadd [Rindex]disp0(RPbasex) REGP
3363 * ADDR = Rpbasex + Rindex
3367 trace_input ("loadd", OP_RP_INDEX_DISP0
, OP_REGP
, OP_VOID
);
3370 addr
= (GPR32 (12)) + (GPR32 (OP
[2])) + OP
[1];
3372 addr
= (GPR32 (13)) + (GPR32 (OP
[2])) + OP
[1];
3375 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3376 SET_GPR32 (OP
[3], tmp
);
3377 trace_output_32 (sd
, tmp
);
3383 OP_21A_A (SIM_DESC sd
, SIM_CPU
*cpu
)
3385 /* loadd [Rindex]disp14(RPbasex) REGP
3386 * ADDR = Rpbasex + Rindex + zext24(disp14)
3390 trace_input ("loadd", OP_RP_INDEX_DISP14
, OP_REGP
, OP_VOID
);
3393 addr
= (GPR32 (12)) + OP
[1] + (GPR32 (OP
[2]));
3395 addr
= (GPR32 (13)) + OP
[1] + (GPR32 (OP
[2]));
3398 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3399 SET_GPR (OP
[3],tmp
);
3400 trace_output_32 (sd
, tmp
);
3406 OP_188_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3408 /* loadd dispe20(REG) REG
3409 * zext24(Rbase) + zext24(dispe20)
3412 uint32 tmp
, addr
= OP
[0] + (GPR (OP
[1]));
3413 trace_input ("loadd", OP_R_BASE_DISPE20
, OP_REGP
, OP_VOID
);
3415 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3416 SET_GPR32 (OP
[2], tmp
);
3417 trace_output_32 (sd
, tmp
);
3423 OP_128_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3425 /* loadd DISP20(REG) REG
3426 * ADDR = zext24(Rbase) + zext24(disp20)
3429 uint32 tmp
, addr
= OP
[0] + (GPR (OP
[1]));
3430 trace_input ("loadd", OP_R_BASE_DISP20
, OP_REGP
, OP_VOID
);
3432 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3433 SET_GPR32 (OP
[2], tmp
);
3434 trace_output_32 (sd
, tmp
);
3439 OP_AF_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3441 /* loadd disp16(REGP) REGP
3442 * ADDR = RPbase + zext24(disp16)
3444 uint32 tmp
, addr
= OP
[0] + (GPR32 (OP
[1]));
3445 trace_input ("loadd", OP_RP_BASE_DISP16
, OP_REGP
, OP_VOID
);
3447 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3448 SET_GPR32 (OP
[2], tmp
);
3449 trace_output_32 (sd
, tmp
);
3455 OP_129_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3457 /* loadd disp20(REGP) REGP
3458 * ADDR = RPbase + zext24(disp20)
3460 uint32 tmp
, addr
= OP
[0] + (GPR32 (OP
[1]));
3461 trace_input ("loadd", OP_RP_BASE_DISP20
, OP_REGP
, OP_VOID
);
3463 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3464 SET_GPR32 (OP
[2], tmp
);
3465 trace_output_32 (sd
, tmp
);
3470 OP_189_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3472 /* loadd -disp20(REGP) REGP
3473 * ADDR = RPbase + zext24(-disp20)
3476 uint32 tmp
, addr
= OP
[0] + (GPR32 (OP
[1]));
3477 trace_input ("loadd", OP_RP_BASE_DISPE20
, OP_REGP
, OP_VOID
);
3479 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3480 SET_GPR32 (OP
[2], tmp
);
3481 trace_output_32 (sd
, tmp
);
3486 OP_12A_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3488 /* loadd [Rindex]disp20(RPbasexb) REGP
3489 * ADDR = RPbasex + Rindex + zext24(disp20)
3493 trace_input ("loadd", OP_RP_INDEX_DISP20
, OP_REGP
, OP_VOID
);
3496 addr
= (GPR32 (12)) + OP
[1] + (GPR32 (OP
[2]));
3498 addr
= (GPR32 (13)) + OP
[1] + (GPR32 (OP
[2]));
3501 tmp
= ((tmp
<< 16) & 0xffff)| ((tmp
>> 16) & 0xffff);
3502 SET_GPR32 (OP
[3], tmp
);
3503 trace_output_32 (sd
, tmp
);
3509 OP_C8_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3512 * ADDR = zext24(abs20) | remap
3515 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3516 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3517 * by the core to 16M-64k to 16M. */
3519 uint8 a
= ((GPR (OP
[0])) & 0xff);
3520 uint32 addr
= OP
[1];
3521 trace_input ("storb", OP_REG
, OP_ABS20_OUTPUT
, OP_VOID
);
3523 trace_output_32 (sd
, addr
);
3528 OP_137_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3534 uint8 a
= ((GPR (OP
[0])) & 0xff);
3535 uint32 addr
= OP
[1];
3536 trace_input ("storb", OP_REG
, OP_ABS24_OUTPUT
, OP_VOID
);
3538 trace_output_32 (sd
, addr
);
3543 OP_65_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
3545 /* storb REG, [Rindex]ABS20
3546 * ADDR = Rindex + zext24(disp20)
3550 uint8 a
= ((GPR (OP
[0])) & 0xff);
3551 trace_input ("storb", OP_REG
, OP_R_INDEX8_ABS20
, OP_VOID
);
3554 addr
= (GPR32 (12)) + OP
[2];
3556 addr
= (GPR32 (13)) + OP
[2];
3559 trace_output_32 (sd
, addr
);
3564 OP_F_4 (SIM_DESC sd
, SIM_CPU
*cpu
)
3566 /* storb REG, DIPS4(REGP)
3567 * ADDR = RPBASE + zext24(DISP4)
3570 uint16 a
= ((GPR (OP
[0])) & 0xff);
3571 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3572 trace_input ("storb", OP_REG
, OP_RP_BASE_DISPE4
, OP_VOID
);
3574 trace_output_32 (sd
, addr
);
3579 OP_FE_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3581 /* storb [Rindex]disp0(RPbasex) REG
3582 * ADDR = Rpbasex + Rindex
3586 uint8 a
= ((GPR (OP
[0])) & 0xff);
3587 trace_input ("storb", OP_REG
, OP_RP_INDEX_DISP0
, OP_VOID
);
3590 addr
= (GPR32 (12)) + (GPR32 (OP
[3])) + OP
[2];
3592 addr
= (GPR32 (13)) + (GPR32 (OP
[3])) + OP
[2];
3595 trace_output_32 (sd
, addr
);
3600 OP_319_A (SIM_DESC sd
, SIM_CPU
*cpu
)
3602 /* storb REG, [Rindex]disp14(RPbasex)
3603 * ADDR = Rpbasex + Rindex + zext24(disp14)
3606 uint8 a
= ((GPR (OP
[0])) & 0xff);
3607 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3608 trace_input ("storb", OP_REG
, OP_RP_INDEX_DISP14
, OP_VOID
);
3610 trace_output_32 (sd
, addr
);
3615 OP_194_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3617 /* storb REG, DISPE20(REG)
3618 * zext24(Rbase) + zext24(dispe20)
3621 uint8 a
= ((GPR (OP
[0])) & 0xff);
3622 uint32 addr
= OP
[1] + (GPR (OP
[2]));
3623 trace_input ("storb", OP_REG
, OP_R_BASE_DISPE20
, OP_VOID
);
3625 trace_output_32 (sd
, addr
);
3630 OP_134_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3632 /* storb REG, DISP20(REG)
3633 * ADDR = zext24(Rbase) + zext24(disp20)
3636 uint8 a
= (GPR (OP
[0]) & 0xff);
3637 uint32 addr
= OP
[1] + (GPR (OP
[2]));
3638 trace_input ("storb", OP_REG
, OP_R_BASE_DISPS20
, OP_VOID
);
3640 trace_output_32 (sd
, addr
);
3645 OP_FF_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3647 /* storb REG, disp16(REGP)
3648 * ADDR = RPbase + zext24(disp16)
3651 uint8 a
= ((GPR (OP
[0])) & 0xff);
3652 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3653 trace_input ("storb", OP_REG
, OP_RP_BASE_DISP16
, OP_VOID
);
3655 trace_output_32 (sd
, addr
);
3660 OP_135_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3662 /* storb REG, disp20(REGP)
3663 * ADDR = RPbase + zext24(disp20)
3666 uint8 a
= ((GPR (OP
[0])) & 0xff);
3667 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3668 trace_input ("storb", OP_REG
, OP_RP_BASE_DISPS20
, OP_VOID
);
3670 trace_output_32 (sd
, addr
);
3675 OP_195_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3677 /* storb REG, -disp20(REGP)
3678 * ADDR = RPbase + zext24(-disp20)
3681 uint8 a
= (GPR (OP
[0]) & 0xff);
3682 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3683 trace_input ("storb", OP_REG
, OP_RP_BASE_DISPE20
, OP_VOID
);
3685 trace_output_32 (sd
, addr
);
3690 OP_136_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3692 /* storb REG, [Rindex]disp20(RPbase)
3693 * ADDR = RPbasex + Rindex + zext24(disp20)
3696 uint8 a
= (GPR (OP
[0])) & 0xff;
3697 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3698 trace_input ("storb", OP_REG
, OP_RP_INDEX_DISPS20
, OP_VOID
);
3700 trace_output_32 (sd
, addr
);
3703 /* STR_IMM instructions. */
3706 OP_81_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3708 uint8 a
= (OP
[0]) & 0xff;
3709 uint32 addr
= OP
[1];
3710 trace_input ("storb", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
3712 trace_output_32 (sd
, addr
);
3717 OP_123_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3719 uint8 a
= (OP
[0]) & 0xff;
3720 uint32 addr
= OP
[1];
3721 trace_input ("storb", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
3723 trace_output_32 (sd
, addr
);
3728 OP_42_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
3731 uint8 a
= (OP
[0]) & 0xff;
3732 trace_input ("storb", OP_CONSTANT4
, OP_R_INDEX8_ABS20
, OP_VOID
);
3735 addr
= (GPR32 (12)) + OP
[2];
3737 addr
= (GPR32 (13)) + OP
[2];
3740 trace_output_32 (sd
, addr
);
3745 OP_218_A (SIM_DESC sd
, SIM_CPU
*cpu
)
3747 uint8 a
= (OP
[0]) & 0xff;
3748 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3749 trace_input ("storb", OP_CONSTANT4
, OP_RP_BASE_DISP14
, OP_VOID
);
3751 trace_output_32 (sd
, addr
);
3756 OP_82_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3758 uint8 a
= (OP
[0]) & 0xff;
3759 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3760 trace_input ("storb", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
3762 trace_output_32 (sd
, addr
);
3767 OP_120_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3769 uint8 a
= (OP
[0]) & 0xff;
3770 uint32 addr
= (GPR (OP
[2])) + OP
[1];
3771 trace_input ("storb", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
3773 trace_output_32 (sd
, addr
);
3778 OP_83_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3780 uint8 a
= (OP
[0]) & 0xff;
3781 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3782 trace_input ("storb", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
3784 trace_output_32 (sd
, addr
);
3789 OP_121_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3791 uint8 a
= (OP
[0]) & 0xff;
3792 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3793 trace_input ("storb", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
3795 trace_output_32 (sd
, addr
);
3800 OP_122_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3802 uint8 a
= (OP
[0]) & 0xff;
3803 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3804 trace_input ("storb", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
3806 trace_output_32 (sd
, addr
);
3808 /* endif for STR_IMM. */
3812 OP_C9_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3814 uint16 a
= GPR (OP
[0]);
3815 uint32 addr
= OP
[1];
3816 trace_input ("storw", OP_REG
, OP_ABS20_OUTPUT
, OP_VOID
);
3818 trace_output_32 (sd
, addr
);
3823 OP_13F_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3825 uint16 a
= GPR (OP
[0]);
3826 uint32 addr
= OP
[1];
3827 trace_input ("storw", OP_REG
, OP_ABS24_OUTPUT
, OP_VOID
);
3829 trace_output_32 (sd
, addr
);
3834 OP_67_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
3837 uint16 a
= GPR (OP
[0]);
3838 trace_input ("storw", OP_REG
, OP_R_INDEX8_ABS20
, OP_VOID
);
3841 addr
= (GPR32 (12)) + OP
[2];
3843 addr
= (GPR32 (13)) + OP
[2];
3846 trace_output_32 (sd
, addr
);
3852 OP_D_4 (SIM_DESC sd
, SIM_CPU
*cpu
)
3854 uint16 a
= (GPR (OP
[0]));
3855 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3856 trace_input ("storw", OP_REGP
, OP_RP_BASE_DISPE4
, OP_VOID
);
3858 trace_output_32 (sd
, addr
);
3863 OP_DE_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3865 uint16 a
= GPR (OP
[0]);
3866 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3867 trace_input ("storw", OP_REG
, OP_RP_INDEX_DISP0
, OP_VOID
);
3869 trace_output_32 (sd
, addr
);
3874 OP_31B_A (SIM_DESC sd
, SIM_CPU
*cpu
)
3876 uint16 a
= GPR (OP
[0]);
3877 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3878 trace_input ("storw", OP_REG
, OP_RP_INDEX_DISP14
, OP_VOID
);
3880 trace_output_32 (sd
, addr
);
3885 OP_19C_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3887 uint16 a
= (GPR (OP
[0]));
3888 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3889 trace_input ("storw", OP_REGP
, OP_RP_BASE_DISPE20
, OP_VOID
);
3891 trace_output_32 (sd
, addr
);
3896 OP_13C_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3898 uint16 a
= (GPR (OP
[0]));
3899 uint32 addr
= (GPR (OP
[2])) + OP
[1];
3900 trace_input ("storw", OP_REG
, OP_R_BASE_DISPS20
, OP_VOID
);
3902 trace_output_32 (sd
, addr
);
3907 OP_DF_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3909 uint16 a
= (GPR (OP
[0]));
3910 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3911 trace_input ("storw", OP_REG
, OP_RP_BASE_DISP16
, OP_VOID
);
3913 trace_output_32 (sd
, addr
);
3918 OP_13D_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3920 uint16 a
= (GPR (OP
[0]));
3921 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3922 trace_input ("storw", OP_REG
, OP_RP_BASE_DISPS20
, OP_VOID
);
3924 trace_output_32 (sd
, addr
);
3929 OP_19D_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3931 uint16 a
= (GPR (OP
[0]));
3932 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3933 trace_input ("storw", OP_REG
, OP_RP_BASE_DISPE20
, OP_VOID
);
3935 trace_output_32 (sd
, addr
);
3940 OP_13E_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3942 uint16 a
= (GPR (OP
[0]));
3943 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3944 trace_input ("storw", OP_REG
, OP_RP_INDEX_DISPS20
, OP_VOID
);
3946 trace_output_32 (sd
, addr
);
3949 /* STORE-w IMM instruction *****/
3952 OP_C1_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
3955 uint32 addr
= OP
[1];
3956 trace_input ("storw", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
3958 trace_output_32 (sd
, addr
);
3963 OP_133_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
3966 uint32 addr
= OP
[1];
3967 trace_input ("storw", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
3969 trace_output_32 (sd
, addr
);
3974 OP_62_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
3978 trace_input ("storw", OP_CONSTANT4
, OP_R_INDEX8_ABS20
, OP_VOID
);
3981 addr
= (GPR32 (12)) + OP
[2];
3983 addr
= (GPR32 (13)) + OP
[2];
3986 trace_output_32 (sd
, addr
);
3991 OP_318_A (SIM_DESC sd
, SIM_CPU
*cpu
)
3994 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3995 trace_input ("storw", OP_CONSTANT4
, OP_RP_BASE_DISP14
, OP_VOID
);
3997 trace_output_32 (sd
, addr
);
4002 OP_C2_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4005 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4006 trace_input ("storw", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
4008 trace_output_32 (sd
, addr
);
4013 OP_130_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
4016 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4017 trace_input ("storw", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
4019 trace_output_32 (sd
, addr
);
4024 OP_C3_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4027 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4028 trace_input ("storw", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
4030 trace_output_32 (sd
, addr
);
4036 OP_131_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
4039 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4040 trace_input ("storw", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
4042 trace_output_32 (sd
, addr
);
4047 OP_132_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
4050 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4051 trace_input ("storw", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
4053 trace_output_32 (sd
, addr
);
4059 OP_C7_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4061 uint32 a
= GPR32 (OP
[0]);
4062 uint32 addr
= OP
[1];
4063 trace_input ("stord", OP_REGP
, OP_ABS20_OUTPUT
, OP_VOID
);
4065 trace_output_32 (sd
, addr
);
4070 OP_13B_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
4072 uint32 a
= GPR32 (OP
[0]);
4073 uint32 addr
= OP
[1];
4074 trace_input ("stord", OP_REGP
, OP_ABS24_OUTPUT
, OP_VOID
);
4076 trace_output_32 (sd
, addr
);
4081 OP_66_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
4083 uint32 addr
, a
= GPR32 (OP
[0]);
4084 trace_input ("stord", OP_REGP
, OP_R_INDEX8_ABS20
, OP_VOID
);
4087 addr
= (GPR32 (12)) + OP
[2];
4089 addr
= (GPR32 (13)) + OP
[2];
4092 trace_output_32 (sd
, addr
);
4097 OP_E_4 (SIM_DESC sd
, SIM_CPU
*cpu
)
4099 uint32 a
= GPR32 (OP
[0]);
4100 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4101 trace_input ("stord", OP_REGP
, OP_RP_BASE_DISPE4
, OP_VOID
);
4103 trace_output_32 (sd
, addr
);
4108 OP_EE_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4110 uint32 a
= GPR32 (OP
[0]);
4111 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4112 trace_input ("stord", OP_REGP
, OP_RP_INDEX_DISP0
, OP_VOID
);
4114 trace_output_32 (sd
, addr
);
4119 OP_31A_A (SIM_DESC sd
, SIM_CPU
*cpu
)
4121 uint32 a
= GPR32 (OP
[0]);
4122 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4123 trace_input ("stord", OP_REGP
, OP_RP_INDEX_DISP14
, OP_VOID
);
4125 trace_output_32 (sd
, addr
);
4130 OP_198_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
4132 uint32 a
= GPR32 (OP
[0]);
4133 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4134 trace_input ("stord", OP_REGP
, OP_R_BASE_DISPE20
, OP_VOID
);
4136 trace_output_32 (sd
, addr
);
4141 OP_138_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
4143 uint32 a
= GPR32 (OP
[0]);
4144 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4145 trace_input ("stord", OP_REGP
, OP_R_BASE_DISPS20
, OP_VOID
);
4147 trace_output_32 (sd
, addr
);
4152 OP_EF_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4154 uint32 a
= GPR32 (OP
[0]);
4155 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4156 trace_input ("stord", OP_REGP
, OP_RP_BASE_DISP16
, OP_VOID
);
4158 trace_output_32 (sd
, addr
);
4163 OP_139_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
4165 uint32 a
= GPR32 (OP
[0]);
4166 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4167 trace_input ("stord", OP_REGP
, OP_RP_BASE_DISPS20
, OP_VOID
);
4169 trace_output_32 (sd
, addr
);
4174 OP_199_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
4176 uint32 a
= GPR32 (OP
[0]);
4177 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4178 trace_input ("stord", OP_REGP
, OP_RP_BASE_DISPE20
, OP_VOID
);
4180 trace_output_32 (sd
, addr
);
4185 OP_13A_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
4187 uint32 a
= GPR32 (OP
[0]);
4188 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4189 trace_input ("stord", OP_REGP
, OP_RP_INDEX_DISPS20
, OP_VOID
);
4191 trace_output_32 (sd
, addr
);
4196 OP_14D_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
4200 trace_input ("macuw", OP_REG
, OP_REG
, OP_REGP
);
4204 /*REVISIT FOR SATURATION and Q FORMAT. */
4205 SET_GPR32 (OP
[2], tmp
);
4206 trace_output_32 (sd
, tmp
);
4211 OP_14E_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
4215 trace_input ("macuw", OP_REG
, OP_REG
, OP_REGP
);
4219 /*REVISIT FOR SATURATION. */
4220 SET_GPR32 (OP
[2], tmp
);
4221 trace_output_32 (sd
, tmp
);
4226 OP_14F_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
4230 trace_input ("macsw", OP_REG
, OP_REG
, OP_REGP
);
4234 /*REVISIT FOR SATURATION. */
4235 SET_GPR32 (OP
[2], tmp
);
4236 trace_output_32 (sd
, tmp
);
4242 OP_64_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4245 int8 a
= (OP
[0]) & 0xff;
4246 int8 b
= (GPR (OP
[1])) & 0xff;
4247 trace_input ("mulb", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
4248 tmp
= (a
* b
) & 0xff;
4249 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
4250 trace_output_16 (sd
, tmp
);
4255 OP_64B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
4258 int8 a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
4259 trace_input ("mulb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4260 tmp
= (a
* b
) & 0xff;
4261 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
4262 trace_output_16 (sd
, tmp
);
4268 OP_65_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4271 int8 a
= (GPR (OP
[0])) & 0xff, b
= (GPR (OP
[1])) & 0xff;
4272 trace_input ("mulb", OP_REG
, OP_REG
, OP_VOID
);
4273 tmp
= (a
* b
) & 0xff;
4274 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
4275 trace_output_16 (sd
, tmp
);
4281 OP_66_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4285 int16 b
= (GPR (OP
[1]));
4286 trace_input ("mulw", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
4287 tmp
= (a
* b
) & 0xffff;
4288 SET_GPR (OP
[1], tmp
);
4289 trace_output_32 (sd
, tmp
);
4294 OP_66B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
4297 int16 a
= OP
[0], b
= (GPR (OP
[1]));
4298 trace_input ("mulw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4299 tmp
= (a
* b
) & 0xffff;
4300 SET_GPR (OP
[1], tmp
);
4301 trace_output_32 (sd
, tmp
);
4307 OP_67_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4310 int16 a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
4311 trace_input ("mulw", OP_REG
, OP_REG
, OP_VOID
);
4312 tmp
= (a
* b
) & 0xffff;
4313 SET_GPR (OP
[1], tmp
);
4314 trace_output_32 (sd
, tmp
);
4320 OP_B_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4323 int8 a
= (GPR (OP
[0])) & 0xff, b
= (GPR (OP
[1])) & 0xff;
4324 trace_input ("mulsb", OP_REG
, OP_REG
, OP_VOID
);
4326 SET_GPR (OP
[1], tmp
);
4327 trace_output_32 (sd
, tmp
);
4332 OP_62_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4335 int16 a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
4336 trace_input ("mulsw", OP_REG
, OP_REGP
, OP_VOID
);
4338 SET_GPR32 (OP
[1], tmp
);
4339 trace_output_32 (sd
, tmp
);
4344 OP_63_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4347 uint16 a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
4348 trace_input ("muluw", OP_REG
, OP_REGP
, OP_VOID
);
4350 SET_GPR32 (OP
[1], tmp
);
4351 trace_output_32 (sd
, tmp
);
4357 OP_2C00_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
4359 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
4362 State
.exception
= SIGTRAP
;
4363 ins_type_counters
[ (int)State
.ins_type
]--; /* don't count nops as normal instructions */
4364 switch (State
.ins_type
)
4367 ins_type_counters
[ (int)INS_UNKNOWN
]++;
4373 trace_output_void (sd
);
4379 OP_24_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4381 uint8 tmp
, a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
4382 trace_input ("orb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4384 SET_GPR (OP
[1], ((GPR (OP
[1]) | tmp
)));
4385 trace_output_16 (sd
, tmp
);
4390 OP_24B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
4392 uint8 tmp
, a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
4393 trace_input ("orb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
4395 SET_GPR (OP
[1], ((GPR (OP
[1]) | tmp
)));
4396 trace_output_16 (sd
, tmp
);
4401 OP_25_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4403 uint8 tmp
, a
= (GPR (OP
[0])) & 0xff, b
= (GPR (OP
[1])) & 0xff;
4404 trace_input ("orb", OP_REG
, OP_REG
, OP_VOID
);
4406 SET_GPR (OP
[1], ((GPR (OP
[1]) | tmp
)));
4407 trace_output_16 (sd
, tmp
);
4412 OP_26_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4414 uint16 tmp
, a
= (OP
[0]), b
= (GPR (OP
[1]));
4415 trace_input ("orw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4417 SET_GPR (OP
[1], tmp
);
4418 trace_output_16 (sd
, tmp
);
4424 OP_26B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
4426 uint16 tmp
, a
= (OP
[0]), b
= (GPR (OP
[1]));
4427 trace_input ("orw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
4429 SET_GPR (OP
[1], tmp
);
4430 trace_output_16 (sd
, tmp
);
4435 OP_27_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4437 uint16 tmp
, a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
4438 trace_input ("orw", OP_REG
, OP_REG
, OP_VOID
);
4440 SET_GPR (OP
[1], tmp
);
4441 trace_output_16 (sd
, tmp
);
4447 OP_13_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
4450 uint16 tmp
, b
= (GPR (OP
[1])) & 0xFF;
4451 trace_input ("lshb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4452 /* A positive count specifies a shift to the left;
4453 * A negative count specifies a shift to the right. */
4459 sign_flag
= 0; /* Reset sign_flag. */
4461 SET_GPR (OP
[1], ((tmp
& 0xFF) | ((GPR (OP
[1])) & 0xFF00)));
4462 trace_output_16 (sd
, tmp
);
4467 OP_44_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4469 uint16 a
= (GPR (OP
[0])) & 0xff;
4470 uint16 tmp
, b
= (GPR (OP
[1])) & 0xFF;
4471 trace_input ("lshb", OP_REG
, OP_REG
, OP_VOID
);
4472 if (a
& ((long)1 << 3))
4477 a
= (unsigned int) (a
& 0x7);
4479 /* A positive count specifies a shift to the left;
4480 * A negative count specifies a shift to the right. */
4486 sign_flag
= 0; /* Reset sign_flag. */
4487 SET_GPR (OP
[1], ((tmp
& 0xFF) | ((GPR (OP
[1])) & 0xFF00)));
4488 trace_output_16 (sd
, tmp
);
4493 OP_46_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4495 uint16 tmp
, b
= GPR (OP
[1]);
4496 int16 a
= GPR (OP
[0]);
4497 trace_input ("lshw", OP_REG
, OP_REG
, OP_VOID
);
4498 if (a
& ((long)1 << 4))
4503 a
= (unsigned int) (a
& 0xf);
4505 /* A positive count specifies a shift to the left;
4506 * A negative count specifies a shift to the right. */
4512 sign_flag
= 0; /* Reset sign_flag. */
4513 SET_GPR (OP
[1], (tmp
& 0xffff));
4514 trace_output_16 (sd
, tmp
);
4519 OP_49_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4521 uint16 tmp
, b
= GPR (OP
[1]);
4523 trace_input ("lshw", OP_CONSTANT5
, OP_REG
, OP_VOID
);
4524 /* A positive count specifies a shift to the left;
4525 * A negative count specifies a shift to the right. */
4531 sign_flag
= 0; /* Reset sign_flag. */
4532 SET_GPR (OP
[1], (tmp
& 0xffff));
4533 trace_output_16 (sd
, tmp
);
4538 OP_25_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
4540 uint32 tmp
, b
= GPR32 (OP
[1]);
4542 trace_input ("lshd", OP_CONSTANT6
, OP_REGP
, OP_VOID
);
4543 /* A positive count specifies a shift to the left;
4544 * A negative count specifies a shift to the right. */
4550 sign_flag
= 0; /* Reset sign flag. */
4552 SET_GPR32 (OP
[1], tmp
);
4553 trace_output_32 (sd
, tmp
);
4558 OP_47_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4560 uint32 tmp
, b
= GPR32 (OP
[1]);
4561 uint16 a
= GPR (OP
[0]);
4562 trace_input ("lshd", OP_REG
, OP_REGP
, OP_VOID
);
4563 if (a
& ((long)1 << 5))
4568 a
= (unsigned int) (a
& 0x1f);
4569 /* A positive count specifies a shift to the left;
4570 * A negative count specifies a shift to the right. */
4576 sign_flag
= 0; /* Reset sign flag. */
4578 SET_GPR32 (OP
[1], tmp
);
4579 trace_output_32 (sd
, tmp
);
4584 OP_80_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
4587 int8 tmp
, b
= (GPR (OP
[1])) & 0xFF;
4588 trace_input ("ashub", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4589 /* A positive count specifies a shift to the left;
4590 * A negative count specifies a shift to the right. */
4596 sign_flag
= 0; /* Reset sign flag. */
4598 SET_GPR (OP
[1], ((tmp
& 0xFF) | ((GPR (OP
[1])) & 0xff00)));
4599 trace_output_16 (sd
, tmp
);
4604 OP_81_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
4607 int8 tmp
, b
= (GPR (OP
[1])) & 0xFF;
4608 trace_input ("ashub", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4609 /* A positive count specifies a shift to the left;
4610 * A negative count specifies a shift to the right. */
4616 sign_flag
= 0; /* Reset sign flag. */
4618 SET_GPR (OP
[1], ((tmp
& 0xFF) | ((GPR (OP
[1])) & 0xFF00)));
4619 trace_output_16 (sd
, tmp
);
4625 OP_41_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4627 int16 a
= (GPR (OP
[0]));
4628 int8 tmp
, b
= (GPR (OP
[1])) & 0xFF;
4629 trace_input ("ashub", OP_REG
, OP_REG
, OP_VOID
);
4631 if (a
& ((long)1 << 3))
4636 a
= (unsigned int) (a
& 0x7);
4638 /* A positive count specifies a shift to the left;
4639 * A negative count specifies a shift to the right. */
4645 sign_flag
= 0; /* Reset sign flag. */
4647 SET_GPR (OP
[1], ((tmp
& 0xFF) | ((GPR (OP
[1])) & 0xFF00)));
4648 trace_output_16 (sd
, tmp
);
4654 OP_42_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4656 int16 tmp
, b
= GPR (OP
[1]);
4658 trace_input ("ashuw", OP_CONSTANT5
, OP_REG
, OP_VOID
);
4659 /* A positive count specifies a shift to the left;
4660 * A negative count specifies a shift to the right. */
4666 sign_flag
= 0; /* Reset sign flag. */
4668 SET_GPR (OP
[1], (tmp
& 0xffff));
4669 trace_output_16 (sd
, tmp
);
4674 OP_43_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4676 int16 tmp
, b
= GPR (OP
[1]);
4678 trace_input ("ashuw", OP_CONSTANT5
, OP_REG
, OP_VOID
);
4679 /* A positive count specifies a shift to the left;
4680 * A negative count specifies a shift to the right. */
4686 sign_flag
= 0; /* Reset sign flag. */
4687 SET_GPR (OP
[1], (tmp
& 0xffff));
4688 trace_output_16 (sd
, tmp
);
4693 OP_45_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4696 int16 a
= GPR (OP
[0]), b
= GPR (OP
[1]);
4697 trace_input ("ashuw", OP_REG
, OP_REG
, OP_VOID
);
4699 if (a
& ((long)1 << 4))
4704 a
= (unsigned int) (a
& 0xf);
4705 /* A positive count specifies a shift to the left;
4706 * A negative count specifies a shift to the right. */
4713 sign_flag
= 0; /* Reset sign flag. */
4714 SET_GPR (OP
[1], (tmp
& 0xffff));
4715 trace_output_16 (sd
, tmp
);
4720 OP_26_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
4722 int32 tmp
,b
= GPR32 (OP
[1]);
4724 trace_input ("ashud", OP_CONSTANT6
, OP_REGP
, OP_VOID
);
4725 /* A positive count specifies a shift to the left;
4726 * A negative count specifies a shift to the right. */
4732 sign_flag
= 0; /* Reset sign flag. */
4733 SET_GPR32 (OP
[1], tmp
);
4734 trace_output_32 (sd
, tmp
);
4739 OP_27_7 (SIM_DESC sd
, SIM_CPU
*cpu
)
4742 int32 a
= OP
[0], b
= GPR32 (OP
[1]);
4743 trace_input ("ashud", OP_CONSTANT6
, OP_REGP
, OP_VOID
);
4744 /* A positive count specifies a shift to the left;
4745 * A negative count specifies a shift to the right. */
4751 sign_flag
= 0; /* Reset sign flag. */
4752 SET_GPR32 (OP
[1], tmp
);
4753 trace_output_32 (sd
, tmp
);
4758 OP_48_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4761 int32 a
= GPR32 (OP
[0]), b
= GPR32 (OP
[1]);
4762 trace_input ("ashud", OP_REGP
, OP_REGP
, OP_VOID
);
4764 if (a
& ((long)1 << 5))
4769 a
= (unsigned int) (a
& 0x1f);
4770 /* A positive count specifies a shift to the left;
4771 * A negative count specifies a shift to the right. */
4777 sign_flag
= 0; /* Reset sign flag. */
4778 SET_GPR32 (OP
[1], tmp
);
4779 trace_output_32 (sd
, tmp
);
4785 OP_16_D (SIM_DESC sd
, SIM_CPU
*cpu
)
4787 uint32 addr
= GPR (1);
4788 uint16 count
= OP
[0], reg
= 2;
4789 trace_input ("storm", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
4792 State
.exception
= SIG_CR16_BUS
;
4793 State
.pc_changed
= 1; /* Don't increment the PC. */
4794 trace_output_void (sd
);
4800 SW (addr
, (GPR (reg
)));
4804 if (reg
== 6) reg
= 8;
4809 trace_output_void (sd
);
4815 OP_17_D (SIM_DESC sd
, SIM_CPU
*cpu
)
4817 uint32 addr
= GPR32 (6);
4818 uint16 count
= OP
[0], reg
= 2;
4819 trace_input ("stormp", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
4822 State
.exception
= SIG_CR16_BUS
;
4823 State
.pc_changed
= 1; /* Don't increment the PC. */
4824 trace_output_void (sd
);
4830 SW (addr
, (GPR (reg
)));
4834 if (reg
== 6) reg
= 8;
4837 SET_GPR32 (6, addr
);
4838 trace_output_void (sd
);
4843 OP_38_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4846 uint8 b
= (GPR (OP
[1])) & 0xff;
4847 uint16 tmp
= (~a
+ 1 + b
) & 0xff;
4848 trace_input ("subb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4849 /* see ../common/sim-alu.h for a more extensive discussion on how to
4850 compute the carry/overflow bits. */
4851 SET_PSR_C (tmp
> 0xff);
4852 SET_PSR_F (((a
& 0x80) != (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
4853 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
4854 trace_output_16 (sd
, tmp
);
4859 OP_38B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
4861 uint8 a
= OP
[0] & 0xFF;
4862 uint8 b
= (GPR (OP
[1])) & 0xFF;
4863 uint16 tmp
= (~a
+ 1 + b
) & 0xFF;
4864 trace_input ("subb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
4865 /* see ../common/sim-alu.h for a more extensive discussion on how to
4866 compute the carry/overflow bits. */
4867 SET_PSR_C (tmp
> 0xff);
4868 SET_PSR_F (((a
& 0x80) != (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
4869 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
4870 trace_output_16 (sd
, tmp
);
4875 OP_39_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4877 uint8 a
= (GPR (OP
[0])) & 0xFF;
4878 uint8 b
= (GPR (OP
[1])) & 0xFF;
4879 uint16 tmp
= (~a
+ 1 + b
) & 0xff;
4880 trace_input ("subb", OP_REG
, OP_REG
, OP_VOID
);
4881 /* see ../common/sim-alu.h for a more extensive discussion on how to
4882 compute the carry/overflow bits. */
4883 SET_PSR_C (tmp
> 0xff);
4884 SET_PSR_F (((a
& 0x80) != (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
4885 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
4886 trace_output_16 (sd
, tmp
);
4891 OP_3A_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4894 uint16 b
= GPR (OP
[1]);
4895 uint16 tmp
= (~a
+ 1 + b
);
4896 trace_input ("subw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4897 /* see ../common/sim-alu.h for a more extensive discussion on how to
4898 compute the carry/overflow bits. */
4899 SET_PSR_C (tmp
> 0xffff);
4900 SET_PSR_F (((a
& 0x8000) != (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
4901 SET_GPR (OP
[1], tmp
);
4902 trace_output_16 (sd
, tmp
);
4907 OP_3AB_C (SIM_DESC sd
, SIM_CPU
*cpu
)
4910 uint16 b
= GPR (OP
[1]);
4911 uint32 tmp
= (~a
+ 1 + b
);
4912 trace_input ("subw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
4913 /* see ../common/sim-alu.h for a more extensive discussion on how to
4914 compute the carry/overflow bits. */
4915 SET_PSR_C (tmp
> 0xffff);
4916 SET_PSR_F (((a
& 0x8000) != (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
4917 SET_GPR (OP
[1], tmp
& 0xffff);
4918 trace_output_16 (sd
, tmp
);
4923 OP_3B_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4925 uint16 a
= GPR (OP
[0]);
4926 uint16 b
= GPR (OP
[1]);
4927 uint32 tmp
= (~a
+ 1 + b
);
4928 trace_input ("subw", OP_REG
, OP_REG
, OP_VOID
);
4929 /* see ../common/sim-alu.h for a more extensive discussion on how to
4930 compute the carry/overflow bits. */
4931 SET_PSR_C (tmp
> 0xffff);
4932 SET_PSR_F (((a
& 0x8000) != (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
4933 SET_GPR (OP
[1], tmp
& 0xffff);
4934 trace_output_16 (sd
, tmp
);
4939 OP_3C_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4942 uint8 b
= (GPR (OP
[1])) & 0xff;
4943 //uint16 tmp1 = a + 1;
4944 uint16 tmp1
= a
+ (PSR_C
);
4945 uint16 tmp
= (~tmp1
+ 1 + b
);
4946 trace_input ("subcb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4947 /* see ../common/sim-alu.h for a more extensive discussion on how to
4948 compute the carry/overflow bits. */
4949 SET_PSR_C (tmp
> 0xff);
4950 SET_PSR_F (((a
& 0x80) != (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
4951 SET_GPR (OP
[1], tmp
);
4952 trace_output_16 (sd
, tmp
);
4957 OP_3CB_C (SIM_DESC sd
, SIM_CPU
*cpu
)
4960 uint16 b
= (GPR (OP
[1])) & 0xff;
4961 //uint16 tmp1 = a + 1;
4962 uint16 tmp1
= a
+ (PSR_C
);
4963 uint16 tmp
= (~tmp1
+ 1 + b
);
4964 trace_input ("subcb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
4965 /* see ../common/sim-alu.h for a more extensive discussion on how to
4966 compute the carry/overflow bits. */
4967 SET_PSR_C (tmp
> 0xff);
4968 SET_PSR_F (((a
& 0x80) != (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
4969 SET_GPR (OP
[1], tmp
);
4970 trace_output_16 (sd
, tmp
);
4975 OP_3D_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4977 uint16 a
= (GPR (OP
[0])) & 0xff;
4978 uint16 b
= (GPR (OP
[1])) & 0xff;
4979 uint16 tmp1
= a
+ (PSR_C
);
4980 uint16 tmp
= (~tmp1
+ 1 + b
);
4981 trace_input ("subcb", OP_REG
, OP_REG
, OP_VOID
);
4982 /* see ../common/sim-alu.h for a more extensive discussion on how to
4983 compute the carry/overflow bits. */
4984 SET_PSR_C (tmp
> 0xff);
4985 SET_PSR_F (((a
& 0x80) != (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
4986 SET_GPR (OP
[1], tmp
);
4987 trace_output_16 (sd
, tmp
);
4992 OP_3E_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
4994 uint16 a
= OP
[0], b
= (GPR (OP
[1]));
4995 uint16 tmp1
= a
+ (PSR_C
);
4996 uint16 tmp
= (~tmp1
+ 1 + b
);
4997 trace_input ("subcw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4998 /* see ../common/sim-alu.h for a more extensive discussion on how to
4999 compute the carry/overflow bits. */
5000 SET_PSR_C (tmp
> 0xffff);
5001 SET_PSR_F (((a
& 0x8000) != (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
5002 SET_GPR (OP
[1], tmp
);
5003 trace_output_16 (sd
, tmp
);
5008 OP_3EB_C (SIM_DESC sd
, SIM_CPU
*cpu
)
5011 uint16 b
= GPR (OP
[1]);
5012 uint16 tmp1
= a
+ (PSR_C
);
5013 uint16 tmp
= (~tmp1
+ 1 + b
);
5014 trace_input ("subcw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
5015 /* see ../common/sim-alu.h for a more extensive discussion on how to
5016 compute the carry/overflow bits. */
5017 SET_PSR_C (tmp
> 0xffff);
5018 SET_PSR_F (((a
& 0x8000) != (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
5019 SET_GPR (OP
[1], tmp
);
5020 trace_output_16 (sd
, tmp
);
5025 OP_3F_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
5027 uint16 a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
5028 uint16 tmp1
= a
+ (PSR_C
);
5029 uint16 tmp
= (~tmp1
+ 1 + b
);
5030 trace_input ("subcw", OP_REG
, OP_REG
, OP_VOID
);
5031 /* see ../common/sim-alu.h for a more extensive discussion on how to
5032 compute the carry/overflow bits. */
5033 SET_PSR_C (tmp
> 0xffff);
5034 SET_PSR_F (((a
& 0x8000) != (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
5035 SET_GPR (OP
[1], tmp
);
5036 trace_output_16 (sd
, tmp
);
5041 OP_3_C (SIM_DESC sd
, SIM_CPU
*cpu
)
5044 uint32 b
= GPR32 (OP
[1]);
5045 uint32 tmp
= (~a
+ 1 + b
);
5046 trace_input ("subd", OP_CONSTANT32
, OP_REGP
, OP_VOID
);
5047 /* see ../common/sim-alu.h for a more extensive discussion on how to
5048 compute the carry/overflow bits. */
5049 SET_PSR_C (tmp
> 0xffffffff);
5050 SET_PSR_F (((a
& 0x80000000) != (b
& 0x80000000)) &&
5051 ((b
& 0x80000000) != (tmp
& 0x80000000)));
5052 SET_GPR32 (OP
[1], tmp
);
5053 trace_output_32 (sd
, tmp
);
5058 OP_14C_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
5060 uint32 a
= GPR32 (OP
[0]);
5061 uint32 b
= GPR32 (OP
[1]);
5062 uint32 tmp
= (~a
+ 1 + b
);
5063 trace_input ("subd", OP_REGP
, OP_REGP
, OP_VOID
);
5064 /* see ../common/sim-alu.h for a more extensive discussion on how to
5065 compute the carry/overflow bits. */
5066 SET_PSR_C (tmp
> 0xffffffff);
5067 SET_PSR_F (((a
& 0x80000000) != (b
& 0x80000000)) &&
5068 ((b
& 0x80000000) != (tmp
& 0x80000000)));
5069 SET_GPR32 (OP
[1], tmp
);
5070 trace_output_32 (sd
, tmp
);
5075 OP_C_C (SIM_DESC sd
, SIM_CPU
*cpu
)
5079 trace_input ("excp", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
5083 #if (DEBUG & DEBUG_TRAP) == 0
5086 uint16 vec
= OP
[0] + TRAP_VECTOR_START
;
5089 SET_PSR (PSR
& PSR_SM_BIT
);
5094 #else /* if debugging use trap to print registers */
5097 static int first_time
= 1;
5102 (*cr16_callback
->printf_filtered
) (cr16_callback
, "Trap # PC ");
5103 for (i
= 0; i
< 16; i
++)
5104 (*cr16_callback
->printf_filtered
) (cr16_callback
, " %sr%d", (i
> 9) ? "" : " ", i
);
5105 (*cr16_callback
->printf_filtered
) (cr16_callback
, " a0 a1 f0 f1 c\n");
5108 (*cr16_callback
->printf_filtered
) (cr16_callback
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
5110 for (i
= 0; i
< 16; i
++)
5111 (*cr16_callback
->printf_filtered
) (cr16_callback
, " %.4x", (int) GPR (i
));
5113 for (i
= 0; i
< 2; i
++)
5114 (*cr16_callback
->printf_filtered
) (cr16_callback
, " %.2x%.8lx",
5115 ((int)(ACC (i
) >> 32) & 0xff),
5116 ((unsigned long) ACC (i
)) & 0xffffffff);
5118 (*cr16_callback
->printf_filtered
) (cr16_callback
, " %d %d %d\n",
5119 PSR_F
!= 0, PSR_F
!= 0, PSR_C
!= 0);
5120 (*cr16_callback
->flush_stdout
) (cr16_callback
);
5124 case 8: /* new system call trap */
5125 /* Trap 8 is used for simulating low-level I/O */
5127 unsigned32 result
= 0;
5130 /* Registers passed to trap 0. */
5132 #define FUNC GPR (0) /* function number. */
5133 #define PARM1 GPR (2) /* optional parm 1. */
5134 #define PARM2 GPR (3) /* optional parm 2. */
5135 #define PARM3 GPR (4) /* optional parm 3. */
5136 #define PARM4 GPR (5) /* optional parm 4. */
5138 /* Registers set by trap 0 */
5140 #define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0)
5141 #define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0)
5142 #define RETERR(X) SET_GPR (4, (X)) /* return error code. */
5144 /* Turn a pointer in a register into a pointer into real memory. */
5146 #define MEMPTR(x) sim_core_trans_addr (sd, cpu, read_map, x)
5150 #if !defined(__GO32__) && !defined(_WIN32)
5151 #ifdef TARGET_SYS_fork
5152 case TARGET_SYS_fork
:
5153 trace_input ("<fork>", OP_VOID
, OP_VOID
, OP_VOID
);
5155 trace_output_16 (sd
, result
);
5160 case TARGET_SYS_getpid
:
5161 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
5163 trace_output_16 (sd
, result
);
5166 case TARGET_SYS_kill
:
5167 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
5168 if (PARM1
== getpid ())
5170 trace_output_void (sd
);
5171 State
.exception
= PARM2
;
5179 case 1: os_sig
= SIGHUP
; break;
5182 case 2: os_sig
= SIGINT
; break;
5185 case 3: os_sig
= SIGQUIT
; break;
5188 case 4: os_sig
= SIGILL
; break;
5191 case 5: os_sig
= SIGTRAP
; break;
5194 case 6: os_sig
= SIGABRT
; break;
5195 #elif defined(SIGIOT)
5196 case 6: os_sig
= SIGIOT
; break;
5199 case 7: os_sig
= SIGEMT
; break;
5202 case 8: os_sig
= SIGFPE
; break;
5205 case 9: os_sig
= SIGKILL
; break;
5208 case 10: os_sig
= SIGBUS
; break;
5211 case 11: os_sig
= SIGSEGV
; break;
5214 case 12: os_sig
= SIGSYS
; break;
5217 case 13: os_sig
= SIGPIPE
; break;
5220 case 14: os_sig
= SIGALRM
; break;
5223 case 15: os_sig
= SIGTERM
; break;
5226 case 16: os_sig
= SIGURG
; break;
5229 case 17: os_sig
= SIGSTOP
; break;
5232 case 18: os_sig
= SIGTSTP
; break;
5235 case 19: os_sig
= SIGCONT
; break;
5238 case 20: os_sig
= SIGCHLD
; break;
5239 #elif defined(SIGCLD)
5240 case 20: os_sig
= SIGCLD
; break;
5243 case 21: os_sig
= SIGTTIN
; break;
5246 case 22: os_sig
= SIGTTOU
; break;
5249 case 23: os_sig
= SIGIO
; break;
5250 #elif defined (SIGPOLL)
5251 case 23: os_sig
= SIGPOLL
; break;
5254 case 24: os_sig
= SIGXCPU
; break;
5257 case 25: os_sig
= SIGXFSZ
; break;
5260 case 26: os_sig
= SIGVTALRM
; break;
5263 case 27: os_sig
= SIGPROF
; break;
5266 case 28: os_sig
= SIGWINCH
; break;
5269 case 29: os_sig
= SIGLOST
; break;
5272 case 30: os_sig
= SIGUSR1
; break;
5275 case 31: os_sig
= SIGUSR2
; break;
5281 trace_output_void (sd
);
5282 (*cr16_callback
->printf_filtered
) (cr16_callback
, "Unknown signal %d\n", PARM2
);
5283 (*cr16_callback
->flush_stdout
) (cr16_callback
);
5284 State
.exception
= SIGILL
;
5288 RETVAL (kill (PARM1
, PARM2
));
5289 trace_output_16 (sd
, result
);
5294 #ifdef TARGET_SYS_execve
5295 case TARGET_SYS_execve
:
5296 trace_input ("<execve>", OP_VOID
, OP_VOID
, OP_VOID
);
5297 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
<<16|PARM3
),
5298 (char **)MEMPTR (PARM4
)));
5299 trace_output_16 (sd
, result
);
5303 #ifdef TARGET_SYS_execv
5304 case TARGET_SYS_execv
:
5305 trace_input ("<execv>", OP_VOID
, OP_VOID
, OP_VOID
);
5306 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
));
5307 trace_output_16 (sd
, result
);
5311 #ifdef TARGET_SYS_pipe
5312 case TARGET_SYS_pipe
:
5317 trace_input ("<pipe>", OP_VOID
, OP_VOID
, OP_VOID
);
5319 RETVAL (pipe (host_fd
));
5320 SW (buf
, host_fd
[0]);
5321 buf
+= sizeof(uint16
);
5322 SW (buf
, host_fd
[1]);
5323 trace_output_16 (sd
, result
);
5328 #ifdef TARGET_SYS_wait
5329 case TARGET_SYS_wait
:
5332 trace_input ("<wait>", OP_REG
, OP_VOID
, OP_VOID
);
5333 RETVAL (wait (&status
));
5336 trace_output_16 (sd
, result
);
5341 case TARGET_SYS_getpid
:
5342 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
5344 trace_output_16 (sd
, result
);
5347 case TARGET_SYS_kill
:
5348 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
5349 trace_output_void (sd
);
5350 State
.exception
= PARM2
;
5354 case TARGET_SYS_read
:
5355 trace_input ("<read>", OP_REG
, OP_MEMREF
, OP_REG
);
5356 RETVAL (cr16_callback
->read (cr16_callback
, PARM1
,
5357 MEMPTR (((unsigned long)PARM3
<< 16)
5358 |((unsigned long)PARM2
)), PARM4
));
5359 trace_output_16 (sd
, result
);
5362 case TARGET_SYS_write
:
5363 trace_input ("<write>", OP_REG
, OP_MEMREF
, OP_REG
);
5364 RETVAL ((int)cr16_callback
->write (cr16_callback
, PARM1
,
5365 MEMPTR (((unsigned long)PARM3
<< 16) | PARM2
), PARM4
));
5366 trace_output_16 (sd
, result
);
5369 case TARGET_SYS_lseek
:
5370 trace_input ("<lseek>", OP_REG
, OP_REGP
, OP_REG
);
5371 RETVAL32 (cr16_callback
->lseek (cr16_callback
, PARM1
,
5372 ((((long) PARM3
) << 16) | PARM2
),
5374 trace_output_32 (sd
, result
);
5377 case TARGET_SYS_close
:
5378 trace_input ("<close>", OP_REG
, OP_VOID
, OP_VOID
);
5379 RETVAL (cr16_callback
->close (cr16_callback
, PARM1
));
5380 trace_output_16 (sd
, result
);
5383 case TARGET_SYS_open
:
5384 trace_input ("<open>", OP_MEMREF
, OP_REG
, OP_VOID
);
5385 RETVAL32 (cr16_callback
->open (cr16_callback
,
5386 MEMPTR ((((unsigned long)PARM2
)<<16)|PARM1
),
5388 trace_output_32 (sd
, result
);
5391 #ifdef TARGET_SYS_rename
5392 case TARGET_SYS_rename
:
5393 trace_input ("<rename>", OP_MEMREF
, OP_MEMREF
, OP_VOID
);
5394 RETVAL (cr16_callback
->rename (cr16_callback
,
5395 MEMPTR ((((unsigned long)PARM2
)<<16) |PARM1
),
5396 MEMPTR ((((unsigned long)PARM4
)<<16) |PARM3
)));
5397 trace_output_16 (sd
, result
);
5401 case 0x408: /* REVISIT: Added a dummy getenv call. */
5402 trace_input ("<getenv>", OP_MEMREF
, OP_MEMREF
, OP_VOID
);
5404 trace_output_32 (sd
, result
);
5407 case TARGET_SYS_exit
:
5408 trace_input ("<exit>", OP_VOID
, OP_VOID
, OP_VOID
);
5409 State
.exception
= SIG_CR16_EXIT
;
5410 trace_output_void (sd
);
5413 case TARGET_SYS_unlink
:
5414 trace_input ("<unlink>", OP_MEMREF
, OP_VOID
, OP_VOID
);
5415 RETVAL (cr16_callback
->unlink (cr16_callback
,
5416 MEMPTR (((unsigned long)PARM2
<<16)|PARM1
)));
5417 trace_output_16 (sd
, result
);
5421 #ifdef TARGET_SYS_stat
5422 case TARGET_SYS_stat
:
5423 trace_input ("<stat>", OP_VOID
, OP_VOID
, OP_VOID
);
5424 /* stat system call. */
5426 struct stat host_stat
;
5429 RETVAL (stat (MEMPTR ((((unsigned long)PARM2
) << 16)|PARM1
), &host_stat
));
5433 /* The hard-coded offsets and sizes were determined by using
5434 * the CR16 compiler on a test program that used struct stat.
5436 SW (buf
, host_stat
.st_dev
);
5437 SW (buf
+2, host_stat
.st_ino
);
5438 SW (buf
+4, host_stat
.st_mode
);
5439 SW (buf
+6, host_stat
.st_nlink
);
5440 SW (buf
+8, host_stat
.st_uid
);
5441 SW (buf
+10, host_stat
.st_gid
);
5442 SW (buf
+12, host_stat
.st_rdev
);
5443 SLW (buf
+16, host_stat
.st_size
);
5444 SLW (buf
+20, host_stat
.st_atime
);
5445 SLW (buf
+28, host_stat
.st_mtime
);
5446 SLW (buf
+36, host_stat
.st_ctime
);
5448 trace_output_16 (sd
, result
);
5452 #ifdef TARGET_SYS_chown
5453 case TARGET_SYS_chown
:
5454 trace_input ("<chown>", OP_VOID
, OP_VOID
, OP_VOID
);
5455 RETVAL (chown (MEMPTR (PARM1
), PARM2
, PARM3
));
5456 trace_output_16 (sd
, result
);
5460 case TARGET_SYS_chmod
:
5461 trace_input ("<chmod>", OP_VOID
, OP_VOID
, OP_VOID
);
5462 RETVAL (chmod (MEMPTR (PARM1
), PARM2
));
5463 trace_output_16 (sd
, result
);
5466 #ifdef TARGET_SYS_utime
5467 case TARGET_SYS_utime
:
5468 trace_input ("<utime>", OP_REG
, OP_REG
, OP_REG
);
5469 /* Cast the second argument to void *, to avoid type mismatch
5470 if a prototype is present. */
5471 RETVAL (utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
)));
5472 trace_output_16 (sd
, result
);
5476 #ifdef TARGET_SYS_time
5477 case TARGET_SYS_time
:
5478 trace_input ("<time>", OP_VOID
, OP_VOID
, OP_REG
);
5479 RETVAL32 (time (NULL
));
5480 trace_output_32 (sd
, result
);
5488 case TRAP_BREAKPOINT
:
5489 State
.exception
= SIGTRAP
;
5492 trace_output_void (sd
);
5494 case SIGTRAP
: /* supervisor call ? */
5495 State
.exception
= SIG_CR16_EXIT
;
5496 trace_output_void (sd
);
5499 cr16_callback
->error (cr16_callback
, "Unknown syscall %d", FUNC
);
5503 if ((uint16
) result
== (uint16
) -1)
5504 RETERR (cr16_callback
->get_errno(cr16_callback
));
5515 OP_3_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
5517 uint16 a
= OP
[0] + 1, b
= OP
[1], c
= OP
[2], i
= 0;
5518 uint32 tmp
, sp_addr
= (GPR32 (15)) - (a
* 2) - 4, is_regp
= 0;
5519 trace_input ("push", OP_CONSTANT3
, OP_REG
, OP_REG
);
5525 SW (sp_addr
, (GPR (b
+i
)));
5531 tmp
= (GPR32 (b
+i
));
5533 tmp
= (GPR32 (b
+i
-1));
5552 /* Store RA address. */
5556 sp_addr
= (GPR32 (15)) - (a
* 2) - 4;
5557 SET_GPR32 (15, sp_addr
); /* Update SP address. */
5559 trace_output_void (sd
);
5564 OP_1_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
5566 uint32 sp_addr
, tmp
, is_regp
= 0;
5567 uint16 a
= OP
[0] + 1, b
= OP
[1], c
= OP
[2], i
= 0;
5568 trace_input ("push", OP_CONSTANT3
, OP_REG
, OP_VOID
);
5571 sp_addr
= (GPR32 (15)) - (a
* 2) - 4;
5573 sp_addr
= (GPR32 (15)) - (a
* 2);
5579 SW (sp_addr
, (GPR (b
+i
)));
5585 tmp
= (GPR32 (b
+i
));
5587 tmp
= (GPR32 (b
+i
-1));
5606 /* Store RA address. */
5609 sp_addr
= (GPR32 (15)) - (a
* 2) - 4;
5612 sp_addr
= (GPR32 (15)) - (a
* 2);
5614 SET_GPR32 (15, sp_addr
); /* Update SP address. */
5616 trace_output_void (sd
);
5622 OP_11E_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5624 uint32 sp_addr
= (GPR32 (15)), tmp
;
5625 trace_input ("push", OP_VOID
, OP_VOID
, OP_VOID
);
5627 SLW(sp_addr
-4,tmp
); /* Store RA address. */
5628 SET_GPR32 (15, (sp_addr
- 4)); /* Update SP address. */
5629 trace_output_void (sd
);
5635 OP_5_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
5637 uint16 a
= OP
[0] + 1, b
= OP
[1], c
= OP
[2], i
= 0;
5638 uint32 tmp
, sp_addr
= (GPR32 (15)), is_regp
= 0;;
5639 trace_input ("pop", OP_CONSTANT3
, OP_REG
, OP_REG
);
5645 SET_GPR ((b
+i
), RW(sp_addr
));
5661 tmp
= (tmp
<< 16) | (GPR32 (b
+i
));
5663 tmp
= (tmp
<< 16) | (GPR32 (b
+i
-1));
5667 SET_GPR32 ((b
+i
), (((tmp
& 0xffff) << 16)
5668 | ((tmp
>> 16) & 0xffff)));
5670 SET_GPR32 ((b
+i
-1), (((tmp
& 0xffff) << 16)
5671 | ((tmp
>> 16) & 0xffff)));
5678 tmp
= RLW(sp_addr
); /* store RA also. */
5679 SET_GPR32 (14, (((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff)));
5681 SET_GPR32 (15, (sp_addr
+ 4)); /* Update SP address. */
5683 trace_output_void (sd
);
5688 OP_2_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
5690 uint16 a
= OP
[0] + 1, b
= OP
[1], c
= OP
[2], i
= 0;
5691 uint32 tmp
, sp_addr
= (GPR32 (15)), is_regp
= 0;
5692 trace_input ("pop", OP_CONSTANT3
, OP_REG
, OP_VOID
);
5698 SET_GPR ((b
+i
), RW(sp_addr
));
5714 tmp
= ((tmp
<< 16) & 0xffffffff) | (GPR32 (b
+i
));
5716 tmp
= ((tmp
<< 16) & 0xffffffff) | (GPR32 (b
+i
-1));
5720 SET_GPR32 ((b
+i
), (((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff)));
5722 SET_GPR32 ((b
+i
-1), (((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff)));
5730 tmp
= RLW(sp_addr
); /* Store RA Reg. */
5731 SET_GPR32 (14, (((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff)));
5735 SET_GPR32 (15, sp_addr
); /* Update SP address. */
5737 trace_output_void (sd
);
5742 OP_21E_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5744 uint32 sp_addr
= GPR32 (15);
5746 trace_input ("pop", OP_VOID
, OP_VOID
, OP_VOID
);
5749 SET_GPR32 (14, (((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff)));
5750 SET_GPR32 (15, (sp_addr
+4)); /* Update SP address. */
5752 trace_output_void (sd
);
5757 OP_7_9 (SIM_DESC sd
, SIM_CPU
*cpu
)
5759 uint16 a
= OP
[0], b
= OP
[1];
5760 trace_input ("popret", OP_CONSTANT3
, OP_REG
, OP_REG
);
5762 JMP(((GPR32(14)) << 1) & 0xffffff);
5764 trace_output_void (sd
);
5769 OP_3_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
5771 uint16 a
= OP
[0], b
= OP
[1];
5772 trace_input ("popret", OP_CONSTANT3
, OP_REG
, OP_VOID
);
5774 JMP(((GPR32(14)) << 1) & 0xffffff);
5776 trace_output_void (sd
);
5781 OP_31E_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5784 trace_input ("popret", OP_VOID
, OP_VOID
, OP_VOID
);
5785 OP_21E_10 (sd
, cpu
);
5786 tmp
= (((GPR32(14)) << 1) & 0xffffff);
5787 /* If the resulting PC value is less than 0x00_0000 or greater
5788 than 0xFF_FFFF, this instruction causes an IAD trap.*/
5790 if ((tmp
< 0x0) || (tmp
> 0xFFFFFF))
5792 State
.exception
= SIG_CR16_BUS
;
5793 State
.pc_changed
= 1; /* Don't increment the PC. */
5794 trace_output_void (sd
);
5800 trace_output_32 (sd
, tmp
);
5806 OP_A_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5808 trace_input ("cinv[i]", OP_VOID
, OP_VOID
, OP_VOID
);
5810 trace_output_void (sd
);
5815 OP_B_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5817 trace_input ("cinv[i,u]", OP_VOID
, OP_VOID
, OP_VOID
);
5819 trace_output_void (sd
);
5824 OP_C_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5826 trace_input ("cinv[d]", OP_VOID
, OP_VOID
, OP_VOID
);
5828 trace_output_void (sd
);
5833 OP_D_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5835 trace_input ("cinv[i,u]", OP_VOID
, OP_VOID
, OP_VOID
);
5837 trace_output_void (sd
);
5842 OP_E_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5844 trace_input ("cinv[d,i]", OP_VOID
, OP_VOID
, OP_VOID
);
5846 trace_output_void (sd
);
5851 OP_F_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5853 trace_input ("cinv[d,i,u]", OP_VOID
, OP_VOID
, OP_VOID
);
5855 trace_output_void (sd
);
5860 OP_3_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5862 trace_input ("retx", OP_VOID
, OP_VOID
, OP_VOID
);
5864 trace_output_void (sd
);
5869 OP_4_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5871 trace_input ("di", OP_VOID
, OP_VOID
, OP_VOID
);
5873 trace_output_void (sd
);
5878 OP_5_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5880 trace_input ("ei", OP_VOID
, OP_VOID
, OP_VOID
);
5882 trace_output_void (sd
);
5887 OP_6_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5889 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
5890 State
.exception
= SIGTRAP
;
5891 trace_output_void (sd
);
5896 OP_7_10 (SIM_DESC sd
, SIM_CPU
*cpu
)
5898 trace_input ("ewait", OP_VOID
, OP_VOID
, OP_VOID
);
5900 trace_output_void (sd
);
5905 OP_28_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
5907 uint8 tmp
, a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
5908 trace_input ("xorb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
5910 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
5911 trace_output_16 (sd
, tmp
);
5916 OP_28B_C (SIM_DESC sd
, SIM_CPU
*cpu
)
5918 uint8 tmp
, a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
5919 trace_input ("xorb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
5921 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
5922 trace_output_16 (sd
, tmp
);
5927 OP_29_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
5929 uint8 tmp
, a
= (GPR (OP
[0])) & 0xff, b
= (GPR (OP
[1])) & 0xff;
5930 trace_input ("xorb", OP_REG
, OP_REG
, OP_VOID
);
5932 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
5933 trace_output_16 (sd
, tmp
);
5938 OP_2A_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
5940 uint16 tmp
, a
= (OP
[0]), b
= (GPR (OP
[1]));
5941 trace_input ("xorw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
5943 SET_GPR (OP
[1], tmp
);
5944 trace_output_16 (sd
, tmp
);
5949 OP_2AB_C (SIM_DESC sd
, SIM_CPU
*cpu
)
5951 uint16 tmp
, a
= (OP
[0]), b
= (GPR (OP
[1]));
5952 trace_input ("xorw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
5954 SET_GPR (OP
[1], tmp
);
5955 trace_output_16 (sd
, tmp
);
5960 OP_2B_8 (SIM_DESC sd
, SIM_CPU
*cpu
)
5962 uint16 tmp
, a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
5963 trace_input ("xorw", OP_REG
, OP_REG
, OP_VOID
);
5965 SET_GPR (OP
[1], tmp
);
5966 trace_output_16 (sd
, tmp
);
5969 /*REVISIT FOR LPR/SPR . */
5973 OP_140_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
5975 uint16 a
= GPR (OP
[0]);
5976 trace_input ("lpr", OP_REG
, OP_REG
, OP_VOID
);
5977 SET_CREG (OP
[1], a
);
5978 trace_output_16 (sd
, a
);
5983 OP_141_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
5985 uint32 a
= GPR32 (OP
[0]);
5986 trace_input ("lprd", OP_REGP
, OP_REG
, OP_VOID
);
5987 SET_CREG (OP
[1], a
);
5988 trace_output_flag (sd
);
5993 OP_142_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
5995 uint16 a
= CREG (OP
[0]);
5996 trace_input ("spr", OP_REG
, OP_REG
, OP_VOID
);
5998 trace_output_16 (sd
, a
);
6003 OP_143_14 (SIM_DESC sd
, SIM_CPU
*cpu
)
6005 uint32 a
= CREG (OP
[0]);
6006 trace_input ("sprd", OP_REGP
, OP_REGP
, OP_VOID
);
6007 SET_GPR32 (OP
[1], a
);
6008 trace_output_32 (sd
, a
);
6013 OP_0_20 (SIM_DESC sd
, SIM_CPU
*cpu
)
6015 trace_input ("null", OP_VOID
, OP_VOID
, OP_VOID
);
6016 State
.exception
= SIG_CR16_STOP
;
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