1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008-2015 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include <sys/types.h>
36 #ifdef HAVE_SYS_TIME_H
42 #include "targ-vals.h"
44 #ifdef TARGET_SYS_utime
47 #ifdef TARGET_SYS_wait
110 PSR_MASK
= (PSR_I_BIT
120 /* The following bits in the PSR _can't_ be set by instructions such
122 PSR_HW_MASK
= (PSR_MASK
)
125 /* cond Code Condition True State
126 * EQ Equal Z flag is 1
127 * NE Not Equal Z flag is 0
128 * CS Carry Set C flag is 1
129 * CC Carry Clear C flag is 0
130 * HI Higher L flag is 1
131 * LS Lower or Same L flag is 0
132 * GT Greater Than N flag is 1
133 * LE Less Than or Equal To N flag is 0
134 * FS Flag Set F flag is 1
135 * FC Flag Clear F flag is 0
136 * LO Lower Z and L flags are 0
137 * HS Higher or Same Z or L flag is 1
138 * LT Less Than Z and N flags are 0
139 * GE Greater Than or Equal To Z or N flag is 1. */
141 static int cond_stat(int cc
)
145 case 0: return PSR_Z
; break;
146 case 1: return !PSR_Z
; break;
147 case 2: return PSR_C
; break;
148 case 3: return !PSR_C
; break;
149 case 4: return PSR_L
; break;
150 case 5: return !PSR_L
; break;
151 case 6: return PSR_N
; break;
152 case 7: return !PSR_N
; break;
153 case 8: return PSR_F
; break;
154 case 9: return !PSR_F
; break;
155 case 10: return !PSR_Z
&& !PSR_L
; break;
156 case 11: return PSR_Z
|| PSR_L
; break;
157 case 12: return !PSR_Z
&& !PSR_N
; break;
158 case 13: return PSR_Z
|| PSR_N
; break;
159 case 14: return 1; break; /*ALWAYS. */
161 // case NEVER: return false; break;
163 //panic("Shouldn't have NO_COND_CODE in an actual instruction!");
171 move_to_cr (int cr
, creg_t mask
, creg_t val
, int psw_hw_p
)
173 /* A MASK bit is set when the corresponding bit in the CR should
175 /* This assumes that (VAL & MASK) == 0. */
184 (*cr16_callback
->printf_filtered
)
186 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC
);
187 State
.exception
= SIGILL
;
189 /* keep an up-to-date psw around for tracing. */
190 State
.trace
.psw
= (State
.trace
.psw
& mask
) | val
;
195 /* only issue an update if the register is being changed. */
196 if ((State
.cregs
[cr
] & ~mask
) != val
)
197 SLOT_PEND_MASK (State
.cregs
[cr
], mask
, val
);
203 static void trace_input_func (const char *name
,
208 #define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (name, in1, in2, in3); } while (0)
210 #ifndef SIZE_INSTRUCTION
211 #define SIZE_INSTRUCTION 8
214 #ifndef SIZE_OPERANDS
215 #define SIZE_OPERANDS 18
219 #define SIZE_VALUES 13
222 #ifndef SIZE_LOCATION
223 #define SIZE_LOCATION 20
230 #ifndef SIZE_LINE_NUMBER
231 #define SIZE_LINE_NUMBER 2
235 trace_input_func (const char *name
, enum op_types in1
, enum op_types in2
, enum op_types in3
)
244 const char *filename
;
245 const char *functionname
;
246 unsigned int linenumber
;
249 if ((cr16_debug
& DEBUG_TRACE
) == 0)
252 switch (State
.ins_type
)
255 case INS_UNKNOWN
: type
= " ?"; break;
258 if ((cr16_debug
& DEBUG_LINE_NUMBER
) == 0)
259 (*cr16_callback
->printf_filtered
) (cr16_callback
,
261 SIZE_PC
, (unsigned)PC
,
263 SIZE_INSTRUCTION
, name
);
267 extern SIM_DESC trace_sd
;
271 if (STATE_TEXT_SECTION (trace_sd
)
272 && byte_pc
>= STATE_TEXT_START (trace_sd
)
273 && byte_pc
< STATE_TEXT_END (trace_sd
))
275 filename
= (const char *)0;
276 functionname
= (const char *)0;
278 if (bfd_find_nearest_line (STATE_PROG_BFD (trace_sd
),
279 STATE_TEXT_SECTION (trace_sd
),
280 (struct bfd_symbol
**)0,
281 byte_pc
- STATE_TEXT_START (trace_sd
),
282 &filename
, &functionname
, &linenumber
))
287 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
292 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
293 p
+= SIZE_LINE_NUMBER
+2;
298 sprintf (p
, "%s ", functionname
);
303 char *q
= strrchr (filename
, '/');
304 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
313 (*cr16_callback
->printf_filtered
) (cr16_callback
,
314 "0x%.*x %s: %-*.*s %-*s ",
315 SIZE_PC
, (unsigned)PC
,
317 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
318 SIZE_INSTRUCTION
, name
);
326 for (i
= 0; i
< 3; i
++)
335 sprintf (p
, "%sr%d", comma
, OP
[i
]);
341 sprintf (p
, "%scr%d", comma
, OP
[i
]);
347 sprintf (p
, "%s%d", comma
, OP
[i
]);
353 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
359 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
365 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
371 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
377 sprintf (p
, "%s@%d", comma
, OP
[i
]);
384 if ((cr16_debug
& DEBUG_VALUES
) == 0)
388 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%s", buf
);
393 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%-*s", SIZE_OPERANDS
, buf
);
396 for (i
= 0; i
< 3; i
++)
402 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s", SIZE_VALUES
, "");
406 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
407 (uint16
) GPR (OP
[i
]));
411 tmp
= (long)((((uint32
) GPR (OP
[i
])) << 16) | ((uint32
) GPR (OP
[i
] + 1)));
412 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
416 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
417 (uint16
) CREG (OP
[i
]));
421 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
426 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
427 (uint16
)SEXT4(OP
[i
]));
431 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
432 (uint16
)SEXT3(OP
[i
]));
436 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
438 (*cr16_callback
->printf_filtered
) (cr16_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
439 (uint16
)GPR (OP
[i
+ 1]));
446 (*cr16_callback
->flush_stdout
) (cr16_callback
);
450 do_trace_output_flush (void)
452 (*cr16_callback
->flush_stdout
) (cr16_callback
);
456 do_trace_output_finish (void)
458 (*cr16_callback
->printf_filtered
) (cr16_callback
,
459 " F0=%d F1=%d C=%d\n",
460 (State
.trace
.psw
& PSR_F_BIT
) != 0,
461 (State
.trace
.psw
& PSR_F_BIT
) != 0,
462 (State
.trace
.psw
& PSR_C_BIT
) != 0);
463 (*cr16_callback
->flush_stdout
) (cr16_callback
);
468 trace_output_40 (uint64 val
)
470 if ((cr16_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
472 (*cr16_callback
->printf_filtered
) (cr16_callback
,
473 " :: %*s0x%.2x%.8lx",
476 ((int)(val
>> 32) & 0xff),
477 ((unsigned long) val
) & 0xffffffff);
478 do_trace_output_finish ();
484 trace_output_32 (uint32 val
)
486 if ((cr16_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
488 (*cr16_callback
->printf_filtered
) (cr16_callback
,
493 do_trace_output_finish ();
498 trace_output_16 (uint16 val
)
500 if ((cr16_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
502 (*cr16_callback
->printf_filtered
) (cr16_callback
,
507 do_trace_output_finish ();
512 trace_output_void (void)
514 if ((cr16_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
516 (*cr16_callback
->printf_filtered
) (cr16_callback
, "\n");
517 do_trace_output_flush ();
522 trace_output_flag (void)
524 if ((cr16_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
526 (*cr16_callback
->printf_filtered
) (cr16_callback
,
530 do_trace_output_finish ();
538 #define trace_input(NAME, IN1, IN2, IN3)
539 #define trace_output(RESULT)
547 uint8 a
= OP
[0] & 0xff;
548 uint16 b
= (GPR (OP
[1])) & 0xff;
549 trace_input ("addub", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
550 tmp
= (a
+ b
) & 0xff;
551 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
552 trace_output_16 (tmp
);
560 uint8 a
= ((OP
[0]) & 0xff), b
= (GPR (OP
[1])) & 0xff;
561 trace_input ("addub", OP_CONSTANT16
, OP_REG
, OP_VOID
);
562 tmp
= (a
+ b
) & 0xff;
563 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
564 trace_output_16 (tmp
);
571 uint8 a
= (GPR (OP
[0])) & 0xff;
572 uint8 b
= (GPR (OP
[1])) & 0xff;
573 uint16 tmp
= (a
+ b
) & 0xff;
574 trace_input ("addub", OP_REG
, OP_REG
, OP_VOID
);
575 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
576 trace_output_16 (tmp
);
584 uint16 b
= GPR (OP
[1]);
585 uint16 tmp
= (a
+ b
);
586 trace_input ("adduw", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
587 SET_GPR (OP
[1], tmp
);
588 trace_output_16 (tmp
);
596 uint16 b
= GPR (OP
[1]);
597 uint16 tmp
= (a
+ b
);
598 trace_input ("adduw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
599 SET_GPR (OP
[1], tmp
);
600 trace_output_16 (tmp
);
607 uint16 a
= GPR (OP
[0]);
608 uint16 b
= GPR (OP
[1]);
609 uint16 tmp
= (a
+ b
);
610 trace_input ("adduw", OP_REG
, OP_REG
, OP_VOID
);
611 SET_GPR (OP
[1], tmp
);
612 trace_output_16 (tmp
);
620 uint8 b
= (GPR (OP
[1]) & 0xff);
621 uint16 tmp
= (a
+ b
) & 0xff;
622 trace_input ("addb", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
623 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
624 SET_PSR_C (tmp
> 0xFF);
625 SET_PSR_F (((a
& 0x80) == (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
626 trace_output_16 (tmp
);
633 uint8 a
= (OP
[0]) & 0xff;
634 uint8 b
= (GPR (OP
[1]) & 0xff);
635 uint16 tmp
= (a
+ b
) & 0xff;
636 trace_input ("addb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
637 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
638 SET_PSR_C (tmp
> 0xFF);
639 SET_PSR_F (((a
& 0x80) == (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
640 trace_output_16 (tmp
);
647 uint8 a
= (GPR (OP
[0]) & 0xff);
648 uint8 b
= (GPR (OP
[1]) & 0xff);
649 uint16 tmp
= (a
+ b
) & 0xff;
650 trace_input ("addb", OP_REG
, OP_REG
, OP_VOID
);
651 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
652 SET_PSR_C (tmp
> 0xFF);
653 SET_PSR_F (((a
& 0x80) == (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
654 trace_output_16 (tmp
);
662 uint16 tmp
, b
= GPR (OP
[1]);
664 trace_input ("addw", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
665 SET_GPR (OP
[1], tmp
);
666 SET_PSR_C (tmp
> 0xFFFF);
667 SET_PSR_F (((a
& 0x8000) == (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
668 trace_output_16 (tmp
);
676 uint16 tmp
, b
= GPR (OP
[1]);
678 trace_input ("addw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
679 SET_GPR (OP
[1], tmp
);
680 SET_PSR_C (tmp
> 0xFFFF);
681 SET_PSR_F (((a
& 0x8000) == (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
682 trace_output_16 (tmp
);
689 uint16 tmp
, a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
690 trace_input ("addw", OP_REG
, OP_REG
, OP_VOID
);
692 SET_GPR (OP
[1], tmp
);
693 SET_PSR_C (tmp
> 0xFFFF);
694 SET_PSR_F (((a
& 0x8000) == (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
695 trace_output_16 (tmp
);
702 uint8 tmp
, a
= OP
[0] & 0xff, b
= (GPR (OP
[1])) & 0xff;
703 trace_input ("addcb", OP_CONSTANT4_1
, OP_REG
, OP_REG
);
704 tmp
= (a
+ b
+ PSR_C
) & 0xff;
705 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
706 SET_PSR_C (tmp
> 0xFF);
707 SET_PSR_F (((a
& 0x80) == (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
708 trace_output_16 (tmp
);
715 int8 a
= OP
[0] & 0xff;
716 uint8 b
= (GPR (OP
[1])) & 0xff;
717 uint8 tmp
= (a
+ b
+ PSR_C
) & 0xff;
718 trace_input ("addcb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
719 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
720 SET_PSR_C (tmp
> 0xFF);
721 SET_PSR_F (((a
& 0x80) == (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
722 trace_output_16 (tmp
);
729 uint8 a
= (GPR (OP
[0])) & 0xff;
730 uint8 b
= (GPR (OP
[1])) & 0xff;
731 uint8 tmp
= (a
+ b
+ PSR_C
) & 0xff;
732 trace_input ("addcb", OP_REG
, OP_REG
, OP_VOID
);
733 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
734 SET_PSR_C (tmp
> 0xFF);
735 SET_PSR_F (((a
& 0x80) == (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
736 trace_output_16 (tmp
);
744 uint16 b
= GPR (OP
[1]);
745 uint16 tmp
= (a
+ b
+ PSR_C
);
746 trace_input ("addcw", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
747 SET_GPR (OP
[1], tmp
);
748 SET_PSR_C (tmp
> 0xFFFF);
749 SET_PSR_F (((a
& 0x8000) == (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
750 trace_output_16 (tmp
);
758 uint16 b
= GPR (OP
[1]);
759 uint16 tmp
= (a
+ b
+ PSR_C
);
760 trace_input ("addcw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
761 SET_GPR (OP
[1], tmp
);
762 SET_PSR_C (tmp
> 0xFFFF);
763 SET_PSR_F (((a
& 0x8000) == (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
764 trace_output_16 (tmp
);
771 uint16 a
= GPR (OP
[1]);
772 uint16 b
= GPR (OP
[1]);
773 uint16 tmp
= (a
+ b
+ PSR_C
);
774 trace_input ("addcw", OP_REG
, OP_REG
, OP_VOID
);
775 SET_GPR (OP
[1], tmp
);
776 SET_PSR_C (tmp
> 0xFFFF);
777 SET_PSR_F (((a
& 0x8000) == (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
778 trace_output_16 (tmp
);
786 uint32 b
= GPR32 (OP
[1]);
787 uint32 tmp
= (a
+ b
);
788 trace_input ("addd", OP_CONSTANT4_1
, OP_REGP
, OP_VOID
);
789 SET_GPR32 (OP
[1], tmp
);
790 SET_PSR_C (tmp
> 0xFFFFFFFF);
791 SET_PSR_F (((a
& 0x80000000) == (b
& 0x80000000)) && ((b
& 0x80000000) != (tmp
& 0x80000000)));
792 trace_output_32 (tmp
);
799 int32 a
= (SEXT16(OP
[0]));
800 uint32 b
= GPR32 (OP
[1]);
801 uint32 tmp
= (a
+ b
);
802 trace_input ("addd", OP_CONSTANT16
, OP_REGP
, OP_VOID
);
803 SET_GPR32 (OP
[1], tmp
);
804 SET_PSR_C (tmp
> 0xFFFFFFFF);
805 SET_PSR_F (((a
& 0x80000000) == (b
& 0x80000000)) && ((b
& 0x80000000) != (tmp
& 0x80000000)));
806 trace_output_32 (tmp
);
813 uint32 a
= GPR32 (OP
[0]);
814 uint32 b
= GPR32 (OP
[1]);
815 uint32 tmp
= (a
+ b
);
816 trace_input ("addd", OP_REGP
, OP_REGP
, OP_VOID
);
817 SET_GPR32 (OP
[1], tmp
);
818 trace_output_32 (tmp
);
819 SET_PSR_C (tmp
> 0xFFFFFFFF);
820 SET_PSR_F (((a
& 0x80000000) == (b
& 0x80000000)) && ((b
& 0x80000000) != (tmp
& 0x80000000)));
828 uint32 b
= GPR32 (OP
[1]);
830 trace_input ("addd", OP_CONSTANT20
, OP_REGP
, OP_VOID
);
832 SET_GPR32 (OP
[1], tmp
);
833 SET_PSR_C (tmp
> 0xFFFFFFFF);
834 SET_PSR_F (((a
& 0x80000000) == (b
& 0x80000000)) && ((b
& 0x80000000) != (tmp
& 0x80000000)));
835 trace_output_32 (tmp
);
843 uint32 b
= GPR32 (OP
[1]);
845 trace_input ("addd", OP_CONSTANT32
, OP_REGP
, OP_VOID
);
847 SET_GPR32 (OP
[1], tmp
);
848 SET_PSR_C (tmp
> 0xFFFFFFFF);
849 SET_PSR_F (((a
& 0x80000000) == (b
& 0x80000000)) && ((b
& 0x80000000) != (tmp
& 0x80000000)));
850 trace_output_32 (tmp
);
857 uint8 tmp
, a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
858 trace_input ("andb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
860 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
861 trace_output_16 (tmp
);
868 uint8 tmp
, a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
869 trace_input ("andb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
871 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
872 trace_output_16 (tmp
);
879 uint8 tmp
, a
= (GPR (OP
[0])) & 0xff, b
= (GPR (OP
[1])) & 0xff;
880 trace_input ("andb", OP_REG
, OP_REG
, OP_VOID
);
882 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
883 trace_output_16 (tmp
);
890 uint16 tmp
, a
= OP
[0], b
= GPR (OP
[1]);
891 trace_input ("andw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
893 SET_GPR (OP
[1], tmp
);
894 trace_output_16 (tmp
);
901 uint16 tmp
, a
= OP
[0], b
= GPR (OP
[1]);
902 trace_input ("andw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
904 SET_GPR (OP
[1], tmp
);
905 trace_output_16 (tmp
);
912 uint16 tmp
, a
= GPR (OP
[0]), b
= GPR (OP
[1]);
913 trace_input ("andw", OP_REG
, OP_REG
, OP_VOID
);
915 SET_GPR (OP
[1], tmp
);
916 trace_output_16 (tmp
);
923 uint32 tmp
, a
= OP
[0], b
= GPR32 (OP
[1]);
924 trace_input ("andd", OP_CONSTANT32
, OP_REGP
, OP_VOID
);
926 SET_GPR32 (OP
[1], tmp
);
927 trace_output_32 (tmp
);
934 uint32 tmp
, a
= (GPR32 (OP
[0])), b
= (GPR32 (OP
[1]));
935 trace_input ("andd", OP_REGP
, OP_REGP
, OP_VOID
);
937 SET_GPR32 (OP
[1], tmp
);
938 trace_output_32 (tmp
);
945 uint32 tmp
, a
= (OP
[0]), b
= GPR32 (OP
[1]);
946 trace_input ("ord", OP_CONSTANT32
, OP_REG
, OP_VOID
);
948 SET_GPR32 (OP
[1], tmp
);
949 trace_output_32 (tmp
);
956 uint32 tmp
, a
= GPR32 (OP
[0]), b
= GPR32 (OP
[1]);
957 trace_input ("ord", OP_REGP
, OP_REGP
, OP_VOID
);
959 SET_GPR32 (OP
[1], tmp
);
960 trace_output_32 (tmp
);
967 uint32 tmp
, a
= (OP
[0]), b
= GPR32 (OP
[1]);
968 trace_input ("xord", OP_CONSTANT32
, OP_REG
, OP_VOID
);
970 SET_GPR32 (OP
[1], tmp
);
971 trace_output_32 (tmp
);
978 uint32 tmp
, a
= GPR32 (OP
[0]), b
= GPR32 (OP
[1]);
979 trace_input ("xord", OP_REGP
, OP_REGP
, OP_VOID
);
981 SET_GPR32 (OP
[1], tmp
);
982 trace_output_32 (tmp
);
990 uint32 tmp
= 0, cc
= cond_stat (OP
[0]);
991 trace_input ("b", OP_CONSTANT4
, OP_DISPE9
, OP_VOID
);
995 tmp
= (PC
- (OP
[1]));
997 tmp
= (PC
+ (OP
[1]));
998 /* If the resulting PC value is less than 0x00_0000 or greater
999 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1001 if ((tmp
< 0x000000) || (tmp
> 0xFFFFFF))
1003 State
.exception
= SIG_CR16_BUS
;
1004 State
.pc_changed
= 1; /* Don't increment the PC. */
1005 trace_output_void ();
1011 sign_flag
= 0; /* Reset sign_flag. */
1012 trace_output_32 (tmp
);
1019 uint32 tmp
= 0, cc
= cond_stat (OP
[0]);
1020 trace_input ("b", OP_CONSTANT4
, OP_DISP17
, OP_VOID
);
1027 /* If the resulting PC value is less than 0x00_0000 or greater
1028 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1030 if ((tmp
< 0x000000) || (tmp
> 0xFFFFFF))
1032 State
.exception
= SIG_CR16_BUS
;
1033 State
.pc_changed
= 1; /* Don't increment the PC. */
1034 trace_output_void ();
1040 sign_flag
= 0; /* Reset sign_flag. */
1041 trace_output_32 (tmp
);
1048 uint32 tmp
= 0, cc
= cond_stat (OP
[0]);
1049 trace_input ("b", OP_CONSTANT4
, OP_DISP25
, OP_VOID
);
1053 tmp
= (PC
- (OP
[1]));
1055 tmp
= (PC
+ (OP
[1]));
1056 /* If the resulting PC value is less than 0x00_0000 or greater
1057 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1059 if ((tmp
< 0x000000) || (tmp
> 0xFFFFFF))
1061 State
.exception
= SIG_CR16_BUS
;
1062 State
.pc_changed
= 1; /* Don't increment the PC. */
1063 trace_output_void ();
1069 sign_flag
= 0; /* Reset sign_flag. */
1070 trace_output_32 (tmp
);
1078 trace_input ("bal", OP_REG
, OP_DISP17
, OP_VOID
);
1079 tmp
= ((PC
+ 4) >> 1); /* Store PC in RA register. */
1080 SET_GPR32 (14, tmp
);
1082 tmp
= (PC
- (OP
[1]));
1084 tmp
= (PC
+ (OP
[1]));
1086 /* If the resulting PC value is less than 0x00_0000 or greater
1087 than 0xFF_FFFF, this instruction causes an IAD trap. */
1089 if ((tmp
< 0x000000) || (tmp
> 0xFFFFFF))
1091 State
.exception
= SIG_CR16_BUS
;
1092 State
.pc_changed
= 1; /* Don't increment the PC. */
1093 trace_output_void ();
1098 sign_flag
= 0; /* Reset sign_flag. */
1099 trace_output_32 (tmp
);
1108 trace_input ("bal", OP_REGP
, OP_DISP25
, OP_VOID
);
1109 tmp
= (((PC
) + 4) >> 1); /* Store PC in reg pair. */
1110 SET_GPR32 (OP
[0], tmp
);
1112 tmp
= ((PC
) - (OP
[1]));
1114 tmp
= ((PC
) + (OP
[1]));
1115 /* If the resulting PC value is less than 0x00_0000 or greater
1116 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1118 if ((tmp
< 0x000000) || (tmp
> 0xFFFFFF))
1120 State
.exception
= SIG_CR16_BUS
;
1121 State
.pc_changed
= 1; /* Don't increment the PC. */
1122 trace_output_void ();
1127 sign_flag
= 0; /* Reset sign_flag. */
1128 trace_output_32 (tmp
);
1136 trace_input ("jal", OP_REGP
, OP_REGP
, OP_VOID
);
1137 SET_GPR32 (OP
[0], (((PC
) + 4) >> 1)); /* Store next PC in RA */
1138 tmp
= GPR32 (OP
[1]);
1139 tmp
= SEXT24(tmp
<< 1);
1140 /* If the resulting PC value is less than 0x00_0000 or greater
1141 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1143 if ((tmp
< 0x0) || (tmp
> 0xFFFFFF))
1145 State
.exception
= SIG_CR16_BUS
;
1146 State
.pc_changed
= 1; /* Don't increment the PC. */
1147 trace_output_void ();
1153 trace_output_32 (tmp
);
1162 trace_input ("jal", OP_REGP
, OP_VOID
, OP_VOID
);
1163 SET_GPR32 (14, (((PC
) + 2) >> 1)); /* Store next PC in RA */
1164 tmp
= GPR32 (OP
[0]);
1165 tmp
= SEXT24(tmp
<< 1);
1166 /* If the resulting PC value is less than 0x00_0000 or greater
1167 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1169 if ((tmp
< 0x0) || (tmp
> 0xFFFFFF))
1171 State
.exception
= SIG_CR16_BUS
;
1172 State
.pc_changed
= 1; /* Don't increment the PC. */
1173 trace_output_void ();
1179 trace_output_32 (tmp
);
1188 uint8 a
= (GPR (OP
[0]) & 0xFF);
1189 trace_input ("beq0b", OP_REG
, OP_DISP5
, OP_VOID
);
1194 addr
= (PC
- OP
[1]);
1196 addr
= (PC
+ OP
[1]);
1200 sign_flag
= 0; /* Reset sign_flag. */
1201 trace_output_void ();
1209 uint8 a
= (GPR (OP
[0]) & 0xFF);
1210 trace_input ("bne0b", OP_REG
, OP_DISP5
, OP_VOID
);
1215 addr
= (PC
- OP
[1]);
1217 addr
= (PC
+ OP
[1]);
1221 sign_flag
= 0; /* Reset sign_flag. */
1222 trace_output_void ();
1230 uint16 a
= GPR (OP
[0]);
1231 trace_input ("beq0w", OP_REG
, OP_DISP5
, OP_VOID
);
1236 addr
= (PC
- OP
[1]);
1238 addr
= (PC
+ OP
[1]);
1242 sign_flag
= 0; /* Reset sign_flag. */
1243 trace_output_void ();
1251 uint16 a
= GPR (OP
[0]);
1252 trace_input ("bne0w", OP_REG
, OP_DISP5
, OP_VOID
);
1257 addr
= (PC
- OP
[1]);
1259 addr
= (PC
+ OP
[1]);
1263 sign_flag
= 0; /* Reset sign_flag. */
1264 trace_output_void ();
1273 trace_input ("jeq", OP_REGP
, OP_VOID
, OP_VOID
);
1276 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1277 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1279 trace_output_32 (tmp
);
1287 trace_input ("jne", OP_REGP
, OP_VOID
, OP_VOID
);
1290 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1291 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1293 trace_output_32 (tmp
);
1301 trace_input ("jcs", OP_REGP
, OP_VOID
, OP_VOID
);
1304 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1305 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1307 trace_output_32 (tmp
);
1315 trace_input ("jcc", OP_REGP
, OP_VOID
, OP_VOID
);
1318 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1319 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1321 trace_output_32 (tmp
);
1329 trace_input ("jhi", OP_REGP
, OP_VOID
, OP_VOID
);
1332 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1333 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1335 trace_output_32 (tmp
);
1343 trace_input ("jls", OP_REGP
, OP_VOID
, OP_VOID
);
1346 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1347 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1349 trace_output_32 (tmp
);
1357 trace_input ("jgt", OP_REGP
, OP_VOID
, OP_VOID
);
1360 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1361 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1363 trace_output_32 (tmp
);
1371 trace_input ("jle", OP_REGP
, OP_VOID
, OP_VOID
);
1374 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1375 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1377 trace_output_32 (tmp
);
1386 trace_input ("jfs", OP_REGP
, OP_VOID
, OP_VOID
);
1389 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1390 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1392 trace_output_32 (tmp
);
1400 trace_input ("jfc", OP_REGP
, OP_VOID
, OP_VOID
);
1403 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1404 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1406 trace_output_32 (tmp
);
1414 trace_input ("jlo", OP_REGP
, OP_VOID
, OP_VOID
);
1415 if (((PSR_Z
) == 0) & ((PSR_L
) == 0))
1417 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1418 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1420 trace_output_32 (tmp
);
1428 trace_input ("jhs", OP_REGP
, OP_VOID
, OP_VOID
);
1429 if (((PSR_Z
) == 1) | ((PSR_L
) == 1))
1431 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1432 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1434 trace_output_32 (tmp
);
1442 trace_input ("jlt", OP_REGP
, OP_VOID
, OP_VOID
);
1443 if (((PSR_Z
) == 0) & ((PSR_N
) == 0))
1445 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1446 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1448 trace_output_32 (tmp
);
1456 trace_input ("jge", OP_REGP
, OP_VOID
, OP_VOID
);
1457 if (((PSR_Z
) == 1) | ((PSR_N
) == 1))
1459 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1460 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1462 trace_output_32 (tmp
);
1470 trace_input ("jump", OP_REGP
, OP_VOID
, OP_VOID
);
1471 tmp
= GPR32 (OP
[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
1472 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1473 trace_output_32 (tmp
);
1481 trace_input ("jusr", OP_REGP
, OP_VOID
, OP_VOID
);
1482 tmp
= (GPR32 (OP
[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1483 JMP (tmp
<< 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1485 trace_output_32 (tmp
);
1492 trace_input ("seq", OP_REG
, OP_VOID
, OP_VOID
);
1497 trace_output_void ();
1503 trace_input ("sne", OP_REG
, OP_VOID
, OP_VOID
);
1508 trace_output_void ();
1515 trace_input ("scs", OP_REG
, OP_VOID
, OP_VOID
);
1520 trace_output_void ();
1527 trace_input ("scc", OP_REG
, OP_VOID
, OP_VOID
);
1532 trace_output_void ();
1539 trace_input ("shi", OP_REG
, OP_VOID
, OP_VOID
);
1544 trace_output_void ();
1551 trace_input ("sls", OP_REG
, OP_VOID
, OP_VOID
);
1556 trace_output_void ();
1563 trace_input ("sgt", OP_REG
, OP_VOID
, OP_VOID
);
1568 trace_output_void ();
1575 trace_input ("sle", OP_REG
, OP_VOID
, OP_VOID
);
1580 trace_output_void ();
1587 trace_input ("sfs", OP_REG
, OP_VOID
, OP_VOID
);
1592 trace_output_void ();
1599 trace_input ("sfc", OP_REG
, OP_VOID
, OP_VOID
);
1604 trace_output_void ();
1612 trace_input ("slo", OP_REG
, OP_VOID
, OP_VOID
);
1613 if (((PSR_Z
) == 0) & ((PSR_L
) == 0))
1617 trace_output_void ();
1624 trace_input ("shs", OP_REG
, OP_VOID
, OP_VOID
);
1625 if ( ((PSR_Z
) == 1) | ((PSR_L
) == 1))
1629 trace_output_void ();
1636 trace_input ("slt", OP_REG
, OP_VOID
, OP_VOID
);
1637 if (((PSR_Z
) == 0) & ((PSR_N
) == 0))
1641 trace_output_void ();
1648 trace_input ("sge", OP_REG
, OP_VOID
, OP_VOID
);
1649 if (((PSR_Z
) == 1) | ((PSR_N
) == 1))
1653 trace_output_void ();
1660 uint8 a
= OP
[0] & 0xff;
1661 uint32 addr
= OP
[1], tmp
;
1662 trace_input ("cbitb", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
1664 SET_PSR_F (tmp
& (1 << a
));
1665 tmp
= tmp
& ~(1 << a
);
1667 trace_output_32 (tmp
);
1674 uint8 a
= OP
[0] & 0xff;
1675 uint32 addr
= OP
[1], tmp
;
1676 trace_input ("cbitb", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
1678 SET_PSR_F (tmp
& (1 << a
));
1679 tmp
= tmp
& ~(1 << a
);
1681 trace_output_32 (tmp
);
1688 uint8 a
= (OP
[0]) & 0xff;
1689 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
1690 trace_input ("cbitb", OP_CONSTANT4
, OP_R_INDEX7_ABS20
, OP_VOID
);
1692 SET_PSR_F (tmp
& (1 << a
));
1693 tmp
= tmp
& ~(1 << a
);
1695 trace_output_32 (addr
);
1702 uint8 a
= (OP
[0]) & 0xff;
1703 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1704 trace_input ("cbitb", OP_CONSTANT4
, OP_RP_INDEX_DISP14
, OP_VOID
);
1706 SET_PSR_F (tmp
& (1 << a
));
1707 tmp
= tmp
& ~(1 << a
);
1709 trace_output_32 (addr
);
1716 uint8 a
= (OP
[0]) & 0xff;
1717 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
1718 trace_input ("cbitb", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
1720 SET_PSR_F (tmp
& (1 << a
));
1721 tmp
= tmp
& ~(1 << a
);
1723 trace_output_32 (addr
);
1730 uint8 a
= (OP
[0]) & 0xff;
1731 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1732 trace_input ("cbitb", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
1734 SET_PSR_F (tmp
& (1 << a
));
1735 tmp
= tmp
& ~(1 << a
);
1737 trace_output_32 (addr
);
1744 uint8 a
= (OP
[0]) & 0xff;
1745 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1746 trace_input ("cbitb", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
1748 SET_PSR_F (tmp
& (1 << a
));
1749 tmp
= tmp
& ~(1 << a
);
1751 trace_output_32 (addr
);
1759 uint8 a
= (OP
[0]) & 0xff;
1760 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1761 trace_input ("cbitb", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
1763 SET_PSR_F (tmp
& (1 << a
));
1764 tmp
= tmp
& ~(1 << a
);
1766 trace_output_32 (addr
);
1773 uint8 a
= (OP
[0]) & 0xff;
1774 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1775 trace_input ("cbitb", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
1777 SET_PSR_F (tmp
& (1 << a
));
1778 tmp
= tmp
& ~(1 << a
);
1780 trace_output_32 (addr
);
1789 uint32 addr
= OP
[1], tmp
;
1790 trace_input ("cbitw", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
1792 SET_PSR_F (tmp
& (1 << a
));
1793 tmp
= tmp
& ~(1 << a
);
1795 trace_output_32 (tmp
);
1803 uint32 addr
= OP
[1], tmp
;
1804 trace_input ("cbitw", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
1806 SET_PSR_F (tmp
& (1 << a
));
1807 tmp
= tmp
& ~(1 << a
);
1809 trace_output_32 (tmp
);
1817 uint16 a
= (OP
[0]), tmp
;
1818 trace_input ("cbitw", OP_CONSTANT4
, OP_R_INDEX8_ABS20
, OP_VOID
);
1821 addr
= (GPR32 (12)) + OP
[2];
1823 addr
= (GPR32 (13)) + OP
[2];
1826 SET_PSR_F (tmp
& (1 << a
));
1827 tmp
= tmp
& ~(1 << a
);
1829 trace_output_32 (addr
);
1838 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1839 trace_input ("cbitw", OP_CONSTANT4
, OP_RP_INDEX_DISP14
, OP_VOID
);
1841 SET_PSR_F (tmp
& (1 << a
));
1842 tmp
= tmp
& ~(1 << a
);
1844 trace_output_32 (addr
);
1852 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
1853 trace_input ("cbitw", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
1855 SET_PSR_F (tmp
& (1 << a
));
1856 tmp
= tmp
& ~(1 << a
);
1858 trace_output_32 (addr
);
1867 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1868 trace_input ("cbitw", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
1870 SET_PSR_F (tmp
& (1 << a
));
1871 tmp
= tmp
& ~(1 << a
);
1873 trace_output_32 (addr
);
1881 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1882 trace_input ("cbitw", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
1884 SET_PSR_F (tmp
& (1 << a
));
1885 tmp
= tmp
& ~(1 << a
);
1887 trace_output_32 (addr
);
1896 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1897 trace_input ("cbitw", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
1899 SET_PSR_F (tmp
& (1 << a
));
1900 tmp
= tmp
& ~(1 << a
);
1902 trace_output_32 (addr
);
1910 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1911 trace_input ("cbitw", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
1913 SET_PSR_F (tmp
& (1 << a
));
1914 tmp
= tmp
& ~(1 << a
);
1916 trace_output_32 (addr
);
1923 uint8 a
= OP
[0] & 0xff;
1924 uint32 addr
= OP
[1], tmp
;
1925 trace_input ("sbitb", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
1927 SET_PSR_F (tmp
& (1 << a
));
1928 tmp
= tmp
| (1 << a
);
1930 trace_output_32 (tmp
);
1937 uint8 a
= OP
[0] & 0xff;
1938 uint32 addr
= OP
[1], tmp
;
1939 trace_input ("sbitb", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
1941 SET_PSR_F (tmp
& (1 << a
));
1942 tmp
= tmp
| (1 << a
);
1944 trace_output_32 (tmp
);
1951 uint8 a
= OP
[0] & 0xff;
1952 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
1953 trace_input ("sbitb", OP_CONSTANT4
, OP_R_INDEX7_ABS20
, OP_VOID
);
1955 SET_PSR_F (tmp
& (1 << a
));
1956 tmp
= tmp
| (1 << a
);
1958 trace_output_32 (tmp
);
1965 uint8 a
= OP
[0] & 0xff;
1966 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1967 trace_input ("sbitb", OP_CONSTANT4
, OP_RP_INDEX_DISP14
, OP_VOID
);
1969 SET_PSR_F (tmp
& (1 << a
));
1970 tmp
= tmp
| (1 << a
);
1972 trace_output_32 (tmp
);
1979 uint8 a
= OP
[0] & 0xff;
1980 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
1981 trace_input ("sbitb", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
1983 SET_PSR_F (tmp
& (1 << a
));
1984 tmp
= tmp
| (1 << a
);
1986 trace_output_32 (tmp
);
1994 uint8 a
= OP
[0] & 0xff;
1995 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
1996 trace_input ("sbitb", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
1998 SET_PSR_F (tmp
& (1 << a
));
1999 tmp
= tmp
| (1 << a
);
2001 trace_output_32 (tmp
);
2008 uint8 a
= OP
[0] & 0xff;
2009 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2010 trace_input ("sbitb", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
2012 SET_PSR_F (tmp
& (1 << a
));
2013 tmp
= tmp
| (1 << a
);
2015 trace_output_32 (tmp
);
2023 uint8 a
= OP
[0] & 0xff;
2024 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2025 trace_input ("sbitb", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
2027 SET_PSR_F (tmp
& (1 << a
));
2028 tmp
= tmp
| (1 << a
);
2030 trace_output_32 (tmp
);
2038 uint8 a
= OP
[0] & 0xff;
2039 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2040 trace_input ("sbitb", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
2042 SET_PSR_F (tmp
& (1 << a
));
2043 tmp
= tmp
| (1 << a
);
2045 trace_output_32 (tmp
);
2054 uint32 addr
= OP
[1], tmp
;
2055 trace_input ("sbitw", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
2057 SET_PSR_F (tmp
& (1 << a
));
2058 tmp
= tmp
| (1 << a
);
2060 trace_output_32 (tmp
);
2068 uint32 addr
= OP
[1], tmp
;
2069 trace_input ("sbitw", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
2071 SET_PSR_F (tmp
& (1 << a
));
2072 tmp
= tmp
| (1 << a
);
2074 trace_output_32 (tmp
);
2082 uint16 a
= (OP
[0]), tmp
;
2083 trace_input ("sbitw", OP_CONSTANT4
, OP_R_INDEX8_ABS20
, OP_VOID
);
2086 addr
= (GPR32 (12)) + OP
[2];
2088 addr
= (GPR32 (13)) + OP
[2];
2091 SET_PSR_F (tmp
& (1 << a
));
2092 tmp
= tmp
| (1 << a
);
2094 trace_output_32 (addr
);
2102 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2103 trace_input ("sbitw", OP_CONSTANT4
, OP_RP_INDEX_DISP14
, OP_VOID
);
2105 SET_PSR_F (tmp
& (1 << a
));
2106 tmp
= tmp
| (1 << a
);
2108 trace_output_32 (addr
);
2116 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
2117 trace_input ("sbitw", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
2119 SET_PSR_F (tmp
& (1 << a
));
2120 tmp
= tmp
| (1 << a
);
2122 trace_output_32 (addr
);
2130 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2131 trace_input ("sbitw", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
2133 SET_PSR_F (tmp
& (1 << a
));
2134 tmp
= tmp
| (1 << a
);
2136 trace_output_32 (addr
);
2144 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2145 trace_input ("sbitw", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
2147 SET_PSR_F (tmp
& (1 << a
));
2148 tmp
= tmp
| (1 << a
);
2150 trace_output_32 (addr
);
2158 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2159 trace_input ("sbitw", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
2161 SET_PSR_F (tmp
& (1 << a
));
2162 tmp
= tmp
| (1 << a
);
2164 trace_output_32 (addr
);
2172 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2173 trace_input ("sbitw", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
2175 SET_PSR_F (tmp
& (1 << a
));
2176 tmp
= tmp
| (1 << a
);
2178 trace_output_32 (addr
);
2186 uint8 a
= OP
[0] & 0xff;
2187 uint32 addr
= OP
[1], tmp
;
2188 trace_input ("tbitb", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
2190 SET_PSR_F (tmp
& (1 << a
));
2191 trace_output_32 (tmp
);
2198 uint8 a
= OP
[0] & 0xff;
2199 uint32 addr
= OP
[1], tmp
;
2200 trace_input ("tbitb", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
2202 SET_PSR_F (tmp
& (1 << a
));
2203 trace_output_32 (tmp
);
2210 uint8 a
= (OP
[0]) & 0xff;
2211 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
2212 trace_input ("tbitb", OP_CONSTANT4
, OP_R_INDEX7_ABS20
, OP_VOID
);
2214 SET_PSR_F (tmp
& (1 << a
));
2215 trace_output_32 (addr
);
2222 uint8 a
= (OP
[0]) & 0xff;
2223 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2224 trace_input ("tbitb", OP_CONSTANT4
, OP_RP_INDEX_DISP14
, OP_VOID
);
2226 SET_PSR_F (tmp
& (1 << a
));
2227 trace_output_32 (addr
);
2234 uint8 a
= (OP
[0]) & 0xff;
2235 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
2236 trace_input ("tbitb", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
2238 SET_PSR_F (tmp
& (1 << a
));
2239 trace_output_32 (addr
);
2246 uint8 a
= (OP
[0]) & 0xff;
2247 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2248 trace_input ("tbitb", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
2250 SET_PSR_F (tmp
& (1 << a
));
2251 trace_output_32 (addr
);
2258 uint8 a
= (OP
[0]) & 0xff;
2259 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2260 trace_input ("tbitb", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
2262 SET_PSR_F (tmp
& (1 << a
));
2263 trace_output_32 (addr
);
2270 uint8 a
= (OP
[0]) & 0xff;
2271 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2272 trace_input ("tbitb", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
2274 SET_PSR_F (tmp
& (1 << a
));
2275 trace_output_32 (addr
);
2282 uint8 a
= (OP
[0]) & 0xff;
2283 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2284 trace_input ("tbitb", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
2286 SET_PSR_F (tmp
& (1 << a
));
2287 trace_output_32 (addr
);
2296 uint32 addr
= OP
[1], tmp
;
2297 trace_input ("tbitw", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
2299 SET_PSR_F (tmp
& (1 << a
));
2300 trace_output_32 (tmp
);
2308 uint32 addr
= OP
[1], tmp
;
2309 trace_input ("tbitw", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
2311 SET_PSR_F (tmp
& (1 << a
));
2312 trace_output_32 (tmp
);
2321 uint16 a
= (OP
[0]), tmp
;
2322 trace_input ("tbitw", OP_CONSTANT4
, OP_R_INDEX8_ABS20
, OP_VOID
);
2325 addr
= (GPR32 (12)) + OP
[2];
2327 addr
= (GPR32 (13)) + OP
[2];
2330 SET_PSR_F (tmp
& (1 << a
));
2331 trace_output_32 (addr
);
2339 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2340 trace_input ("tbitw", OP_CONSTANT4
, OP_RP_INDEX_DISP14
, OP_VOID
);
2342 SET_PSR_F (tmp
& (1 << a
));
2343 trace_output_32 (addr
);
2351 uint32 addr
= (GPR (OP
[2])) + OP
[1], tmp
;
2352 trace_input ("tbitw", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
2354 SET_PSR_F (tmp
& (1 << a
));
2355 trace_output_32 (addr
);
2363 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2364 trace_input ("tbitw", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
2366 SET_PSR_F (tmp
& (1 << a
));
2367 trace_output_32 (addr
);
2375 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2376 trace_input ("tbitw", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
2378 SET_PSR_F (tmp
& (1 << a
));
2379 trace_output_32 (addr
);
2387 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2388 trace_input ("tbitw", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
2390 SET_PSR_F (tmp
& (1 << a
));
2391 trace_output_32 (addr
);
2400 uint32 addr
= (GPR32 (OP
[2])) + OP
[1], tmp
;
2401 trace_input ("tbitw", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
2403 SET_PSR_F (tmp
& (1 << a
));
2404 trace_output_32 (addr
);
2413 uint16 b
= (GPR (OP
[1]));
2414 trace_input ("tbit", OP_CONSTANT4
, OP_REG
, OP_VOID
);
2415 SET_PSR_F (b
& (1 << a
));
2416 trace_output_16 (b
);
2423 uint16 a
= GPR (OP
[0]);
2424 uint16 b
= (GPR (OP
[1]));
2425 trace_input ("tbit", OP_REG
, OP_REG
, OP_VOID
);
2426 SET_PSR_F (b
& (1 << a
));
2427 trace_output_16 (b
);
2435 uint8 a
= (OP
[0]) & 0xFF;
2436 uint8 b
= (GPR (OP
[1])) & 0xFF;
2437 trace_input ("cmpb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
2439 SET_PSR_N ((int8
)a
> (int8
)b
);
2441 trace_output_flag ();
2448 uint8 a
= (OP
[0]) & 0xFF;
2449 uint8 b
= (GPR (OP
[1])) & 0xFF;
2450 trace_input ("cmpb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
2452 SET_PSR_N ((int8
)a
> (int8
)b
);
2454 trace_output_flag ();
2461 uint8 a
= (GPR (OP
[0])) & 0xFF;
2462 uint8 b
= (GPR (OP
[1])) & 0xFF;
2463 trace_input ("cmpb", OP_REG
, OP_REG
, OP_VOID
);
2465 SET_PSR_N ((int8
)a
> (int8
)b
);
2467 trace_output_flag ();
2475 uint16 b
= GPR (OP
[1]);
2476 trace_input ("cmpw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
2478 SET_PSR_N ((int16
)a
> (int16
)b
);
2480 trace_output_flag ();
2488 uint16 b
= GPR (OP
[1]);
2489 trace_input ("cmpw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
2491 SET_PSR_N ((int16
)a
> (int16
)b
);
2493 trace_output_flag ();
2500 uint16 a
= GPR (OP
[0]) ;
2501 uint16 b
= GPR (OP
[1]) ;
2502 trace_input ("cmpw", OP_REG
, OP_REG
, OP_VOID
);
2504 SET_PSR_N ((int16
)a
> (int16
)b
);
2506 trace_output_flag ();
2514 uint32 b
= GPR32 (OP
[1]);
2515 trace_input ("cmpd", OP_CONSTANT4
, OP_REGP
, OP_VOID
);
2517 SET_PSR_N ((int32
)a
> (int32
)b
);
2519 trace_output_flag ();
2526 uint32 a
= (SEXT16(OP
[0]));
2527 uint32 b
= GPR32 (OP
[1]);
2528 trace_input ("cmpd", OP_CONSTANT16
, OP_REGP
, OP_VOID
);
2530 SET_PSR_N ((int32
)a
> (int32
)b
);
2532 trace_output_flag ();
2539 uint32 a
= GPR32 (OP
[0]) ;
2540 uint32 b
= GPR32 (OP
[1]) ;
2541 trace_input ("cmpd", OP_REGP
, OP_REGP
, OP_VOID
);
2543 SET_PSR_N ((int32
)a
> (int32
)b
);
2545 trace_output_flag ();
2553 uint32 b
= GPR32 (OP
[1]);
2554 trace_input ("cmpd", OP_CONSTANT32
, OP_REGP
, OP_VOID
);
2556 SET_PSR_N ((int32
)a
> (int32
)b
);
2558 trace_output_flag ();
2566 uint8 tmp
= OP
[0] & 0xFF;
2567 uint16 a
= (GPR (OP
[1])) & 0xFF00;
2568 trace_input ("movb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
2569 SET_GPR (OP
[1], (a
| tmp
));
2570 trace_output_16 (tmp
);
2577 uint8 tmp
= OP
[0] & 0xFF;
2578 uint16 a
= (GPR (OP
[1])) & 0xFF00;
2579 trace_input ("movb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
2580 SET_GPR (OP
[1], (a
| tmp
));
2581 trace_output_16 (tmp
);
2588 uint8 tmp
= (GPR (OP
[0])) & 0xFF;
2589 uint16 a
= (GPR (OP
[1])) & 0xFF00;
2590 trace_input ("movb", OP_REG
, OP_REG
, OP_VOID
);
2591 SET_GPR (OP
[1], (a
| tmp
));
2592 trace_output_16 (tmp
);
2600 trace_input ("movw", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
2601 SET_GPR (OP
[1], (tmp
& 0xffff));
2602 trace_output_16 (tmp
);
2610 trace_input ("movw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
2611 SET_GPR (OP
[1], (tmp
& 0xffff));
2612 trace_output_16 (tmp
);
2619 uint16 tmp
= GPR (OP
[0]);
2620 uint32 a
= GPR32 (OP
[1]);
2621 trace_input ("movw", OP_REG
, OP_REGP
, OP_VOID
);
2622 a
= (a
& 0xffff0000) | tmp
;
2623 SET_GPR32 (OP
[1], a
);
2624 trace_output_16 (tmp
);
2631 uint8 tmp
= (GPR (OP
[0])) & 0xFF;
2632 trace_input ("movxb", OP_REG
, OP_REG
, OP_VOID
);
2633 SET_GPR (OP
[1], ((SEXT8(tmp
)) & 0xffff));
2634 trace_output_16 (tmp
);
2641 uint8 tmp
= (GPR (OP
[0])) & 0xFF;
2642 trace_input ("movzb", OP_REG
, OP_REG
, OP_VOID
);
2643 SET_GPR (OP
[1], tmp
);
2644 trace_output_16 (tmp
);
2651 uint16 tmp
= GPR (OP
[0]);
2652 trace_input ("movxw", OP_REG
, OP_REGP
, OP_VOID
);
2653 SET_GPR32 (OP
[1], SEXT16(tmp
));
2654 trace_output_16 (tmp
);
2661 uint16 tmp
= GPR (OP
[0]);
2662 trace_input ("movzw", OP_REG
, OP_REGP
, OP_VOID
);
2663 SET_GPR32 (OP
[1], (tmp
& 0x0000FFFF));
2664 trace_output_16 (tmp
);
2672 trace_input ("movd", OP_CONSTANT4
, OP_REGP
, OP_VOID
);
2673 SET_GPR32 (OP
[1], tmp
);
2674 trace_output_32 (tmp
);
2681 int32 tmp
= SEXT16(OP
[0]);
2682 trace_input ("movd", OP_CONSTANT16
, OP_REGP
, OP_VOID
);
2683 SET_GPR32 (OP
[1], tmp
);
2684 trace_output_32 (tmp
);
2691 uint32 tmp
= GPR32 (OP
[0]);
2692 trace_input ("movd", OP_REGP
, OP_REGP
, OP_VOID
);
2693 SET_GPR32 (OP
[1], tmp
);
2694 trace_output_32 (tmp
);
2702 trace_input ("movd", OP_CONSTANT20
, OP_REGP
, OP_VOID
);
2703 SET_GPR32 (OP
[1], tmp
);
2704 trace_output_32 (tmp
);
2712 trace_input ("movd", OP_CONSTANT32
, OP_REGP
, OP_VOID
);
2713 SET_GPR32 (OP
[1], tmp
);
2714 trace_output_32 (tmp
);
2721 uint32 addr
= GPR (0);
2722 uint16 count
= OP
[0], reg
= 2, tmp
;
2723 trace_input ("loadm", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
2726 State
.exception
= SIG_CR16_BUS
;
2727 State
.pc_changed
= 1; /* Don't increment the PC. */
2728 trace_output_void ();
2739 if (reg
== 6) reg
= 8;
2743 trace_output_void ();
2751 uint32 addr
= GPR32 (0);
2752 uint16 count
= OP
[0], reg
= 2, tmp
;
2753 trace_input ("loadm", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
2756 State
.exception
= SIG_CR16_BUS
;
2757 State
.pc_changed
= 1; /* Don't increment the PC. */
2758 trace_output_void ();
2769 if (reg
== 6) reg
= 8;
2772 SET_GPR32 (0, addr
);
2773 trace_output_void ();
2782 * ADDR = zext24(abs20) | remap (ie 0xF00000)
2785 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2786 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2787 * by the core to 16M-64k to 16M. */
2789 uint16 tmp
, a
= (GPR (OP
[1])) & 0xFF00;
2790 uint32 addr
= OP
[0];
2791 trace_input ("loadb", OP_ABS20
, OP_REG
, OP_VOID
);
2792 if (addr
> 0xEFFFF) addr
|= 0xF00000;
2794 SET_GPR (OP
[1], (a
| tmp
));
2795 trace_output_16 (tmp
);
2806 uint16 tmp
, a
= (GPR (OP
[1])) & 0xFF00;
2807 uint32 addr
= OP
[0];
2808 trace_input ("loadb", OP_ABS24
, OP_REG
, OP_VOID
);
2810 SET_GPR (OP
[1], (a
| tmp
));
2811 trace_output_16 (tmp
);
2818 /* loadb [Rindex]ABS20 REG
2819 * ADDR = Rindex + zext24(disp20)
2823 uint16 tmp
, a
= (GPR (OP
[2])) & 0xFF00;
2824 trace_input ("loadb", OP_R_INDEX8_ABS20
, OP_REG
, OP_VOID
);
2827 addr
= (GPR32 (12)) + OP
[1];
2829 addr
= (GPR32 (13)) + OP
[1];
2832 SET_GPR (OP
[2], (a
| tmp
));
2833 trace_output_16 (tmp
);
2841 /* loadb DIPS4(REGP) REG
2842 * ADDR = RPBASE + zext24(DISP4)
2844 uint16 tmp
, a
= (GPR (OP
[2])) & 0xFF00;
2845 uint32 addr
= (GPR32 (OP
[1])) + OP
[0];
2846 trace_input ("loadb", OP_RP_BASE_DISP4
, OP_REG
, OP_VOID
);
2848 SET_GPR (OP
[2], (a
| tmp
));
2849 trace_output_16 (tmp
);
2856 /* loadb [Rindex]disp0(RPbasex) REG
2857 * ADDR = Rpbasex + Rindex
2861 uint16 tmp
, a
= (GPR (OP
[3])) & 0xFF00;
2862 trace_input ("loadb", OP_RP_INDEX_DISP0
, OP_REG
, OP_VOID
);
2864 addr
= (GPR32 (OP
[2])) + OP
[1];
2867 addr
= (GPR32 (12)) + addr
;
2869 addr
= (GPR32 (13)) + addr
;
2872 SET_GPR (OP
[3], (a
| tmp
));
2873 trace_output_16 (tmp
);
2880 /* loadb [Rindex]disp14(RPbasex) REG
2881 * ADDR = Rpbasex + Rindex + zext24(disp14)
2885 uint16 tmp
, a
= (GPR (OP
[3])) & 0xFF00;
2887 addr
= (GPR32 (OP
[2])) + OP
[1];
2890 addr
= (GPR32 (12)) + addr
;
2892 addr
= (GPR32 (13)) + addr
;
2894 trace_input ("loadb", OP_RP_INDEX_DISP14
, OP_REG
, OP_VOID
);
2896 SET_GPR (OP
[3], (a
| tmp
));
2897 trace_output_16 (tmp
);
2905 /* loadb DISPE20(REG) REG
2906 * zext24(Rbase) + zext24(dispe20)
2909 uint16 tmp
,a
= (GPR (OP
[2])) & 0xFF00;
2910 uint32 addr
= OP
[0] + (GPR (OP
[1]));
2911 trace_input ("loadb", OP_R_BASE_DISPE20
, OP_REG
, OP_VOID
);
2913 SET_GPR (OP
[2], (a
| tmp
));
2914 trace_output_16 (tmp
);
2921 /* loadb DISP20(REG) REG
2922 * ADDR = zext24(Rbase) + zext24(disp20)
2925 uint16 tmp
,a
= (GPR (OP
[2])) & 0xFF00;
2926 uint32 addr
= OP
[0] + (GPR (OP
[1]));
2927 trace_input ("loadb", OP_R_BASE_DISP20
, OP_REG
, OP_VOID
);
2929 SET_GPR (OP
[2], (a
| tmp
));
2930 trace_output_16 (tmp
);
2937 /* loadb disp16(REGP) REG
2938 * ADDR = RPbase + zext24(disp16)
2941 uint16 tmp
,a
= (GPR (OP
[2])) & 0xFF00;
2942 uint32 addr
= (GPR32 (OP
[1])) + OP
[0];
2943 trace_input ("loadb", OP_RP_BASE_DISP16
, OP_REG
, OP_VOID
);
2945 SET_GPR (OP
[2], (a
| tmp
));
2946 trace_output_16 (tmp
);
2953 /* loadb disp20(REGP) REG
2954 * ADDR = RPbase + zext24(disp20)
2956 uint16 tmp
,a
= (GPR (OP
[2])) & 0xFF00;
2957 uint32 addr
= (GPR32 (OP
[1])) + OP
[0];
2958 trace_input ("loadb", OP_RP_BASE_DISP20
, OP_REG
, OP_VOID
);
2960 SET_GPR (OP
[2], (a
| tmp
));
2961 trace_output_16 (tmp
);
2969 /* loadb -disp20(REGP) REG
2970 * ADDR = RPbase + zext24(-disp20)
2972 uint16 tmp
,a
= (GPR (OP
[2])) & 0xFF00;
2973 uint32 addr
= (GPR32 (OP
[1])) + OP
[1];
2974 trace_input ("loadb", OP_RP_BASE_DISPE20
, OP_REG
, OP_VOID
);
2976 SET_GPR (OP
[2], (a
| tmp
));
2977 trace_output_16 (tmp
);
2984 /* loadb [Rindex]disp20(RPbasexb) REG
2985 * ADDR = RPbasex + Rindex + zext24(disp20)
2989 uint16 tmp
, a
= (GPR (OP
[3])) & 0xFF00;
2990 trace_input ("loadb", OP_RP_INDEX_DISP20
, OP_REG
, OP_VOID
);
2992 addr
= (GPR32 (OP
[2])) + OP
[1];
2995 addr
= (GPR32 (12)) + addr
;
2997 addr
= (GPR32 (13)) + addr
;
3000 SET_GPR (OP
[3], (a
| tmp
));
3001 trace_output_16 (tmp
);
3010 * ADDR = zext24(abs20) | remap
3013 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3014 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3015 * by the core to 16M-64k to 16M. */
3018 uint32 addr
= OP
[0];
3019 trace_input ("loadw", OP_ABS20
, OP_REG
, OP_VOID
);
3020 if (addr
> 0xEFFFF) addr
|= 0xF00000;
3022 SET_GPR (OP
[1], tmp
);
3023 trace_output_16 (tmp
);
3035 uint32 addr
= OP
[0];
3036 trace_input ("loadw", OP_ABS24
, OP_REG
, OP_VOID
);
3038 SET_GPR (OP
[1], tmp
);
3039 trace_output_16 (tmp
);
3046 /* loadw [Rindex]ABS20 REG
3047 * ADDR = Rindex + zext24(disp20)
3052 trace_input ("loadw", OP_R_INDEX8_ABS20
, OP_REG
, OP_VOID
);
3055 addr
= (GPR32 (12)) + OP
[1];
3057 addr
= (GPR32 (13)) + OP
[1];
3060 SET_GPR (OP
[2], tmp
);
3061 trace_output_16 (tmp
);
3069 /* loadw DIPS4(REGP) REGP
3070 * ADDR = RPBASE + zext24(DISP4)
3074 trace_input ("loadw", OP_RP_BASE_DISP4
, OP_REG
, OP_VOID
);
3075 addr
= (GPR32 (OP
[1])) + OP
[0];
3079 a
= (GPR32 (OP
[2])) & 0xffff0000;
3080 SET_GPR32 (OP
[2], (a
| tmp
));
3083 SET_GPR (OP
[2], tmp
);
3085 trace_output_16 (tmp
);
3093 /* loadw [Rindex]disp0(RPbasex) REG
3094 * ADDR = Rpbasex + Rindex
3099 trace_input ("loadw", OP_RP_INDEX_DISP0
, OP_REG
, OP_VOID
);
3101 addr
= (GPR32 (OP
[2])) + OP
[1];
3104 addr
= (GPR32 (12)) + addr
;
3106 addr
= (GPR32 (13)) + addr
;
3109 SET_GPR (OP
[3], tmp
);
3110 trace_output_16 (tmp
);
3118 /* loadw [Rindex]disp14(RPbasex) REG
3119 * ADDR = Rpbasex + Rindex + zext24(disp14)
3124 trace_input ("loadw", OP_RP_INDEX_DISP14
, OP_REG
, OP_VOID
);
3125 addr
= (GPR32 (OP
[2])) + OP
[1];
3128 addr
= (GPR32 (12)) + addr
;
3130 addr
= (GPR32 (13)) + addr
;
3133 SET_GPR (OP
[3], tmp
);
3134 trace_output_16 (tmp
);
3141 /* loadw dispe20(REG) REGP
3142 * REGP = [DISPE20+[REG]] */
3146 trace_input ("loadw", OP_R_BASE_DISPE20
, OP_REGP
, OP_VOID
);
3147 addr
= OP
[0] + (GPR (OP
[1]));
3151 a
= (GPR32 (OP
[2])) & 0xffff0000;
3152 SET_GPR32 (OP
[2], (a
| tmp
));
3155 SET_GPR (OP
[2], tmp
);
3157 trace_output_16 (tmp
);
3165 /* loadw DISP20(REG) REGP
3166 * ADDR = zext24(Rbase) + zext24(disp20)
3171 trace_input ("loadw", OP_R_BASE_DISP20
, OP_REGP
, OP_VOID
);
3172 addr
= OP
[0] + (GPR (OP
[1]));
3176 a
= (GPR32 (OP
[2])) & 0xffff0000;
3177 SET_GPR32 (OP
[2], (a
| tmp
));
3180 SET_GPR (OP
[2], tmp
);
3182 trace_output_16 (tmp
);
3189 /* loadw disp16(REGP) REGP
3190 * ADDR = RPbase + zext24(disp16)
3194 trace_input ("loadw", OP_RP_BASE_DISP16
, OP_REGP
, OP_VOID
);
3195 addr
= (GPR32 (OP
[1])) + OP
[0];
3199 a
= (GPR32 (OP
[2])) & 0xffff0000;
3200 SET_GPR32 (OP
[2], (a
| tmp
));
3203 SET_GPR (OP
[2], tmp
);
3205 trace_output_16 (tmp
);
3212 /* loadw disp20(REGP) REGP
3213 * ADDR = RPbase + zext24(disp20)
3217 trace_input ("loadw", OP_RP_BASE_DISP20
, OP_REG
, OP_VOID
);
3218 addr
= (GPR32 (OP
[1])) + OP
[0];
3222 a
= (GPR32 (OP
[2])) & 0xffff0000;
3223 SET_GPR32 (OP
[2], (a
| tmp
));
3226 SET_GPR (OP
[2], tmp
);
3228 trace_output_16 (tmp
);
3235 /* loadw -disp20(REGP) REG
3236 * ADDR = RPbase + zext24(-disp20)
3241 trace_input ("loadw", OP_RP_BASE_DISPE20
, OP_REG
, OP_VOID
);
3242 addr
= (GPR32 (OP
[1])) + OP
[0];
3246 a
= (GPR32 (OP
[2])) & 0xffff0000;
3247 SET_GPR32 (OP
[2], (a
| tmp
));
3250 SET_GPR (OP
[2], tmp
);
3252 trace_output_16 (tmp
);
3260 /* loadw [Rindex]disp20(RPbasexb) REG
3261 * ADDR = RPbasex + Rindex + zext24(disp20)
3266 trace_input ("loadw", OP_RP_INDEX_DISP20
, OP_REG
, OP_VOID
);
3269 addr
= (GPR32 (12)) + OP
[1] + (GPR32 (OP
[2]));
3271 addr
= (GPR32 (13)) + OP
[1] + (GPR32 (OP
[2]));
3274 SET_GPR (OP
[3], tmp
);
3275 trace_output_16 (tmp
);
3283 /* loadd ABS20, REGP
3284 * ADDR = zext24(abs20) | remap
3287 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3288 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3289 * by the core to 16M-64k to 16M. */
3293 trace_input ("loadd", OP_ABS20
, OP_REGP
, OP_VOID
);
3294 if (addr
> 0xEFFFF) addr
|= 0xF00000;
3296 tmp
= ((tmp
<< 16) & 0xffff)| ((tmp
>> 16) & 0xffff);
3297 SET_GPR32 (OP
[1], tmp
);
3298 trace_output_32 (tmp
);
3305 /* loadd ABS24, REGP
3309 uint32 addr
= OP
[0];
3311 trace_input ("loadd", OP_ABS24
, OP_REGP
, OP_VOID
);
3313 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3314 SET_GPR32 (OP
[1],tmp
);
3315 trace_output_32 (tmp
);
3323 /* loadd [Rindex]ABS20 REGP
3324 * ADDR = Rindex + zext24(disp20)
3328 trace_input ("loadd", OP_R_INDEX8_ABS20
, OP_REGP
, OP_VOID
);
3331 addr
= (GPR32 (12)) + OP
[1];
3333 addr
= (GPR32 (13)) + OP
[1];
3336 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3337 SET_GPR32 (OP
[2], tmp
);
3338 trace_output_32 (tmp
);
3346 /* loadd dips4(regp) REGP
3347 * ADDR = Rpbase + zext24(disp4)
3350 uint32 tmp
, addr
= (GPR32 (OP
[1])) + OP
[0];
3351 trace_input ("loadd", OP_RP_BASE_DISP4
, OP_REGP
, OP_VOID
);
3353 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3354 SET_GPR32 (OP
[2], tmp
);
3355 trace_output_32 (tmp
);
3363 /* loadd [Rindex]disp0(RPbasex) REGP
3364 * ADDR = Rpbasex + Rindex
3368 trace_input ("loadd", OP_RP_INDEX_DISP0
, OP_REGP
, OP_VOID
);
3371 addr
= (GPR32 (12)) + (GPR32 (OP
[2])) + OP
[1];
3373 addr
= (GPR32 (13)) + (GPR32 (OP
[2])) + OP
[1];
3376 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3377 SET_GPR32 (OP
[3], tmp
);
3378 trace_output_32 (tmp
);
3386 /* loadd [Rindex]disp14(RPbasex) REGP
3387 * ADDR = Rpbasex + Rindex + zext24(disp14)
3391 trace_input ("loadd", OP_RP_INDEX_DISP14
, OP_REGP
, OP_VOID
);
3394 addr
= (GPR32 (12)) + OP
[1] + (GPR32 (OP
[2]));
3396 addr
= (GPR32 (13)) + OP
[1] + (GPR32 (OP
[2]));
3399 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3400 SET_GPR (OP
[3],tmp
);
3401 trace_output_32 (tmp
);
3409 /* loadd dispe20(REG) REG
3410 * zext24(Rbase) + zext24(dispe20)
3413 uint32 tmp
, addr
= OP
[0] + (GPR (OP
[1]));
3414 trace_input ("loadd", OP_R_BASE_DISPE20
, OP_REGP
, OP_VOID
);
3416 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3417 SET_GPR32 (OP
[2], tmp
);
3418 trace_output_32 (tmp
);
3426 /* loadd DISP20(REG) REG
3427 * ADDR = zext24(Rbase) + zext24(disp20)
3430 uint32 tmp
, addr
= OP
[0] + (GPR (OP
[1]));
3431 trace_input ("loadd", OP_R_BASE_DISP20
, OP_REGP
, OP_VOID
);
3433 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3434 SET_GPR32 (OP
[2], tmp
);
3435 trace_output_32 (tmp
);
3442 /* loadd disp16(REGP) REGP
3443 * ADDR = RPbase + zext24(disp16)
3445 uint32 tmp
, addr
= OP
[0] + (GPR32 (OP
[1]));
3446 trace_input ("loadd", OP_RP_BASE_DISP16
, OP_REGP
, OP_VOID
);
3448 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3449 SET_GPR32 (OP
[2], tmp
);
3450 trace_output_32 (tmp
);
3458 /* loadd disp20(REGP) REGP
3459 * ADDR = RPbase + zext24(disp20)
3461 uint32 tmp
, addr
= OP
[0] + (GPR32 (OP
[1]));
3462 trace_input ("loadd", OP_RP_BASE_DISP20
, OP_REGP
, OP_VOID
);
3464 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3465 SET_GPR32 (OP
[2], tmp
);
3466 trace_output_32 (tmp
);
3473 /* loadd -disp20(REGP) REGP
3474 * ADDR = RPbase + zext24(-disp20)
3477 uint32 tmp
, addr
= OP
[0] + (GPR32 (OP
[1]));
3478 trace_input ("loadd", OP_RP_BASE_DISPE20
, OP_REGP
, OP_VOID
);
3480 tmp
= ((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff);
3481 SET_GPR32 (OP
[2], tmp
);
3482 trace_output_32 (tmp
);
3489 /* loadd [Rindex]disp20(RPbasexb) REGP
3490 * ADDR = RPbasex + Rindex + zext24(disp20)
3494 trace_input ("loadd", OP_RP_INDEX_DISP20
, OP_REGP
, OP_VOID
);
3497 addr
= (GPR32 (12)) + OP
[1] + (GPR32 (OP
[2]));
3499 addr
= (GPR32 (13)) + OP
[1] + (GPR32 (OP
[2]));
3502 tmp
= ((tmp
<< 16) & 0xffff)| ((tmp
>> 16) & 0xffff);
3503 SET_GPR32 (OP
[3], tmp
);
3504 trace_output_32 (tmp
);
3513 * ADDR = zext24(abs20) | remap
3516 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3517 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3518 * by the core to 16M-64k to 16M. */
3520 uint8 a
= ((GPR (OP
[0])) & 0xff);
3521 uint32 addr
= OP
[1];
3522 trace_input ("storb", OP_REG
, OP_ABS20_OUTPUT
, OP_VOID
);
3524 trace_output_32 (addr
);
3535 uint8 a
= ((GPR (OP
[0])) & 0xff);
3536 uint32 addr
= OP
[1];
3537 trace_input ("storb", OP_REG
, OP_ABS24_OUTPUT
, OP_VOID
);
3539 trace_output_32 (addr
);
3546 /* storb REG, [Rindex]ABS20
3547 * ADDR = Rindex + zext24(disp20)
3551 uint8 a
= ((GPR (OP
[0])) & 0xff);
3552 trace_input ("storb", OP_REG
, OP_R_INDEX8_ABS20
, OP_VOID
);
3555 addr
= (GPR32 (12)) + OP
[2];
3557 addr
= (GPR32 (13)) + OP
[2];
3560 trace_output_32 (addr
);
3567 /* storb REG, DIPS4(REGP)
3568 * ADDR = RPBASE + zext24(DISP4)
3571 uint16 a
= ((GPR (OP
[0])) & 0xff);
3572 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3573 trace_input ("storb", OP_REG
, OP_RP_BASE_DISPE4
, OP_VOID
);
3575 trace_output_32 (addr
);
3582 /* storb [Rindex]disp0(RPbasex) REG
3583 * ADDR = Rpbasex + Rindex
3587 uint8 a
= ((GPR (OP
[0])) & 0xff);
3588 trace_input ("storb", OP_REG
, OP_RP_INDEX_DISP0
, OP_VOID
);
3591 addr
= (GPR32 (12)) + (GPR32 (OP
[3])) + OP
[2];
3593 addr
= (GPR32 (13)) + (GPR32 (OP
[3])) + OP
[2];
3596 trace_output_32 (addr
);
3603 /* storb REG, [Rindex]disp14(RPbasex)
3604 * ADDR = Rpbasex + Rindex + zext24(disp14)
3607 uint8 a
= ((GPR (OP
[0])) & 0xff);
3608 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3609 trace_input ("storb", OP_REG
, OP_RP_INDEX_DISP14
, OP_VOID
);
3611 trace_output_32 (addr
);
3618 /* storb REG, DISPE20(REG)
3619 * zext24(Rbase) + zext24(dispe20)
3622 uint8 a
= ((GPR (OP
[0])) & 0xff);
3623 uint32 addr
= OP
[1] + (GPR (OP
[2]));
3624 trace_input ("storb", OP_REG
, OP_R_BASE_DISPE20
, OP_VOID
);
3626 trace_output_32 (addr
);
3633 /* storb REG, DISP20(REG)
3634 * ADDR = zext24(Rbase) + zext24(disp20)
3637 uint8 a
= (GPR (OP
[0]) & 0xff);
3638 uint32 addr
= OP
[1] + (GPR (OP
[2]));
3639 trace_input ("storb", OP_REG
, OP_R_BASE_DISPS20
, OP_VOID
);
3641 trace_output_32 (addr
);
3648 /* storb REG, disp16(REGP)
3649 * ADDR = RPbase + zext24(disp16)
3652 uint8 a
= ((GPR (OP
[0])) & 0xff);
3653 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3654 trace_input ("storb", OP_REG
, OP_RP_BASE_DISP16
, OP_VOID
);
3656 trace_output_32 (addr
);
3663 /* storb REG, disp20(REGP)
3664 * ADDR = RPbase + zext24(disp20)
3667 uint8 a
= ((GPR (OP
[0])) & 0xff);
3668 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3669 trace_input ("storb", OP_REG
, OP_RP_BASE_DISPS20
, OP_VOID
);
3671 trace_output_32 (addr
);
3678 /* storb REG, -disp20(REGP)
3679 * ADDR = RPbase + zext24(-disp20)
3682 uint8 a
= (GPR (OP
[0]) & 0xff);
3683 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3684 trace_input ("storb", OP_REG
, OP_RP_BASE_DISPE20
, OP_VOID
);
3686 trace_output_32 (addr
);
3693 /* storb REG, [Rindex]disp20(RPbase)
3694 * ADDR = RPbasex + Rindex + zext24(disp20)
3697 uint8 a
= (GPR (OP
[0])) & 0xff;
3698 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3699 trace_input ("storb", OP_REG
, OP_RP_INDEX_DISPS20
, OP_VOID
);
3701 trace_output_32 (addr
);
3704 /* STR_IMM instructions. */
3709 uint8 a
= (OP
[0]) & 0xff;
3710 uint32 addr
= OP
[1];
3711 trace_input ("storb", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
3713 trace_output_32 (addr
);
3720 uint8 a
= (OP
[0]) & 0xff;
3721 uint32 addr
= OP
[1];
3722 trace_input ("storb", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
3724 trace_output_32 (addr
);
3732 uint8 a
= (OP
[0]) & 0xff;
3733 trace_input ("storb", OP_CONSTANT4
, OP_R_INDEX8_ABS20
, OP_VOID
);
3736 addr
= (GPR32 (12)) + OP
[2];
3738 addr
= (GPR32 (13)) + OP
[2];
3741 trace_output_32 (addr
);
3748 uint8 a
= (OP
[0]) & 0xff;
3749 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3750 trace_input ("storb", OP_CONSTANT4
, OP_RP_BASE_DISP14
, OP_VOID
);
3752 trace_output_32 (addr
);
3759 uint8 a
= (OP
[0]) & 0xff;
3760 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3761 trace_input ("storb", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
3763 trace_output_32 (addr
);
3770 uint8 a
= (OP
[0]) & 0xff;
3771 uint32 addr
= (GPR (OP
[2])) + OP
[1];
3772 trace_input ("storb", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
3774 trace_output_32 (addr
);
3781 uint8 a
= (OP
[0]) & 0xff;
3782 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3783 trace_input ("storb", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
3785 trace_output_32 (addr
);
3792 uint8 a
= (OP
[0]) & 0xff;
3793 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3794 trace_input ("storb", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
3796 trace_output_32 (addr
);
3803 uint8 a
= (OP
[0]) & 0xff;
3804 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3805 trace_input ("storb", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
3807 trace_output_32 (addr
);
3809 /* endif for STR_IMM. */
3815 uint16 a
= GPR (OP
[0]);
3816 uint32 addr
= OP
[1];
3817 trace_input ("storw", OP_REG
, OP_ABS20_OUTPUT
, OP_VOID
);
3819 trace_output_32 (addr
);
3826 uint16 a
= GPR (OP
[0]);
3827 uint32 addr
= OP
[1];
3828 trace_input ("storw", OP_REG
, OP_ABS24_OUTPUT
, OP_VOID
);
3830 trace_output_32 (addr
);
3838 uint16 a
= GPR (OP
[0]);
3839 trace_input ("storw", OP_REG
, OP_R_INDEX8_ABS20
, OP_VOID
);
3842 addr
= (GPR32 (12)) + OP
[2];
3844 addr
= (GPR32 (13)) + OP
[2];
3847 trace_output_32 (addr
);
3855 uint16 a
= (GPR (OP
[0]));
3856 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3857 trace_input ("storw", OP_REGP
, OP_RP_BASE_DISPE4
, OP_VOID
);
3859 trace_output_32 (addr
);
3866 uint16 a
= GPR (OP
[0]);
3867 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3868 trace_input ("storw", OP_REG
, OP_RP_INDEX_DISP0
, OP_VOID
);
3870 trace_output_32 (addr
);
3877 uint16 a
= GPR (OP
[0]);
3878 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3879 trace_input ("storw", OP_REG
, OP_RP_INDEX_DISP14
, OP_VOID
);
3881 trace_output_32 (addr
);
3888 uint16 a
= (GPR (OP
[0]));
3889 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3890 trace_input ("storw", OP_REGP
, OP_RP_BASE_DISPE20
, OP_VOID
);
3892 trace_output_32 (addr
);
3899 uint16 a
= (GPR (OP
[0]));
3900 uint32 addr
= (GPR (OP
[2])) + OP
[1];
3901 trace_input ("storw", OP_REG
, OP_R_BASE_DISPS20
, OP_VOID
);
3903 trace_output_32 (addr
);
3910 uint16 a
= (GPR (OP
[0]));
3911 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3912 trace_input ("storw", OP_REG
, OP_RP_BASE_DISP16
, OP_VOID
);
3914 trace_output_32 (addr
);
3921 uint16 a
= (GPR (OP
[0]));
3922 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3923 trace_input ("storw", OP_REG
, OP_RP_BASE_DISPS20
, OP_VOID
);
3925 trace_output_32 (addr
);
3932 uint16 a
= (GPR (OP
[0]));
3933 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3934 trace_input ("storw", OP_REG
, OP_RP_BASE_DISPE20
, OP_VOID
);
3936 trace_output_32 (addr
);
3943 uint16 a
= (GPR (OP
[0]));
3944 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3945 trace_input ("storw", OP_REG
, OP_RP_INDEX_DISPS20
, OP_VOID
);
3947 trace_output_32 (addr
);
3950 /* STORE-w IMM instruction *****/
3956 uint32 addr
= OP
[1];
3957 trace_input ("storw", OP_CONSTANT4
, OP_ABS20_OUTPUT
, OP_VOID
);
3959 trace_output_32 (addr
);
3967 uint32 addr
= OP
[1];
3968 trace_input ("storw", OP_CONSTANT4
, OP_ABS24_OUTPUT
, OP_VOID
);
3970 trace_output_32 (addr
);
3979 trace_input ("storw", OP_CONSTANT4
, OP_R_INDEX8_ABS20
, OP_VOID
);
3982 addr
= (GPR32 (12)) + OP
[2];
3984 addr
= (GPR32 (13)) + OP
[2];
3987 trace_output_32 (addr
);
3995 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
3996 trace_input ("storw", OP_CONSTANT4
, OP_RP_BASE_DISP14
, OP_VOID
);
3998 trace_output_32 (addr
);
4006 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4007 trace_input ("storw", OP_CONSTANT4
, OP_RP_INDEX_DISP0
, OP_VOID
);
4009 trace_output_32 (addr
);
4017 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4018 trace_input ("storw", OP_CONSTANT4
, OP_R_BASE_DISPS20
, OP_VOID
);
4020 trace_output_32 (addr
);
4028 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4029 trace_input ("storw", OP_CONSTANT4
, OP_RP_BASE_DISP16
, OP_VOID
);
4031 trace_output_32 (addr
);
4040 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4041 trace_input ("storw", OP_CONSTANT4
, OP_RP_BASE_DISPS20
, OP_VOID
);
4043 trace_output_32 (addr
);
4051 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4052 trace_input ("storw", OP_CONSTANT4
, OP_RP_INDEX_DISPS20
, OP_VOID
);
4054 trace_output_32 (addr
);
4062 uint32 a
= GPR32 (OP
[0]);
4063 uint32 addr
= OP
[1];
4064 trace_input ("stord", OP_REGP
, OP_ABS20_OUTPUT
, OP_VOID
);
4066 trace_output_32 (addr
);
4073 uint32 a
= GPR32 (OP
[0]);
4074 uint32 addr
= OP
[1];
4075 trace_input ("stord", OP_REGP
, OP_ABS24_OUTPUT
, OP_VOID
);
4077 trace_output_32 (addr
);
4084 uint32 addr
, a
= GPR32 (OP
[0]);
4085 trace_input ("stord", OP_REGP
, OP_R_INDEX8_ABS20
, OP_VOID
);
4088 addr
= (GPR32 (12)) + OP
[2];
4090 addr
= (GPR32 (13)) + OP
[2];
4093 trace_output_32 (addr
);
4100 uint32 a
= GPR32 (OP
[0]);
4101 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4102 trace_input ("stord", OP_REGP
, OP_RP_BASE_DISPE4
, OP_VOID
);
4104 trace_output_32 (addr
);
4111 uint32 a
= GPR32 (OP
[0]);
4112 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4113 trace_input ("stord", OP_REGP
, OP_RP_INDEX_DISP0
, OP_VOID
);
4115 trace_output_32 (addr
);
4122 uint32 a
= GPR32 (OP
[0]);
4123 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4124 trace_input ("stord", OP_REGP
, OP_RP_INDEX_DISP14
, OP_VOID
);
4126 trace_output_32 (addr
);
4133 uint32 a
= GPR32 (OP
[0]);
4134 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4135 trace_input ("stord", OP_REGP
, OP_R_BASE_DISPE20
, OP_VOID
);
4137 trace_output_32 (addr
);
4144 uint32 a
= GPR32 (OP
[0]);
4145 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4146 trace_input ("stord", OP_REGP
, OP_R_BASE_DISPS20
, OP_VOID
);
4148 trace_output_32 (addr
);
4155 uint32 a
= GPR32 (OP
[0]);
4156 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4157 trace_input ("stord", OP_REGP
, OP_RP_BASE_DISP16
, OP_VOID
);
4159 trace_output_32 (addr
);
4166 uint32 a
= GPR32 (OP
[0]);
4167 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4168 trace_input ("stord", OP_REGP
, OP_RP_BASE_DISPS20
, OP_VOID
);
4170 trace_output_32 (addr
);
4177 uint32 a
= GPR32 (OP
[0]);
4178 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4179 trace_input ("stord", OP_REGP
, OP_RP_BASE_DISPE20
, OP_VOID
);
4181 trace_output_32 (addr
);
4188 uint32 a
= GPR32 (OP
[0]);
4189 uint32 addr
= (GPR32 (OP
[2])) + OP
[1];
4190 trace_input ("stord", OP_REGP
, OP_RP_INDEX_DISPS20
, OP_VOID
);
4192 trace_output_32 (addr
);
4201 trace_input ("macuw", OP_REG
, OP_REG
, OP_REGP
);
4205 /*REVISIT FOR SATURATION and Q FORMAT. */
4206 SET_GPR32 (OP
[2], tmp
);
4207 trace_output_32 (tmp
);
4216 trace_input ("macuw", OP_REG
, OP_REG
, OP_REGP
);
4220 /*REVISIT FOR SATURATION. */
4221 SET_GPR32 (OP
[2], tmp
);
4222 trace_output_32 (tmp
);
4231 trace_input ("macsw", OP_REG
, OP_REG
, OP_REGP
);
4235 /*REVISIT FOR SATURATION. */
4236 SET_GPR32 (OP
[2], tmp
);
4237 trace_output_32 (tmp
);
4246 int8 a
= (OP
[0]) & 0xff;
4247 int8 b
= (GPR (OP
[1])) & 0xff;
4248 trace_input ("mulb", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
4249 tmp
= (a
* b
) & 0xff;
4250 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
4251 trace_output_16 (tmp
);
4259 int8 a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
4260 trace_input ("mulb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4261 tmp
= (a
* b
) & 0xff;
4262 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
4263 trace_output_16 (tmp
);
4272 int8 a
= (GPR (OP
[0])) & 0xff, b
= (GPR (OP
[1])) & 0xff;
4273 trace_input ("mulb", OP_REG
, OP_REG
, OP_VOID
);
4274 tmp
= (a
* b
) & 0xff;
4275 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
4276 trace_output_16 (tmp
);
4286 int16 b
= (GPR (OP
[1]));
4287 trace_input ("mulw", OP_CONSTANT4_1
, OP_REG
, OP_VOID
);
4288 tmp
= (a
* b
) & 0xffff;
4289 SET_GPR (OP
[1], tmp
);
4290 trace_output_32 (tmp
);
4298 int16 a
= OP
[0], b
= (GPR (OP
[1]));
4299 trace_input ("mulw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4300 tmp
= (a
* b
) & 0xffff;
4301 SET_GPR (OP
[1], tmp
);
4302 trace_output_32 (tmp
);
4311 int16 a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
4312 trace_input ("mulw", OP_REG
, OP_REG
, OP_VOID
);
4313 tmp
= (a
* b
) & 0xffff;
4314 SET_GPR (OP
[1], tmp
);
4315 trace_output_32 (tmp
);
4324 int8 a
= (GPR (OP
[0])) & 0xff, b
= (GPR (OP
[1])) & 0xff;
4325 trace_input ("mulsb", OP_REG
, OP_REG
, OP_VOID
);
4327 SET_GPR (OP
[1], tmp
);
4328 trace_output_32 (tmp
);
4336 int16 a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
4337 trace_input ("mulsw", OP_REG
, OP_REGP
, OP_VOID
);
4339 SET_GPR32 (OP
[1], tmp
);
4340 trace_output_32 (tmp
);
4348 uint16 a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
4349 trace_input ("muluw", OP_REG
, OP_REGP
, OP_VOID
);
4351 SET_GPR32 (OP
[1], tmp
);
4352 trace_output_32 (tmp
);
4360 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
4363 State
.exception
= SIGTRAP
;
4364 ins_type_counters
[ (int)State
.ins_type
]--; /* don't count nops as normal instructions */
4365 switch (State
.ins_type
)
4368 ins_type_counters
[ (int)INS_UNKNOWN
]++;
4374 trace_output_void ();
4382 uint8 tmp
, a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
4383 trace_input ("orb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4385 SET_GPR (OP
[1], ((GPR (OP
[1]) | tmp
)));
4386 trace_output_16 (tmp
);
4393 uint8 tmp
, a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
4394 trace_input ("orb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
4396 SET_GPR (OP
[1], ((GPR (OP
[1]) | tmp
)));
4397 trace_output_16 (tmp
);
4404 uint8 tmp
, a
= (GPR (OP
[0])) & 0xff, b
= (GPR (OP
[1])) & 0xff;
4405 trace_input ("orb", OP_REG
, OP_REG
, OP_VOID
);
4407 SET_GPR (OP
[1], ((GPR (OP
[1]) | tmp
)));
4408 trace_output_16 (tmp
);
4415 uint16 tmp
, a
= (OP
[0]), b
= (GPR (OP
[1]));
4416 trace_input ("orw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4418 SET_GPR (OP
[1], tmp
);
4419 trace_output_16 (tmp
);
4427 uint16 tmp
, a
= (OP
[0]), b
= (GPR (OP
[1]));
4428 trace_input ("orw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
4430 SET_GPR (OP
[1], tmp
);
4431 trace_output_16 (tmp
);
4438 uint16 tmp
, a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
4439 trace_input ("orw", OP_REG
, OP_REG
, OP_VOID
);
4441 SET_GPR (OP
[1], tmp
);
4442 trace_output_16 (tmp
);
4451 uint16 tmp
, b
= (GPR (OP
[1])) & 0xFF;
4452 trace_input ("lshb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4453 /* A positive count specifies a shift to the left;
4454 * A negative count specifies a shift to the right. */
4460 sign_flag
= 0; /* Reset sign_flag. */
4462 SET_GPR (OP
[1], ((tmp
& 0xFF) | ((GPR (OP
[1])) & 0xFF00)));
4463 trace_output_16 (tmp
);
4470 uint16 a
= (GPR (OP
[0])) & 0xff;
4471 uint16 tmp
, b
= (GPR (OP
[1])) & 0xFF;
4472 trace_input ("lshb", OP_REG
, OP_REG
, OP_VOID
);
4473 if (a
& ((long)1 << 3))
4478 a
= (unsigned int) (a
& 0x7);
4480 /* A positive count specifies a shift to the left;
4481 * A negative count specifies a shift to the right. */
4487 sign_flag
= 0; /* Reset sign_flag. */
4488 SET_GPR (OP
[1], ((tmp
& 0xFF) | ((GPR (OP
[1])) & 0xFF00)));
4489 trace_output_16 (tmp
);
4496 uint16 tmp
, b
= GPR (OP
[1]);
4497 int16 a
= GPR (OP
[0]);
4498 trace_input ("lshw", OP_REG
, OP_REG
, OP_VOID
);
4499 if (a
& ((long)1 << 4))
4504 a
= (unsigned int) (a
& 0xf);
4506 /* A positive count specifies a shift to the left;
4507 * A negative count specifies a shift to the right. */
4513 sign_flag
= 0; /* Reset sign_flag. */
4514 SET_GPR (OP
[1], (tmp
& 0xffff));
4515 trace_output_16 (tmp
);
4522 uint16 tmp
, b
= GPR (OP
[1]);
4524 trace_input ("lshw", OP_CONSTANT5
, OP_REG
, OP_VOID
);
4525 /* A positive count specifies a shift to the left;
4526 * A negative count specifies a shift to the right. */
4532 sign_flag
= 0; /* Reset sign_flag. */
4533 SET_GPR (OP
[1], (tmp
& 0xffff));
4534 trace_output_16 (tmp
);
4541 uint32 tmp
, b
= GPR32 (OP
[1]);
4543 trace_input ("lshd", OP_CONSTANT6
, OP_REGP
, OP_VOID
);
4544 /* A positive count specifies a shift to the left;
4545 * A negative count specifies a shift to the right. */
4551 sign_flag
= 0; /* Reset sign flag. */
4553 SET_GPR32 (OP
[1], tmp
);
4554 trace_output_32 (tmp
);
4561 uint32 tmp
, b
= GPR32 (OP
[1]);
4562 uint16 a
= GPR (OP
[0]);
4563 trace_input ("lshd", OP_REG
, OP_REGP
, OP_VOID
);
4564 if (a
& ((long)1 << 5))
4569 a
= (unsigned int) (a
& 0x1f);
4570 /* A positive count specifies a shift to the left;
4571 * A negative count specifies a shift to the right. */
4577 sign_flag
= 0; /* Reset sign flag. */
4579 SET_GPR32 (OP
[1], tmp
);
4580 trace_output_32 (tmp
);
4588 int8 tmp
, b
= (GPR (OP
[1])) & 0xFF;
4589 trace_input ("ashub", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4590 /* A positive count specifies a shift to the left;
4591 * A negative count specifies a shift to the right. */
4597 sign_flag
= 0; /* Reset sign flag. */
4599 SET_GPR (OP
[1], ((tmp
& 0xFF) | ((GPR (OP
[1])) & 0xff00)));
4600 trace_output_16 (tmp
);
4608 int8 tmp
, b
= (GPR (OP
[1])) & 0xFF;
4609 trace_input ("ashub", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4610 /* A positive count specifies a shift to the left;
4611 * A negative count specifies a shift to the right. */
4617 sign_flag
= 0; /* Reset sign flag. */
4619 SET_GPR (OP
[1], ((tmp
& 0xFF) | ((GPR (OP
[1])) & 0xFF00)));
4620 trace_output_16 (tmp
);
4628 int16 a
= (GPR (OP
[0]));
4629 int8 tmp
, b
= (GPR (OP
[1])) & 0xFF;
4630 trace_input ("ashub", OP_REG
, OP_REG
, OP_VOID
);
4632 if (a
& ((long)1 << 3))
4637 a
= (unsigned int) (a
& 0x7);
4639 /* A positive count specifies a shift to the left;
4640 * A negative count specifies a shift to the right. */
4646 sign_flag
= 0; /* Reset sign flag. */
4648 SET_GPR (OP
[1], ((tmp
& 0xFF) | ((GPR (OP
[1])) & 0xFF00)));
4649 trace_output_16 (tmp
);
4657 int16 tmp
, b
= GPR (OP
[1]);
4659 trace_input ("ashuw", OP_CONSTANT5
, OP_REG
, OP_VOID
);
4660 /* A positive count specifies a shift to the left;
4661 * A negative count specifies a shift to the right. */
4667 sign_flag
= 0; /* Reset sign flag. */
4669 SET_GPR (OP
[1], (tmp
& 0xffff));
4670 trace_output_16 (tmp
);
4677 int16 tmp
, b
= GPR (OP
[1]);
4679 trace_input ("ashuw", OP_CONSTANT5
, OP_REG
, OP_VOID
);
4680 /* A positive count specifies a shift to the left;
4681 * A negative count specifies a shift to the right. */
4687 sign_flag
= 0; /* Reset sign flag. */
4688 SET_GPR (OP
[1], (tmp
& 0xffff));
4689 trace_output_16 (tmp
);
4697 int16 a
= GPR (OP
[0]), b
= GPR (OP
[1]);
4698 trace_input ("ashuw", OP_REG
, OP_REG
, OP_VOID
);
4700 if (a
& ((long)1 << 4))
4705 a
= (unsigned int) (a
& 0xf);
4706 /* A positive count specifies a shift to the left;
4707 * A negative count specifies a shift to the right. */
4714 sign_flag
= 0; /* Reset sign flag. */
4715 SET_GPR (OP
[1], (tmp
& 0xffff));
4716 trace_output_16 (tmp
);
4723 int32 tmp
,b
= GPR32 (OP
[1]);
4725 trace_input ("ashud", OP_CONSTANT6
, OP_REGP
, OP_VOID
);
4726 /* A positive count specifies a shift to the left;
4727 * A negative count specifies a shift to the right. */
4733 sign_flag
= 0; /* Reset sign flag. */
4734 SET_GPR32 (OP
[1], tmp
);
4735 trace_output_32 (tmp
);
4743 int32 a
= OP
[0], b
= GPR32 (OP
[1]);
4744 trace_input ("ashud", OP_CONSTANT6
, OP_REGP
, OP_VOID
);
4745 /* A positive count specifies a shift to the left;
4746 * A negative count specifies a shift to the right. */
4752 sign_flag
= 0; /* Reset sign flag. */
4753 SET_GPR32 (OP
[1], tmp
);
4754 trace_output_32 (tmp
);
4762 int32 a
= GPR32 (OP
[0]), b
= GPR32 (OP
[1]);
4763 trace_input ("ashud", OP_REGP
, OP_REGP
, OP_VOID
);
4765 if (a
& ((long)1 << 5))
4770 a
= (unsigned int) (a
& 0x1f);
4771 /* A positive count specifies a shift to the left;
4772 * A negative count specifies a shift to the right. */
4778 sign_flag
= 0; /* Reset sign flag. */
4779 SET_GPR32 (OP
[1], tmp
);
4780 trace_output_32 (tmp
);
4788 uint32 addr
= GPR (1);
4789 uint16 count
= OP
[0], reg
= 2;
4790 trace_input ("storm", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
4793 State
.exception
= SIG_CR16_BUS
;
4794 State
.pc_changed
= 1; /* Don't increment the PC. */
4795 trace_output_void ();
4801 SW (addr
, (GPR (reg
)));
4805 if (reg
== 6) reg
= 8;
4810 trace_output_void ();
4818 uint32 addr
= GPR32 (6);
4819 uint16 count
= OP
[0], reg
= 2;
4820 trace_input ("stormp", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
4823 State
.exception
= SIG_CR16_BUS
;
4824 State
.pc_changed
= 1; /* Don't increment the PC. */
4825 trace_output_void ();
4831 SW (addr
, (GPR (reg
)));
4835 if (reg
== 6) reg
= 8;
4838 SET_GPR32 (6, addr
);
4839 trace_output_void ();
4847 uint8 b
= (GPR (OP
[1])) & 0xff;
4848 uint16 tmp
= (~a
+ 1 + b
) & 0xff;
4849 trace_input ("subb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4850 /* see ../common/sim-alu.h for a more extensive discussion on how to
4851 compute the carry/overflow bits. */
4852 SET_PSR_C (tmp
> 0xff);
4853 SET_PSR_F (((a
& 0x80) != (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
4854 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
4855 trace_output_16 (tmp
);
4862 uint8 a
= OP
[0] & 0xFF;
4863 uint8 b
= (GPR (OP
[1])) & 0xFF;
4864 uint16 tmp
= (~a
+ 1 + b
) & 0xFF;
4865 trace_input ("subb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
4866 /* see ../common/sim-alu.h for a more extensive discussion on how to
4867 compute the carry/overflow bits. */
4868 SET_PSR_C (tmp
> 0xff);
4869 SET_PSR_F (((a
& 0x80) != (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
4870 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
4871 trace_output_16 (tmp
);
4878 uint8 a
= (GPR (OP
[0])) & 0xFF;
4879 uint8 b
= (GPR (OP
[1])) & 0xFF;
4880 uint16 tmp
= (~a
+ 1 + b
) & 0xff;
4881 trace_input ("subb", OP_REG
, OP_REG
, OP_VOID
);
4882 /* see ../common/sim-alu.h for a more extensive discussion on how to
4883 compute the carry/overflow bits. */
4884 SET_PSR_C (tmp
> 0xff);
4885 SET_PSR_F (((a
& 0x80) != (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
4886 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
4887 trace_output_16 (tmp
);
4895 uint16 b
= GPR (OP
[1]);
4896 uint16 tmp
= (~a
+ 1 + b
);
4897 trace_input ("subw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4898 /* see ../common/sim-alu.h for a more extensive discussion on how to
4899 compute the carry/overflow bits. */
4900 SET_PSR_C (tmp
> 0xffff);
4901 SET_PSR_F (((a
& 0x8000) != (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
4902 SET_GPR (OP
[1], tmp
);
4903 trace_output_16 (tmp
);
4911 uint16 b
= GPR (OP
[1]);
4912 uint32 tmp
= (~a
+ 1 + b
);
4913 trace_input ("subw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
4914 /* see ../common/sim-alu.h for a more extensive discussion on how to
4915 compute the carry/overflow bits. */
4916 SET_PSR_C (tmp
> 0xffff);
4917 SET_PSR_F (((a
& 0x8000) != (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
4918 SET_GPR (OP
[1], tmp
& 0xffff);
4919 trace_output_16 (tmp
);
4926 uint16 a
= GPR (OP
[0]);
4927 uint16 b
= GPR (OP
[1]);
4928 uint32 tmp
= (~a
+ 1 + b
);
4929 trace_input ("subw", OP_REG
, OP_REG
, OP_VOID
);
4930 /* see ../common/sim-alu.h for a more extensive discussion on how to
4931 compute the carry/overflow bits. */
4932 SET_PSR_C (tmp
> 0xffff);
4933 SET_PSR_F (((a
& 0x8000) != (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
4934 SET_GPR (OP
[1], tmp
& 0xffff);
4935 trace_output_16 (tmp
);
4943 uint8 b
= (GPR (OP
[1])) & 0xff;
4944 //uint16 tmp1 = a + 1;
4945 uint16 tmp1
= a
+ (PSR_C
);
4946 uint16 tmp
= (~tmp1
+ 1 + b
);
4947 trace_input ("subcb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4948 /* see ../common/sim-alu.h for a more extensive discussion on how to
4949 compute the carry/overflow bits. */
4950 SET_PSR_C (tmp
> 0xff);
4951 SET_PSR_F (((a
& 0x80) != (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
4952 SET_GPR (OP
[1], tmp
);
4953 trace_output_16 (tmp
);
4961 uint16 b
= (GPR (OP
[1])) & 0xff;
4962 //uint16 tmp1 = a + 1;
4963 uint16 tmp1
= a
+ (PSR_C
);
4964 uint16 tmp
= (~tmp1
+ 1 + b
);
4965 trace_input ("subcb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
4966 /* see ../common/sim-alu.h for a more extensive discussion on how to
4967 compute the carry/overflow bits. */
4968 SET_PSR_C (tmp
> 0xff);
4969 SET_PSR_F (((a
& 0x80) != (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
4970 SET_GPR (OP
[1], tmp
);
4971 trace_output_16 (tmp
);
4978 uint16 a
= (GPR (OP
[0])) & 0xff;
4979 uint16 b
= (GPR (OP
[1])) & 0xff;
4980 uint16 tmp1
= a
+ (PSR_C
);
4981 uint16 tmp
= (~tmp1
+ 1 + b
);
4982 trace_input ("subcb", OP_REG
, OP_REG
, OP_VOID
);
4983 /* see ../common/sim-alu.h for a more extensive discussion on how to
4984 compute the carry/overflow bits. */
4985 SET_PSR_C (tmp
> 0xff);
4986 SET_PSR_F (((a
& 0x80) != (b
& 0x80)) && ((b
& 0x80) != (tmp
& 0x80)));
4987 SET_GPR (OP
[1], tmp
);
4988 trace_output_16 (tmp
);
4995 uint16 a
= OP
[0], b
= (GPR (OP
[1]));
4996 uint16 tmp1
= a
+ (PSR_C
);
4997 uint16 tmp
= (~tmp1
+ 1 + b
);
4998 trace_input ("subcw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
4999 /* see ../common/sim-alu.h for a more extensive discussion on how to
5000 compute the carry/overflow bits. */
5001 SET_PSR_C (tmp
> 0xffff);
5002 SET_PSR_F (((a
& 0x8000) != (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
5003 SET_GPR (OP
[1], tmp
);
5004 trace_output_16 (tmp
);
5012 uint16 b
= GPR (OP
[1]);
5013 uint16 tmp1
= a
+ (PSR_C
);
5014 uint16 tmp
= (~tmp1
+ 1 + b
);
5015 trace_input ("subcw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
5016 /* see ../common/sim-alu.h for a more extensive discussion on how to
5017 compute the carry/overflow bits. */
5018 SET_PSR_C (tmp
> 0xffff);
5019 SET_PSR_F (((a
& 0x8000) != (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
5020 SET_GPR (OP
[1], tmp
);
5021 trace_output_16 (tmp
);
5028 uint16 a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
5029 uint16 tmp1
= a
+ (PSR_C
);
5030 uint16 tmp
= (~tmp1
+ 1 + b
);
5031 trace_input ("subcw", OP_REG
, OP_REG
, OP_VOID
);
5032 /* see ../common/sim-alu.h for a more extensive discussion on how to
5033 compute the carry/overflow bits. */
5034 SET_PSR_C (tmp
> 0xffff);
5035 SET_PSR_F (((a
& 0x8000) != (b
& 0x8000)) && ((b
& 0x8000) != (tmp
& 0x8000)));
5036 SET_GPR (OP
[1], tmp
);
5037 trace_output_16 (tmp
);
5045 uint32 b
= GPR32 (OP
[1]);
5046 uint32 tmp
= (~a
+ 1 + b
);
5047 trace_input ("subd", OP_CONSTANT32
, OP_REGP
, OP_VOID
);
5048 /* see ../common/sim-alu.h for a more extensive discussion on how to
5049 compute the carry/overflow bits. */
5050 SET_PSR_C (tmp
> 0xffffffff);
5051 SET_PSR_F (((a
& 0x80000000) != (b
& 0x80000000)) &&
5052 ((b
& 0x80000000) != (tmp
& 0x80000000)));
5053 SET_GPR32 (OP
[1], tmp
);
5054 trace_output_32 (tmp
);
5061 uint32 a
= GPR32 (OP
[0]);
5062 uint32 b
= GPR32 (OP
[1]);
5063 uint32 tmp
= (~a
+ 1 + b
);
5064 trace_input ("subd", OP_REGP
, OP_REGP
, OP_VOID
);
5065 /* see ../common/sim-alu.h for a more extensive discussion on how to
5066 compute the carry/overflow bits. */
5067 SET_PSR_C (tmp
> 0xffffffff);
5068 SET_PSR_F (((a
& 0x80000000) != (b
& 0x80000000)) &&
5069 ((b
& 0x80000000) != (tmp
& 0x80000000)));
5070 SET_GPR32 (OP
[1], tmp
);
5071 trace_output_32 (tmp
);
5080 trace_input ("excp", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
5084 #if (DEBUG & DEBUG_TRAP) == 0
5087 uint16 vec
= OP
[0] + TRAP_VECTOR_START
;
5090 SET_PSR (PSR
& PSR_SM_BIT
);
5095 #else /* if debugging use trap to print registers */
5098 static int first_time
= 1;
5103 (*cr16_callback
->printf_filtered
) (cr16_callback
, "Trap # PC ");
5104 for (i
= 0; i
< 16; i
++)
5105 (*cr16_callback
->printf_filtered
) (cr16_callback
, " %sr%d", (i
> 9) ? "" : " ", i
);
5106 (*cr16_callback
->printf_filtered
) (cr16_callback
, " a0 a1 f0 f1 c\n");
5109 (*cr16_callback
->printf_filtered
) (cr16_callback
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
5111 for (i
= 0; i
< 16; i
++)
5112 (*cr16_callback
->printf_filtered
) (cr16_callback
, " %.4x", (int) GPR (i
));
5114 for (i
= 0; i
< 2; i
++)
5115 (*cr16_callback
->printf_filtered
) (cr16_callback
, " %.2x%.8lx",
5116 ((int)(ACC (i
) >> 32) & 0xff),
5117 ((unsigned long) ACC (i
)) & 0xffffffff);
5119 (*cr16_callback
->printf_filtered
) (cr16_callback
, " %d %d %d\n",
5120 PSR_F
!= 0, PSR_F
!= 0, PSR_C
!= 0);
5121 (*cr16_callback
->flush_stdout
) (cr16_callback
);
5125 case 8: /* new system call trap */
5126 /* Trap 8 is used for simulating low-level I/O */
5128 unsigned32 result
= 0;
5131 /* Registers passed to trap 0. */
5133 #define FUNC GPR (0) /* function number. */
5134 #define PARM1 GPR (2) /* optional parm 1. */
5135 #define PARM2 GPR (3) /* optional parm 2. */
5136 #define PARM3 GPR (4) /* optional parm 3. */
5137 #define PARM4 GPR (5) /* optional parm 4. */
5139 /* Registers set by trap 0 */
5141 #define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0)
5142 #define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0)
5143 #define RETERR(X) SET_GPR (4, (X)) /* return error code. */
5145 /* Turn a pointer in a register into a pointer into real memory. */
5147 #define MEMPTR(x) ((char *)(dmem_addr(x)))
5151 #if !defined(__GO32__) && !defined(_WIN32)
5152 #ifdef TARGET_SYS_fork
5153 case TARGET_SYS_fork
:
5154 trace_input ("<fork>", OP_VOID
, OP_VOID
, OP_VOID
);
5156 trace_output_16 (result
);
5161 case TARGET_SYS_getpid
:
5162 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
5164 trace_output_16 (result
);
5167 case TARGET_SYS_kill
:
5168 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
5169 if (PARM1
== getpid ())
5171 trace_output_void ();
5172 State
.exception
= PARM2
;
5180 case 1: os_sig
= SIGHUP
; break;
5183 case 2: os_sig
= SIGINT
; break;
5186 case 3: os_sig
= SIGQUIT
; break;
5189 case 4: os_sig
= SIGILL
; break;
5192 case 5: os_sig
= SIGTRAP
; break;
5195 case 6: os_sig
= SIGABRT
; break;
5196 #elif defined(SIGIOT)
5197 case 6: os_sig
= SIGIOT
; break;
5200 case 7: os_sig
= SIGEMT
; break;
5203 case 8: os_sig
= SIGFPE
; break;
5206 case 9: os_sig
= SIGKILL
; break;
5209 case 10: os_sig
= SIGBUS
; break;
5212 case 11: os_sig
= SIGSEGV
; break;
5215 case 12: os_sig
= SIGSYS
; break;
5218 case 13: os_sig
= SIGPIPE
; break;
5221 case 14: os_sig
= SIGALRM
; break;
5224 case 15: os_sig
= SIGTERM
; break;
5227 case 16: os_sig
= SIGURG
; break;
5230 case 17: os_sig
= SIGSTOP
; break;
5233 case 18: os_sig
= SIGTSTP
; break;
5236 case 19: os_sig
= SIGCONT
; break;
5239 case 20: os_sig
= SIGCHLD
; break;
5240 #elif defined(SIGCLD)
5241 case 20: os_sig
= SIGCLD
; break;
5244 case 21: os_sig
= SIGTTIN
; break;
5247 case 22: os_sig
= SIGTTOU
; break;
5250 case 23: os_sig
= SIGIO
; break;
5251 #elif defined (SIGPOLL)
5252 case 23: os_sig
= SIGPOLL
; break;
5255 case 24: os_sig
= SIGXCPU
; break;
5258 case 25: os_sig
= SIGXFSZ
; break;
5261 case 26: os_sig
= SIGVTALRM
; break;
5264 case 27: os_sig
= SIGPROF
; break;
5267 case 28: os_sig
= SIGWINCH
; break;
5270 case 29: os_sig
= SIGLOST
; break;
5273 case 30: os_sig
= SIGUSR1
; break;
5276 case 31: os_sig
= SIGUSR2
; break;
5282 trace_output_void ();
5283 (*cr16_callback
->printf_filtered
) (cr16_callback
, "Unknown signal %d\n", PARM2
);
5284 (*cr16_callback
->flush_stdout
) (cr16_callback
);
5285 State
.exception
= SIGILL
;
5289 RETVAL (kill (PARM1
, PARM2
));
5290 trace_output_16 (result
);
5295 #ifdef TARGET_SYS_execve
5296 case TARGET_SYS_execve
:
5297 trace_input ("<execve>", OP_VOID
, OP_VOID
, OP_VOID
);
5298 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
<<16|PARM3
),
5299 (char **)MEMPTR (PARM4
)));
5300 trace_output_16 (result
);
5304 #ifdef TARGET_SYS_execv
5305 case TARGET_SYS_execv
:
5306 trace_input ("<execv>", OP_VOID
, OP_VOID
, OP_VOID
);
5307 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
));
5308 trace_output_16 (result
);
5312 #ifdef TARGET_SYS_pipe
5313 case TARGET_SYS_pipe
:
5318 trace_input ("<pipe>", OP_VOID
, OP_VOID
, OP_VOID
);
5320 RETVAL (pipe (host_fd
));
5321 SW (buf
, host_fd
[0]);
5322 buf
+= sizeof(uint16
);
5323 SW (buf
, host_fd
[1]);
5324 trace_output_16 (result
);
5329 #ifdef TARGET_SYS_wait
5330 case TARGET_SYS_wait
:
5333 trace_input ("<wait>", OP_REG
, OP_VOID
, OP_VOID
);
5334 RETVAL (wait (&status
));
5337 trace_output_16 (result
);
5342 case TARGET_SYS_getpid
:
5343 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
5345 trace_output_16 (result
);
5348 case TARGET_SYS_kill
:
5349 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
5350 trace_output_void ();
5351 State
.exception
= PARM2
;
5355 case TARGET_SYS_read
:
5356 trace_input ("<read>", OP_REG
, OP_MEMREF
, OP_REG
);
5357 RETVAL (cr16_callback
->read (cr16_callback
, PARM1
,
5358 MEMPTR (((unsigned long)PARM3
<< 16)
5359 |((unsigned long)PARM2
)), PARM4
));
5360 trace_output_16 (result
);
5363 case TARGET_SYS_write
:
5364 trace_input ("<write>", OP_REG
, OP_MEMREF
, OP_REG
);
5365 RETVAL ((int)cr16_callback
->write (cr16_callback
, PARM1
,
5366 MEMPTR (((unsigned long)PARM3
<< 16) | PARM2
), PARM4
));
5367 trace_output_16 (result
);
5370 case TARGET_SYS_lseek
:
5371 trace_input ("<lseek>", OP_REG
, OP_REGP
, OP_REG
);
5372 RETVAL32 (cr16_callback
->lseek (cr16_callback
, PARM1
,
5373 ((((long) PARM3
) << 16) | PARM2
),
5375 trace_output_32 (result
);
5378 case TARGET_SYS_close
:
5379 trace_input ("<close>", OP_REG
, OP_VOID
, OP_VOID
);
5380 RETVAL (cr16_callback
->close (cr16_callback
, PARM1
));
5381 trace_output_16 (result
);
5384 case TARGET_SYS_open
:
5385 trace_input ("<open>", OP_MEMREF
, OP_REG
, OP_VOID
);
5386 RETVAL32 (cr16_callback
->open (cr16_callback
,
5387 MEMPTR ((((unsigned long)PARM2
)<<16)|PARM1
),
5389 trace_output_32 (result
);
5392 #ifdef TARGET_SYS_rename
5393 case TARGET_SYS_rename
:
5394 trace_input ("<rename>", OP_MEMREF
, OP_MEMREF
, OP_VOID
);
5395 RETVAL (cr16_callback
->rename (cr16_callback
,
5396 MEMPTR ((((unsigned long)PARM2
)<<16) |PARM1
),
5397 MEMPTR ((((unsigned long)PARM4
)<<16) |PARM3
)));
5398 trace_output_16 (result
);
5402 case 0x408: /* REVISIT: Added a dummy getenv call. */
5403 trace_input ("<getenv>", OP_MEMREF
, OP_MEMREF
, OP_VOID
);
5405 trace_output_32 (result
);
5408 case TARGET_SYS_exit
:
5409 trace_input ("<exit>", OP_VOID
, OP_VOID
, OP_VOID
);
5410 State
.exception
= SIG_CR16_EXIT
;
5411 trace_output_void ();
5414 case TARGET_SYS_unlink
:
5415 trace_input ("<unlink>", OP_MEMREF
, OP_VOID
, OP_VOID
);
5416 RETVAL (cr16_callback
->unlink (cr16_callback
,
5417 MEMPTR (((unsigned long)PARM2
<<16)|PARM1
)));
5418 trace_output_16 (result
);
5422 #ifdef TARGET_SYS_stat
5423 case TARGET_SYS_stat
:
5424 trace_input ("<stat>", OP_VOID
, OP_VOID
, OP_VOID
);
5425 /* stat system call. */
5427 struct stat host_stat
;
5430 RETVAL (stat (MEMPTR ((((unsigned long)PARM2
) << 16)|PARM1
), &host_stat
));
5434 /* The hard-coded offsets and sizes were determined by using
5435 * the CR16 compiler on a test program that used struct stat.
5437 SW (buf
, host_stat
.st_dev
);
5438 SW (buf
+2, host_stat
.st_ino
);
5439 SW (buf
+4, host_stat
.st_mode
);
5440 SW (buf
+6, host_stat
.st_nlink
);
5441 SW (buf
+8, host_stat
.st_uid
);
5442 SW (buf
+10, host_stat
.st_gid
);
5443 SW (buf
+12, host_stat
.st_rdev
);
5444 SLW (buf
+16, host_stat
.st_size
);
5445 SLW (buf
+20, host_stat
.st_atime
);
5446 SLW (buf
+28, host_stat
.st_mtime
);
5447 SLW (buf
+36, host_stat
.st_ctime
);
5449 trace_output_16 (result
);
5453 #ifdef TARGET_SYS_chown
5454 case TARGET_SYS_chown
:
5455 trace_input ("<chown>", OP_VOID
, OP_VOID
, OP_VOID
);
5456 RETVAL (chown (MEMPTR (PARM1
), PARM2
, PARM3
));
5457 trace_output_16 (result
);
5461 case TARGET_SYS_chmod
:
5462 trace_input ("<chmod>", OP_VOID
, OP_VOID
, OP_VOID
);
5463 RETVAL (chmod (MEMPTR (PARM1
), PARM2
));
5464 trace_output_16 (result
);
5467 #ifdef TARGET_SYS_utime
5468 case TARGET_SYS_utime
:
5469 trace_input ("<utime>", OP_REG
, OP_REG
, OP_REG
);
5470 /* Cast the second argument to void *, to avoid type mismatch
5471 if a prototype is present. */
5472 RETVAL (utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
)));
5473 trace_output_16 (result
);
5477 #ifdef TARGET_SYS_time
5478 case TARGET_SYS_time
:
5479 trace_input ("<time>", OP_VOID
, OP_VOID
, OP_REG
);
5480 RETVAL32 (time (NULL
));
5481 trace_output_32 (result
);
5489 case TRAP_BREAKPOINT
:
5490 State
.exception
= SIGTRAP
;
5493 trace_output_void ();
5495 case SIGTRAP
: /* supervisor call ? */
5496 State
.exception
= SIG_CR16_EXIT
;
5497 trace_output_void ();
5500 cr16_callback
->error (cr16_callback
, "Unknown syscall %d", FUNC
);
5504 if ((uint16
) result
== (uint16
) -1)
5505 RETERR (cr16_callback
->get_errno(cr16_callback
));
5518 uint16 a
= OP
[0] + 1, b
= OP
[1], c
= OP
[2], i
= 0;
5519 uint32 tmp
, sp_addr
= (GPR32 (15)) - (a
* 2) - 4, is_regp
= 0;
5520 trace_input ("push", OP_CONSTANT3
, OP_REG
, OP_REG
);
5526 SW (sp_addr
, (GPR (b
+i
)));
5532 tmp
= (GPR32 (b
+i
));
5534 tmp
= (GPR32 (b
+i
-1));
5553 /* Store RA address. */
5557 sp_addr
= (GPR32 (15)) - (a
* 2) - 4;
5558 SET_GPR32 (15, sp_addr
); /* Update SP address. */
5560 trace_output_void ();
5567 uint32 sp_addr
, tmp
, is_regp
= 0;
5568 uint16 a
= OP
[0] + 1, b
= OP
[1], c
= OP
[2], i
= 0;
5569 trace_input ("push", OP_CONSTANT3
, OP_REG
, OP_VOID
);
5572 sp_addr
= (GPR32 (15)) - (a
* 2) - 4;
5574 sp_addr
= (GPR32 (15)) - (a
* 2);
5580 SW (sp_addr
, (GPR (b
+i
)));
5586 tmp
= (GPR32 (b
+i
));
5588 tmp
= (GPR32 (b
+i
-1));
5607 /* Store RA address. */
5610 sp_addr
= (GPR32 (15)) - (a
* 2) - 4;
5613 sp_addr
= (GPR32 (15)) - (a
* 2);
5615 SET_GPR32 (15, sp_addr
); /* Update SP address. */
5617 trace_output_void ();
5625 uint32 sp_addr
= (GPR32 (15)), tmp
;
5626 trace_input ("push", OP_VOID
, OP_VOID
, OP_VOID
);
5628 SLW(sp_addr
-4,tmp
); /* Store RA address. */
5629 SET_GPR32 (15, (sp_addr
- 4)); /* Update SP address. */
5630 trace_output_void ();
5638 uint16 a
= OP
[0] + 1, b
= OP
[1], c
= OP
[2], i
= 0;
5639 uint32 tmp
, sp_addr
= (GPR32 (15)), is_regp
= 0;;
5640 trace_input ("pop", OP_CONSTANT3
, OP_REG
, OP_REG
);
5646 SET_GPR ((b
+i
), RW(sp_addr
));
5662 tmp
= (tmp
<< 16) | (GPR32 (b
+i
));
5664 tmp
= (tmp
<< 16) | (GPR32 (b
+i
-1));
5668 SET_GPR32 ((b
+i
), (((tmp
& 0xffff) << 16)
5669 | ((tmp
>> 16) & 0xffff)));
5671 SET_GPR32 ((b
+i
-1), (((tmp
& 0xffff) << 16)
5672 | ((tmp
>> 16) & 0xffff)));
5679 tmp
= RLW(sp_addr
); /* store RA also. */
5680 SET_GPR32 (14, (((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff)));
5682 SET_GPR32 (15, (sp_addr
+ 4)); /* Update SP address. */
5684 trace_output_void ();
5691 uint16 a
= OP
[0] + 1, b
= OP
[1], c
= OP
[2], i
= 0;
5692 uint32 tmp
, sp_addr
= (GPR32 (15)), is_regp
= 0;
5693 trace_input ("pop", OP_CONSTANT3
, OP_REG
, OP_VOID
);
5699 SET_GPR ((b
+i
), RW(sp_addr
));
5715 tmp
= ((tmp
<< 16) & 0xffffffff) | (GPR32 (b
+i
));
5717 tmp
= ((tmp
<< 16) & 0xffffffff) | (GPR32 (b
+i
-1));
5721 SET_GPR32 ((b
+i
), (((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff)));
5723 SET_GPR32 ((b
+i
-1), (((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff)));
5731 tmp
= RLW(sp_addr
); /* Store RA Reg. */
5732 SET_GPR32 (14, (((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff)));
5736 SET_GPR32 (15, sp_addr
); /* Update SP address. */
5738 trace_output_void ();
5745 uint32 sp_addr
= GPR32 (15);
5747 trace_input ("pop", OP_VOID
, OP_VOID
, OP_VOID
);
5750 SET_GPR32 (14, (((tmp
& 0xffff) << 16)| ((tmp
>> 16) & 0xffff)));
5751 SET_GPR32 (15, (sp_addr
+4)); /* Update SP address. */
5753 trace_output_void ();
5760 uint16 a
= OP
[0], b
= OP
[1];
5761 trace_input ("popret", OP_CONSTANT3
, OP_REG
, OP_REG
);
5763 JMP(((GPR32(14)) << 1) & 0xffffff);
5765 trace_output_void ();
5772 uint16 a
= OP
[0], b
= OP
[1];
5773 trace_input ("popret", OP_CONSTANT3
, OP_REG
, OP_VOID
);
5775 JMP(((GPR32(14)) << 1) & 0xffffff);
5777 trace_output_void ();
5785 trace_input ("popret", OP_VOID
, OP_VOID
, OP_VOID
);
5787 tmp
= (((GPR32(14)) << 1) & 0xffffff);
5788 /* If the resulting PC value is less than 0x00_0000 or greater
5789 than 0xFF_FFFF, this instruction causes an IAD trap.*/
5791 if ((tmp
< 0x0) || (tmp
> 0xFFFFFF))
5793 State
.exception
= SIG_CR16_BUS
;
5794 State
.pc_changed
= 1; /* Don't increment the PC. */
5795 trace_output_void ();
5801 trace_output_32 (tmp
);
5809 trace_input ("cinv[i]", OP_VOID
, OP_VOID
, OP_VOID
);
5811 trace_output_void ();
5818 trace_input ("cinv[i,u]", OP_VOID
, OP_VOID
, OP_VOID
);
5820 trace_output_void ();
5827 trace_input ("cinv[d]", OP_VOID
, OP_VOID
, OP_VOID
);
5829 trace_output_void ();
5836 trace_input ("cinv[i,u]", OP_VOID
, OP_VOID
, OP_VOID
);
5838 trace_output_void ();
5845 trace_input ("cinv[d,i]", OP_VOID
, OP_VOID
, OP_VOID
);
5847 trace_output_void ();
5854 trace_input ("cinv[d,i,u]", OP_VOID
, OP_VOID
, OP_VOID
);
5856 trace_output_void ();
5863 trace_input ("retx", OP_VOID
, OP_VOID
, OP_VOID
);
5865 trace_output_void ();
5872 trace_input ("di", OP_VOID
, OP_VOID
, OP_VOID
);
5874 trace_output_void ();
5881 trace_input ("ei", OP_VOID
, OP_VOID
, OP_VOID
);
5883 trace_output_void ();
5890 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
5891 State
.exception
= SIGTRAP
;
5892 trace_output_void ();
5899 trace_input ("ewait", OP_VOID
, OP_VOID
, OP_VOID
);
5901 trace_output_void ();
5908 uint8 tmp
, a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
5909 trace_input ("xorb", OP_CONSTANT4
, OP_REG
, OP_VOID
);
5911 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
5912 trace_output_16 (tmp
);
5919 uint8 tmp
, a
= (OP
[0]) & 0xff, b
= (GPR (OP
[1])) & 0xff;
5920 trace_input ("xorb", OP_CONSTANT16
, OP_REG
, OP_VOID
);
5922 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
5923 trace_output_16 (tmp
);
5930 uint8 tmp
, a
= (GPR (OP
[0])) & 0xff, b
= (GPR (OP
[1])) & 0xff;
5931 trace_input ("xorb", OP_REG
, OP_REG
, OP_VOID
);
5933 SET_GPR (OP
[1], (tmp
| ((GPR (OP
[1])) & 0xff00)));
5934 trace_output_16 (tmp
);
5941 uint16 tmp
, a
= (OP
[0]), b
= (GPR (OP
[1]));
5942 trace_input ("xorw", OP_CONSTANT4
, OP_REG
, OP_VOID
);
5944 SET_GPR (OP
[1], tmp
);
5945 trace_output_16 (tmp
);
5952 uint16 tmp
, a
= (OP
[0]), b
= (GPR (OP
[1]));
5953 trace_input ("xorw", OP_CONSTANT16
, OP_REG
, OP_VOID
);
5955 SET_GPR (OP
[1], tmp
);
5956 trace_output_16 (tmp
);
5963 uint16 tmp
, a
= (GPR (OP
[0])), b
= (GPR (OP
[1]));
5964 trace_input ("xorw", OP_REG
, OP_REG
, OP_VOID
);
5966 SET_GPR (OP
[1], tmp
);
5967 trace_output_16 (tmp
);
5970 /*REVISIT FOR LPR/SPR . */
5976 uint16 a
= GPR (OP
[0]);
5977 trace_input ("lpr", OP_REG
, OP_REG
, OP_VOID
);
5978 SET_CREG (OP
[1], a
);
5979 trace_output_16 (a
);
5986 uint32 a
= GPR32 (OP
[0]);
5987 trace_input ("lprd", OP_REGP
, OP_REG
, OP_VOID
);
5988 SET_CREG (OP
[1], a
);
5989 trace_output_flag ();
5996 uint16 a
= CREG (OP
[0]);
5997 trace_input ("spr", OP_REG
, OP_REG
, OP_VOID
);
5999 trace_output_16 (a
);
6006 uint32 a
= CREG (OP
[0]);
6007 trace_input ("sprd", OP_REGP
, OP_REGP
, OP_VOID
);
6008 SET_GPR32 (OP
[1], a
);
6009 trace_output_32 (a
);
6016 trace_input ("null", OP_VOID
, OP_VOID
, OP_VOID
);
6017 State
.exception
= SIG_CR16_STOP
;
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