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sim: cr16: clean up misc warnings
[deliverable/binutils-gdb.git] / sim / cr16 / simops.c
1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008-2015 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20
21 #include "config.h"
22
23 #include <signal.h>
24 #include <errno.h>
25 #include <sys/types.h>
26 #include <sys/stat.h>
27 #ifdef HAVE_UNISTD_H
28 #include <unistd.h>
29 #endif
30 #ifdef HAVE_STRING_H
31 #include <string.h>
32 #endif
33 #ifdef HAVE_TIME_H
34 #include <time.h>
35 #endif
36 #ifdef HAVE_SYS_TIME_H
37 #include <sys/time.h>
38 #endif
39
40 #include "cr16_sim.h"
41 #include "simops.h"
42 #include "targ-vals.h"
43
44 #ifdef TARGET_SYS_utime
45 #include <utime.h>
46 #endif
47 #ifdef TARGET_SYS_wait
48 #include <sys/wait.h>
49 #endif
50
51 enum op_types {
52 OP_VOID,
53 OP_CONSTANT3,
54 OP_UCONSTANT3,
55 OP_CONSTANT4,
56 OP_CONSTANT4_1,
57 OP_CONSTANT5,
58 OP_CONSTANT6,
59 OP_CONSTANT16,
60 OP_UCONSTANT16,
61 OP_CONSTANT20,
62 OP_UCONSTANT20,
63 OP_CONSTANT32,
64 OP_UCONSTANT32,
65 OP_MEMREF,
66 OP_MEMREF2,
67 OP_MEMREF3,
68
69 OP_DISP5,
70 OP_DISP17,
71 OP_DISP25,
72 OP_DISPE9,
73 //OP_ABS20,
74 OP_ABS20_OUTPUT,
75 //OP_ABS24,
76 OP_ABS24_OUTPUT,
77
78 OP_R_BASE_DISPS16,
79 OP_R_BASE_DISP20,
80 OP_R_BASE_DISPS20,
81 OP_R_BASE_DISPE20,
82
83 OP_RP_BASE_DISPE0,
84 OP_RP_BASE_DISP4,
85 OP_RP_BASE_DISPE4,
86 OP_RP_BASE_DISP14,
87 OP_RP_BASE_DISP16,
88 OP_RP_BASE_DISP20,
89 OP_RP_BASE_DISPS20,
90 OP_RP_BASE_DISPE20,
91
92 OP_R_INDEX7_ABS20,
93 OP_R_INDEX8_ABS20,
94
95 OP_RP_INDEX_DISP0,
96 OP_RP_INDEX_DISP14,
97 OP_RP_INDEX_DISP20,
98 OP_RP_INDEX_DISPS20,
99
100 OP_REG,
101 OP_REGP,
102 OP_PROC_REG,
103 OP_PROC_REGP,
104 OP_COND,
105 OP_RA
106 };
107
108
109 enum {
110 PSR_MASK = (PSR_I_BIT
111 | PSR_P_BIT
112 | PSR_E_BIT
113 | PSR_N_BIT
114 | PSR_Z_BIT
115 | PSR_F_BIT
116 | PSR_U_BIT
117 | PSR_L_BIT
118 | PSR_T_BIT
119 | PSR_C_BIT),
120 /* The following bits in the PSR _can't_ be set by instructions such
121 as mvtc. */
122 PSR_HW_MASK = (PSR_MASK)
123 };
124
125 /* cond Code Condition True State
126 * EQ Equal Z flag is 1
127 * NE Not Equal Z flag is 0
128 * CS Carry Set C flag is 1
129 * CC Carry Clear C flag is 0
130 * HI Higher L flag is 1
131 * LS Lower or Same L flag is 0
132 * GT Greater Than N flag is 1
133 * LE Less Than or Equal To N flag is 0
134 * FS Flag Set F flag is 1
135 * FC Flag Clear F flag is 0
136 * LO Lower Z and L flags are 0
137 * HS Higher or Same Z or L flag is 1
138 * LT Less Than Z and N flags are 0
139 * GE Greater Than or Equal To Z or N flag is 1. */
140
141 static int cond_stat(int cc)
142 {
143 switch (cc)
144 {
145 case 0: return PSR_Z; break;
146 case 1: return !PSR_Z; break;
147 case 2: return PSR_C; break;
148 case 3: return !PSR_C; break;
149 case 4: return PSR_L; break;
150 case 5: return !PSR_L; break;
151 case 6: return PSR_N; break;
152 case 7: return !PSR_N; break;
153 case 8: return PSR_F; break;
154 case 9: return !PSR_F; break;
155 case 10: return !PSR_Z && !PSR_L; break;
156 case 11: return PSR_Z || PSR_L; break;
157 case 12: return !PSR_Z && !PSR_N; break;
158 case 13: return PSR_Z || PSR_N; break;
159 case 14: return 1; break; /*ALWAYS. */
160 default:
161 // case NEVER: return false; break;
162 //case NO_COND_CODE:
163 //panic("Shouldn't have NO_COND_CODE in an actual instruction!");
164 return 0; break;
165 }
166 return 0;
167 }
168
169
170 creg_t
171 move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p)
172 {
173 /* A MASK bit is set when the corresponding bit in the CR should
174 be left alone. */
175 /* This assumes that (VAL & MASK) == 0. */
176 switch (cr)
177 {
178 case PSR_CR:
179 if (psw_hw_p)
180 val &= PSR_HW_MASK;
181 #if 0
182 else
183 val &= PSR_MASK;
184 (*cr16_callback->printf_filtered)
185 (cr16_callback,
186 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC);
187 State.exception = SIGILL;
188 #endif
189 /* keep an up-to-date psw around for tracing. */
190 State.trace.psw = (State.trace.psw & mask) | val;
191 break;
192 default:
193 break;
194 }
195 /* only issue an update if the register is being changed. */
196 if ((State.cregs[cr] & ~mask) != val)
197 SLOT_PEND_MASK (State.cregs[cr], mask, val);
198
199 return val;
200 }
201
202 #ifdef DEBUG
203 static void trace_input_func (const char *name,
204 enum op_types in1,
205 enum op_types in2,
206 enum op_types in3);
207
208 #define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (name, in1, in2, in3); } while (0)
209
210 #ifndef SIZE_INSTRUCTION
211 #define SIZE_INSTRUCTION 8
212 #endif
213
214 #ifndef SIZE_OPERANDS
215 #define SIZE_OPERANDS 18
216 #endif
217
218 #ifndef SIZE_VALUES
219 #define SIZE_VALUES 13
220 #endif
221
222 #ifndef SIZE_LOCATION
223 #define SIZE_LOCATION 20
224 #endif
225
226 #ifndef SIZE_PC
227 #define SIZE_PC 4
228 #endif
229
230 #ifndef SIZE_LINE_NUMBER
231 #define SIZE_LINE_NUMBER 2
232 #endif
233
234 static void
235 trace_input_func (const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
236 {
237 char *comma;
238 enum op_types in[3];
239 int i;
240 char buf[1024];
241 char *p;
242 long tmp;
243 char *type;
244 const char *filename;
245 const char *functionname;
246 unsigned int linenumber;
247 bfd_vma byte_pc;
248
249 if ((cr16_debug & DEBUG_TRACE) == 0)
250 return;
251
252 switch (State.ins_type)
253 {
254 default:
255 case INS_UNKNOWN: type = " ?"; break;
256 }
257
258 if ((cr16_debug & DEBUG_LINE_NUMBER) == 0)
259 (*cr16_callback->printf_filtered) (cr16_callback,
260 "0x%.*x %s: %-*s ",
261 SIZE_PC, (unsigned)PC,
262 type,
263 SIZE_INSTRUCTION, name);
264
265 else
266 {
267 buf[0] = '\0';
268 byte_pc = decode_pc ();
269 if (text && byte_pc >= text_start && byte_pc < text_end)
270 {
271 filename = (const char *)0;
272 functionname = (const char *)0;
273 linenumber = 0;
274 if (bfd_find_nearest_line (prog_bfd, text, (struct bfd_symbol **)0, byte_pc - text_start,
275 &filename, &functionname, &linenumber))
276 {
277 p = buf;
278 if (linenumber)
279 {
280 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
281 p += strlen (p);
282 }
283 else
284 {
285 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
286 p += SIZE_LINE_NUMBER+2;
287 }
288
289 if (functionname)
290 {
291 sprintf (p, "%s ", functionname);
292 p += strlen (p);
293 }
294 else if (filename)
295 {
296 char *q = strrchr (filename, '/');
297 sprintf (p, "%s ", (q) ? q+1 : filename);
298 p += strlen (p);
299 }
300
301 if (*p == ' ')
302 *p = '\0';
303 }
304 }
305
306 (*cr16_callback->printf_filtered) (cr16_callback,
307 "0x%.*x %s: %-*.*s %-*s ",
308 SIZE_PC, (unsigned)PC,
309 type,
310 SIZE_LOCATION, SIZE_LOCATION, buf,
311 SIZE_INSTRUCTION, name);
312 }
313
314 in[0] = in1;
315 in[1] = in2;
316 in[2] = in3;
317 comma = "";
318 p = buf;
319 for (i = 0; i < 3; i++)
320 {
321 switch (in[i])
322 {
323 case OP_VOID:
324 break;
325
326 case OP_REG:
327 case OP_REGP:
328 sprintf (p, "%sr%d", comma, OP[i]);
329 p += strlen (p);
330 comma = ",";
331 break;
332
333 case OP_PROC_REG:
334 sprintf (p, "%scr%d", comma, OP[i]);
335 p += strlen (p);
336 comma = ",";
337 break;
338
339 case OP_CONSTANT16:
340 sprintf (p, "%s%d", comma, OP[i]);
341 p += strlen (p);
342 comma = ",";
343 break;
344
345 case OP_CONSTANT4:
346 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
347 p += strlen (p);
348 comma = ",";
349 break;
350
351 case OP_CONSTANT3:
352 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
353 p += strlen (p);
354 comma = ",";
355 break;
356
357 case OP_MEMREF:
358 sprintf (p, "%s@r%d", comma, OP[i]);
359 p += strlen (p);
360 comma = ",";
361 break;
362
363 case OP_MEMREF2:
364 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
365 p += strlen (p);
366 comma = ",";
367 break;
368
369 case OP_MEMREF3:
370 sprintf (p, "%s@%d", comma, OP[i]);
371 p += strlen (p);
372 comma = ",";
373 break;
374 }
375 }
376
377 if ((cr16_debug & DEBUG_VALUES) == 0)
378 {
379 *p++ = '\n';
380 *p = '\0';
381 (*cr16_callback->printf_filtered) (cr16_callback, "%s", buf);
382 }
383 else
384 {
385 *p = '\0';
386 (*cr16_callback->printf_filtered) (cr16_callback, "%-*s", SIZE_OPERANDS, buf);
387
388 p = buf;
389 for (i = 0; i < 3; i++)
390 {
391 buf[0] = '\0';
392 switch (in[i])
393 {
394 case OP_VOID:
395 (*cr16_callback->printf_filtered) (cr16_callback, "%*s", SIZE_VALUES, "");
396 break;
397
398 case OP_REG:
399 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
400 (uint16) GPR (OP[i]));
401 break;
402
403 case OP_REGP:
404 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
405 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
406 break;
407
408 case OP_PROC_REG:
409 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
410 (uint16) CREG (OP[i]));
411 break;
412
413 case OP_CONSTANT16:
414 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
415 (uint16)OP[i]);
416 break;
417
418 case OP_CONSTANT4:
419 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
420 (uint16)SEXT4(OP[i]));
421 break;
422
423 case OP_CONSTANT3:
424 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
425 (uint16)SEXT3(OP[i]));
426 break;
427
428 case OP_MEMREF2:
429 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
430 (uint16)OP[i]);
431 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
432 (uint16)GPR (OP[i + 1]));
433 i++;
434 break;
435 }
436 }
437 }
438
439 (*cr16_callback->flush_stdout) (cr16_callback);
440 }
441
442 static void
443 do_trace_output_flush (void)
444 {
445 (*cr16_callback->flush_stdout) (cr16_callback);
446 }
447
448 static void
449 do_trace_output_finish (void)
450 {
451 (*cr16_callback->printf_filtered) (cr16_callback,
452 " F0=%d F1=%d C=%d\n",
453 (State.trace.psw & PSR_F_BIT) != 0,
454 (State.trace.psw & PSR_F_BIT) != 0,
455 (State.trace.psw & PSR_C_BIT) != 0);
456 (*cr16_callback->flush_stdout) (cr16_callback);
457 }
458
459 #if 0
460 static void
461 trace_output_40 (uint64 val)
462 {
463 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
464 {
465 (*cr16_callback->printf_filtered) (cr16_callback,
466 " :: %*s0x%.2x%.8lx",
467 SIZE_VALUES - 12,
468 "",
469 ((int)(val >> 32) & 0xff),
470 ((unsigned long) val) & 0xffffffff);
471 do_trace_output_finish ();
472 }
473 }
474 #endif
475
476 static void
477 trace_output_32 (uint32 val)
478 {
479 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
480 {
481 (*cr16_callback->printf_filtered) (cr16_callback,
482 " :: %*s0x%.8x",
483 SIZE_VALUES - 10,
484 "",
485 (int) val);
486 do_trace_output_finish ();
487 }
488 }
489
490 static void
491 trace_output_16 (uint16 val)
492 {
493 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
494 {
495 (*cr16_callback->printf_filtered) (cr16_callback,
496 " :: %*s0x%.4x",
497 SIZE_VALUES - 6,
498 "",
499 (int) val);
500 do_trace_output_finish ();
501 }
502 }
503
504 static void
505 trace_output_void (void)
506 {
507 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
508 {
509 (*cr16_callback->printf_filtered) (cr16_callback, "\n");
510 do_trace_output_flush ();
511 }
512 }
513
514 static void
515 trace_output_flag (void)
516 {
517 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
518 {
519 (*cr16_callback->printf_filtered) (cr16_callback,
520 " :: %*s",
521 SIZE_VALUES,
522 "");
523 do_trace_output_finish ();
524 }
525 }
526
527
528
529
530 #else
531 #define trace_input(NAME, IN1, IN2, IN3)
532 #define trace_output(RESULT)
533 #endif
534
535 /* addub. */
536 void
537 OP_2C_8 (void)
538 {
539 uint8 tmp;
540 uint8 a = OP[0] & 0xff;
541 uint16 b = (GPR (OP[1])) & 0xff;
542 trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
543 tmp = (a + b) & 0xff;
544 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
545 trace_output_16 (tmp);
546 }
547
548 /* addub. */
549 void
550 OP_2CB_C (void)
551 {
552 uint16 tmp;
553 uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
554 trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
555 tmp = (a + b) & 0xff;
556 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
557 trace_output_16 (tmp);
558 }
559
560 /* addub. */
561 void
562 OP_2D_8 (void)
563 {
564 uint8 a = (GPR (OP[0])) & 0xff;
565 uint8 b = (GPR (OP[1])) & 0xff;
566 uint16 tmp = (a + b) & 0xff;
567 trace_input ("addub", OP_REG, OP_REG, OP_VOID);
568 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
569 trace_output_16 (tmp);
570 }
571
572 /* adduw. */
573 void
574 OP_2E_8 (void)
575 {
576 uint16 a = OP[0];
577 uint16 b = GPR (OP[1]);
578 uint16 tmp = (a + b);
579 trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
580 SET_GPR (OP[1], tmp);
581 trace_output_16 (tmp);
582 }
583
584 /* adduw. */
585 void
586 OP_2EB_C (void)
587 {
588 uint16 a = OP[0];
589 uint16 b = GPR (OP[1]);
590 uint16 tmp = (a + b);
591 trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
592 SET_GPR (OP[1], tmp);
593 trace_output_16 (tmp);
594 }
595
596 /* adduw. */
597 void
598 OP_2F_8 (void)
599 {
600 uint16 a = GPR (OP[0]);
601 uint16 b = GPR (OP[1]);
602 uint16 tmp = (a + b);
603 trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
604 SET_GPR (OP[1], tmp);
605 trace_output_16 (tmp);
606 }
607
608 /* addb. */
609 void
610 OP_30_8 (void)
611 {
612 uint8 a = OP[0];
613 uint8 b = (GPR (OP[1]) & 0xff);
614 uint16 tmp = (a + b) & 0xff;
615 trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
616 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
617 SET_PSR_C (tmp > 0xFF);
618 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
619 trace_output_16 (tmp);
620 }
621
622 /* addb. */
623 void
624 OP_30B_C (void)
625 {
626 uint8 a = (OP[0]) & 0xff;
627 uint8 b = (GPR (OP[1]) & 0xff);
628 uint16 tmp = (a + b) & 0xff;
629 trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
630 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
631 SET_PSR_C (tmp > 0xFF);
632 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
633 trace_output_16 (tmp);
634 }
635
636 /* addb. */
637 void
638 OP_31_8 (void)
639 {
640 uint8 a = (GPR (OP[0]) & 0xff);
641 uint8 b = (GPR (OP[1]) & 0xff);
642 uint16 tmp = (a + b) & 0xff;
643 trace_input ("addb", OP_REG, OP_REG, OP_VOID);
644 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
645 SET_PSR_C (tmp > 0xFF);
646 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
647 trace_output_16 (tmp);
648 }
649
650 /* addw. */
651 void
652 OP_32_8 (void)
653 {
654 int16 a = OP[0];
655 uint16 tmp, b = GPR (OP[1]);
656 tmp = (a + b);
657 trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
658 SET_GPR (OP[1], tmp);
659 SET_PSR_C (tmp > 0xFFFF);
660 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
661 trace_output_16 (tmp);
662 }
663
664 /* addw. */
665 void
666 OP_32B_C (void)
667 {
668 int16 a = OP[0];
669 uint16 tmp, b = GPR (OP[1]);
670 tmp = (a + b);
671 trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
672 SET_GPR (OP[1], tmp);
673 SET_PSR_C (tmp > 0xFFFF);
674 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
675 trace_output_16 (tmp);
676 }
677
678 /* addw. */
679 void
680 OP_33_8 (void)
681 {
682 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
683 trace_input ("addw", OP_REG, OP_REG, OP_VOID);
684 tmp = (a + b);
685 SET_GPR (OP[1], tmp);
686 SET_PSR_C (tmp > 0xFFFF);
687 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
688 trace_output_16 (tmp);
689 }
690
691 /* addcb. */
692 void
693 OP_34_8 (void)
694 {
695 uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
696 trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
697 tmp = (a + b + PSR_C) & 0xff;
698 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
699 SET_PSR_C (tmp > 0xFF);
700 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
701 trace_output_16 (tmp);
702 }
703
704 /* addcb. */
705 void
706 OP_34B_C (void)
707 {
708 int8 a = OP[0] & 0xff;
709 uint8 b = (GPR (OP[1])) & 0xff;
710 uint8 tmp = (a + b + PSR_C) & 0xff;
711 trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
712 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
713 SET_PSR_C (tmp > 0xFF);
714 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
715 trace_output_16 (tmp);
716 }
717
718 /* addcb. */
719 void
720 OP_35_8 (void)
721 {
722 uint8 a = (GPR (OP[0])) & 0xff;
723 uint8 b = (GPR (OP[1])) & 0xff;
724 uint8 tmp = (a + b + PSR_C) & 0xff;
725 trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
726 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
727 SET_PSR_C (tmp > 0xFF);
728 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
729 trace_output_16 (tmp);
730 }
731
732 /* addcw. */
733 void
734 OP_36_8 (void)
735 {
736 uint16 a = OP[0];
737 uint16 b = GPR (OP[1]);
738 uint16 tmp = (a + b + PSR_C);
739 trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
740 SET_GPR (OP[1], tmp);
741 SET_PSR_C (tmp > 0xFFFF);
742 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
743 trace_output_16 (tmp);
744 }
745
746 /* addcw. */
747 void
748 OP_36B_C (void)
749 {
750 int16 a = OP[0];
751 uint16 b = GPR (OP[1]);
752 uint16 tmp = (a + b + PSR_C);
753 trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
754 SET_GPR (OP[1], tmp);
755 SET_PSR_C (tmp > 0xFFFF);
756 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
757 trace_output_16 (tmp);
758 }
759
760 /* addcw. */
761 void
762 OP_37_8 (void)
763 {
764 uint16 a = GPR (OP[1]);
765 uint16 b = GPR (OP[1]);
766 uint16 tmp = (a + b + PSR_C);
767 trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
768 SET_GPR (OP[1], tmp);
769 SET_PSR_C (tmp > 0xFFFF);
770 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
771 trace_output_16 (tmp);
772 }
773
774 /* addd. */
775 void
776 OP_60_8 (void)
777 {
778 int16 a = (OP[0]);
779 uint32 b = GPR32 (OP[1]);
780 uint32 tmp = (a + b);
781 trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
782 SET_GPR32 (OP[1], tmp);
783 SET_PSR_C (tmp > 0xFFFFFFFF);
784 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
785 trace_output_32 (tmp);
786 }
787
788 /* addd. */
789 void
790 OP_60B_C (void)
791 {
792 int32 a = (SEXT16(OP[0]));
793 uint32 b = GPR32 (OP[1]);
794 uint32 tmp = (a + b);
795 trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
796 SET_GPR32 (OP[1], tmp);
797 SET_PSR_C (tmp > 0xFFFFFFFF);
798 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
799 trace_output_32 (tmp);
800 }
801
802 /* addd. */
803 void
804 OP_61_8 (void)
805 {
806 uint32 a = GPR32 (OP[0]);
807 uint32 b = GPR32 (OP[1]);
808 uint32 tmp = (a + b);
809 trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
810 SET_GPR32 (OP[1], tmp);
811 trace_output_32 (tmp);
812 SET_PSR_C (tmp > 0xFFFFFFFF);
813 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
814 }
815
816 /* addd. */
817 void
818 OP_4_8 (void)
819 {
820 uint32 a = OP[0];
821 uint32 b = GPR32 (OP[1]);
822 uint32 tmp;
823 trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
824 tmp = (a + b);
825 SET_GPR32 (OP[1], tmp);
826 SET_PSR_C (tmp > 0xFFFFFFFF);
827 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
828 trace_output_32 (tmp);
829 }
830
831 /* addd. */
832 void
833 OP_2_C (void)
834 {
835 int32 a = OP[0];
836 uint32 b = GPR32 (OP[1]);
837 uint32 tmp;
838 trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
839 tmp = (a + b);
840 SET_GPR32 (OP[1], tmp);
841 SET_PSR_C (tmp > 0xFFFFFFFF);
842 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
843 trace_output_32 (tmp);
844 }
845
846 /* andb. */
847 void
848 OP_20_8 (void)
849 {
850 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
851 trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
852 tmp = a & b;
853 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
854 trace_output_16 (tmp);
855 }
856
857 /* andb. */
858 void
859 OP_20B_C (void)
860 {
861 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
862 trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
863 tmp = a & b;
864 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
865 trace_output_16 (tmp);
866 }
867
868 /* andb. */
869 void
870 OP_21_8 (void)
871 {
872 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
873 trace_input ("andb", OP_REG, OP_REG, OP_VOID);
874 tmp = a & b;
875 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
876 trace_output_16 (tmp);
877 }
878
879 /* andw. */
880 void
881 OP_22_8 (void)
882 {
883 uint16 tmp, a = OP[0], b = GPR (OP[1]);
884 trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
885 tmp = a & b;
886 SET_GPR (OP[1], tmp);
887 trace_output_16 (tmp);
888 }
889
890 /* andw. */
891 void
892 OP_22B_C (void)
893 {
894 uint16 tmp, a = OP[0], b = GPR (OP[1]);
895 trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
896 tmp = a & b;
897 SET_GPR (OP[1], tmp);
898 trace_output_16 (tmp);
899 }
900
901 /* andw. */
902 void
903 OP_23_8 (void)
904 {
905 uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]);
906 trace_input ("andw", OP_REG, OP_REG, OP_VOID);
907 tmp = a & b;
908 SET_GPR (OP[1], tmp);
909 trace_output_16 (tmp);
910 }
911
912 /* andd. */
913 void
914 OP_4_C (void)
915 {
916 uint32 tmp, a = OP[0], b = GPR32 (OP[1]);
917 trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
918 tmp = a & b;
919 SET_GPR32 (OP[1], tmp);
920 trace_output_32 (tmp);
921 }
922
923 /* andd. */
924 void
925 OP_14B_14 (void)
926 {
927 uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
928 trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
929 tmp = a & b;
930 SET_GPR32 (OP[1], tmp);
931 trace_output_32 (tmp);
932 }
933
934 /* ord. */
935 void
936 OP_5_C (void)
937 {
938 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
939 trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
940 tmp = a | b;
941 SET_GPR32 (OP[1], tmp);
942 trace_output_32 (tmp);
943 }
944
945 /* ord. */
946 void
947 OP_149_14 (void)
948 {
949 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
950 trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
951 tmp = a | b;
952 SET_GPR32 (OP[1], tmp);
953 trace_output_32 (tmp);
954 }
955
956 /* xord. */
957 void
958 OP_6_C (void)
959 {
960 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
961 trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
962 tmp = a ^ b;
963 SET_GPR32 (OP[1], tmp);
964 trace_output_32 (tmp);
965 }
966
967 /* xord. */
968 void
969 OP_14A_14 (void)
970 {
971 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
972 trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
973 tmp = a ^ b;
974 SET_GPR32 (OP[1], tmp);
975 trace_output_32 (tmp);
976 }
977
978
979 /* b. */
980 void
981 OP_1_4 (void)
982 {
983 uint32 tmp = 0, cc = cond_stat (OP[0]);
984 trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
985 if (cc)
986 {
987 if (sign_flag)
988 tmp = (PC - (OP[1]));
989 else
990 tmp = (PC + (OP[1]));
991 /* If the resulting PC value is less than 0x00_0000 or greater
992 than 0xFF_FFFF, this instruction causes an IAD trap.*/
993
994 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
995 {
996 State.exception = SIG_CR16_BUS;
997 State.pc_changed = 1; /* Don't increment the PC. */
998 trace_output_void ();
999 return;
1000 }
1001 else
1002 JMP (tmp);
1003 }
1004 sign_flag = 0; /* Reset sign_flag. */
1005 trace_output_32 (tmp);
1006 }
1007
1008 /* b. */
1009 void
1010 OP_18_8 (void)
1011 {
1012 uint32 tmp = 0, cc = cond_stat (OP[0]);
1013 trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
1014 if (cc)
1015 {
1016 if (sign_flag)
1017 tmp = (PC - OP[1]);
1018 else
1019 tmp = (PC + OP[1]);
1020 /* If the resulting PC value is less than 0x00_0000 or greater
1021 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1022
1023 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1024 {
1025 State.exception = SIG_CR16_BUS;
1026 State.pc_changed = 1; /* Don't increment the PC. */
1027 trace_output_void ();
1028 return;
1029 }
1030 else
1031 JMP (tmp);
1032 }
1033 sign_flag = 0; /* Reset sign_flag. */
1034 trace_output_32 (tmp);
1035 }
1036
1037 /* b. */
1038 void
1039 OP_10_10 (void)
1040 {
1041 uint32 tmp = 0, cc = cond_stat (OP[0]);
1042 trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
1043 if (cc)
1044 {
1045 if (sign_flag)
1046 tmp = (PC - (OP[1]));
1047 else
1048 tmp = (PC + (OP[1]));
1049 /* If the resulting PC value is less than 0x00_0000 or greater
1050 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1051
1052 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1053 {
1054 State.exception = SIG_CR16_BUS;
1055 State.pc_changed = 1; /* Don't increment the PC. */
1056 trace_output_void ();
1057 return;
1058 }
1059 else
1060 JMP (tmp);
1061 }
1062 sign_flag = 0; /* Reset sign_flag. */
1063 trace_output_32 (tmp);
1064 }
1065
1066 /* bal. */
1067 void
1068 OP_C0_8 (void)
1069 {
1070 uint32 tmp;
1071 trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
1072 tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
1073 SET_GPR32 (14, tmp);
1074 if (sign_flag)
1075 tmp = (PC - (OP[1]));
1076 else
1077 tmp = (PC + (OP[1]));
1078
1079 /* If the resulting PC value is less than 0x00_0000 or greater
1080 than 0xFF_FFFF, this instruction causes an IAD trap. */
1081
1082 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1083 {
1084 State.exception = SIG_CR16_BUS;
1085 State.pc_changed = 1; /* Don't increment the PC. */
1086 trace_output_void ();
1087 return;
1088 }
1089 else
1090 JMP (tmp);
1091 sign_flag = 0; /* Reset sign_flag. */
1092 trace_output_32 (tmp);
1093 }
1094
1095
1096 /* bal. */
1097 void
1098 OP_102_14 (void)
1099 {
1100 uint32 tmp;
1101 trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
1102 tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
1103 SET_GPR32 (OP[0], tmp);
1104 if (sign_flag)
1105 tmp = ((PC) - (OP[1]));
1106 else
1107 tmp = ((PC) + (OP[1]));
1108 /* If the resulting PC value is less than 0x00_0000 or greater
1109 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1110
1111 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1112 {
1113 State.exception = SIG_CR16_BUS;
1114 State.pc_changed = 1; /* Don't increment the PC. */
1115 trace_output_void ();
1116 return;
1117 }
1118 else
1119 JMP (tmp);
1120 sign_flag = 0; /* Reset sign_flag. */
1121 trace_output_32 (tmp);
1122 }
1123
1124 /* jal. */
1125 void
1126 OP_148_14 (void)
1127 {
1128 uint32 tmp;
1129 trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
1130 SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
1131 tmp = GPR32 (OP[1]);
1132 tmp = SEXT24(tmp << 1);
1133 /* If the resulting PC value is less than 0x00_0000 or greater
1134 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1135
1136 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1137 {
1138 State.exception = SIG_CR16_BUS;
1139 State.pc_changed = 1; /* Don't increment the PC. */
1140 trace_output_void ();
1141 return;
1142 }
1143 else
1144 JMP (tmp);
1145
1146 trace_output_32 (tmp);
1147 }
1148
1149
1150 /* jal. */
1151 void
1152 OP_D_C (void)
1153 {
1154 uint32 tmp;
1155 trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
1156 SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
1157 tmp = GPR32 (OP[0]);
1158 tmp = SEXT24(tmp << 1);
1159 /* If the resulting PC value is less than 0x00_0000 or greater
1160 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1161
1162 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1163 {
1164 State.exception = SIG_CR16_BUS;
1165 State.pc_changed = 1; /* Don't increment the PC. */
1166 trace_output_void ();
1167 return;
1168 }
1169 else
1170 JMP (tmp);
1171
1172 trace_output_32 (tmp);
1173 }
1174
1175
1176 /* beq0b. */
1177 void
1178 OP_C_8 (void)
1179 {
1180 uint32 addr;
1181 uint8 a = (GPR (OP[0]) & 0xFF);
1182 trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
1183 addr = OP[1];
1184 if (a == 0)
1185 {
1186 if (sign_flag)
1187 addr = (PC - OP[1]);
1188 else
1189 addr = (PC + OP[1]);
1190
1191 JMP (addr);
1192 }
1193 sign_flag = 0; /* Reset sign_flag. */
1194 trace_output_void ();
1195 }
1196
1197 /* bne0b. */
1198 void
1199 OP_D_8 (void)
1200 {
1201 uint32 addr;
1202 uint8 a = (GPR (OP[0]) & 0xFF);
1203 trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
1204 addr = OP[1];
1205 if (a != 0)
1206 {
1207 if (sign_flag)
1208 addr = (PC - OP[1]);
1209 else
1210 addr = (PC + OP[1]);
1211
1212 JMP (addr);
1213 }
1214 sign_flag = 0; /* Reset sign_flag. */
1215 trace_output_void ();
1216 }
1217
1218 /* beq0w. */
1219 void
1220 OP_E_8 (void)
1221 {
1222 uint32 addr;
1223 uint16 a = GPR (OP[0]);
1224 trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
1225 addr = OP[1];
1226 if (a == 0)
1227 {
1228 if (sign_flag)
1229 addr = (PC - OP[1]);
1230 else
1231 addr = (PC + OP[1]);
1232
1233 JMP (addr);
1234 }
1235 sign_flag = 0; /* Reset sign_flag. */
1236 trace_output_void ();
1237 }
1238
1239 /* bne0w. */
1240 void
1241 OP_F_8 (void)
1242 {
1243 uint32 addr;
1244 uint16 a = GPR (OP[0]);
1245 trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
1246 addr = OP[1];
1247 if (a != 0)
1248 {
1249 if (sign_flag)
1250 addr = (PC - OP[1]);
1251 else
1252 addr = (PC + OP[1]);
1253
1254 JMP (addr);
1255 }
1256 sign_flag = 0; /* Reset sign_flag. */
1257 trace_output_void ();
1258 }
1259
1260
1261 /* jeq. */
1262 void
1263 OP_A0_C (void)
1264 {
1265 uint32 tmp = 0;
1266 trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
1267 if ((PSR_Z) == 1)
1268 {
1269 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1270 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1271 }
1272 trace_output_32 (tmp);
1273 }
1274
1275 /* jne. */
1276 void
1277 OP_A1_C (void)
1278 {
1279 uint32 tmp = 0;
1280 trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
1281 if ((PSR_Z) == 0)
1282 {
1283 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1284 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1285 }
1286 trace_output_32 (tmp);
1287 }
1288
1289 /* jcs. */
1290 void
1291 OP_A2_C (void)
1292 {
1293 uint32 tmp = 0;
1294 trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
1295 if ((PSR_C) == 1)
1296 {
1297 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1298 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1299 }
1300 trace_output_32 (tmp);
1301 }
1302
1303 /* jcc. */
1304 void
1305 OP_A3_C (void)
1306 {
1307 uint32 tmp = 0;
1308 trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
1309 if ((PSR_C) == 0)
1310 {
1311 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1312 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1313 }
1314 trace_output_32 (tmp);
1315 }
1316
1317 /* jhi. */
1318 void
1319 OP_A4_C (void)
1320 {
1321 uint32 tmp = 0;
1322 trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
1323 if ((PSR_L) == 1)
1324 {
1325 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1326 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1327 }
1328 trace_output_32 (tmp);
1329 }
1330
1331 /* jls. */
1332 void
1333 OP_A5_C (void)
1334 {
1335 uint32 tmp = 0;
1336 trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
1337 if ((PSR_L) == 0)
1338 {
1339 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1340 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1341 }
1342 trace_output_32 (tmp);
1343 }
1344
1345 /* jgt. */
1346 void
1347 OP_A6_C (void)
1348 {
1349 uint32 tmp = 0;
1350 trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
1351 if ((PSR_N) == 1)
1352 {
1353 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1354 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1355 }
1356 trace_output_32 (tmp);
1357 }
1358
1359 /* jle. */
1360 void
1361 OP_A7_C (void)
1362 {
1363 uint32 tmp = 0;
1364 trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
1365 if ((PSR_N) == 0)
1366 {
1367 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1368 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1369 }
1370 trace_output_32 (tmp);
1371 }
1372
1373
1374 /* jfs. */
1375 void
1376 OP_A8_C (void)
1377 {
1378 uint32 tmp = 0;
1379 trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
1380 if ((PSR_F) == 1)
1381 {
1382 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1383 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1384 }
1385 trace_output_32 (tmp);
1386 }
1387
1388 /* jfc. */
1389 void
1390 OP_A9_C (void)
1391 {
1392 uint32 tmp = 0;
1393 trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
1394 if ((PSR_F) == 0)
1395 {
1396 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1397 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1398 }
1399 trace_output_32 (tmp);
1400 }
1401
1402 /* jlo. */
1403 void
1404 OP_AA_C (void)
1405 {
1406 uint32 tmp = 0;
1407 trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
1408 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1409 {
1410 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1411 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1412 }
1413 trace_output_32 (tmp);
1414 }
1415
1416 /* jhs. */
1417 void
1418 OP_AB_C (void)
1419 {
1420 uint32 tmp = 0;
1421 trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
1422 if (((PSR_Z) == 1) | ((PSR_L) == 1))
1423 {
1424 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1425 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1426 }
1427 trace_output_32 (tmp);
1428 }
1429
1430 /* jlt. */
1431 void
1432 OP_AC_C (void)
1433 {
1434 uint32 tmp = 0;
1435 trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
1436 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1437 {
1438 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1439 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1440 }
1441 trace_output_32 (tmp);
1442 }
1443
1444 /* jge. */
1445 void
1446 OP_AD_C (void)
1447 {
1448 uint32 tmp = 0;
1449 trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
1450 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1451 {
1452 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1453 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1454 }
1455 trace_output_32 (tmp);
1456 }
1457
1458 /* jump. */
1459 void
1460 OP_AE_C (void)
1461 {
1462 uint32 tmp;
1463 trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
1464 tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
1465 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1466 trace_output_32 (tmp);
1467 }
1468
1469 /* jusr. */
1470 void
1471 OP_AF_C (void)
1472 {
1473 uint32 tmp;
1474 trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
1475 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1476 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1477 SET_PSR_U(1);
1478 trace_output_32 (tmp);
1479 }
1480
1481 /* seq. */
1482 void
1483 OP_80_C (void)
1484 {
1485 trace_input ("seq", OP_REG, OP_VOID, OP_VOID);
1486 if ((PSR_Z) == 1)
1487 SET_GPR (OP[0], 1);
1488 else
1489 SET_GPR (OP[0], 0);
1490 trace_output_void ();
1491 }
1492 /* sne. */
1493 void
1494 OP_81_C (void)
1495 {
1496 trace_input ("sne", OP_REG, OP_VOID, OP_VOID);
1497 if ((PSR_Z) == 0)
1498 SET_GPR (OP[0], 1);
1499 else
1500 SET_GPR (OP[0], 0);
1501 trace_output_void ();
1502 }
1503
1504 /* scs. */
1505 void
1506 OP_82_C (void)
1507 {
1508 trace_input ("scs", OP_REG, OP_VOID, OP_VOID);
1509 if ((PSR_C) == 1)
1510 SET_GPR (OP[0], 1);
1511 else
1512 SET_GPR (OP[0], 0);
1513 trace_output_void ();
1514 }
1515
1516 /* scc. */
1517 void
1518 OP_83_C (void)
1519 {
1520 trace_input ("scc", OP_REG, OP_VOID, OP_VOID);
1521 if ((PSR_C) == 0)
1522 SET_GPR (OP[0], 1);
1523 else
1524 SET_GPR (OP[0], 0);
1525 trace_output_void ();
1526 }
1527
1528 /* shi. */
1529 void
1530 OP_84_C (void)
1531 {
1532 trace_input ("shi", OP_REG, OP_VOID, OP_VOID);
1533 if ((PSR_L) == 1)
1534 SET_GPR (OP[0], 1);
1535 else
1536 SET_GPR (OP[0], 0);
1537 trace_output_void ();
1538 }
1539
1540 /* sls. */
1541 void
1542 OP_85_C (void)
1543 {
1544 trace_input ("sls", OP_REG, OP_VOID, OP_VOID);
1545 if ((PSR_L) == 0)
1546 SET_GPR (OP[0], 1);
1547 else
1548 SET_GPR (OP[0], 0);
1549 trace_output_void ();
1550 }
1551
1552 /* sgt. */
1553 void
1554 OP_86_C (void)
1555 {
1556 trace_input ("sgt", OP_REG, OP_VOID, OP_VOID);
1557 if ((PSR_N) == 1)
1558 SET_GPR (OP[0], 1);
1559 else
1560 SET_GPR (OP[0], 0);
1561 trace_output_void ();
1562 }
1563
1564 /* sle. */
1565 void
1566 OP_87_C (void)
1567 {
1568 trace_input ("sle", OP_REG, OP_VOID, OP_VOID);
1569 if ((PSR_N) == 0)
1570 SET_GPR (OP[0], 1);
1571 else
1572 SET_GPR (OP[0], 0);
1573 trace_output_void ();
1574 }
1575
1576 /* sfs. */
1577 void
1578 OP_88_C (void)
1579 {
1580 trace_input ("sfs", OP_REG, OP_VOID, OP_VOID);
1581 if ((PSR_F) == 1)
1582 SET_GPR (OP[0], 1);
1583 else
1584 SET_GPR (OP[0], 0);
1585 trace_output_void ();
1586 }
1587
1588 /* sfc. */
1589 void
1590 OP_89_C (void)
1591 {
1592 trace_input ("sfc", OP_REG, OP_VOID, OP_VOID);
1593 if ((PSR_F) == 0)
1594 SET_GPR (OP[0], 1);
1595 else
1596 SET_GPR (OP[0], 0);
1597 trace_output_void ();
1598 }
1599
1600
1601 /* slo. */
1602 void
1603 OP_8A_C (void)
1604 {
1605 trace_input ("slo", OP_REG, OP_VOID, OP_VOID);
1606 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1607 SET_GPR (OP[0], 1);
1608 else
1609 SET_GPR (OP[0], 0);
1610 trace_output_void ();
1611 }
1612
1613 /* shs. */
1614 void
1615 OP_8B_C (void)
1616 {
1617 trace_input ("shs", OP_REG, OP_VOID, OP_VOID);
1618 if ( ((PSR_Z) == 1) | ((PSR_L) == 1))
1619 SET_GPR (OP[0], 1);
1620 else
1621 SET_GPR (OP[0], 0);
1622 trace_output_void ();
1623 }
1624
1625 /* slt. */
1626 void
1627 OP_8C_C (void)
1628 {
1629 trace_input ("slt", OP_REG, OP_VOID, OP_VOID);
1630 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1631 SET_GPR (OP[0], 1);
1632 else
1633 SET_GPR (OP[0], 0);
1634 trace_output_void ();
1635 }
1636
1637 /* sge. */
1638 void
1639 OP_8D_C (void)
1640 {
1641 trace_input ("sge", OP_REG, OP_VOID, OP_VOID);
1642 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1643 SET_GPR (OP[0], 1);
1644 else
1645 SET_GPR (OP[0], 0);
1646 trace_output_void ();
1647 }
1648
1649 /* cbitb. */
1650 void
1651 OP_D7_9 (void)
1652 {
1653 uint8 a = OP[0] & 0xff;
1654 uint32 addr = OP[1], tmp;
1655 trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1656 tmp = RB (addr);
1657 SET_PSR_F (tmp & (1 << a));
1658 tmp = tmp & ~(1 << a);
1659 SB (addr, tmp);
1660 trace_output_32 (tmp);
1661 }
1662
1663 /* cbitb. */
1664 void
1665 OP_107_14 (void)
1666 {
1667 uint8 a = OP[0] & 0xff;
1668 uint32 addr = OP[1], tmp;
1669 trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1670 tmp = RB (addr);
1671 SET_PSR_F (tmp & (1 << a));
1672 tmp = tmp & ~(1 << a);
1673 SB (addr, tmp);
1674 trace_output_32 (tmp);
1675 }
1676
1677 /* cbitb. */
1678 void
1679 OP_68_8 (void)
1680 {
1681 uint8 a = (OP[0]) & 0xff;
1682 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1683 trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1684 tmp = RB (addr);
1685 SET_PSR_F (tmp & (1 << a));
1686 tmp = tmp & ~(1 << a);
1687 SB (addr, tmp);
1688 trace_output_32 (addr);
1689 }
1690
1691 /* cbitb. */
1692 void
1693 OP_1AA_A (void)
1694 {
1695 uint8 a = (OP[0]) & 0xff;
1696 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1697 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1698 tmp = RB (addr);
1699 SET_PSR_F (tmp & (1 << a));
1700 tmp = tmp & ~(1 << a);
1701 SB (addr, tmp);
1702 trace_output_32 (addr);
1703 }
1704
1705 /* cbitb. */
1706 void
1707 OP_104_14 (void)
1708 {
1709 uint8 a = (OP[0]) & 0xff;
1710 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1711 trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1712 tmp = RB (addr);
1713 SET_PSR_F (tmp & (1 << a));
1714 tmp = tmp & ~(1 << a);
1715 SB (addr, tmp);
1716 trace_output_32 (addr);
1717 }
1718
1719 /* cbitb. */
1720 void
1721 OP_D4_9 (void)
1722 {
1723 uint8 a = (OP[0]) & 0xff;
1724 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1725 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1726 tmp = RB (addr);
1727 SET_PSR_F (tmp & (1 << a));
1728 tmp = tmp & ~(1 << a);
1729 SB (addr, tmp);
1730 trace_output_32 (addr);
1731 }
1732
1733 /* cbitb. */
1734 void
1735 OP_D6_9 (void)
1736 {
1737 uint8 a = (OP[0]) & 0xff;
1738 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1739 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1740 tmp = RB (addr);
1741 SET_PSR_F (tmp & (1 << a));
1742 tmp = tmp & ~(1 << a);
1743 SB (addr, tmp);
1744 trace_output_32 (addr);
1745
1746 }
1747
1748 /* cbitb. */
1749 void
1750 OP_105_14 (void)
1751 {
1752 uint8 a = (OP[0]) & 0xff;
1753 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1754 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1755 tmp = RB (addr);
1756 SET_PSR_F (tmp & (1 << a));
1757 tmp = tmp & ~(1 << a);
1758 SB (addr, tmp);
1759 trace_output_32 (addr);
1760 }
1761
1762 /* cbitb. */
1763 void
1764 OP_106_14 (void)
1765 {
1766 uint8 a = (OP[0]) & 0xff;
1767 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1768 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1769 tmp = RB (addr);
1770 SET_PSR_F (tmp & (1 << a));
1771 tmp = tmp & ~(1 << a);
1772 SB (addr, tmp);
1773 trace_output_32 (addr);
1774 }
1775
1776
1777 /* cbitw. */
1778 void
1779 OP_6F_8 (void)
1780 {
1781 uint16 a = OP[0];
1782 uint32 addr = OP[1], tmp;
1783 trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1784 tmp = RW (addr);
1785 SET_PSR_F (tmp & (1 << a));
1786 tmp = tmp & ~(1 << a);
1787 SW (addr, tmp);
1788 trace_output_32 (tmp);
1789 }
1790
1791 /* cbitw. */
1792 void
1793 OP_117_14 (void)
1794 {
1795 uint16 a = OP[0];
1796 uint32 addr = OP[1], tmp;
1797 trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1798 tmp = RW (addr);
1799 SET_PSR_F (tmp & (1 << a));
1800 tmp = tmp & ~(1 << a);
1801 SW (addr, tmp);
1802 trace_output_32 (tmp);
1803 }
1804
1805 /* cbitw. */
1806 void
1807 OP_36_7 (void)
1808 {
1809 uint32 addr;
1810 uint16 a = (OP[0]), tmp;
1811 trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
1812
1813 if (OP[1] == 0)
1814 addr = (GPR32 (12)) + OP[2];
1815 else
1816 addr = (GPR32 (13)) + OP[2];
1817
1818 tmp = RW (addr);
1819 SET_PSR_F (tmp & (1 << a));
1820 tmp = tmp & ~(1 << a);
1821 SW (addr, tmp);
1822 trace_output_32 (addr);
1823
1824 }
1825
1826 /* cbitw. */
1827 void
1828 OP_1AB_A (void)
1829 {
1830 uint16 a = (OP[0]);
1831 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1832 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1833 tmp = RW (addr);
1834 SET_PSR_F (tmp & (1 << a));
1835 tmp = tmp & ~(1 << a);
1836 SW (addr, tmp);
1837 trace_output_32 (addr);
1838 }
1839
1840 /* cbitw. */
1841 void
1842 OP_114_14 (void)
1843 {
1844 uint16 a = (OP[0]);
1845 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1846 trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1847 tmp = RW (addr);
1848 SET_PSR_F (tmp & (1 << a));
1849 tmp = tmp & ~(1 << a);
1850 SW (addr, tmp);
1851 trace_output_32 (addr);
1852 }
1853
1854
1855 /* cbitw. */
1856 void
1857 OP_6E_8 (void)
1858 {
1859 uint16 a = (OP[0]);
1860 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1861 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1862 tmp = RW (addr);
1863 SET_PSR_F (tmp & (1 << a));
1864 tmp = tmp & ~(1 << a);
1865 SW (addr, tmp);
1866 trace_output_32 (addr);
1867 }
1868
1869 /* cbitw. */
1870 void
1871 OP_69_8 (void)
1872 {
1873 uint16 a = (OP[0]);
1874 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1875 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1876 tmp = RW (addr);
1877 SET_PSR_F (tmp & (1 << a));
1878 tmp = tmp & ~(1 << a);
1879 SW (addr, tmp);
1880 trace_output_32 (addr);
1881 }
1882
1883
1884 /* cbitw. */
1885 void
1886 OP_115_14 (void)
1887 {
1888 uint16 a = (OP[0]);
1889 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1890 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1891 tmp = RW (addr);
1892 SET_PSR_F (tmp & (1 << a));
1893 tmp = tmp & ~(1 << a);
1894 SW (addr, tmp);
1895 trace_output_32 (addr);
1896 }
1897
1898 /* cbitw. */
1899 void
1900 OP_116_14 (void)
1901 {
1902 uint16 a = (OP[0]);
1903 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1904 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1905 tmp = RW (addr);
1906 SET_PSR_F (tmp & (1 << a));
1907 tmp = tmp & ~(1 << a);
1908 SW (addr, tmp);
1909 trace_output_32 (addr);
1910 }
1911
1912 /* sbitb. */
1913 void
1914 OP_E7_9 (void)
1915 {
1916 uint8 a = OP[0] & 0xff;
1917 uint32 addr = OP[1], tmp;
1918 trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1919 tmp = RB (addr);
1920 SET_PSR_F (tmp & (1 << a));
1921 tmp = tmp | (1 << a);
1922 SB (addr, tmp);
1923 trace_output_32 (tmp);
1924 }
1925
1926 /* sbitb. */
1927 void
1928 OP_10B_14 (void)
1929 {
1930 uint8 a = OP[0] & 0xff;
1931 uint32 addr = OP[1], tmp;
1932 trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1933 tmp = RB (addr);
1934 SET_PSR_F (tmp & (1 << a));
1935 tmp = tmp | (1 << a);
1936 SB (addr, tmp);
1937 trace_output_32 (tmp);
1938 }
1939
1940 /* sbitb. */
1941 void
1942 OP_70_8 (void)
1943 {
1944 uint8 a = OP[0] & 0xff;
1945 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1946 trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1947 tmp = RB (addr);
1948 SET_PSR_F (tmp & (1 << a));
1949 tmp = tmp | (1 << a);
1950 SB (addr, tmp);
1951 trace_output_32 (tmp);
1952 }
1953
1954 /* sbitb. */
1955 void
1956 OP_1CA_A (void)
1957 {
1958 uint8 a = OP[0] & 0xff;
1959 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1960 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1961 tmp = RB (addr);
1962 SET_PSR_F (tmp & (1 << a));
1963 tmp = tmp | (1 << a);
1964 SB (addr, tmp);
1965 trace_output_32 (tmp);
1966 }
1967
1968 /* sbitb. */
1969 void
1970 OP_108_14 (void)
1971 {
1972 uint8 a = OP[0] & 0xff;
1973 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1974 trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1975 tmp = RB (addr);
1976 SET_PSR_F (tmp & (1 << a));
1977 tmp = tmp | (1 << a);
1978 SB (addr, tmp);
1979 trace_output_32 (tmp);
1980 }
1981
1982
1983 /* sbitb. */
1984 void
1985 OP_E4_9 (void)
1986 {
1987 uint8 a = OP[0] & 0xff;
1988 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1989 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1990 tmp = RB (addr);
1991 SET_PSR_F (tmp & (1 << a));
1992 tmp = tmp | (1 << a);
1993 SB (addr, tmp);
1994 trace_output_32 (tmp);
1995 }
1996
1997 /* sbitb. */
1998 void
1999 OP_E6_9 (void)
2000 {
2001 uint8 a = OP[0] & 0xff;
2002 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2003 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2004 tmp = RB (addr);
2005 SET_PSR_F (tmp & (1 << a));
2006 tmp = tmp | (1 << a);
2007 SB (addr, tmp);
2008 trace_output_32 (tmp);
2009 }
2010
2011
2012 /* sbitb. */
2013 void
2014 OP_109_14 (void)
2015 {
2016 uint8 a = OP[0] & 0xff;
2017 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2018 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2019 tmp = RB (addr);
2020 SET_PSR_F (tmp & (1 << a));
2021 tmp = tmp | (1 << a);
2022 SB (addr, tmp);
2023 trace_output_32 (tmp);
2024 }
2025
2026
2027 /* sbitb. */
2028 void
2029 OP_10A_14 (void)
2030 {
2031 uint8 a = OP[0] & 0xff;
2032 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2033 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2034 tmp = RB (addr);
2035 SET_PSR_F (tmp & (1 << a));
2036 tmp = tmp | (1 << a);
2037 SB (addr, tmp);
2038 trace_output_32 (tmp);
2039 }
2040
2041
2042 /* sbitw. */
2043 void
2044 OP_77_8 (void)
2045 {
2046 uint16 a = OP[0];
2047 uint32 addr = OP[1], tmp;
2048 trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2049 tmp = RW (addr);
2050 SET_PSR_F (tmp & (1 << a));
2051 tmp = tmp | (1 << a);
2052 SW (addr, tmp);
2053 trace_output_32 (tmp);
2054 }
2055
2056 /* sbitw. */
2057 void
2058 OP_11B_14 (void)
2059 {
2060 uint16 a = OP[0];
2061 uint32 addr = OP[1], tmp;
2062 trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2063 tmp = RW (addr);
2064 SET_PSR_F (tmp & (1 << a));
2065 tmp = tmp | (1 << a);
2066 SW (addr, tmp);
2067 trace_output_32 (tmp);
2068 }
2069
2070 /* sbitw. */
2071 void
2072 OP_3A_7 (void)
2073 {
2074 uint32 addr;
2075 uint16 a = (OP[0]), tmp;
2076 trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2077
2078 if (OP[1] == 0)
2079 addr = (GPR32 (12)) + OP[2];
2080 else
2081 addr = (GPR32 (13)) + OP[2];
2082
2083 tmp = RW (addr);
2084 SET_PSR_F (tmp & (1 << a));
2085 tmp = tmp | (1 << a);
2086 SW (addr, tmp);
2087 trace_output_32 (addr);
2088 }
2089
2090 /* sbitw. */
2091 void
2092 OP_1CB_A (void)
2093 {
2094 uint16 a = (OP[0]);
2095 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2096 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2097 tmp = RW (addr);
2098 SET_PSR_F (tmp & (1 << a));
2099 tmp = tmp | (1 << a);
2100 SW (addr, tmp);
2101 trace_output_32 (addr);
2102 }
2103
2104 /* sbitw. */
2105 void
2106 OP_118_14 (void)
2107 {
2108 uint16 a = (OP[0]);
2109 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2110 trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2111 tmp = RW (addr);
2112 SET_PSR_F (tmp & (1 << a));
2113 tmp = tmp | (1 << a);
2114 SW (addr, tmp);
2115 trace_output_32 (addr);
2116 }
2117
2118 /* sbitw. */
2119 void
2120 OP_76_8 (void)
2121 {
2122 uint16 a = (OP[0]);
2123 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2124 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2125 tmp = RW (addr);
2126 SET_PSR_F (tmp & (1 << a));
2127 tmp = tmp | (1 << a);
2128 SW (addr, tmp);
2129 trace_output_32 (addr);
2130 }
2131
2132 /* sbitw. */
2133 void
2134 OP_71_8 (void)
2135 {
2136 uint16 a = (OP[0]);
2137 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2138 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2139 tmp = RW (addr);
2140 SET_PSR_F (tmp & (1 << a));
2141 tmp = tmp | (1 << a);
2142 SW (addr, tmp);
2143 trace_output_32 (addr);
2144 }
2145
2146 /* sbitw. */
2147 void
2148 OP_119_14 (void)
2149 {
2150 uint16 a = (OP[0]);
2151 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2152 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2153 tmp = RW (addr);
2154 SET_PSR_F (tmp & (1 << a));
2155 tmp = tmp | (1 << a);
2156 SW (addr, tmp);
2157 trace_output_32 (addr);
2158 }
2159
2160 /* sbitw. */
2161 void
2162 OP_11A_14 (void)
2163 {
2164 uint16 a = (OP[0]);
2165 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2166 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2167 tmp = RW (addr);
2168 SET_PSR_F (tmp & (1 << a));
2169 tmp = tmp | (1 << a);
2170 SW (addr, tmp);
2171 trace_output_32 (addr);
2172 }
2173
2174
2175 /* tbitb. */
2176 void
2177 OP_F7_9 (void)
2178 {
2179 uint8 a = OP[0] & 0xff;
2180 uint32 addr = OP[1], tmp;
2181 trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2182 tmp = RB (addr);
2183 SET_PSR_F (tmp & (1 << a));
2184 trace_output_32 (tmp);
2185 }
2186
2187 /* tbitb. */
2188 void
2189 OP_10F_14 (void)
2190 {
2191 uint8 a = OP[0] & 0xff;
2192 uint32 addr = OP[1], tmp;
2193 trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2194 tmp = RB (addr);
2195 SET_PSR_F (tmp & (1 << a));
2196 trace_output_32 (tmp);
2197 }
2198
2199 /* tbitb. */
2200 void
2201 OP_78_8 (void)
2202 {
2203 uint8 a = (OP[0]) & 0xff;
2204 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2205 trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
2206 tmp = RB (addr);
2207 SET_PSR_F (tmp & (1 << a));
2208 trace_output_32 (addr);
2209 }
2210
2211 /* tbitb. */
2212 void
2213 OP_1EA_A (void)
2214 {
2215 uint8 a = (OP[0]) & 0xff;
2216 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2217 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2218 tmp = RB (addr);
2219 SET_PSR_F (tmp & (1 << a));
2220 trace_output_32 (addr);
2221 }
2222
2223 /* tbitb. */
2224 void
2225 OP_10C_14 (void)
2226 {
2227 uint8 a = (OP[0]) & 0xff;
2228 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2229 trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2230 tmp = RB (addr);
2231 SET_PSR_F (tmp & (1 << a));
2232 trace_output_32 (addr);
2233 }
2234
2235 /* tbitb. */
2236 void
2237 OP_F4_9 (void)
2238 {
2239 uint8 a = (OP[0]) & 0xff;
2240 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2241 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2242 tmp = RB (addr);
2243 SET_PSR_F (tmp & (1 << a));
2244 trace_output_32 (addr);
2245 }
2246
2247 /* tbitb. */
2248 void
2249 OP_F6_9 (void)
2250 {
2251 uint8 a = (OP[0]) & 0xff;
2252 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2253 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2254 tmp = RB (addr);
2255 SET_PSR_F (tmp & (1 << a));
2256 trace_output_32 (addr);
2257 }
2258
2259 /* tbitb. */
2260 void
2261 OP_10D_14 (void)
2262 {
2263 uint8 a = (OP[0]) & 0xff;
2264 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2265 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2266 tmp = RB (addr);
2267 SET_PSR_F (tmp & (1 << a));
2268 trace_output_32 (addr);
2269 }
2270
2271 /* tbitb. */
2272 void
2273 OP_10E_14 (void)
2274 {
2275 uint8 a = (OP[0]) & 0xff;
2276 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2277 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2278 tmp = RB (addr);
2279 SET_PSR_F (tmp & (1 << a));
2280 trace_output_32 (addr);
2281 }
2282
2283
2284 /* tbitw. */
2285 void
2286 OP_7F_8 (void)
2287 {
2288 uint16 a = OP[0];
2289 uint32 addr = OP[1], tmp;
2290 trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2291 tmp = RW (addr);
2292 SET_PSR_F (tmp & (1 << a));
2293 trace_output_32 (tmp);
2294 }
2295
2296 /* tbitw. */
2297 void
2298 OP_11F_14 (void)
2299 {
2300 uint16 a = OP[0];
2301 uint32 addr = OP[1], tmp;
2302 trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2303 tmp = RW (addr);
2304 SET_PSR_F (tmp & (1 << a));
2305 trace_output_32 (tmp);
2306 }
2307
2308
2309 /* tbitw. */
2310 void
2311 OP_3E_7 (void)
2312 {
2313 uint32 addr;
2314 uint16 a = (OP[0]), tmp;
2315 trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2316
2317 if (OP[1] == 0)
2318 addr = (GPR32 (12)) + OP[2];
2319 else
2320 addr = (GPR32 (13)) + OP[2];
2321
2322 tmp = RW (addr);
2323 SET_PSR_F (tmp & (1 << a));
2324 trace_output_32 (addr);
2325 }
2326
2327 /* tbitw. */
2328 void
2329 OP_1EB_A (void)
2330 {
2331 uint16 a = (OP[0]);
2332 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2333 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2334 tmp = RW (addr);
2335 SET_PSR_F (tmp & (1 << a));
2336 trace_output_32 (addr);
2337 }
2338
2339 /* tbitw. */
2340 void
2341 OP_11C_14 (void)
2342 {
2343 uint16 a = (OP[0]);
2344 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2345 trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2346 tmp = RW (addr);
2347 SET_PSR_F (tmp & (1 << a));
2348 trace_output_32 (addr);
2349 }
2350
2351 /* tbitw. */
2352 void
2353 OP_7E_8 (void)
2354 {
2355 uint16 a = (OP[0]);
2356 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2357 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2358 tmp = RW (addr);
2359 SET_PSR_F (tmp & (1 << a));
2360 trace_output_32 (addr);
2361 }
2362
2363 /* tbitw. */
2364 void
2365 OP_79_8 (void)
2366 {
2367 uint16 a = (OP[0]);
2368 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2369 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2370 tmp = RW (addr);
2371 SET_PSR_F (tmp & (1 << a));
2372 trace_output_32 (addr);
2373 }
2374
2375 /* tbitw. */
2376 void
2377 OP_11D_14 (void)
2378 {
2379 uint16 a = (OP[0]);
2380 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2381 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2382 tmp = RW (addr);
2383 SET_PSR_F (tmp & (1 << a));
2384 trace_output_32 (addr);
2385 }
2386
2387
2388 /* tbitw. */
2389 void
2390 OP_11E_14 (void)
2391 {
2392 uint16 a = (OP[0]);
2393 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2394 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2395 tmp = RW (addr);
2396 SET_PSR_F (tmp & (1 << a));
2397 trace_output_32 (addr);
2398 }
2399
2400
2401 /* tbit. */
2402 void
2403 OP_6_8 (void)
2404 {
2405 uint16 a = OP[0];
2406 uint16 b = (GPR (OP[1]));
2407 trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
2408 SET_PSR_F (b & (1 << a));
2409 trace_output_16 (b);
2410 }
2411
2412 /* tbit. */
2413 void
2414 OP_7_8 (void)
2415 {
2416 uint16 a = GPR (OP[0]);
2417 uint16 b = (GPR (OP[1]));
2418 trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
2419 SET_PSR_F (b & (1 << a));
2420 trace_output_16 (b);
2421 }
2422
2423
2424 /* cmpb. */
2425 void
2426 OP_50_8 (void)
2427 {
2428 uint8 a = (OP[0]) & 0xFF;
2429 uint8 b = (GPR (OP[1])) & 0xFF;
2430 trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
2431 SET_PSR_Z (a == b);
2432 SET_PSR_N ((int8)a > (int8)b);
2433 SET_PSR_L (a > b);
2434 trace_output_flag ();
2435 }
2436
2437 /* cmpb. */
2438 void
2439 OP_50B_C (void)
2440 {
2441 uint8 a = (OP[0]) & 0xFF;
2442 uint8 b = (GPR (OP[1])) & 0xFF;
2443 trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
2444 SET_PSR_Z (a == b);
2445 SET_PSR_N ((int8)a > (int8)b);
2446 SET_PSR_L (a > b);
2447 trace_output_flag ();
2448 }
2449
2450 /* cmpb. */
2451 void
2452 OP_51_8 (void)
2453 {
2454 uint8 a = (GPR (OP[0])) & 0xFF;
2455 uint8 b = (GPR (OP[1])) & 0xFF;
2456 trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
2457 SET_PSR_Z (a == b);
2458 SET_PSR_N ((int8)a > (int8)b);
2459 SET_PSR_L (a > b);
2460 trace_output_flag ();
2461 }
2462
2463 /* cmpw. */
2464 void
2465 OP_52_8 (void)
2466 {
2467 uint16 a = (OP[0]);
2468 uint16 b = GPR (OP[1]);
2469 trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
2470 SET_PSR_Z (a == b);
2471 SET_PSR_N ((int16)a > (int16)b);
2472 SET_PSR_L (a > b);
2473 trace_output_flag ();
2474 }
2475
2476 /* cmpw. */
2477 void
2478 OP_52B_C (void)
2479 {
2480 uint16 a = (OP[0]);
2481 uint16 b = GPR (OP[1]);
2482 trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
2483 SET_PSR_Z (a == b);
2484 SET_PSR_N ((int16)a > (int16)b);
2485 SET_PSR_L (a > b);
2486 trace_output_flag ();
2487 }
2488
2489 /* cmpw. */
2490 void
2491 OP_53_8 (void)
2492 {
2493 uint16 a = GPR (OP[0]) ;
2494 uint16 b = GPR (OP[1]) ;
2495 trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
2496 SET_PSR_Z (a == b);
2497 SET_PSR_N ((int16)a > (int16)b);
2498 SET_PSR_L (a > b);
2499 trace_output_flag ();
2500 }
2501
2502 /* cmpd. */
2503 void
2504 OP_56_8 (void)
2505 {
2506 uint32 a = (OP[0]);
2507 uint32 b = GPR32 (OP[1]);
2508 trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
2509 SET_PSR_Z (a == b);
2510 SET_PSR_N ((int32)a > (int32)b);
2511 SET_PSR_L (a > b);
2512 trace_output_flag ();
2513 }
2514
2515 /* cmpd. */
2516 void
2517 OP_56B_C (void)
2518 {
2519 uint32 a = (SEXT16(OP[0]));
2520 uint32 b = GPR32 (OP[1]);
2521 trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
2522 SET_PSR_Z (a == b);
2523 SET_PSR_N ((int32)a > (int32)b);
2524 SET_PSR_L (a > b);
2525 trace_output_flag ();
2526 }
2527
2528 /* cmpd. */
2529 void
2530 OP_57_8 (void)
2531 {
2532 uint32 a = GPR32 (OP[0]) ;
2533 uint32 b = GPR32 (OP[1]) ;
2534 trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
2535 SET_PSR_Z (a == b);
2536 SET_PSR_N ((int32)a > (int32)b);
2537 SET_PSR_L (a > b);
2538 trace_output_flag ();
2539 }
2540
2541 /* cmpd. */
2542 void
2543 OP_9_C (void)
2544 {
2545 uint32 a = (OP[0]);
2546 uint32 b = GPR32 (OP[1]);
2547 trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
2548 SET_PSR_Z (a == b);
2549 SET_PSR_N ((int32)a > (int32)b);
2550 SET_PSR_L (a > b);
2551 trace_output_flag ();
2552 }
2553
2554
2555 /* movb. */
2556 void
2557 OP_58_8 (void)
2558 {
2559 uint8 tmp = OP[0] & 0xFF;
2560 uint16 a = (GPR (OP[1])) & 0xFF00;
2561 trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
2562 SET_GPR (OP[1], (a | tmp));
2563 trace_output_16 (tmp);
2564 }
2565
2566 /* movb. */
2567 void
2568 OP_58B_C (void)
2569 {
2570 uint8 tmp = OP[0] & 0xFF;
2571 uint16 a = (GPR (OP[1])) & 0xFF00;
2572 trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
2573 SET_GPR (OP[1], (a | tmp));
2574 trace_output_16 (tmp);
2575 }
2576
2577 /* movb. */
2578 void
2579 OP_59_8 (void)
2580 {
2581 uint8 tmp = (GPR (OP[0])) & 0xFF;
2582 uint16 a = (GPR (OP[1])) & 0xFF00;
2583 trace_input ("movb", OP_REG, OP_REG, OP_VOID);
2584 SET_GPR (OP[1], (a | tmp));
2585 trace_output_16 (tmp);
2586 }
2587
2588 /* movw. */
2589 void
2590 OP_5A_8 (void)
2591 {
2592 uint16 tmp = OP[0];
2593 trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
2594 SET_GPR (OP[1], (tmp & 0xffff));
2595 trace_output_16 (tmp);
2596 }
2597
2598 /* movw. */
2599 void
2600 OP_5AB_C (void)
2601 {
2602 int16 tmp = OP[0];
2603 trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
2604 SET_GPR (OP[1], (tmp & 0xffff));
2605 trace_output_16 (tmp);
2606 }
2607
2608 /* movw. */
2609 void
2610 OP_5B_8 (void)
2611 {
2612 uint16 tmp = GPR (OP[0]);
2613 uint32 a = GPR32 (OP[1]);
2614 trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
2615 a = (a & 0xffff0000) | tmp;
2616 SET_GPR32 (OP[1], a);
2617 trace_output_16 (tmp);
2618 }
2619
2620 /* movxb. */
2621 void
2622 OP_5C_8 (void)
2623 {
2624 uint8 tmp = (GPR (OP[0])) & 0xFF;
2625 trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
2626 SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
2627 trace_output_16 (tmp);
2628 }
2629
2630 /* movzb. */
2631 void
2632 OP_5D_8 (void)
2633 {
2634 uint8 tmp = (GPR (OP[0])) & 0xFF;
2635 trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
2636 SET_GPR (OP[1], tmp);
2637 trace_output_16 (tmp);
2638 }
2639
2640 /* movxw. */
2641 void
2642 OP_5E_8 (void)
2643 {
2644 uint16 tmp = GPR (OP[0]);
2645 trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
2646 SET_GPR32 (OP[1], SEXT16(tmp));
2647 trace_output_16 (tmp);
2648 }
2649
2650 /* movzw. */
2651 void
2652 OP_5F_8 (void)
2653 {
2654 uint16 tmp = GPR (OP[0]);
2655 trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
2656 SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
2657 trace_output_16 (tmp);
2658 }
2659
2660 /* movd. */
2661 void
2662 OP_54_8 (void)
2663 {
2664 int32 tmp = OP[0];
2665 trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
2666 SET_GPR32 (OP[1], tmp);
2667 trace_output_32 (tmp);
2668 }
2669
2670 /* movd. */
2671 void
2672 OP_54B_C (void)
2673 {
2674 int32 tmp = SEXT16(OP[0]);
2675 trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
2676 SET_GPR32 (OP[1], tmp);
2677 trace_output_32 (tmp);
2678 }
2679
2680 /* movd. */
2681 void
2682 OP_55_8 (void)
2683 {
2684 uint32 tmp = GPR32 (OP[0]);
2685 trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
2686 SET_GPR32 (OP[1], tmp);
2687 trace_output_32 (tmp);
2688 }
2689
2690 /* movd. */
2691 void
2692 OP_5_8 (void)
2693 {
2694 uint32 tmp = OP[0];
2695 trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
2696 SET_GPR32 (OP[1], tmp);
2697 trace_output_32 (tmp);
2698 }
2699
2700 /* movd. */
2701 void
2702 OP_7_C (void)
2703 {
2704 int32 tmp = OP[0];
2705 trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
2706 SET_GPR32 (OP[1], tmp);
2707 trace_output_32 (tmp);
2708 }
2709
2710 /* loadm. */
2711 void
2712 OP_14_D (void)
2713 {
2714 uint32 addr = GPR (0);
2715 uint16 count = OP[0], reg = 2, tmp;
2716 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2717 if ((addr & 1))
2718 {
2719 State.exception = SIG_CR16_BUS;
2720 State.pc_changed = 1; /* Don't increment the PC. */
2721 trace_output_void ();
2722 return;
2723 }
2724
2725 while (count)
2726 {
2727 tmp = RW (addr);
2728 SET_GPR (reg, tmp);
2729 addr +=2;
2730 --count;
2731 reg++;
2732 if (reg == 6) reg = 8;
2733 };
2734
2735 SET_GPR (0, addr);
2736 trace_output_void ();
2737 }
2738
2739
2740 /* loadmp. */
2741 void
2742 OP_15_D (void)
2743 {
2744 uint32 addr = GPR32 (0);
2745 uint16 count = OP[0], reg = 2, tmp;
2746 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2747 if ((addr & 1))
2748 {
2749 State.exception = SIG_CR16_BUS;
2750 State.pc_changed = 1; /* Don't increment the PC. */
2751 trace_output_void ();
2752 return;
2753 }
2754
2755 while (count)
2756 {
2757 tmp = RW (addr);
2758 SET_GPR (reg, tmp);
2759 addr +=2;
2760 --count;
2761 reg++;
2762 if (reg == 6) reg = 8;
2763 };
2764
2765 SET_GPR32 (0, addr);
2766 trace_output_void ();
2767 }
2768
2769
2770 /* loadb. */
2771 void
2772 OP_88_8 (void)
2773 {
2774 /* loadb ABS20, REG
2775 * ADDR = zext24(abs20) | remap (ie 0xF00000)
2776 * REG = [ADDR]
2777 * NOTE: remap is
2778 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2779 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2780 * by the core to 16M-64k to 16M. */
2781
2782 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2783 uint32 addr = OP[0];
2784 trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
2785 if (addr > 0xEFFFF) addr |= 0xF00000;
2786 tmp = (RB (addr));
2787 SET_GPR (OP[1], (a | tmp));
2788 trace_output_16 (tmp);
2789 }
2790
2791 /* loadb. */
2792 void
2793 OP_127_14 (void)
2794 {
2795 /* loadb ABS24, REG
2796 * ADDR = abs24
2797 * REGR = [ADDR]. */
2798
2799 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2800 uint32 addr = OP[0];
2801 trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
2802 tmp = (RB (addr));
2803 SET_GPR (OP[1], (a | tmp));
2804 trace_output_16 (tmp);
2805 }
2806
2807 /* loadb. */
2808 void
2809 OP_45_7 (void)
2810 {
2811 /* loadb [Rindex]ABS20 REG
2812 * ADDR = Rindex + zext24(disp20)
2813 * REGR = [ADDR]. */
2814
2815 uint32 addr;
2816 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2817 trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
2818
2819 if (OP[0] == 0)
2820 addr = (GPR32 (12)) + OP[1];
2821 else
2822 addr = (GPR32 (13)) + OP[1];
2823
2824 tmp = (RB (addr));
2825 SET_GPR (OP[2], (a | tmp));
2826 trace_output_16 (tmp);
2827 }
2828
2829
2830 /* loadb. */
2831 void
2832 OP_B_4 (void)
2833 {
2834 /* loadb DIPS4(REGP) REG
2835 * ADDR = RPBASE + zext24(DISP4)
2836 * REG = [ADDR]. */
2837 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2838 uint32 addr = (GPR32 (OP[1])) + OP[0];
2839 trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
2840 tmp = (RB (addr));
2841 SET_GPR (OP[2], (a | tmp));
2842 trace_output_16 (tmp);
2843 }
2844
2845 /* loadb. */
2846 void
2847 OP_BE_8 (void)
2848 {
2849 /* loadb [Rindex]disp0(RPbasex) REG
2850 * ADDR = Rpbasex + Rindex
2851 * REGR = [ADDR] */
2852
2853 uint32 addr;
2854 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2855 trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
2856
2857 addr = (GPR32 (OP[2])) + OP[1];
2858
2859 if (OP[0] == 0)
2860 addr = (GPR32 (12)) + addr;
2861 else
2862 addr = (GPR32 (13)) + addr;
2863
2864 tmp = (RB (addr));
2865 SET_GPR (OP[3], (a | tmp));
2866 trace_output_16 (tmp);
2867 }
2868
2869 /* loadb. */
2870 void
2871 OP_219_A (void)
2872 {
2873 /* loadb [Rindex]disp14(RPbasex) REG
2874 * ADDR = Rpbasex + Rindex + zext24(disp14)
2875 * REGR = [ADDR] */
2876
2877 uint32 addr;
2878 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2879
2880 addr = (GPR32 (OP[2])) + OP[1];
2881
2882 if (OP[0] == 0)
2883 addr = (GPR32 (12)) + addr;
2884 else
2885 addr = (GPR32 (13)) + addr;
2886
2887 trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
2888 tmp = (RB (addr));
2889 SET_GPR (OP[3], (a | tmp));
2890 trace_output_16 (tmp);
2891 }
2892
2893
2894 /* loadb. */
2895 void
2896 OP_184_14 (void)
2897 {
2898 /* loadb DISPE20(REG) REG
2899 * zext24(Rbase) + zext24(dispe20)
2900 * REG = [ADDR] */
2901
2902 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2903 uint32 addr = OP[0] + (GPR (OP[1]));
2904 trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
2905 tmp = (RB (addr));
2906 SET_GPR (OP[2], (a | tmp));
2907 trace_output_16 (tmp);
2908 }
2909
2910 /* loadb. */
2911 void
2912 OP_124_14 (void)
2913 {
2914 /* loadb DISP20(REG) REG
2915 * ADDR = zext24(Rbase) + zext24(disp20)
2916 * REG = [ADDR] */
2917
2918 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2919 uint32 addr = OP[0] + (GPR (OP[1]));
2920 trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
2921 tmp = (RB (addr));
2922 SET_GPR (OP[2], (a | tmp));
2923 trace_output_16 (tmp);
2924 }
2925
2926 /* loadb. */
2927 void
2928 OP_BF_8 (void)
2929 {
2930 /* loadb disp16(REGP) REG
2931 * ADDR = RPbase + zext24(disp16)
2932 * REGR = [ADDR] */
2933
2934 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2935 uint32 addr = (GPR32 (OP[1])) + OP[0];
2936 trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
2937 tmp = (RB (addr));
2938 SET_GPR (OP[2], (a | tmp));
2939 trace_output_16 (tmp);
2940 }
2941
2942 /* loadb. */
2943 void
2944 OP_125_14 (void)
2945 {
2946 /* loadb disp20(REGP) REG
2947 * ADDR = RPbase + zext24(disp20)
2948 * REGR = [ADDR] */
2949 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2950 uint32 addr = (GPR32 (OP[1])) + OP[0];
2951 trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
2952 tmp = (RB (addr));
2953 SET_GPR (OP[2], (a | tmp));
2954 trace_output_16 (tmp);
2955 }
2956
2957
2958 /* loadb. */
2959 void
2960 OP_185_14 (void)
2961 {
2962 /* loadb -disp20(REGP) REG
2963 * ADDR = RPbase + zext24(-disp20)
2964 * REGR = [ADDR] */
2965 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2966 uint32 addr = (GPR32 (OP[1])) + OP[1];
2967 trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
2968 tmp = (RB (addr));
2969 SET_GPR (OP[2], (a | tmp));
2970 trace_output_16 (tmp);
2971 }
2972
2973 /* loadb. */
2974 void
2975 OP_126_14 (void)
2976 {
2977 /* loadb [Rindex]disp20(RPbasexb) REG
2978 * ADDR = RPbasex + Rindex + zext24(disp20)
2979 * REGR = [ADDR] */
2980
2981 uint32 addr;
2982 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2983 trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
2984
2985 addr = (GPR32 (OP[2])) + OP[1];
2986
2987 if (OP[0] == 0)
2988 addr = (GPR32 (12)) + addr;
2989 else
2990 addr = (GPR32 (13)) + addr;
2991
2992 tmp = (RB (addr));
2993 SET_GPR (OP[3], (a | tmp));
2994 trace_output_16 (tmp);
2995 }
2996
2997
2998 /* loadw. */
2999 void
3000 OP_89_8 (void)
3001 {
3002 /* loadw ABS20, REG
3003 * ADDR = zext24(abs20) | remap
3004 * REGR = [ADDR]
3005 * NOTE: remap is
3006 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3007 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3008 * by the core to 16M-64k to 16M. */
3009
3010 uint16 tmp;
3011 uint32 addr = OP[0];
3012 trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
3013 if (addr > 0xEFFFF) addr |= 0xF00000;
3014 tmp = (RW (addr));
3015 SET_GPR (OP[1], tmp);
3016 trace_output_16 (tmp);
3017 }
3018
3019
3020 /* loadw. */
3021 void
3022 OP_12F_14 (void)
3023 {
3024 /* loadw ABS24, REG
3025 * ADDR = abs24
3026 * REGR = [ADDR] */
3027 uint16 tmp;
3028 uint32 addr = OP[0];
3029 trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
3030 tmp = (RW (addr));
3031 SET_GPR (OP[1], tmp);
3032 trace_output_16 (tmp);
3033 }
3034
3035 /* loadw. */
3036 void
3037 OP_47_7 (void)
3038 {
3039 /* loadw [Rindex]ABS20 REG
3040 * ADDR = Rindex + zext24(disp20)
3041 * REGR = [ADDR] */
3042
3043 uint32 addr;
3044 uint16 tmp;
3045 trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
3046
3047 if (OP[0] == 0)
3048 addr = (GPR32 (12)) + OP[1];
3049 else
3050 addr = (GPR32 (13)) + OP[1];
3051
3052 tmp = (RW (addr));
3053 SET_GPR (OP[2], tmp);
3054 trace_output_16 (tmp);
3055 }
3056
3057
3058 /* loadw. */
3059 void
3060 OP_9_4 (void)
3061 {
3062 /* loadw DIPS4(REGP) REGP
3063 * ADDR = RPBASE + zext24(DISP4)
3064 * REGP = [ADDR]. */
3065 uint16 tmp;
3066 uint32 addr, a;
3067 trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
3068 addr = (GPR32 (OP[1])) + OP[0];
3069 tmp = (RW (addr));
3070 if (OP[2] > 11)
3071 {
3072 a = (GPR32 (OP[2])) & 0xffff0000;
3073 SET_GPR32 (OP[2], (a | tmp));
3074 }
3075 else
3076 SET_GPR (OP[2], tmp);
3077
3078 trace_output_16 (tmp);
3079 }
3080
3081
3082 /* loadw. */
3083 void
3084 OP_9E_8 (void)
3085 {
3086 /* loadw [Rindex]disp0(RPbasex) REG
3087 * ADDR = Rpbasex + Rindex
3088 * REGR = [ADDR] */
3089
3090 uint32 addr;
3091 uint16 tmp;
3092 trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
3093
3094 addr = (GPR32 (OP[2])) + OP[1];
3095
3096 if (OP[0] == 0)
3097 addr = (GPR32 (12)) + addr;
3098 else
3099 addr = (GPR32 (13)) + addr;
3100
3101 tmp = RW (addr);
3102 SET_GPR (OP[3], tmp);
3103 trace_output_16 (tmp);
3104 }
3105
3106
3107 /* loadw. */
3108 void
3109 OP_21B_A (void)
3110 {
3111 /* loadw [Rindex]disp14(RPbasex) REG
3112 * ADDR = Rpbasex + Rindex + zext24(disp14)
3113 * REGR = [ADDR] */
3114
3115 uint32 addr;
3116 uint16 tmp;
3117 trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
3118 addr = (GPR32 (OP[2])) + OP[1];
3119
3120 if (OP[0] == 0)
3121 addr = (GPR32 (12)) + addr;
3122 else
3123 addr = (GPR32 (13)) + addr;
3124
3125 tmp = (RW (addr));
3126 SET_GPR (OP[3], tmp);
3127 trace_output_16 (tmp);
3128 }
3129
3130 /* loadw. */
3131 void
3132 OP_18C_14 (void)
3133 {
3134 /* loadw dispe20(REG) REGP
3135 * REGP = [DISPE20+[REG]] */
3136
3137 uint16 tmp;
3138 uint32 addr, a;
3139 trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3140 addr = OP[0] + (GPR (OP[1]));
3141 tmp = (RW (addr));
3142 if (OP[2] > 11)
3143 {
3144 a = (GPR32 (OP[2])) & 0xffff0000;
3145 SET_GPR32 (OP[2], (a | tmp));
3146 }
3147 else
3148 SET_GPR (OP[2], tmp);
3149
3150 trace_output_16 (tmp);
3151 }
3152
3153
3154 /* loadw. */
3155 void
3156 OP_12C_14 (void)
3157 {
3158 /* loadw DISP20(REG) REGP
3159 * ADDR = zext24(Rbase) + zext24(disp20)
3160 * REGP = [ADDR] */
3161
3162 uint16 tmp;
3163 uint32 addr, a;
3164 trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3165 addr = OP[0] + (GPR (OP[1]));
3166 tmp = (RW (addr));
3167 if (OP[2] > 11)
3168 {
3169 a = (GPR32 (OP[2])) & 0xffff0000;
3170 SET_GPR32 (OP[2], (a | tmp));
3171 }
3172 else
3173 SET_GPR (OP[2], tmp);
3174
3175 trace_output_16 (tmp);
3176 }
3177
3178 /* loadw. */
3179 void
3180 OP_9F_8 (void)
3181 {
3182 /* loadw disp16(REGP) REGP
3183 * ADDR = RPbase + zext24(disp16)
3184 * REGP = [ADDR] */
3185 uint16 tmp;
3186 uint32 addr, a;
3187 trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3188 addr = (GPR32 (OP[1])) + OP[0];
3189 tmp = (RW (addr));
3190 if (OP[2] > 11)
3191 {
3192 a = (GPR32 (OP[2])) & 0xffff0000;
3193 SET_GPR32 (OP[2], (a | tmp));
3194 }
3195 else
3196 SET_GPR (OP[2], tmp);
3197
3198 trace_output_16 (tmp);
3199 }
3200
3201 /* loadw. */
3202 void
3203 OP_12D_14 (void)
3204 {
3205 /* loadw disp20(REGP) REGP
3206 * ADDR = RPbase + zext24(disp20)
3207 * REGP = [ADDR] */
3208 uint16 tmp;
3209 uint32 addr, a;
3210 trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
3211 addr = (GPR32 (OP[1])) + OP[0];
3212 tmp = (RW (addr));
3213 if (OP[2] > 11)
3214 {
3215 a = (GPR32 (OP[2])) & 0xffff0000;
3216 SET_GPR32 (OP[2], (a | tmp));
3217 }
3218 else
3219 SET_GPR (OP[2], tmp);
3220
3221 trace_output_16 (tmp);
3222 }
3223
3224 /* loadw. */
3225 void
3226 OP_18D_14 (void)
3227 {
3228 /* loadw -disp20(REGP) REG
3229 * ADDR = RPbase + zext24(-disp20)
3230 * REGR = [ADDR] */
3231
3232 uint16 tmp;
3233 uint32 addr, a;
3234 trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
3235 addr = (GPR32 (OP[1])) + OP[0];
3236 tmp = (RB (addr));
3237 if (OP[2] > 11)
3238 {
3239 a = (GPR32 (OP[2])) & 0xffff0000;
3240 SET_GPR32 (OP[2], (a | tmp));
3241 }
3242 else
3243 SET_GPR (OP[2], tmp);
3244
3245 trace_output_16 (tmp);
3246 }
3247
3248
3249 /* loadw. */
3250 void
3251 OP_12E_14 (void)
3252 {
3253 /* loadw [Rindex]disp20(RPbasexb) REG
3254 * ADDR = RPbasex + Rindex + zext24(disp20)
3255 * REGR = [ADDR] */
3256
3257 uint32 addr;
3258 uint16 tmp;
3259 trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
3260
3261 if (OP[0] == 0)
3262 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3263 else
3264 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3265
3266 tmp = (RW (addr));
3267 SET_GPR (OP[3], tmp);
3268 trace_output_16 (tmp);
3269 }
3270
3271
3272 /* loadd. */
3273 void
3274 OP_87_8 (void)
3275 {
3276 /* loadd ABS20, REGP
3277 * ADDR = zext24(abs20) | remap
3278 * REGP = [ADDR]
3279 * NOTE: remap is
3280 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3281 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3282 * by the core to 16M-64k to 16M. */
3283
3284 uint32 addr, tmp;
3285 addr = OP[0];
3286 trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
3287 if (addr > 0xEFFFF) addr |= 0xF00000;
3288 tmp = RLW (addr);
3289 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3290 SET_GPR32 (OP[1], tmp);
3291 trace_output_32 (tmp);
3292 }
3293
3294 /* loadd. */
3295 void
3296 OP_12B_14 (void)
3297 {
3298 /* loadd ABS24, REGP
3299 * ADDR = abs24
3300 * REGP = [ADDR] */
3301
3302 uint32 addr = OP[0];
3303 uint32 tmp;
3304 trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
3305 tmp = RLW (addr);
3306 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3307 SET_GPR32 (OP[1],tmp);
3308 trace_output_32 (tmp);
3309 }
3310
3311
3312 /* loadd. */
3313 void
3314 OP_46_7 (void)
3315 {
3316 /* loadd [Rindex]ABS20 REGP
3317 * ADDR = Rindex + zext24(disp20)
3318 * REGP = [ADDR] */
3319
3320 uint32 addr, tmp;
3321 trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
3322
3323 if (OP[0] == 0)
3324 addr = (GPR32 (12)) + OP[1];
3325 else
3326 addr = (GPR32 (13)) + OP[1];
3327
3328 tmp = RLW (addr);
3329 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3330 SET_GPR32 (OP[2], tmp);
3331 trace_output_32 (tmp);
3332 }
3333
3334
3335 /* loadd. */
3336 void
3337 OP_A_4 (void)
3338 {
3339 /* loadd dips4(regp) REGP
3340 * ADDR = Rpbase + zext24(disp4)
3341 * REGP = [ADDR] */
3342
3343 uint32 tmp, addr = (GPR32 (OP[1])) + OP[0];
3344 trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
3345 tmp = RLW (addr);
3346 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3347 SET_GPR32 (OP[2], tmp);
3348 trace_output_32 (tmp);
3349 }
3350
3351
3352 /* loadd. */
3353 void
3354 OP_AE_8 (void)
3355 {
3356 /* loadd [Rindex]disp0(RPbasex) REGP
3357 * ADDR = Rpbasex + Rindex
3358 * REGP = [ADDR] */
3359
3360 uint32 addr, tmp;
3361 trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
3362
3363 if (OP[0] == 0)
3364 addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1];
3365 else
3366 addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1];
3367
3368 tmp = RLW (addr);
3369 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3370 SET_GPR32 (OP[3], tmp);
3371 trace_output_32 (tmp);
3372 }
3373
3374
3375 /* loadd. */
3376 void
3377 OP_21A_A (void)
3378 {
3379 /* loadd [Rindex]disp14(RPbasex) REGP
3380 * ADDR = Rpbasex + Rindex + zext24(disp14)
3381 * REGR = [ADDR] */
3382
3383 uint32 addr, tmp;
3384 trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
3385
3386 if (OP[0] == 0)
3387 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3388 else
3389 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3390
3391 tmp = RLW (addr);
3392 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3393 SET_GPR (OP[3],tmp);
3394 trace_output_32 (tmp);
3395 }
3396
3397
3398 /* loadd. */
3399 void
3400 OP_188_14 (void)
3401 {
3402 /* loadd dispe20(REG) REG
3403 * zext24(Rbase) + zext24(dispe20)
3404 * REG = [ADDR] */
3405
3406 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3407 trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3408 tmp = RLW (addr);
3409 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3410 SET_GPR32 (OP[2], tmp);
3411 trace_output_32 (tmp);
3412 }
3413
3414
3415 /* loadd. */
3416 void
3417 OP_128_14 (void)
3418 {
3419 /* loadd DISP20(REG) REG
3420 * ADDR = zext24(Rbase) + zext24(disp20)
3421 * REG = [ADDR] */
3422
3423 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3424 trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3425 tmp = RLW (addr);
3426 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3427 SET_GPR32 (OP[2], tmp);
3428 trace_output_32 (tmp);
3429 }
3430
3431 /* loadd. */
3432 void
3433 OP_AF_8 (void)
3434 {
3435 /* loadd disp16(REGP) REGP
3436 * ADDR = RPbase + zext24(disp16)
3437 * REGR = [ADDR] */
3438 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3439 trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3440 tmp = RLW (addr);
3441 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3442 SET_GPR32 (OP[2], tmp);
3443 trace_output_32 (tmp);
3444 }
3445
3446
3447 /* loadd. */
3448 void
3449 OP_129_14 (void)
3450 {
3451 /* loadd disp20(REGP) REGP
3452 * ADDR = RPbase + zext24(disp20)
3453 * REGP = [ADDR] */
3454 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3455 trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
3456 tmp = RLW (addr);
3457 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3458 SET_GPR32 (OP[2], tmp);
3459 trace_output_32 (tmp);
3460 }
3461
3462 /* loadd. */
3463 void
3464 OP_189_14 (void)
3465 {
3466 /* loadd -disp20(REGP) REGP
3467 * ADDR = RPbase + zext24(-disp20)
3468 * REGP = [ADDR] */
3469
3470 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3471 trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
3472 tmp = RLW (addr);
3473 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3474 SET_GPR32 (OP[2], tmp);
3475 trace_output_32 (tmp);
3476 }
3477
3478 /* loadd. */
3479 void
3480 OP_12A_14 (void)
3481 {
3482 /* loadd [Rindex]disp20(RPbasexb) REGP
3483 * ADDR = RPbasex + Rindex + zext24(disp20)
3484 * REGP = [ADDR] */
3485
3486 uint32 addr, tmp;
3487 trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
3488
3489 if (OP[0] == 0)
3490 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3491 else
3492 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3493
3494 tmp = RLW (addr);
3495 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3496 SET_GPR32 (OP[3], tmp);
3497 trace_output_32 (tmp);
3498 }
3499
3500
3501 /* storb. */
3502 void
3503 OP_C8_8 (void)
3504 {
3505 /* storb REG, ABS20
3506 * ADDR = zext24(abs20) | remap
3507 * [ADDR] = REGR
3508 * NOTE: remap is
3509 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3510 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3511 * by the core to 16M-64k to 16M. */
3512
3513 uint8 a = ((GPR (OP[0])) & 0xff);
3514 uint32 addr = OP[1];
3515 trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3516 SB (addr, a);
3517 trace_output_32 (addr);
3518 }
3519
3520 /* storb. */
3521 void
3522 OP_137_14 (void)
3523 {
3524 /* storb REG, ABS24
3525 * ADDR = abs24
3526 * [ADDR] = REGR. */
3527
3528 uint8 a = ((GPR (OP[0])) & 0xff);
3529 uint32 addr = OP[1];
3530 trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3531 SB (addr, a);
3532 trace_output_32 (addr);
3533 }
3534
3535 /* storb. */
3536 void
3537 OP_65_7 (void)
3538 {
3539 /* storb REG, [Rindex]ABS20
3540 * ADDR = Rindex + zext24(disp20)
3541 * [ADDR] = REGR */
3542
3543 uint32 addr;
3544 uint8 a = ((GPR (OP[0])) & 0xff);
3545 trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3546
3547 if (OP[1] == 0)
3548 addr = (GPR32 (12)) + OP[2];
3549 else
3550 addr = (GPR32 (13)) + OP[2];
3551
3552 SB (addr, a);
3553 trace_output_32 (addr);
3554 }
3555
3556 /* storb. */
3557 void
3558 OP_F_4 (void)
3559 {
3560 /* storb REG, DIPS4(REGP)
3561 * ADDR = RPBASE + zext24(DISP4)
3562 * [ADDR] = REG. */
3563
3564 uint16 a = ((GPR (OP[0])) & 0xff);
3565 uint32 addr = (GPR32 (OP[2])) + OP[1];
3566 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
3567 SB (addr, a);
3568 trace_output_32 (addr);
3569 }
3570
3571 /* storb. */
3572 void
3573 OP_FE_8 (void)
3574 {
3575 /* storb [Rindex]disp0(RPbasex) REG
3576 * ADDR = Rpbasex + Rindex
3577 * [ADDR] = REGR */
3578
3579 uint32 addr;
3580 uint8 a = ((GPR (OP[0])) & 0xff);
3581 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3582
3583 if (OP[1] == 0)
3584 addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2];
3585 else
3586 addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2];
3587
3588 SB (addr, a);
3589 trace_output_32 (addr);
3590 }
3591
3592 /* storb. */
3593 void
3594 OP_319_A (void)
3595 {
3596 /* storb REG, [Rindex]disp14(RPbasex)
3597 * ADDR = Rpbasex + Rindex + zext24(disp14)
3598 * [ADDR] = REGR */
3599
3600 uint8 a = ((GPR (OP[0])) & 0xff);
3601 uint32 addr = (GPR32 (OP[2])) + OP[1];
3602 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3603 SB (addr, a);
3604 trace_output_32 (addr);
3605 }
3606
3607 /* storb. */
3608 void
3609 OP_194_14 (void)
3610 {
3611 /* storb REG, DISPE20(REG)
3612 * zext24(Rbase) + zext24(dispe20)
3613 * [ADDR] = REG */
3614
3615 uint8 a = ((GPR (OP[0])) & 0xff);
3616 uint32 addr = OP[1] + (GPR (OP[2]));
3617 trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
3618 SB (addr, a);
3619 trace_output_32 (addr);
3620 }
3621
3622 /* storb. */
3623 void
3624 OP_134_14 (void)
3625 {
3626 /* storb REG, DISP20(REG)
3627 * ADDR = zext24(Rbase) + zext24(disp20)
3628 * [ADDR] = REG */
3629
3630 uint8 a = (GPR (OP[0]) & 0xff);
3631 uint32 addr = OP[1] + (GPR (OP[2]));
3632 trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3633 SB (addr, a);
3634 trace_output_32 (addr);
3635 }
3636
3637 /* storb. */
3638 void
3639 OP_FF_8 (void)
3640 {
3641 /* storb REG, disp16(REGP)
3642 * ADDR = RPbase + zext24(disp16)
3643 * [ADDR] = REGP */
3644
3645 uint8 a = ((GPR (OP[0])) & 0xff);
3646 uint32 addr = (GPR32 (OP[2])) + OP[1];
3647 trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3648 SB (addr, a);
3649 trace_output_32 (addr);
3650 }
3651
3652 /* storb. */
3653 void
3654 OP_135_14 (void)
3655 {
3656 /* storb REG, disp20(REGP)
3657 * ADDR = RPbase + zext24(disp20)
3658 * [ADDR] = REGP */
3659
3660 uint8 a = ((GPR (OP[0])) & 0xff);
3661 uint32 addr = (GPR32 (OP[2])) + OP[1];
3662 trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3663 SB (addr, a);
3664 trace_output_32 (addr);
3665 }
3666
3667 /* storb. */
3668 void
3669 OP_195_14 (void)
3670 {
3671 /* storb REG, -disp20(REGP)
3672 * ADDR = RPbase + zext24(-disp20)
3673 * [ADDR] = REGP */
3674
3675 uint8 a = (GPR (OP[0]) & 0xff);
3676 uint32 addr = (GPR32 (OP[2])) + OP[1];
3677 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3678 SB (addr, a);
3679 trace_output_32 (addr);
3680 }
3681
3682 /* storb. */
3683 void
3684 OP_136_14 (void)
3685 {
3686 /* storb REG, [Rindex]disp20(RPbase)
3687 * ADDR = RPbasex + Rindex + zext24(disp20)
3688 * [ADDR] = REGP */
3689
3690 uint8 a = (GPR (OP[0])) & 0xff;
3691 uint32 addr = (GPR32 (OP[2])) + OP[1];
3692 trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3693 SB (addr, a);
3694 trace_output_32 (addr);
3695 }
3696
3697 /* STR_IMM instructions. */
3698 /* storb . */
3699 void
3700 OP_81_8 (void)
3701 {
3702 uint8 a = (OP[0]) & 0xff;
3703 uint32 addr = OP[1];
3704 trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3705 SB (addr, a);
3706 trace_output_32 (addr);
3707 }
3708
3709 /* storb. */
3710 void
3711 OP_123_14 (void)
3712 {
3713 uint8 a = (OP[0]) & 0xff;
3714 uint32 addr = OP[1];
3715 trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3716 SB (addr, a);
3717 trace_output_32 (addr);
3718 }
3719
3720 /* storb. */
3721 void
3722 OP_42_7 (void)
3723 {
3724 uint32 addr;
3725 uint8 a = (OP[0]) & 0xff;
3726 trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3727
3728 if (OP[1] == 0)
3729 addr = (GPR32 (12)) + OP[2];
3730 else
3731 addr = (GPR32 (13)) + OP[2];
3732
3733 SB (addr, a);
3734 trace_output_32 (addr);
3735 }
3736
3737 /* storb. */
3738 void
3739 OP_218_A (void)
3740 {
3741 uint8 a = (OP[0]) & 0xff;
3742 uint32 addr = (GPR32 (OP[2])) + OP[1];
3743 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3744 SB (addr, a);
3745 trace_output_32 (addr);
3746 }
3747
3748 /* storb. */
3749 void
3750 OP_82_8 (void)
3751 {
3752 uint8 a = (OP[0]) & 0xff;
3753 uint32 addr = (GPR32 (OP[2])) + OP[1];
3754 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
3755 SB (addr, a);
3756 trace_output_32 (addr);
3757 }
3758
3759 /* storb. */
3760 void
3761 OP_120_14 (void)
3762 {
3763 uint8 a = (OP[0]) & 0xff;
3764 uint32 addr = (GPR (OP[2])) + OP[1];
3765 trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
3766 SB (addr, a);
3767 trace_output_32 (addr);
3768 }
3769
3770 /* storb. */
3771 void
3772 OP_83_8 (void)
3773 {
3774 uint8 a = (OP[0]) & 0xff;
3775 uint32 addr = (GPR32 (OP[2])) + OP[1];
3776 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
3777 SB (addr, a);
3778 trace_output_32 (addr);
3779 }
3780
3781 /* storb. */
3782 void
3783 OP_121_14 (void)
3784 {
3785 uint8 a = (OP[0]) & 0xff;
3786 uint32 addr = (GPR32 (OP[2])) + OP[1];
3787 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
3788 SB (addr, a);
3789 trace_output_32 (addr);
3790 }
3791
3792 /* storb. */
3793 void
3794 OP_122_14 (void)
3795 {
3796 uint8 a = (OP[0]) & 0xff;
3797 uint32 addr = (GPR32 (OP[2])) + OP[1];
3798 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
3799 SB (addr, a);
3800 trace_output_32 (addr);
3801 }
3802 /* endif for STR_IMM. */
3803
3804 /* storw . */
3805 void
3806 OP_C9_8 (void)
3807 {
3808 uint16 a = GPR (OP[0]);
3809 uint32 addr = OP[1];
3810 trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3811 SW (addr, a);
3812 trace_output_32 (addr);
3813 }
3814
3815 /* storw. */
3816 void
3817 OP_13F_14 (void)
3818 {
3819 uint16 a = GPR (OP[0]);
3820 uint32 addr = OP[1];
3821 trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3822 SW (addr, a);
3823 trace_output_32 (addr);
3824 }
3825
3826 /* storw. */
3827 void
3828 OP_67_7 (void)
3829 {
3830 uint32 addr;
3831 uint16 a = GPR (OP[0]);
3832 trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3833
3834 if (OP[1] == 0)
3835 addr = (GPR32 (12)) + OP[2];
3836 else
3837 addr = (GPR32 (13)) + OP[2];
3838
3839 SW (addr, a);
3840 trace_output_32 (addr);
3841 }
3842
3843
3844 /* storw. */
3845 void
3846 OP_D_4 (void)
3847 {
3848 uint16 a = (GPR (OP[0]));
3849 uint32 addr = (GPR32 (OP[2])) + OP[1];
3850 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
3851 SW (addr, a);
3852 trace_output_32 (addr);
3853 }
3854
3855 /* storw. */
3856 void
3857 OP_DE_8 (void)
3858 {
3859 uint16 a = GPR (OP[0]);
3860 uint32 addr = (GPR32 (OP[2])) + OP[1];
3861 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3862 SW (addr, a);
3863 trace_output_32 (addr);
3864 }
3865
3866 /* storw. */
3867 void
3868 OP_31B_A (void)
3869 {
3870 uint16 a = GPR (OP[0]);
3871 uint32 addr = (GPR32 (OP[2])) + OP[1];
3872 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3873 SW (addr, a);
3874 trace_output_32 (addr);
3875 }
3876
3877 /* storw. */
3878 void
3879 OP_19C_14 (void)
3880 {
3881 uint16 a = (GPR (OP[0]));
3882 uint32 addr = (GPR32 (OP[2])) + OP[1];
3883 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
3884 SW (addr, a);
3885 trace_output_32 (addr);
3886 }
3887
3888 /* storw. */
3889 void
3890 OP_13C_14 (void)
3891 {
3892 uint16 a = (GPR (OP[0]));
3893 uint32 addr = (GPR (OP[2])) + OP[1];
3894 trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3895 SW (addr, a);
3896 trace_output_32 (addr);
3897 }
3898
3899 /* storw. */
3900 void
3901 OP_DF_8 (void)
3902 {
3903 uint16 a = (GPR (OP[0]));
3904 uint32 addr = (GPR32 (OP[2])) + OP[1];
3905 trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3906 SW (addr, a);
3907 trace_output_32 (addr);
3908 }
3909
3910 /* storw. */
3911 void
3912 OP_13D_14 (void)
3913 {
3914 uint16 a = (GPR (OP[0]));
3915 uint32 addr = (GPR32 (OP[2])) + OP[1];
3916 trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3917 SW (addr, a);
3918 trace_output_32 (addr);
3919 }
3920
3921 /* storw. */
3922 void
3923 OP_19D_14 (void)
3924 {
3925 uint16 a = (GPR (OP[0]));
3926 uint32 addr = (GPR32 (OP[2])) + OP[1];
3927 trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3928 SW (addr, a);
3929 trace_output_32 (addr);
3930 }
3931
3932 /* storw. */
3933 void
3934 OP_13E_14 (void)
3935 {
3936 uint16 a = (GPR (OP[0]));
3937 uint32 addr = (GPR32 (OP[2])) + OP[1];
3938 trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3939 SW (addr, a);
3940 trace_output_32 (addr);
3941 }
3942
3943 /* STORE-w IMM instruction *****/
3944 /* storw . */
3945 void
3946 OP_C1_8 (void)
3947 {
3948 uint16 a = OP[0];
3949 uint32 addr = OP[1];
3950 trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3951 SW (addr, a);
3952 trace_output_32 (addr);
3953 }
3954
3955 /* storw. */
3956 void
3957 OP_133_14 (void)
3958 {
3959 uint16 a = OP[0];
3960 uint32 addr = OP[1];
3961 trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3962 SW (addr, a);
3963 trace_output_32 (addr);
3964 }
3965
3966 /* storw. */
3967 void
3968 OP_62_7 (void)
3969 {
3970 uint32 addr;
3971 uint16 a = OP[0];
3972 trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3973
3974 if (OP[1] == 0)
3975 addr = (GPR32 (12)) + OP[2];
3976 else
3977 addr = (GPR32 (13)) + OP[2];
3978
3979 SW (addr, a);
3980 trace_output_32 (addr);
3981 }
3982
3983 /* storw. */
3984 void
3985 OP_318_A (void)
3986 {
3987 uint16 a = OP[0];
3988 uint32 addr = (GPR32 (OP[2])) + OP[1];
3989 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3990 SW (addr, a);
3991 trace_output_32 (addr);
3992 }
3993
3994 /* storw. */
3995 void
3996 OP_C2_8 (void)
3997 {
3998 uint16 a = OP[0];
3999 uint32 addr = (GPR32 (OP[2])) + OP[1];
4000 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
4001 SW (addr, a);
4002 trace_output_32 (addr);
4003 }
4004
4005 /* storw. */
4006 void
4007 OP_130_14 (void)
4008 {
4009 uint16 a = OP[0];
4010 uint32 addr = (GPR32 (OP[2])) + OP[1];
4011 trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
4012 SW (addr, a);
4013 trace_output_32 (addr);
4014 }
4015
4016 /* storw. */
4017 void
4018 OP_C3_8 (void)
4019 {
4020 uint16 a = OP[0];
4021 uint32 addr = (GPR32 (OP[2])) + OP[1];
4022 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
4023 SW (addr, a);
4024 trace_output_32 (addr);
4025 }
4026
4027
4028 /* storw. */
4029 void
4030 OP_131_14 (void)
4031 {
4032 uint16 a = OP[0];
4033 uint32 addr = (GPR32 (OP[2])) + OP[1];
4034 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
4035 SW (addr, a);
4036 trace_output_32 (addr);
4037 }
4038
4039 /* storw. */
4040 void
4041 OP_132_14 (void)
4042 {
4043 uint16 a = OP[0];
4044 uint32 addr = (GPR32 (OP[2])) + OP[1];
4045 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
4046 SW (addr, a);
4047 trace_output_32 (addr);
4048 }
4049
4050
4051 /* stord. */
4052 void
4053 OP_C7_8 (void)
4054 {
4055 uint32 a = GPR32 (OP[0]);
4056 uint32 addr = OP[1];
4057 trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
4058 SLW (addr, a);
4059 trace_output_32 (addr);
4060 }
4061
4062 /* stord. */
4063 void
4064 OP_13B_14 (void)
4065 {
4066 uint32 a = GPR32 (OP[0]);
4067 uint32 addr = OP[1];
4068 trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
4069 SLW (addr, a);
4070 trace_output_32 (addr);
4071 }
4072
4073 /* stord. */
4074 void
4075 OP_66_7 (void)
4076 {
4077 uint32 addr, a = GPR32 (OP[0]);
4078 trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
4079
4080 if (OP[1] == 0)
4081 addr = (GPR32 (12)) + OP[2];
4082 else
4083 addr = (GPR32 (13)) + OP[2];
4084
4085 SLW (addr, a);
4086 trace_output_32 (addr);
4087 }
4088
4089 /* stord. */
4090 void
4091 OP_E_4 (void)
4092 {
4093 uint32 a = GPR32 (OP[0]);
4094 uint32 addr = (GPR32 (OP[2])) + OP[1];
4095 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
4096 SLW (addr, a);
4097 trace_output_32 (addr);
4098 }
4099
4100 /* stord. */
4101 void
4102 OP_EE_8 (void)
4103 {
4104 uint32 a = GPR32 (OP[0]);
4105 uint32 addr = (GPR32 (OP[2])) + OP[1];
4106 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
4107 SLW (addr, a);
4108 trace_output_32 (addr);
4109 }
4110
4111 /* stord. */
4112 void
4113 OP_31A_A (void)
4114 {
4115 uint32 a = GPR32 (OP[0]);
4116 uint32 addr = (GPR32 (OP[2])) + OP[1];
4117 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
4118 SLW (addr, a);
4119 trace_output_32 (addr);
4120 }
4121
4122 /* stord. */
4123 void
4124 OP_198_14 (void)
4125 {
4126 uint32 a = GPR32 (OP[0]);
4127 uint32 addr = (GPR32 (OP[2])) + OP[1];
4128 trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
4129 SLW (addr, a);
4130 trace_output_32 (addr);
4131 }
4132
4133 /* stord. */
4134 void
4135 OP_138_14 (void)
4136 {
4137 uint32 a = GPR32 (OP[0]);
4138 uint32 addr = (GPR32 (OP[2])) + OP[1];
4139 trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
4140 SLW (addr, a);
4141 trace_output_32 (addr);
4142 }
4143
4144 /* stord. */
4145 void
4146 OP_EF_8 (void)
4147 {
4148 uint32 a = GPR32 (OP[0]);
4149 uint32 addr = (GPR32 (OP[2])) + OP[1];
4150 trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
4151 SLW (addr, a);
4152 trace_output_32 (addr);
4153 }
4154
4155 /* stord. */
4156 void
4157 OP_139_14 (void)
4158 {
4159 uint32 a = GPR32 (OP[0]);
4160 uint32 addr = (GPR32 (OP[2])) + OP[1];
4161 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
4162 SLW (addr, a);
4163 trace_output_32 (addr);
4164 }
4165
4166 /* stord. */
4167 void
4168 OP_199_14 (void)
4169 {
4170 uint32 a = GPR32 (OP[0]);
4171 uint32 addr = (GPR32 (OP[2])) + OP[1];
4172 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
4173 SLW (addr, a);
4174 trace_output_32 (addr);
4175 }
4176
4177 /* stord. */
4178 void
4179 OP_13A_14 (void)
4180 {
4181 uint32 a = GPR32 (OP[0]);
4182 uint32 addr = (GPR32 (OP[2])) + OP[1];
4183 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
4184 SLW (addr, a);
4185 trace_output_32 (addr);
4186 }
4187
4188 /* macqu. */
4189 void
4190 OP_14D_14 (void)
4191 {
4192 int32 tmp;
4193 int16 src1, src2;
4194 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4195 src1 = GPR (OP[0]);
4196 src2 = GPR (OP[1]);
4197 tmp = src1 * src2;
4198 /*REVISIT FOR SATURATION and Q FORMAT. */
4199 SET_GPR32 (OP[2], tmp);
4200 trace_output_32 (tmp);
4201 }
4202
4203 /* macuw. */
4204 void
4205 OP_14E_14 (void)
4206 {
4207 uint32 tmp;
4208 uint16 src1, src2;
4209 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4210 src1 = GPR (OP[0]);
4211 src2 = GPR (OP[1]);
4212 tmp = src1 * src2;
4213 /*REVISIT FOR SATURATION. */
4214 SET_GPR32 (OP[2], tmp);
4215 trace_output_32 (tmp);
4216 }
4217
4218 /* macsw. */
4219 void
4220 OP_14F_14 (void)
4221 {
4222 int32 tmp;
4223 int16 src1, src2;
4224 trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
4225 src1 = GPR (OP[0]);
4226 src2 = GPR (OP[1]);
4227 tmp = src1 * src2;
4228 /*REVISIT FOR SATURATION. */
4229 SET_GPR32 (OP[2], tmp);
4230 trace_output_32 (tmp);
4231 }
4232
4233
4234 /* mulb. */
4235 void
4236 OP_64_8 (void)
4237 {
4238 int16 tmp;
4239 int8 a = (OP[0]) & 0xff;
4240 int8 b = (GPR (OP[1])) & 0xff;
4241 trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
4242 tmp = (a * b) & 0xff;
4243 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4244 trace_output_16 (tmp);
4245 }
4246
4247 /* mulb. */
4248 void
4249 OP_64B_C (void)
4250 {
4251 int16 tmp;
4252 int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4253 trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
4254 tmp = (a * b) & 0xff;
4255 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4256 trace_output_16 (tmp);
4257 }
4258
4259
4260 /* mulb. */
4261 void
4262 OP_65_8 (void)
4263 {
4264 int16 tmp;
4265 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4266 trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
4267 tmp = (a * b) & 0xff;
4268 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4269 trace_output_16 (tmp);
4270 }
4271
4272
4273 /* mulw. */
4274 void
4275 OP_66_8 (void)
4276 {
4277 int32 tmp;
4278 uint16 a = OP[0];
4279 int16 b = (GPR (OP[1]));
4280 trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
4281 tmp = (a * b) & 0xffff;
4282 SET_GPR (OP[1], tmp);
4283 trace_output_32 (tmp);
4284 }
4285
4286 /* mulw. */
4287 void
4288 OP_66B_C (void)
4289 {
4290 int32 tmp;
4291 int16 a = OP[0], b = (GPR (OP[1]));
4292 trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
4293 tmp = (a * b) & 0xffff;
4294 SET_GPR (OP[1], tmp);
4295 trace_output_32 (tmp);
4296 }
4297
4298
4299 /* mulw. */
4300 void
4301 OP_67_8 (void)
4302 {
4303 int32 tmp;
4304 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4305 trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
4306 tmp = (a * b) & 0xffff;
4307 SET_GPR (OP[1], tmp);
4308 trace_output_32 (tmp);
4309 }
4310
4311
4312 /* mulsb. */
4313 void
4314 OP_B_8 (void)
4315 {
4316 int16 tmp;
4317 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4318 trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
4319 tmp = a * b;
4320 SET_GPR (OP[1], tmp);
4321 trace_output_32 (tmp);
4322 }
4323
4324 /* mulsw. */
4325 void
4326 OP_62_8 (void)
4327 {
4328 int32 tmp;
4329 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4330 trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
4331 tmp = a * b;
4332 SET_GPR32 (OP[1], tmp);
4333 trace_output_32 (tmp);
4334 }
4335
4336 /* muluw. */
4337 void
4338 OP_63_8 (void)
4339 {
4340 uint32 tmp;
4341 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4342 trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
4343 tmp = a * b;
4344 SET_GPR32 (OP[1], tmp);
4345 trace_output_32 (tmp);
4346 }
4347
4348
4349 /* nop. */
4350 void
4351 OP_2C00_10 (void)
4352 {
4353 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
4354
4355 #if 0
4356 State.exception = SIGTRAP;
4357 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
4358 switch (State.ins_type)
4359 {
4360 default:
4361 ins_type_counters[ (int)INS_UNKNOWN ]++;
4362 break;
4363
4364 }
4365
4366 #endif
4367 trace_output_void ();
4368 }
4369
4370
4371 /* orb. */
4372 void
4373 OP_24_8 (void)
4374 {
4375 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4376 trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
4377 tmp = a | b;
4378 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4379 trace_output_16 (tmp);
4380 }
4381
4382 /* orb. */
4383 void
4384 OP_24B_C (void)
4385 {
4386 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4387 trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
4388 tmp = a | b;
4389 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4390 trace_output_16 (tmp);
4391 }
4392
4393 /* orb. */
4394 void
4395 OP_25_8 (void)
4396 {
4397 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4398 trace_input ("orb", OP_REG, OP_REG, OP_VOID);
4399 tmp = a | b;
4400 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4401 trace_output_16 (tmp);
4402 }
4403
4404 /* orw. */
4405 void
4406 OP_26_8 (void)
4407 {
4408 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4409 trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
4410 tmp = a | b;
4411 SET_GPR (OP[1], tmp);
4412 trace_output_16 (tmp);
4413 }
4414
4415
4416 /* orw. */
4417 void
4418 OP_26B_C (void)
4419 {
4420 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4421 trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
4422 tmp = a | b;
4423 SET_GPR (OP[1], tmp);
4424 trace_output_16 (tmp);
4425 }
4426
4427 /* orw. */
4428 void
4429 OP_27_8 (void)
4430 {
4431 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
4432 trace_input ("orw", OP_REG, OP_REG, OP_VOID);
4433 tmp = a | b;
4434 SET_GPR (OP[1], tmp);
4435 trace_output_16 (tmp);
4436 }
4437
4438
4439 /* lshb. */
4440 void
4441 OP_13_9 (void)
4442 {
4443 uint16 a = OP[0];
4444 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4445 trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
4446 /* A positive count specifies a shift to the left;
4447 * A negative count specifies a shift to the right. */
4448 if (sign_flag)
4449 tmp = b >> a;
4450 else
4451 tmp = b << a;
4452
4453 sign_flag = 0; /* Reset sign_flag. */
4454
4455 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4456 trace_output_16 (tmp);
4457 }
4458
4459 /* lshb. */
4460 void
4461 OP_44_8 (void)
4462 {
4463 uint16 a = (GPR (OP[0])) & 0xff;
4464 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4465 trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
4466 if (a & ((long)1 << 3))
4467 {
4468 sign_flag = 1;
4469 a = ~(a) + 1;
4470 }
4471 a = (unsigned int) (a & 0x7);
4472
4473 /* A positive count specifies a shift to the left;
4474 * A negative count specifies a shift to the right. */
4475 if (sign_flag)
4476 tmp = b >> a;
4477 else
4478 tmp = b << a;
4479
4480 sign_flag = 0; /* Reset sign_flag. */
4481 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4482 trace_output_16 (tmp);
4483 }
4484
4485 /* lshw. */
4486 void
4487 OP_46_8 (void)
4488 {
4489 uint16 tmp, b = GPR (OP[1]);
4490 int16 a = GPR (OP[0]);
4491 trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
4492 if (a & ((long)1 << 4))
4493 {
4494 sign_flag = 1;
4495 a = ~(a) + 1;
4496 }
4497 a = (unsigned int) (a & 0xf);
4498
4499 /* A positive count specifies a shift to the left;
4500 * A negative count specifies a shift to the right. */
4501 if (sign_flag)
4502 tmp = b >> a;
4503 else
4504 tmp = b << a;
4505
4506 sign_flag = 0; /* Reset sign_flag. */
4507 SET_GPR (OP[1], (tmp & 0xffff));
4508 trace_output_16 (tmp);
4509 }
4510
4511 /* lshw. */
4512 void
4513 OP_49_8 (void)
4514 {
4515 uint16 tmp, b = GPR (OP[1]);
4516 uint16 a = OP[0];
4517 trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
4518 /* A positive count specifies a shift to the left;
4519 * A negative count specifies a shift to the right. */
4520 if (sign_flag)
4521 tmp = b >> a;
4522 else
4523 tmp = b << a;
4524
4525 sign_flag = 0; /* Reset sign_flag. */
4526 SET_GPR (OP[1], (tmp & 0xffff));
4527 trace_output_16 (tmp);
4528 }
4529
4530 /* lshd. */
4531 void
4532 OP_25_7 (void)
4533 {
4534 uint32 tmp, b = GPR32 (OP[1]);
4535 uint16 a = OP[0];
4536 trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
4537 /* A positive count specifies a shift to the left;
4538 * A negative count specifies a shift to the right. */
4539 if (sign_flag)
4540 tmp = b >> a;
4541 else
4542 tmp = b << a;
4543
4544 sign_flag = 0; /* Reset sign flag. */
4545
4546 SET_GPR32 (OP[1], tmp);
4547 trace_output_32 (tmp);
4548 }
4549
4550 /* lshd. */
4551 void
4552 OP_47_8 (void)
4553 {
4554 uint32 tmp, b = GPR32 (OP[1]);
4555 uint16 a = GPR (OP[0]);
4556 trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
4557 if (a & ((long)1 << 5))
4558 {
4559 sign_flag = 1;
4560 a = ~(a) + 1;
4561 }
4562 a = (unsigned int) (a & 0x1f);
4563 /* A positive count specifies a shift to the left;
4564 * A negative count specifies a shift to the right. */
4565 if (sign_flag)
4566 tmp = b >> a;
4567 else
4568 tmp = b << a;
4569
4570 sign_flag = 0; /* Reset sign flag. */
4571
4572 SET_GPR32 (OP[1], tmp);
4573 trace_output_32 (tmp);
4574 }
4575
4576 /* ashub. */
4577 void
4578 OP_80_9 (void)
4579 {
4580 uint16 a = OP[0];
4581 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4582 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4583 /* A positive count specifies a shift to the left;
4584 * A negative count specifies a shift to the right. */
4585 if (sign_flag)
4586 tmp = b >> a;
4587 else
4588 tmp = b << a;
4589
4590 sign_flag = 0; /* Reset sign flag. */
4591
4592 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00)));
4593 trace_output_16 (tmp);
4594 }
4595
4596 /* ashub. */
4597 void
4598 OP_81_9 (void)
4599 {
4600 uint16 a = OP[0];
4601 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4602 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4603 /* A positive count specifies a shift to the left;
4604 * A negative count specifies a shift to the right. */
4605 if (sign_flag)
4606 tmp = b >> a;
4607 else
4608 tmp = b << a;
4609
4610 sign_flag = 0; /* Reset sign flag. */
4611
4612 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4613 trace_output_16 (tmp);
4614 }
4615
4616
4617 /* ashub. */
4618 void
4619 OP_41_8 (void)
4620 {
4621 int16 a = (GPR (OP[0]));
4622 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4623 trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
4624
4625 if (a & ((long)1 << 3))
4626 {
4627 sign_flag = 1;
4628 a = ~(a) + 1;
4629 }
4630 a = (unsigned int) (a & 0x7);
4631
4632 /* A positive count specifies a shift to the left;
4633 * A negative count specifies a shift to the right. */
4634 if (sign_flag)
4635 tmp = b >> a;
4636 else
4637 tmp = b << a;
4638
4639 sign_flag = 0; /* Reset sign flag. */
4640
4641 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4642 trace_output_16 (tmp);
4643 }
4644
4645
4646 /* ashuw. */
4647 void
4648 OP_42_8 (void)
4649 {
4650 int16 tmp, b = GPR (OP[1]);
4651 uint16 a = OP[0];
4652 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4653 /* A positive count specifies a shift to the left;
4654 * A negative count specifies a shift to the right. */
4655 if (sign_flag)
4656 tmp = b >> a;
4657 else
4658 tmp = b << a;
4659
4660 sign_flag = 0; /* Reset sign flag. */
4661
4662 SET_GPR (OP[1], (tmp & 0xffff));
4663 trace_output_16 (tmp);
4664 }
4665
4666 /* ashuw. */
4667 void
4668 OP_43_8 (void)
4669 {
4670 int16 tmp, b = GPR (OP[1]);
4671 uint16 a = OP[0];
4672 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4673 /* A positive count specifies a shift to the left;
4674 * A negative count specifies a shift to the right. */
4675 if (sign_flag)
4676 tmp = b >> a;
4677 else
4678 tmp = b << a;
4679
4680 sign_flag = 0; /* Reset sign flag. */
4681 SET_GPR (OP[1], (tmp & 0xffff));
4682 trace_output_16 (tmp);
4683 }
4684
4685 /* ashuw. */
4686 void
4687 OP_45_8 (void)
4688 {
4689 int16 tmp;
4690 int16 a = GPR (OP[0]), b = GPR (OP[1]);
4691 trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
4692
4693 if (a & ((long)1 << 4))
4694 {
4695 sign_flag = 1;
4696 a = ~(a) + 1;
4697 }
4698 a = (unsigned int) (a & 0xf);
4699 /* A positive count specifies a shift to the left;
4700 * A negative count specifies a shift to the right. */
4701
4702 if (sign_flag)
4703 tmp = b >> a;
4704 else
4705 tmp = b << a;
4706
4707 sign_flag = 0; /* Reset sign flag. */
4708 SET_GPR (OP[1], (tmp & 0xffff));
4709 trace_output_16 (tmp);
4710 }
4711
4712 /* ashud. */
4713 void
4714 OP_26_7 (void)
4715 {
4716 int32 tmp,b = GPR32 (OP[1]);
4717 uint32 a = OP[0];
4718 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4719 /* A positive count specifies a shift to the left;
4720 * A negative count specifies a shift to the right. */
4721 if (sign_flag)
4722 tmp = b >> a;
4723 else
4724 tmp = b << a;
4725
4726 sign_flag = 0; /* Reset sign flag. */
4727 SET_GPR32 (OP[1], tmp);
4728 trace_output_32 (tmp);
4729 }
4730
4731 /* ashud. */
4732 void
4733 OP_27_7 (void)
4734 {
4735 int32 tmp;
4736 int32 a = OP[0], b = GPR32 (OP[1]);
4737 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4738 /* A positive count specifies a shift to the left;
4739 * A negative count specifies a shift to the right. */
4740 if (sign_flag)
4741 tmp = b >> a;
4742 else
4743 tmp = b << a;
4744
4745 sign_flag = 0; /* Reset sign flag. */
4746 SET_GPR32 (OP[1], tmp);
4747 trace_output_32 (tmp);
4748 }
4749
4750 /* ashud. */
4751 void
4752 OP_48_8 (void)
4753 {
4754 int32 tmp;
4755 int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]);
4756 trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
4757
4758 if (a & ((long)1 << 5))
4759 {
4760 sign_flag = 1;
4761 a = ~(a) + 1;
4762 }
4763 a = (unsigned int) (a & 0x1f);
4764 /* A positive count specifies a shift to the left;
4765 * A negative count specifies a shift to the right. */
4766 if (sign_flag)
4767 tmp = b >> a;
4768 else
4769 tmp = b << a;
4770
4771 sign_flag = 0; /* Reset sign flag. */
4772 SET_GPR32 (OP[1], tmp);
4773 trace_output_32 (tmp);
4774 }
4775
4776
4777 /* storm. */
4778 void
4779 OP_16_D (void)
4780 {
4781 uint32 addr = GPR (1);
4782 uint16 count = OP[0], reg = 2;
4783 trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
4784 if ((addr & 1))
4785 {
4786 State.exception = SIG_CR16_BUS;
4787 State.pc_changed = 1; /* Don't increment the PC. */
4788 trace_output_void ();
4789 return;
4790 }
4791
4792 while (count)
4793 {
4794 SW (addr, (GPR (reg)));
4795 addr +=2;
4796 --count;
4797 reg++;
4798 if (reg == 6) reg = 8;
4799 };
4800
4801 SET_GPR (1, addr);
4802
4803 trace_output_void ();
4804 }
4805
4806
4807 /* stormp. */
4808 void
4809 OP_17_D (void)
4810 {
4811 uint32 addr = GPR32 (6);
4812 uint16 count = OP[0], reg = 2;
4813 trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
4814 if ((addr & 1))
4815 {
4816 State.exception = SIG_CR16_BUS;
4817 State.pc_changed = 1; /* Don't increment the PC. */
4818 trace_output_void ();
4819 return;
4820 }
4821
4822 while (count)
4823 {
4824 SW (addr, (GPR (reg)));
4825 addr +=2;
4826 --count;
4827 reg++;
4828 if (reg == 6) reg = 8;
4829 };
4830
4831 SET_GPR32 (6, addr);
4832 trace_output_void ();
4833 }
4834
4835 /* subb. */
4836 void
4837 OP_38_8 (void)
4838 {
4839 uint8 a = OP[0];
4840 uint8 b = (GPR (OP[1])) & 0xff;
4841 uint16 tmp = (~a + 1 + b) & 0xff;
4842 trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
4843 /* see ../common/sim-alu.h for a more extensive discussion on how to
4844 compute the carry/overflow bits. */
4845 SET_PSR_C (tmp > 0xff);
4846 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4847 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4848 trace_output_16 (tmp);
4849 }
4850
4851 /* subb. */
4852 void
4853 OP_38B_C (void)
4854 {
4855 uint8 a = OP[0] & 0xFF;
4856 uint8 b = (GPR (OP[1])) & 0xFF;
4857 uint16 tmp = (~a + 1 + b) & 0xFF;
4858 trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
4859 /* see ../common/sim-alu.h for a more extensive discussion on how to
4860 compute the carry/overflow bits. */
4861 SET_PSR_C (tmp > 0xff);
4862 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4863 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4864 trace_output_16 (tmp);
4865 }
4866
4867 /* subb. */
4868 void
4869 OP_39_8 (void)
4870 {
4871 uint8 a = (GPR (OP[0])) & 0xFF;
4872 uint8 b = (GPR (OP[1])) & 0xFF;
4873 uint16 tmp = (~a + 1 + b) & 0xff;
4874 trace_input ("subb", OP_REG, OP_REG, OP_VOID);
4875 /* see ../common/sim-alu.h for a more extensive discussion on how to
4876 compute the carry/overflow bits. */
4877 SET_PSR_C (tmp > 0xff);
4878 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4879 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4880 trace_output_16 (tmp);
4881 }
4882
4883 /* subw. */
4884 void
4885 OP_3A_8 (void)
4886 {
4887 uint16 a = OP[0];
4888 uint16 b = GPR (OP[1]);
4889 uint16 tmp = (~a + 1 + b);
4890 trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
4891 /* see ../common/sim-alu.h for a more extensive discussion on how to
4892 compute the carry/overflow bits. */
4893 SET_PSR_C (tmp > 0xffff);
4894 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4895 SET_GPR (OP[1], tmp);
4896 trace_output_16 (tmp);
4897 }
4898
4899 /* subw. */
4900 void
4901 OP_3AB_C (void)
4902 {
4903 uint16 a = OP[0];
4904 uint16 b = GPR (OP[1]);
4905 uint32 tmp = (~a + 1 + b);
4906 trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
4907 /* see ../common/sim-alu.h for a more extensive discussion on how to
4908 compute the carry/overflow bits. */
4909 SET_PSR_C (tmp > 0xffff);
4910 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4911 SET_GPR (OP[1], tmp & 0xffff);
4912 trace_output_16 (tmp);
4913 }
4914
4915 /* subw. */
4916 void
4917 OP_3B_8 (void)
4918 {
4919 uint16 a = GPR (OP[0]);
4920 uint16 b = GPR (OP[1]);
4921 uint32 tmp = (~a + 1 + b);
4922 trace_input ("subw", OP_REG, OP_REG, OP_VOID);
4923 /* see ../common/sim-alu.h for a more extensive discussion on how to
4924 compute the carry/overflow bits. */
4925 SET_PSR_C (tmp > 0xffff);
4926 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4927 SET_GPR (OP[1], tmp & 0xffff);
4928 trace_output_16 (tmp);
4929 }
4930
4931 /* subcb. */
4932 void
4933 OP_3C_8 (void)
4934 {
4935 uint8 a = OP[0];
4936 uint8 b = (GPR (OP[1])) & 0xff;
4937 //uint16 tmp1 = a + 1;
4938 uint16 tmp1 = a + (PSR_C);
4939 uint16 tmp = (~tmp1 + 1 + b);
4940 trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
4941 /* see ../common/sim-alu.h for a more extensive discussion on how to
4942 compute the carry/overflow bits. */
4943 SET_PSR_C (tmp > 0xff);
4944 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4945 SET_GPR (OP[1], tmp);
4946 trace_output_16 (tmp);
4947 }
4948
4949 /* subcb. */
4950 void
4951 OP_3CB_C (void)
4952 {
4953 uint16 a = OP[0];
4954 uint16 b = (GPR (OP[1])) & 0xff;
4955 //uint16 tmp1 = a + 1;
4956 uint16 tmp1 = a + (PSR_C);
4957 uint16 tmp = (~tmp1 + 1 + b);
4958 trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
4959 /* see ../common/sim-alu.h for a more extensive discussion on how to
4960 compute the carry/overflow bits. */
4961 SET_PSR_C (tmp > 0xff);
4962 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4963 SET_GPR (OP[1], tmp);
4964 trace_output_16 (tmp);
4965 }
4966
4967 /* subcb. */
4968 void
4969 OP_3D_8 (void)
4970 {
4971 uint16 a = (GPR (OP[0])) & 0xff;
4972 uint16 b = (GPR (OP[1])) & 0xff;
4973 uint16 tmp1 = a + (PSR_C);
4974 uint16 tmp = (~tmp1 + 1 + b);
4975 trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
4976 /* see ../common/sim-alu.h for a more extensive discussion on how to
4977 compute the carry/overflow bits. */
4978 SET_PSR_C (tmp > 0xff);
4979 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4980 SET_GPR (OP[1], tmp);
4981 trace_output_16 (tmp);
4982 }
4983
4984 /* subcw. */
4985 void
4986 OP_3E_8 (void)
4987 {
4988 uint16 a = OP[0], b = (GPR (OP[1]));
4989 uint16 tmp1 = a + (PSR_C);
4990 uint16 tmp = (~tmp1 + 1 + b);
4991 trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
4992 /* see ../common/sim-alu.h for a more extensive discussion on how to
4993 compute the carry/overflow bits. */
4994 SET_PSR_C (tmp > 0xffff);
4995 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4996 SET_GPR (OP[1], tmp);
4997 trace_output_16 (tmp);
4998 }
4999
5000 /* subcw. */
5001 void
5002 OP_3EB_C (void)
5003 {
5004 int16 a = OP[0];
5005 uint16 b = GPR (OP[1]);
5006 uint16 tmp1 = a + (PSR_C);
5007 uint16 tmp = (~tmp1 + 1 + b);
5008 trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
5009 /* see ../common/sim-alu.h for a more extensive discussion on how to
5010 compute the carry/overflow bits. */
5011 SET_PSR_C (tmp > 0xffff);
5012 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5013 SET_GPR (OP[1], tmp);
5014 trace_output_16 (tmp);
5015 }
5016
5017 /* subcw. */
5018 void
5019 OP_3F_8 (void)
5020 {
5021 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
5022 uint16 tmp1 = a + (PSR_C);
5023 uint16 tmp = (~tmp1 + 1 + b);
5024 trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
5025 /* see ../common/sim-alu.h for a more extensive discussion on how to
5026 compute the carry/overflow bits. */
5027 SET_PSR_C (tmp > 0xffff);
5028 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5029 SET_GPR (OP[1], tmp);
5030 trace_output_16 (tmp);
5031 }
5032
5033 /* subd. */
5034 void
5035 OP_3_C (void)
5036 {
5037 int32 a = OP[0];
5038 uint32 b = GPR32 (OP[1]);
5039 uint32 tmp = (~a + 1 + b);
5040 trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
5041 /* see ../common/sim-alu.h for a more extensive discussion on how to
5042 compute the carry/overflow bits. */
5043 SET_PSR_C (tmp > 0xffffffff);
5044 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5045 ((b & 0x80000000) != (tmp & 0x80000000)));
5046 SET_GPR32 (OP[1], tmp);
5047 trace_output_32 (tmp);
5048 }
5049
5050 /* subd. */
5051 void
5052 OP_14C_14 (void)
5053 {
5054 uint32 a = GPR32 (OP[0]);
5055 uint32 b = GPR32 (OP[1]);
5056 uint32 tmp = (~a + 1 + b);
5057 trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
5058 /* see ../common/sim-alu.h for a more extensive discussion on how to
5059 compute the carry/overflow bits. */
5060 SET_PSR_C (tmp > 0xffffffff);
5061 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5062 ((b & 0x80000000) != (tmp & 0x80000000)));
5063 SET_GPR32 (OP[1], tmp);
5064 trace_output_32 (tmp);
5065 }
5066
5067 /* excp. */
5068 void
5069 OP_C_C (void)
5070 {
5071 uint32 tmp;
5072 uint16 a;
5073 trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
5074 switch (OP[0])
5075 {
5076 default:
5077 #if (DEBUG & DEBUG_TRAP) == 0
5078 {
5079 #if 0
5080 uint16 vec = OP[0] + TRAP_VECTOR_START;
5081 SET_BPC (PC + 1);
5082 SET_BPSR (PSR);
5083 SET_PSR (PSR & PSR_SM_BIT);
5084 JMP (vec);
5085 break;
5086 #endif
5087 }
5088 #else /* if debugging use trap to print registers */
5089 {
5090 int i;
5091 static int first_time = 1;
5092
5093 if (first_time)
5094 {
5095 first_time = 0;
5096 (*cr16_callback->printf_filtered) (cr16_callback, "Trap # PC ");
5097 for (i = 0; i < 16; i++)
5098 (*cr16_callback->printf_filtered) (cr16_callback, " %sr%d", (i > 9) ? "" : " ", i);
5099 (*cr16_callback->printf_filtered) (cr16_callback, " a0 a1 f0 f1 c\n");
5100 }
5101
5102 (*cr16_callback->printf_filtered) (cr16_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
5103
5104 for (i = 0; i < 16; i++)
5105 (*cr16_callback->printf_filtered) (cr16_callback, " %.4x", (int) GPR (i));
5106
5107 for (i = 0; i < 2; i++)
5108 (*cr16_callback->printf_filtered) (cr16_callback, " %.2x%.8lx",
5109 ((int)(ACC (i) >> 32) & 0xff),
5110 ((unsigned long) ACC (i)) & 0xffffffff);
5111
5112 (*cr16_callback->printf_filtered) (cr16_callback, " %d %d %d\n",
5113 PSR_F != 0, PSR_F != 0, PSR_C != 0);
5114 (*cr16_callback->flush_stdout) (cr16_callback);
5115 break;
5116 }
5117 #endif
5118 case 8: /* new system call trap */
5119 /* Trap 8 is used for simulating low-level I/O */
5120 {
5121 unsigned32 result = 0;
5122 errno = 0;
5123
5124 /* Registers passed to trap 0. */
5125
5126 #define FUNC GPR (0) /* function number. */
5127 #define PARM1 GPR (2) /* optional parm 1. */
5128 #define PARM2 GPR (3) /* optional parm 2. */
5129 #define PARM3 GPR (4) /* optional parm 3. */
5130 #define PARM4 GPR (5) /* optional parm 4. */
5131
5132 /* Registers set by trap 0 */
5133
5134 #define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0)
5135 #define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0)
5136 #define RETERR(X) SET_GPR (4, (X)) /* return error code. */
5137
5138 /* Turn a pointer in a register into a pointer into real memory. */
5139
5140 #define MEMPTR(x) ((char *)(dmem_addr(x)))
5141
5142 switch (FUNC)
5143 {
5144 #if !defined(__GO32__) && !defined(_WIN32)
5145 #ifdef TARGET_SYS_fork
5146 case TARGET_SYS_fork:
5147 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
5148 RETVAL (fork ());
5149 trace_output_16 (result);
5150 break;
5151 #endif
5152
5153 #define getpid() 47
5154 case TARGET_SYS_getpid:
5155 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5156 RETVAL (getpid ());
5157 trace_output_16 (result);
5158 break;
5159
5160 case TARGET_SYS_kill:
5161 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5162 if (PARM1 == getpid ())
5163 {
5164 trace_output_void ();
5165 State.exception = PARM2;
5166 }
5167 else
5168 {
5169 int os_sig = -1;
5170 switch (PARM2)
5171 {
5172 #ifdef SIGHUP
5173 case 1: os_sig = SIGHUP; break;
5174 #endif
5175 #ifdef SIGINT
5176 case 2: os_sig = SIGINT; break;
5177 #endif
5178 #ifdef SIGQUIT
5179 case 3: os_sig = SIGQUIT; break;
5180 #endif
5181 #ifdef SIGILL
5182 case 4: os_sig = SIGILL; break;
5183 #endif
5184 #ifdef SIGTRAP
5185 case 5: os_sig = SIGTRAP; break;
5186 #endif
5187 #ifdef SIGABRT
5188 case 6: os_sig = SIGABRT; break;
5189 #elif defined(SIGIOT)
5190 case 6: os_sig = SIGIOT; break;
5191 #endif
5192 #ifdef SIGEMT
5193 case 7: os_sig = SIGEMT; break;
5194 #endif
5195 #ifdef SIGFPE
5196 case 8: os_sig = SIGFPE; break;
5197 #endif
5198 #ifdef SIGKILL
5199 case 9: os_sig = SIGKILL; break;
5200 #endif
5201 #ifdef SIGBUS
5202 case 10: os_sig = SIGBUS; break;
5203 #endif
5204 #ifdef SIGSEGV
5205 case 11: os_sig = SIGSEGV; break;
5206 #endif
5207 #ifdef SIGSYS
5208 case 12: os_sig = SIGSYS; break;
5209 #endif
5210 #ifdef SIGPIPE
5211 case 13: os_sig = SIGPIPE; break;
5212 #endif
5213 #ifdef SIGALRM
5214 case 14: os_sig = SIGALRM; break;
5215 #endif
5216 #ifdef SIGTERM
5217 case 15: os_sig = SIGTERM; break;
5218 #endif
5219 #ifdef SIGURG
5220 case 16: os_sig = SIGURG; break;
5221 #endif
5222 #ifdef SIGSTOP
5223 case 17: os_sig = SIGSTOP; break;
5224 #endif
5225 #ifdef SIGTSTP
5226 case 18: os_sig = SIGTSTP; break;
5227 #endif
5228 #ifdef SIGCONT
5229 case 19: os_sig = SIGCONT; break;
5230 #endif
5231 #ifdef SIGCHLD
5232 case 20: os_sig = SIGCHLD; break;
5233 #elif defined(SIGCLD)
5234 case 20: os_sig = SIGCLD; break;
5235 #endif
5236 #ifdef SIGTTIN
5237 case 21: os_sig = SIGTTIN; break;
5238 #endif
5239 #ifdef SIGTTOU
5240 case 22: os_sig = SIGTTOU; break;
5241 #endif
5242 #ifdef SIGIO
5243 case 23: os_sig = SIGIO; break;
5244 #elif defined (SIGPOLL)
5245 case 23: os_sig = SIGPOLL; break;
5246 #endif
5247 #ifdef SIGXCPU
5248 case 24: os_sig = SIGXCPU; break;
5249 #endif
5250 #ifdef SIGXFSZ
5251 case 25: os_sig = SIGXFSZ; break;
5252 #endif
5253 #ifdef SIGVTALRM
5254 case 26: os_sig = SIGVTALRM; break;
5255 #endif
5256 #ifdef SIGPROF
5257 case 27: os_sig = SIGPROF; break;
5258 #endif
5259 #ifdef SIGWINCH
5260 case 28: os_sig = SIGWINCH; break;
5261 #endif
5262 #ifdef SIGLOST
5263 case 29: os_sig = SIGLOST; break;
5264 #endif
5265 #ifdef SIGUSR1
5266 case 30: os_sig = SIGUSR1; break;
5267 #endif
5268 #ifdef SIGUSR2
5269 case 31: os_sig = SIGUSR2; break;
5270 #endif
5271 }
5272
5273 if (os_sig == -1)
5274 {
5275 trace_output_void ();
5276 (*cr16_callback->printf_filtered) (cr16_callback, "Unknown signal %d\n", PARM2);
5277 (*cr16_callback->flush_stdout) (cr16_callback);
5278 State.exception = SIGILL;
5279 }
5280 else
5281 {
5282 RETVAL (kill (PARM1, PARM2));
5283 trace_output_16 (result);
5284 }
5285 }
5286 break;
5287
5288 #ifdef TARGET_SYS_execve
5289 case TARGET_SYS_execve:
5290 trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID);
5291 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3),
5292 (char **)MEMPTR (PARM4)));
5293 trace_output_16 (result);
5294 break;
5295 #endif
5296
5297 #ifdef TARGET_SYS_execv
5298 case TARGET_SYS_execv:
5299 trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID);
5300 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
5301 trace_output_16 (result);
5302 break;
5303 #endif
5304
5305 #ifdef TARGET_SYS_pipe
5306 case TARGET_SYS_pipe:
5307 {
5308 reg_t buf;
5309 int host_fd[2];
5310
5311 trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID);
5312 buf = PARM1;
5313 RETVAL (pipe (host_fd));
5314 SW (buf, host_fd[0]);
5315 buf += sizeof(uint16);
5316 SW (buf, host_fd[1]);
5317 trace_output_16 (result);
5318 }
5319 break;
5320 #endif
5321
5322 #ifdef TARGET_SYS_wait
5323 case TARGET_SYS_wait:
5324 {
5325 int status;
5326 trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID);
5327 RETVAL (wait (&status));
5328 if (PARM1)
5329 SW (PARM1, status);
5330 trace_output_16 (result);
5331 }
5332 break;
5333 #endif
5334 #else
5335 case TARGET_SYS_getpid:
5336 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5337 RETVAL (1);
5338 trace_output_16 (result);
5339 break;
5340
5341 case TARGET_SYS_kill:
5342 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5343 trace_output_void ();
5344 State.exception = PARM2;
5345 break;
5346 #endif
5347
5348 case TARGET_SYS_read:
5349 trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG);
5350 RETVAL (cr16_callback->read (cr16_callback, PARM1,
5351 MEMPTR (((unsigned long)PARM3 << 16)
5352 |((unsigned long)PARM2)), PARM4));
5353 trace_output_16 (result);
5354 break;
5355
5356 case TARGET_SYS_write:
5357 trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG);
5358 RETVAL ((int)cr16_callback->write (cr16_callback, PARM1,
5359 MEMPTR (((unsigned long)PARM3 << 16) | PARM2), PARM4));
5360 trace_output_16 (result);
5361 break;
5362
5363 case TARGET_SYS_lseek:
5364 trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG);
5365 RETVAL32 (cr16_callback->lseek (cr16_callback, PARM1,
5366 ((((long) PARM3) << 16) | PARM2),
5367 PARM4));
5368 trace_output_32 (result);
5369 break;
5370
5371 case TARGET_SYS_close:
5372 trace_input ("<close>", OP_REG, OP_VOID, OP_VOID);
5373 RETVAL (cr16_callback->close (cr16_callback, PARM1));
5374 trace_output_16 (result);
5375 break;
5376
5377 case TARGET_SYS_open:
5378 trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID);
5379 RETVAL32 (cr16_callback->open (cr16_callback,
5380 MEMPTR ((((unsigned long)PARM2)<<16)|PARM1),
5381 PARM3));
5382 trace_output_32 (result);
5383 break;
5384
5385 #ifdef TARGET_SYS_rename
5386 case TARGET_SYS_rename:
5387 trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID);
5388 RETVAL (cr16_callback->rename (cr16_callback,
5389 MEMPTR ((((unsigned long)PARM2)<<16) |PARM1),
5390 MEMPTR ((((unsigned long)PARM4)<<16) |PARM3)));
5391 trace_output_16 (result);
5392 break;
5393 #endif
5394
5395 case 0x408: /* REVISIT: Added a dummy getenv call. */
5396 trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID);
5397 RETVAL32 (0);
5398 trace_output_32 (result);
5399 break;
5400
5401 case TARGET_SYS_exit:
5402 trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID);
5403 State.exception = SIG_CR16_EXIT;
5404 trace_output_void ();
5405 break;
5406
5407 case TARGET_SYS_unlink:
5408 trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID);
5409 RETVAL (cr16_callback->unlink (cr16_callback,
5410 MEMPTR (((unsigned long)PARM2<<16)|PARM1)));
5411 trace_output_16 (result);
5412 break;
5413
5414
5415 #ifdef TARGET_SYS_stat
5416 case TARGET_SYS_stat:
5417 trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID);
5418 /* stat system call. */
5419 {
5420 struct stat host_stat;
5421 reg_t buf;
5422
5423 RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat));
5424
5425 buf = PARM2;
5426
5427 /* The hard-coded offsets and sizes were determined by using
5428 * the CR16 compiler on a test program that used struct stat.
5429 */
5430 SW (buf, host_stat.st_dev);
5431 SW (buf+2, host_stat.st_ino);
5432 SW (buf+4, host_stat.st_mode);
5433 SW (buf+6, host_stat.st_nlink);
5434 SW (buf+8, host_stat.st_uid);
5435 SW (buf+10, host_stat.st_gid);
5436 SW (buf+12, host_stat.st_rdev);
5437 SLW (buf+16, host_stat.st_size);
5438 SLW (buf+20, host_stat.st_atime);
5439 SLW (buf+28, host_stat.st_mtime);
5440 SLW (buf+36, host_stat.st_ctime);
5441 }
5442 trace_output_16 (result);
5443 break;
5444 #endif
5445
5446 #ifdef TARGET_SYS_chown
5447 case TARGET_SYS_chown:
5448 trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID);
5449 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
5450 trace_output_16 (result);
5451 break;
5452 #endif
5453
5454 case TARGET_SYS_chmod:
5455 trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID);
5456 RETVAL (chmod (MEMPTR (PARM1), PARM2));
5457 trace_output_16 (result);
5458 break;
5459
5460 #ifdef TARGET_SYS_utime
5461 case TARGET_SYS_utime:
5462 trace_input ("<utime>", OP_REG, OP_REG, OP_REG);
5463 /* Cast the second argument to void *, to avoid type mismatch
5464 if a prototype is present. */
5465 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
5466 trace_output_16 (result);
5467 break;
5468 #endif
5469
5470 #ifdef TARGET_SYS_time
5471 case TARGET_SYS_time:
5472 trace_input ("<time>", OP_VOID, OP_VOID, OP_REG);
5473 RETVAL32 (time (NULL));
5474 trace_output_32 (result);
5475 break;
5476 #endif
5477
5478 default:
5479 a = OP[0];
5480 switch (a)
5481 {
5482 case TRAP_BREAKPOINT:
5483 State.exception = SIGTRAP;
5484 tmp = (PC);
5485 JMP(tmp);
5486 trace_output_void ();
5487 break;
5488 case SIGTRAP: /* supervisor call ? */
5489 State.exception = SIG_CR16_EXIT;
5490 trace_output_void ();
5491 break;
5492 default:
5493 cr16_callback->error (cr16_callback, "Unknown syscall %d", FUNC);
5494 break;
5495 }
5496 }
5497 if ((uint16) result == (uint16) -1)
5498 RETERR (cr16_callback->get_errno(cr16_callback));
5499 else
5500 RETERR (0);
5501 break;
5502 }
5503 }
5504 }
5505
5506
5507 /* push. */
5508 void
5509 OP_3_9 (void)
5510 {
5511 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5512 uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
5513 trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
5514
5515 for (; i < a; ++i)
5516 {
5517 if ((b+i) <= 11)
5518 {
5519 SW (sp_addr, (GPR (b+i)));
5520 sp_addr +=2;
5521 }
5522 else
5523 {
5524 if (is_regp == 0)
5525 tmp = (GPR32 (b+i));
5526 else
5527 tmp = (GPR32 (b+i-1));
5528
5529 if ((a-i) > 1)
5530 {
5531 SLW (sp_addr, tmp);
5532 sp_addr +=4;
5533 }
5534 else
5535 {
5536 SW (sp_addr, tmp);
5537 sp_addr +=2;
5538 }
5539 ++i;
5540 is_regp = 1;
5541 }
5542 }
5543
5544 sp_addr +=4;
5545
5546 /* Store RA address. */
5547 tmp = (GPR32 (14));
5548 SLW(sp_addr,tmp);
5549
5550 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5551 SET_GPR32 (15, sp_addr); /* Update SP address. */
5552
5553 trace_output_void ();
5554 }
5555
5556 /* push. */
5557 void
5558 OP_1_8 (void)
5559 {
5560 uint32 sp_addr, tmp, is_regp = 0;
5561 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5562 trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
5563
5564 if (c == 1)
5565 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5566 else
5567 sp_addr = (GPR32 (15)) - (a * 2);
5568
5569 for (; i < a; ++i)
5570 {
5571 if ((b+i) <= 11)
5572 {
5573 SW (sp_addr, (GPR (b+i)));
5574 sp_addr +=2;
5575 }
5576 else
5577 {
5578 if (is_regp == 0)
5579 tmp = (GPR32 (b+i));
5580 else
5581 tmp = (GPR32 (b+i-1));
5582
5583 if ((a-i) > 1)
5584 {
5585 SLW (sp_addr, tmp);
5586 sp_addr +=4;
5587 }
5588 else
5589 {
5590 SW (sp_addr, tmp);
5591 sp_addr +=2;
5592 }
5593 ++i;
5594 is_regp = 1;
5595 }
5596 }
5597
5598 if (c == 1)
5599 {
5600 /* Store RA address. */
5601 tmp = (GPR32 (14));
5602 SLW(sp_addr,tmp);
5603 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5604 }
5605 else
5606 sp_addr = (GPR32 (15)) - (a * 2);
5607
5608 SET_GPR32 (15, sp_addr); /* Update SP address. */
5609
5610 trace_output_void ();
5611 }
5612
5613
5614 /* push. */
5615 void
5616 OP_11E_10 (void)
5617 {
5618 uint32 sp_addr = (GPR32 (15)), tmp;
5619 trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
5620 tmp = (GPR32 (14));
5621 SLW(sp_addr-4,tmp); /* Store RA address. */
5622 SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */
5623 trace_output_void ();
5624 }
5625
5626
5627 /* pop. */
5628 void
5629 OP_5_9 (void)
5630 {
5631 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5632 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
5633 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
5634
5635 for (; i < a; ++i)
5636 {
5637 if ((b+i) <= 11)
5638 {
5639 SET_GPR ((b+i), RW(sp_addr));
5640 sp_addr +=2;
5641 }
5642 else
5643 {
5644 if ((a-i) > 1)
5645 {
5646 tmp = RLW(sp_addr);
5647 sp_addr +=4;
5648 }
5649 else
5650 {
5651 tmp = RW(sp_addr);
5652 sp_addr +=2;
5653
5654 if (is_regp == 0)
5655 tmp = (tmp << 16) | (GPR32 (b+i));
5656 else
5657 tmp = (tmp << 16) | (GPR32 (b+i-1));
5658 }
5659
5660 if (is_regp == 0)
5661 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)
5662 | ((tmp >> 16) & 0xffff)));
5663 else
5664 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)
5665 | ((tmp >> 16) & 0xffff)));
5666
5667 ++i;
5668 is_regp = 1;
5669 }
5670 }
5671
5672 tmp = RLW(sp_addr); /* store RA also. */
5673 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5674
5675 SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */
5676
5677 trace_output_void ();
5678 }
5679
5680 /* pop. */
5681 void
5682 OP_2_8 (void)
5683 {
5684 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5685 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;
5686 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
5687
5688 for (; i < a; ++i)
5689 {
5690 if ((b+i) <= 11)
5691 {
5692 SET_GPR ((b+i), RW(sp_addr));
5693 sp_addr +=2;
5694 }
5695 else
5696 {
5697 if ((a-i) > 1)
5698 {
5699 tmp = RLW(sp_addr);
5700 sp_addr +=4;
5701 }
5702 else
5703 {
5704 tmp = RW(sp_addr);
5705 sp_addr +=2;
5706
5707 if (is_regp == 0)
5708 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i));
5709 else
5710 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1));
5711 }
5712
5713 if (is_regp == 0)
5714 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5715 else
5716 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5717 ++i;
5718 is_regp = 1;
5719 }
5720 }
5721
5722 if (c == 1)
5723 {
5724 tmp = RLW(sp_addr); /* Store RA Reg. */
5725 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5726 sp_addr +=4;
5727 }
5728
5729 SET_GPR32 (15, sp_addr); /* Update SP address. */
5730
5731 trace_output_void ();
5732 }
5733
5734 /* pop. */
5735 void
5736 OP_21E_10 (void)
5737 {
5738 uint32 sp_addr = GPR32 (15);
5739 uint32 tmp;
5740 trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
5741
5742 tmp = RLW(sp_addr);
5743 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5744 SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */
5745
5746 trace_output_void ();
5747 }
5748
5749 /* popret. */
5750 void
5751 OP_7_9 (void)
5752 {
5753 uint16 a = OP[0], b = OP[1];
5754 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
5755 OP_5_9 ();
5756 JMP(((GPR32(14)) << 1) & 0xffffff);
5757
5758 trace_output_void ();
5759 }
5760
5761 /* popret. */
5762 void
5763 OP_3_8 (void)
5764 {
5765 uint16 a = OP[0], b = OP[1];
5766 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
5767 OP_2_8 ();
5768 JMP(((GPR32(14)) << 1) & 0xffffff);
5769
5770 trace_output_void ();
5771 }
5772
5773 /* popret. */
5774 void
5775 OP_31E_10 (void)
5776 {
5777 uint32 tmp;
5778 trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
5779 OP_21E_10 ();
5780 tmp = (((GPR32(14)) << 1) & 0xffffff);
5781 /* If the resulting PC value is less than 0x00_0000 or greater
5782 than 0xFF_FFFF, this instruction causes an IAD trap.*/
5783
5784 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
5785 {
5786 State.exception = SIG_CR16_BUS;
5787 State.pc_changed = 1; /* Don't increment the PC. */
5788 trace_output_void ();
5789 return;
5790 }
5791 else
5792 JMP (tmp);
5793
5794 trace_output_32 (tmp);
5795 }
5796
5797
5798 /* cinv[i]. */
5799 void
5800 OP_A_10 (void)
5801 {
5802 trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID);
5803 SET_PSR_I (1);
5804 trace_output_void ();
5805 }
5806
5807 /* cinv[i,u]. */
5808 void
5809 OP_B_10 (void)
5810 {
5811 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5812 SET_PSR_I (1);
5813 trace_output_void ();
5814 }
5815
5816 /* cinv[d]. */
5817 void
5818 OP_C_10 (void)
5819 {
5820 trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID);
5821 SET_PSR_I (1);
5822 trace_output_void ();
5823 }
5824
5825 /* cinv[d,u]. */
5826 void
5827 OP_D_10 (void)
5828 {
5829 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5830 SET_PSR_I (1);
5831 trace_output_void ();
5832 }
5833
5834 /* cinv[d,i]. */
5835 void
5836 OP_E_10 (void)
5837 {
5838 trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID);
5839 SET_PSR_I (1);
5840 trace_output_void ();
5841 }
5842
5843 /* cinv[d,i,u]. */
5844 void
5845 OP_F_10 (void)
5846 {
5847 trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID);
5848 SET_PSR_I (1);
5849 trace_output_void ();
5850 }
5851
5852 /* retx. */
5853 void
5854 OP_3_10 (void)
5855 {
5856 trace_input ("retx", OP_VOID, OP_VOID, OP_VOID);
5857 SET_PSR_I (1);
5858 trace_output_void ();
5859 }
5860
5861 /* di. */
5862 void
5863 OP_4_10 (void)
5864 {
5865 trace_input ("di", OP_VOID, OP_VOID, OP_VOID);
5866 SET_PSR_I (1);
5867 trace_output_void ();
5868 }
5869
5870 /* ei. */
5871 void
5872 OP_5_10 (void)
5873 {
5874 trace_input ("ei", OP_VOID, OP_VOID, OP_VOID);
5875 SET_PSR_I (1);
5876 trace_output_void ();
5877 }
5878
5879 /* wait. */
5880 void
5881 OP_6_10 (void)
5882 {
5883 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
5884 State.exception = SIGTRAP;
5885 trace_output_void ();
5886 }
5887
5888 /* ewait. */
5889 void
5890 OP_7_10 (void)
5891 {
5892 trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID);
5893 SET_PSR_I (1);
5894 trace_output_void ();
5895 }
5896
5897 /* xorb. */
5898 void
5899 OP_28_8 (void)
5900 {
5901 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5902 trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
5903 tmp = a ^ b;
5904 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5905 trace_output_16 (tmp);
5906 }
5907
5908 /* xorb. */
5909 void
5910 OP_28B_C (void)
5911 {
5912 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5913 trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
5914 tmp = a ^ b;
5915 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5916 trace_output_16 (tmp);
5917 }
5918
5919 /* xorb. */
5920 void
5921 OP_29_8 (void)
5922 {
5923 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
5924 trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
5925 tmp = a ^ b;
5926 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5927 trace_output_16 (tmp);
5928 }
5929
5930 /* xorw. */
5931 void
5932 OP_2A_8 (void)
5933 {
5934 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5935 trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
5936 tmp = a ^ b;
5937 SET_GPR (OP[1], tmp);
5938 trace_output_16 (tmp);
5939 }
5940
5941 /* xorw. */
5942 void
5943 OP_2AB_C (void)
5944 {
5945 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5946 trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
5947 tmp = a ^ b;
5948 SET_GPR (OP[1], tmp);
5949 trace_output_16 (tmp);
5950 }
5951
5952 /* xorw. */
5953 void
5954 OP_2B_8 (void)
5955 {
5956 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
5957 trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
5958 tmp = a ^ b;
5959 SET_GPR (OP[1], tmp);
5960 trace_output_16 (tmp);
5961 }
5962
5963 /*REVISIT FOR LPR/SPR . */
5964
5965 /* lpr. */
5966 void
5967 OP_140_14 (void)
5968 {
5969 uint16 a = GPR (OP[0]);
5970 trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
5971 SET_CREG (OP[1], a);
5972 trace_output_16 (a);
5973 }
5974
5975 /* lprd. */
5976 void
5977 OP_141_14 (void)
5978 {
5979 uint32 a = GPR32 (OP[0]);
5980 trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
5981 SET_CREG (OP[1], a);
5982 trace_output_flag ();
5983 }
5984
5985 /* spr. */
5986 void
5987 OP_142_14 (void)
5988 {
5989 uint16 a = CREG (OP[0]);
5990 trace_input ("spr", OP_REG, OP_REG, OP_VOID);
5991 SET_GPR (OP[1], a);
5992 trace_output_16 (a);
5993 }
5994
5995 /* sprd. */
5996 void
5997 OP_143_14 (void)
5998 {
5999 uint32 a = CREG (OP[0]);
6000 trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
6001 SET_GPR32 (OP[1], a);
6002 trace_output_32 (a);
6003 }
6004
6005 /* null. */
6006 void
6007 OP_0_20 (void)
6008 {
6009 trace_input ("null", OP_VOID, OP_VOID, OP_VOID);
6010 State.exception = SIG_CR16_STOP;
6011 }
GDB Binutils - Deliverables
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