* common/genmloop.sh: Add new parameter: -shell to specify the
[deliverable/binutils-gdb.git] / sim / cris / Makefile.in
1 # Makefile template for Configure for the CRIS simulator, based on a mix
2 # of the ones for m32r and i960.
3 #
4 # Copyright (C) 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
5 # Contributed by Axis Communications.
6 #
7 # This program is free software; you can redistribute it and/or modify
8 # it under the terms of the GNU General Public License as published by
9 # the Free Software Foundation; either version 3 of the License, or
10 # (at your option) any later version.
11 #
12 # This program is distributed in the hope that it will be useful,
13 # but WITHOUT ANY WARRANTY; without even the implied warranty of
14 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 # GNU General Public License for more details.
16 #
17 # You should have received a copy of the GNU General Public License
18 # along with this program. If not, see <http://www.gnu.org/licenses/>.
19
20 ## COMMON_PRE_CONFIG_FRAG
21
22 CRISV10F_OBJS = crisv10f.o cpuv10.o decodev10.o modelv10.o mloopv10f.o
23 CRISV32F_OBJS = crisv32f.o cpuv32.o decodev32.o modelv32.o mloopv32f.o
24
25 CONFIG_DEVICES =
26
27 SIM_OBJS = \
28 $(SIM_NEW_COMMON_OBJS) \
29 sim-cpu.o \
30 sim-hload.o \
31 sim-hrw.o \
32 sim-model.o \
33 sim-reg.o \
34 cgen-utils.o cgen-trace.o cgen-scache.o \
35 cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
36 sim-if.o arch.o \
37 $(CRISV10F_OBJS) \
38 $(CRISV32F_OBJS) \
39 traps.o devices.o \
40 $(CONFIG_DEVICES) \
41 cris-desc.o
42
43 # Extra headers included by sim-main.h.
44 # FIXME: $(srccom)/cgen-ops.h should be in CGEN_INCLUDE_DEPS.
45 SIM_EXTRA_DEPS = \
46 $(CGEN_INCLUDE_DEPS) $(srccom)/cgen-ops.h \
47 arch.h cpuall.h cris-sim.h cris-desc.h
48
49 SIM_RUN_OBJS = nrun.o
50 SIM_EXTRA_CLEAN = cris-clean
51
52 # This selects the cris newlib/libgloss syscall definitions.
53 NL_TARGET = -DNL_TARGET_cris
54
55 ## COMMON_POST_CONFIG_FRAG
56
57 CGEN_CPU_DIR = $(CGENDIR)/../cpu
58
59 arch = cris
60
61 sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(sim-core_h) $(sim-options_h)
62
63 # Needs CPU-specific knowledge.
64 dv-cris.o: dv-cris.c $(SIM_MAIN_DEPS) $(sim-core_h)
65
66 # This is the same rule as dv-core.o etc.
67 dv-rv.o: dv-rv.c $(hw_main_headers) $(sim_main_headers)
68
69 arch.o: arch.c $(SIM_MAIN_DEPS)
70
71 traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS) $(sim-options_h)
72 devices.o: devices.c $(SIM_MAIN_DEPS)
73
74 # rvdummy is just used for testing. It does nothing if
75 # --enable-sim-hardware isn't active.
76
77 all: rvdummy$(EXEEXT)
78
79 check: rvdummy$(EXEEXT)
80
81 rvdummy$(EXEEXT): rvdummy.o $(EXTRA_LIBDEPS)
82 $(CC) $(ALL_CFLAGS) -o rvdummy$(EXEEXT) rvdummy.o $(EXTRA_LIBS)
83
84 rvdummy.o: rvdummy.c config.h tconfig.h $(remote_sim_h) $(callback_h)
85
86 # CRISV10 objs
87
88 CRISV10F_INCLUDE_DEPS = \
89 $(CGEN_MAIN_CPU_DEPS) \
90 cpuv10.h decodev10.h engv10.h
91
92 crisv10f.o: crisv10f.c cris-tmpl.c $(CRISV10F_INCLUDE_DEPS)
93
94 # FIXME: What is mono and what does "Use of `mono' is wip" mean (other
95 # than the apparent; some "mono" feature is work in progress)?
96 mloopv10f.c engv10.h: stamp-v10fmloop
97 stamp-v10fmloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
98 $(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
99 -mono -no-fast -pbb -switch semcrisv10f-switch.c \
100 -cpu crisv10f -infile $(srcdir)/mloop.in
101 $(SHELL) $(srcroot)/move-if-change eng.hin engv10.h
102 $(SHELL) $(srcroot)/move-if-change mloop.cin mloopv10f.c
103 touch stamp-v10fmloop
104 mloopv10f.o: mloopv10f.c semcrisv10f-switch.c $(CRISV10F_INCLUDE_DEPS)
105
106 cpuv10.o: cpuv10.c $(CRISV10F_INCLUDE_DEPS)
107 decodev10.o: decodev10.c $(CRISV10F_INCLUDE_DEPS)
108 modelv10.o: modelv10.c $(CRISV10F_INCLUDE_DEPS)
109
110 # CRISV32 objs
111
112 CRISV32F_INCLUDE_DEPS = \
113 $(CGEN_MAIN_CPU_DEPS) \
114 cpuv32.h decodev32.h engv32.h
115
116 crisv32f.o: crisv32f.c cris-tmpl.c $(CRISV32F_INCLUDE_DEPS)
117
118 # FIXME: What is mono and what does "Use of `mono' is wip" mean (other
119 # than the apparent; some "mono" feature is work in progress)?
120 mloopv32f.c engv32.h: stamp-v32fmloop
121 # We depend on stamp-v10fmloop to get serialization to avoid
122 # racing with it for the same temporary file-names when "make -j".
123 stamp-v32fmloop: stamp-v10fmloop $(srcdir)/../common/genmloop.sh mloop.in Makefile
124 $(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
125 -mono -no-fast -pbb -switch semcrisv32f-switch.c \
126 -cpu crisv32f -infile $(srcdir)/mloop.in
127 $(SHELL) $(srcroot)/move-if-change eng.hin engv32.h
128 $(SHELL) $(srcroot)/move-if-change mloop.cin mloopv32f.c
129 touch stamp-v32fmloop
130 mloopv32f.o: mloopv32f.c semcrisv32f-switch.c $(CRISV32F_INCLUDE_DEPS)
131
132 cpuv32.o: cpuv32.c $(CRISV32F_INCLUDE_DEPS)
133 decodev32.o: decodev32.c $(CRISV32F_INCLUDE_DEPS)
134 modelv32.o: modelv32.c $(CRISV32F_INCLUDE_DEPS)
135
136 cris-clean:
137 for v in 10 32; do \
138 rm -f mloopv$${v}f.c engv$${v}.h stamp-v$${v}fmloop; \
139 rm -f stamp-v$${v}fcpu; \
140 done
141 -rm -f stamp-arch stamp-desc
142 -rm -f tmp-*
143
144 # cgen support, enable with --enable-cgen-maint
145 CGEN_MAINT = ; @true
146 # The following line is commented in or out depending upon --enable-cgen-maint.
147 @CGEN_MAINT@CGEN_MAINT =
148
149 # Useful when making CGEN-generated files manually, without --enable-cgen-maint.
150 stamps: stamp-v10fmloop stamp-v32fmloop stamp-arch stamp-v10fcpu stamp-v32fcpu stamp-desc
151
152 stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/cris.cpu Makefile
153 $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=crisv10,crisv32 \
154 archfile=$(CGEN_CPU_DIR)/cris.cpu \
155 FLAGS="with-scache with-profile=fn"
156 touch stamp-arch
157 arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
158
159 # The sed-hack is supposed to be temporary, until we get CGEN to emit it.
160 stamp-v10fcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/cris.cpu Makefile
161 $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
162 archfile=$(CGEN_CPU_DIR)/cris.cpu \
163 cpu=crisv10f mach=crisv10 SUFFIX=v10 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"
164 $(SHELL) $(srcroot)/move-if-change $(srcdir)/semv10-switch.c $(srcdir)/semcrisv10f-switch.c
165 sed -ne 'p; s/^\(#include "sim-assert.h"\)$$/#include "cgen-ops.h"/p' < $(srcdir)/decodev10.c > decodev10.c.tmp
166 mv decodev10.c.tmp $(srcdir)/decodev10.c
167 touch stamp-v10fcpu
168 cpuv10.h cpuv10.c semcrisv10f-switch.c modelv10.c decodev10.c decodev10.h: $(CGEN_MAINT) stamp-v10fcpu
169
170 stamp-v32fcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/cris.cpu Makefile
171 $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
172 archfile=$(CGEN_CPU_DIR)/cris.cpu \
173 cpu=crisv32f mach=crisv32 SUFFIX=v32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"
174 $(SHELL) $(srcroot)/move-if-change $(srcdir)/semv32-switch.c $(srcdir)/semcrisv32f-switch.c
175 sed -ne 'p; s/^\(#include "sim-assert.h"\)$$/#include "cgen-ops.h"/p' < $(srcdir)/decodev32.c > decodev32.c.tmp
176 mv decodev32.c.tmp $(srcdir)/decodev32.c
177 touch stamp-v32fcpu
178 cpuv32.h cpuv32.c semcrisv32f-switch.c modelv32.c decodev32.c decodev32.h: $(CGEN_MAINT) stamp-v32fcpu
179
180 stamp-desc: $(CGEN_READ_SCM) $(CGEN_DESC_SCM) $(CGEN_CPU_DIR)/cris.cpu Makefile
181 $(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) \
182 archfile=$(CGEN_CPU_DIR)/cris.cpu \
183 cpu=cris mach=all
184 touch stamp-desc
185 cris-desc.c cris-desc.h cris-opc.h: $(CGEN_MAINT) stamp-desc
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