1 /* CPU family header for crisv10f.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996-2009 Free Software Foundation, Inc.
7 This file is part of the GNU simulators.
9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
25 #ifndef CPU_CRISV10F_H
26 #define CPU_CRISV10F_H
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 1
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 1
35 /* The size of an "int" needed to hold an instruction word.
36 This is usually 32 bits, but some architectures needs 64 bits. */
37 typedef CGEN_INSN_INT CGEN_INSN_WORD
;
39 #include "cgen-engine.h"
41 /* CPU state information. */
43 /* Hardware elements. */
47 #define GET_H_PC() CPU (h_pc)
50 CPU (h_pc) = ANDSI ((x), (~ (1)));\
52 /* General purpose registers */
54 #define GET_H_GR_REAL_PC(a1) CPU (h_gr_real_pc)[a1]
55 #define SET_H_GR_REAL_PC(a1, x) (CPU (h_gr_real_pc)[a1] = (x))
56 /* Special registers for v10 */
58 #define GET_H_SR_V10(index) (ORIF (ORIF (((index) == (((UINT) 0))), ((index) == (((UINT) 4)))), ((index) == (((UINT) 8))))) ? (0) : (((index) == (((UINT) 1)))) ? (10) : (ORIF (((index) == (((UINT) 5))), ((index) == (((UINT) 13))))) ? (ORSI (ANDSI (CPU (h_sr_v10[((UINT) 5)]), 0xffffff00), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 1), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 2), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 3), ORSI (SLLSI (ZEXTBISI (CPU (h_xbit)), 4), ORSI (SLLSI (ZEXTBISI (GET_H_IBIT ()), 5), ORSI (SLLSI (ZEXTBISI (GET_H_UBIT ()), 6), ORSI (SLLSI (ZEXTBISI (CPU (h_pbit)), 7), 0)))))))))) : (CPU (h_sr_v10[index]))
59 #define SET_H_SR_V10(index, x) \
61 if (ORIF (ORIF ((((index)) == (((UINT) 0))), (((index)) == (((UINT) 4)))), ORIF ((((index)) == (((UINT) 8))), (((index)) == (((UINT) 1)))))) {\
64 else if (ORIF ((((index)) == (((UINT) 5))), (((index)) == (((UINT) 13))))) {\
66 CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\
67 CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\
68 CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\
69 CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\
70 CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\
71 SET_H_IBIT (((NESI (ANDSI ((x), ((1) << (5))), 0)) ? (1) : (0)));\
72 SET_H_UBIT (((NESI (ANDSI ((x), ((1) << (6))), 0)) ? (1) : (0)));\
73 CPU (h_pbit) = ((NESI (ANDSI ((x), ((1) << (7))), 0)) ? (1) : (0));\
74 CPU (h_sr_v10[((UINT) 5)]) = (x);\
75 CPU (h_sr_v10[((UINT) 13)]) = (x);\
79 CPU (h_sr_v10[(index)]) = (x);\
84 #define GET_H_CBIT() CPU (h_cbit)
85 #define SET_H_CBIT(x) (CPU (h_cbit) = (x))
88 #define GET_H_VBIT() CPU (h_vbit)
89 #define SET_H_VBIT(x) (CPU (h_vbit) = (x))
92 #define GET_H_ZBIT() CPU (h_zbit)
93 #define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
96 #define GET_H_NBIT() CPU (h_nbit)
97 #define SET_H_NBIT(x) (CPU (h_nbit) = (x))
98 /* extended-arithmetic bit */
100 #define GET_H_XBIT() CPU (h_xbit)
101 #define SET_H_XBIT(x) (CPU (h_xbit) = (x))
102 /* interrupt-enable bit */
104 #define GET_H_IBIT_PRE_V32() CPU (h_ibit_pre_v32)
105 #define SET_H_IBIT_PRE_V32(x) (CPU (h_ibit_pre_v32) = (x))
106 /* sequence-broken bit */
108 #define GET_H_PBIT() CPU (h_pbit)
109 #define SET_H_PBIT(x) (CPU (h_pbit) = (x))
112 #define GET_H_UBIT_PRE_V32() CPU (h_ubit_pre_v32)
113 #define SET_H_UBIT_PRE_V32(x) (CPU (h_ubit_pre_v32) = (x))
114 /* instruction-is-prefixed bit */
115 BI h_insn_prefixed_p_pre_v32
;
116 #define GET_H_INSN_PREFIXED_P_PRE_V32() CPU (h_insn_prefixed_p_pre_v32)
117 #define SET_H_INSN_PREFIXED_P_PRE_V32(x) (CPU (h_insn_prefixed_p_pre_v32) = (x))
118 /* Prefix-address register */
119 SI h_prefixreg_pre_v32
;
120 #define GET_H_PREFIXREG_PRE_V32() CPU (h_prefixreg_pre_v32)
121 #define SET_H_PREFIXREG_PRE_V32(x) (CPU (h_prefixreg_pre_v32) = (x))
123 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
128 #define GET_H_V32_NON_V32() 0
129 #define SET_H_V32_NON_V32(x) \
131 cgen_rtx_error (current_cpu, "Can't set h-v32");\
133 #define GET_H_GR(index) GET_H_GR_PC (index)
134 #define SET_H_GR(index, x) \
136 SET_H_GR_PC ((index), (x));\
138 #define GET_H_GR_PC(index) ((((index) == (15))) ? ((cgen_rtx_error (current_cpu, "General register read of PC is not implemented."), 0)) : (CPU (h_gr_real_pc[index])))
139 #define SET_H_GR_PC(index, x) \
142 if ((((index)) == (15))) {\
143 cgen_rtx_error (current_cpu, "General register write to PC is not implemented.");\
145 CPU (h_gr_real_pc[(index)]) = (x);\
148 #define GET_H_RAW_GR_PC(index) CPU (h_gr_real_pc[index])
149 #define SET_H_RAW_GR_PC(index, x) \
151 CPU (h_gr_real_pc[(index)]) = (x);\
153 #define GET_H_SR(index) GET_H_SR_V10 (index)
154 #define SET_H_SR(index, x) \
156 SET_H_SR_V10 ((index), (x));\
158 #define GET_H_CBIT_MOVE() GET_H_CBIT_MOVE_PRE_V32 ()
159 #define SET_H_CBIT_MOVE(x) \
161 SET_H_CBIT_MOVE_PRE_V32 ((x));\
163 #define GET_H_CBIT_MOVE_PRE_V32() CPU (h_cbit)
164 #define SET_H_CBIT_MOVE_PRE_V32(x) \
168 #define GET_H_VBIT_MOVE() GET_H_VBIT_MOVE_PRE_V32 ()
169 #define SET_H_VBIT_MOVE(x) \
171 SET_H_VBIT_MOVE_PRE_V32 ((x));\
173 #define GET_H_VBIT_MOVE_PRE_V32() CPU (h_vbit)
174 #define SET_H_VBIT_MOVE_PRE_V32(x) \
178 #define GET_H_ZBIT_MOVE() GET_H_ZBIT_MOVE_PRE_V32 ()
179 #define SET_H_ZBIT_MOVE(x) \
181 SET_H_ZBIT_MOVE_PRE_V32 ((x));\
183 #define GET_H_ZBIT_MOVE_PRE_V32() CPU (h_zbit)
184 #define SET_H_ZBIT_MOVE_PRE_V32(x) \
188 #define GET_H_NBIT_MOVE() GET_H_NBIT_MOVE_PRE_V32 ()
189 #define SET_H_NBIT_MOVE(x) \
191 SET_H_NBIT_MOVE_PRE_V32 ((x));\
193 #define GET_H_NBIT_MOVE_PRE_V32() CPU (h_nbit)
194 #define SET_H_NBIT_MOVE_PRE_V32(x) \
198 #define GET_H_IBIT() CPU (h_ibit_pre_v32)
199 #define SET_H_IBIT(x) \
201 CPU (h_ibit_pre_v32) = (x);\
203 #define GET_H_UBIT() CPU (h_ubit_pre_v32)
204 #define SET_H_UBIT(x) \
206 CPU (h_ubit_pre_v32) = (x);\
208 #define GET_H_INSN_PREFIXED_P() CPU (h_insn_prefixed_p_pre_v32)
209 #define SET_H_INSN_PREFIXED_P(x) \
211 CPU (h_insn_prefixed_p_pre_v32) = (x);\
214 /* Cover fns for register access. */
215 BI
crisv10f_h_v32_non_v32_get (SIM_CPU
*);
216 void crisv10f_h_v32_non_v32_set (SIM_CPU
*, BI
);
217 USI
crisv10f_h_pc_get (SIM_CPU
*);
218 void crisv10f_h_pc_set (SIM_CPU
*, USI
);
219 SI
crisv10f_h_gr_get (SIM_CPU
*, UINT
);
220 void crisv10f_h_gr_set (SIM_CPU
*, UINT
, SI
);
221 SI
crisv10f_h_gr_pc_get (SIM_CPU
*, UINT
);
222 void crisv10f_h_gr_pc_set (SIM_CPU
*, UINT
, SI
);
223 SI
crisv10f_h_gr_real_pc_get (SIM_CPU
*, UINT
);
224 void crisv10f_h_gr_real_pc_set (SIM_CPU
*, UINT
, SI
);
225 SI
crisv10f_h_raw_gr_pc_get (SIM_CPU
*, UINT
);
226 void crisv10f_h_raw_gr_pc_set (SIM_CPU
*, UINT
, SI
);
227 SI
crisv10f_h_sr_get (SIM_CPU
*, UINT
);
228 void crisv10f_h_sr_set (SIM_CPU
*, UINT
, SI
);
229 SI
crisv10f_h_sr_v10_get (SIM_CPU
*, UINT
);
230 void crisv10f_h_sr_v10_set (SIM_CPU
*, UINT
, SI
);
231 BI
crisv10f_h_cbit_get (SIM_CPU
*);
232 void crisv10f_h_cbit_set (SIM_CPU
*, BI
);
233 BI
crisv10f_h_cbit_move_get (SIM_CPU
*);
234 void crisv10f_h_cbit_move_set (SIM_CPU
*, BI
);
235 BI
crisv10f_h_cbit_move_pre_v32_get (SIM_CPU
*);
236 void crisv10f_h_cbit_move_pre_v32_set (SIM_CPU
*, BI
);
237 BI
crisv10f_h_vbit_get (SIM_CPU
*);
238 void crisv10f_h_vbit_set (SIM_CPU
*, BI
);
239 BI
crisv10f_h_vbit_move_get (SIM_CPU
*);
240 void crisv10f_h_vbit_move_set (SIM_CPU
*, BI
);
241 BI
crisv10f_h_vbit_move_pre_v32_get (SIM_CPU
*);
242 void crisv10f_h_vbit_move_pre_v32_set (SIM_CPU
*, BI
);
243 BI
crisv10f_h_zbit_get (SIM_CPU
*);
244 void crisv10f_h_zbit_set (SIM_CPU
*, BI
);
245 BI
crisv10f_h_zbit_move_get (SIM_CPU
*);
246 void crisv10f_h_zbit_move_set (SIM_CPU
*, BI
);
247 BI
crisv10f_h_zbit_move_pre_v32_get (SIM_CPU
*);
248 void crisv10f_h_zbit_move_pre_v32_set (SIM_CPU
*, BI
);
249 BI
crisv10f_h_nbit_get (SIM_CPU
*);
250 void crisv10f_h_nbit_set (SIM_CPU
*, BI
);
251 BI
crisv10f_h_nbit_move_get (SIM_CPU
*);
252 void crisv10f_h_nbit_move_set (SIM_CPU
*, BI
);
253 BI
crisv10f_h_nbit_move_pre_v32_get (SIM_CPU
*);
254 void crisv10f_h_nbit_move_pre_v32_set (SIM_CPU
*, BI
);
255 BI
crisv10f_h_xbit_get (SIM_CPU
*);
256 void crisv10f_h_xbit_set (SIM_CPU
*, BI
);
257 BI
crisv10f_h_ibit_get (SIM_CPU
*);
258 void crisv10f_h_ibit_set (SIM_CPU
*, BI
);
259 BI
crisv10f_h_ibit_pre_v32_get (SIM_CPU
*);
260 void crisv10f_h_ibit_pre_v32_set (SIM_CPU
*, BI
);
261 BI
crisv10f_h_pbit_get (SIM_CPU
*);
262 void crisv10f_h_pbit_set (SIM_CPU
*, BI
);
263 BI
crisv10f_h_ubit_get (SIM_CPU
*);
264 void crisv10f_h_ubit_set (SIM_CPU
*, BI
);
265 BI
crisv10f_h_ubit_pre_v32_get (SIM_CPU
*);
266 void crisv10f_h_ubit_pre_v32_set (SIM_CPU
*, BI
);
267 BI
crisv10f_h_insn_prefixed_p_get (SIM_CPU
*);
268 void crisv10f_h_insn_prefixed_p_set (SIM_CPU
*, BI
);
269 BI
crisv10f_h_insn_prefixed_p_pre_v32_get (SIM_CPU
*);
270 void crisv10f_h_insn_prefixed_p_pre_v32_set (SIM_CPU
*, BI
);
271 SI
crisv10f_h_prefixreg_pre_v32_get (SIM_CPU
*);
272 void crisv10f_h_prefixreg_pre_v32_set (SIM_CPU
*, SI
);
274 /* These must be hand-written. */
275 extern CPUREG_FETCH_FN crisv10f_fetch_register
;
276 extern CPUREG_STORE_FN crisv10f_store_register
;
280 } MODEL_CRISV10_DATA
;
282 /* Instruction argument buffer. */
285 struct { /* no operands */
295 IADDR i_o_word_pcrel
;
304 unsigned char in_h_gr_SI_14
;
305 unsigned char out_h_gr_SI_14
;
306 } sfmt_move_m_spplus_p8
;
313 INT f_indir_pc__dword
;
315 unsigned char out_Pd
;
316 } sfmt_move_c_sprv10_p9
;
318 INT f_indir_pc__word
;
320 unsigned char out_Pd
;
321 } sfmt_move_c_sprv10_p5
;
325 unsigned char out_Rd
;
328 INT f_indir_pc__dword
;
331 unsigned char out_Rd
;
334 INT f_indir_pc__word
;
337 unsigned char out_Rd
;
340 INT f_indir_pc__byte
;
343 unsigned char out_Rd
;
349 unsigned char out_Rd
;
355 unsigned char out_h_gr_SI_index_of__INT_Rd
;
358 INT f_indir_pc__dword
;
361 unsigned char out_h_gr_SI_index_of__INT_Rd
;
364 INT f_indir_pc__word
;
367 unsigned char out_h_gr_SI_index_of__INT_Rd
;
370 INT f_indir_pc__byte
;
373 unsigned char out_h_gr_SI_index_of__INT_Rd
;
379 unsigned char out_h_gr_SI_index_of__INT_Rs
;
380 } sfmt_move_spr_rv10
;
385 unsigned char out_h_gr_SI_index_of__INT_Rd
;
392 unsigned char out_h_gr_SI_index_of__INT_Rd
;
399 unsigned char out_Rd
;
400 unsigned char out_h_sr_SI_7
;
408 unsigned char out_Rs
;
409 } sfmt_move_spr_mv10
;
415 unsigned char out_Pd
;
416 unsigned char out_Rs
;
417 } sfmt_move_m_sprv10
;
424 unsigned char out_Rd
;
425 unsigned char out_Rs
;
433 unsigned char out_Rs
;
434 unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__UINT_inc_index_of__INT_Rs_index_of__INT_Rd
;
442 unsigned char out_Rs
;
443 unsigned char out_h_gr_SI_0
;
444 unsigned char out_h_gr_SI_1
;
445 unsigned char out_h_gr_SI_10
;
446 unsigned char out_h_gr_SI_11
;
447 unsigned char out_h_gr_SI_12
;
448 unsigned char out_h_gr_SI_13
;
449 unsigned char out_h_gr_SI_14
;
450 unsigned char out_h_gr_SI_2
;
451 unsigned char out_h_gr_SI_3
;
452 unsigned char out_h_gr_SI_4
;
453 unsigned char out_h_gr_SI_5
;
454 unsigned char out_h_gr_SI_6
;
455 unsigned char out_h_gr_SI_7
;
456 unsigned char out_h_gr_SI_8
;
457 unsigned char out_h_gr_SI_9
;
465 unsigned char in_h_gr_SI_0
;
466 unsigned char in_h_gr_SI_1
;
467 unsigned char in_h_gr_SI_10
;
468 unsigned char in_h_gr_SI_11
;
469 unsigned char in_h_gr_SI_12
;
470 unsigned char in_h_gr_SI_13
;
471 unsigned char in_h_gr_SI_14
;
472 unsigned char in_h_gr_SI_15
;
473 unsigned char in_h_gr_SI_2
;
474 unsigned char in_h_gr_SI_3
;
475 unsigned char in_h_gr_SI_4
;
476 unsigned char in_h_gr_SI_5
;
477 unsigned char in_h_gr_SI_6
;
478 unsigned char in_h_gr_SI_7
;
479 unsigned char in_h_gr_SI_8
;
480 unsigned char in_h_gr_SI_9
;
481 unsigned char out_Rs
;
484 /* Writeback handler. */
486 /* Pointer to argbuf entry for insn whose results need writing back. */
487 const struct argbuf
*abuf
;
489 /* x-before handler */
491 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
494 /* x-after handler */
498 /* This entry is used to terminate each pbb. */
500 /* Number of insns in pbb. */
502 /* Next pbb to execute. */
504 SCACHE
*branch_target
;
509 /* The ARGBUF struct. */
511 /* These are the baseclass definitions. */
516 /* ??? Temporary hack for skip insns. */
519 /* cpu specific data follows */
522 union sem_fields fields
;
527 ??? SCACHE used to contain more than just argbuf. We could delete the
528 type entirely and always just use ARGBUF, but for future concerns and as
529 a level of abstraction it is left in. */
532 struct argbuf argbuf
;
535 /* Macros to simplify extraction, reading and semantic code.
536 These define and assign the local vars that contain the insn's fields. */
538 #define EXTRACT_IFMT_EMPTY_VARS \
540 #define EXTRACT_IFMT_EMPTY_CODE \
543 #define EXTRACT_IFMT_NOP_VARS \
550 #define EXTRACT_IFMT_NOP_CODE \
552 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
553 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
554 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
555 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
556 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
558 #define EXTRACT_IFMT_MOVE_B_R_VARS \
565 #define EXTRACT_IFMT_MOVE_B_R_CODE \
567 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
568 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
569 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
570 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
571 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
573 #define EXTRACT_IFMT_MOVEPCR_VARS \
580 #define EXTRACT_IFMT_MOVEPCR_CODE \
582 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
583 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
584 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
585 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
586 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
588 #define EXTRACT_IFMT_MOVEQ_VARS \
594 #define EXTRACT_IFMT_MOVEQ_CODE \
596 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
597 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
598 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
599 f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6); \
601 #define EXTRACT_IFMT_MOVECBR_VARS \
603 INT f_indir_pc__byte; \
608 /* Contents of trailing part of insn. */ \
611 #define EXTRACT_IFMT_MOVECBR_CODE \
613 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
614 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
615 f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
616 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
617 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
618 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
619 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
621 #define EXTRACT_IFMT_MOVECWR_VARS \
623 INT f_indir_pc__word; \
628 /* Contents of trailing part of insn. */ \
631 #define EXTRACT_IFMT_MOVECWR_CODE \
633 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
634 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
635 f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
636 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
637 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
638 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
639 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
641 #define EXTRACT_IFMT_MOVECDR_VARS \
642 INT f_indir_pc__dword; \
648 /* Contents of trailing part of insn. */ \
651 #define EXTRACT_IFMT_MOVECDR_CODE \
653 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
654 f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
655 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
656 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
657 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
658 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
659 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
661 #define EXTRACT_IFMT_MOVUCBR_VARS \
663 INT f_indir_pc__byte; \
668 /* Contents of trailing part of insn. */ \
671 #define EXTRACT_IFMT_MOVUCBR_CODE \
673 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
674 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
675 f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
676 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
677 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
678 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
679 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
681 #define EXTRACT_IFMT_MOVUCWR_VARS \
683 INT f_indir_pc__word; \
688 /* Contents of trailing part of insn. */ \
691 #define EXTRACT_IFMT_MOVUCWR_CODE \
693 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
694 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
695 f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
696 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
697 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
698 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
699 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
701 #define EXTRACT_IFMT_ADDQ_VARS \
707 #define EXTRACT_IFMT_ADDQ_CODE \
709 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
710 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
711 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
712 f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6); \
714 #define EXTRACT_IFMT_CMP_M_B_M_VARS \
722 #define EXTRACT_IFMT_CMP_M_B_M_CODE \
724 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
725 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
726 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
727 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
728 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
729 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
731 #define EXTRACT_IFMT_MOVE_R_SPRV10_VARS \
738 #define EXTRACT_IFMT_MOVE_R_SPRV10_CODE \
740 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
741 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
742 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
743 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
744 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
746 #define EXTRACT_IFMT_MOVE_SPR_RV10_VARS \
753 #define EXTRACT_IFMT_MOVE_SPR_RV10_CODE \
755 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
756 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
757 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
758 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
759 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
761 #define EXTRACT_IFMT_RET_TYPE_VARS \
768 #define EXTRACT_IFMT_RET_TYPE_CODE \
770 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
771 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
772 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
773 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
774 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
776 #define EXTRACT_IFMT_MOVE_M_SPRV10_VARS \
784 #define EXTRACT_IFMT_MOVE_M_SPRV10_CODE \
786 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
787 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
788 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
789 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
790 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
791 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
793 #define EXTRACT_IFMT_MOVE_C_SPRV10_P5_VARS \
795 INT f_indir_pc__word; \
800 /* Contents of trailing part of insn. */ \
803 #define EXTRACT_IFMT_MOVE_C_SPRV10_P5_CODE \
805 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
806 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
807 f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
808 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
809 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
810 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
811 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
813 #define EXTRACT_IFMT_MOVE_C_SPRV10_P9_VARS \
814 INT f_indir_pc__dword; \
820 /* Contents of trailing part of insn. */ \
823 #define EXTRACT_IFMT_MOVE_C_SPRV10_P9_CODE \
825 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
826 f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
827 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
828 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
829 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
830 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
831 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
833 #define EXTRACT_IFMT_MOVE_SPR_MV10_VARS \
841 #define EXTRACT_IFMT_MOVE_SPR_MV10_CODE \
843 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
844 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
845 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
846 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
847 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
848 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
850 #define EXTRACT_IFMT_SBFS_VARS \
858 #define EXTRACT_IFMT_SBFS_CODE \
860 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
861 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
862 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
863 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
864 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
865 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
867 #define EXTRACT_IFMT_SWAP_VARS \
874 #define EXTRACT_IFMT_SWAP_CODE \
876 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
877 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
878 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
879 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
880 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
882 #define EXTRACT_IFMT_ASRQ_VARS \
889 #define EXTRACT_IFMT_ASRQ_CODE \
891 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
892 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
893 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
894 f_b5 = EXTRACT_LSB0_UINT (insn, 16, 5, 1); \
895 f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5); \
897 #define EXTRACT_IFMT_SETF_VARS \
905 #define EXTRACT_IFMT_SETF_CODE \
907 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
908 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
909 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
910 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
911 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
912 f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));\
914 #define EXTRACT_IFMT_BCC_B_VARS \
922 #define EXTRACT_IFMT_BCC_B_CODE \
924 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
925 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
926 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
927 f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
928 f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
932 tmp_abslo = ((f_disp9_lo) << (1));\
933 tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
934 f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\
937 #define EXTRACT_IFMT_BA_B_VARS \
945 #define EXTRACT_IFMT_BA_B_CODE \
947 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
948 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
949 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
950 f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
951 f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
955 tmp_abslo = ((f_disp9_lo) << (1));\
956 tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
957 f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\
960 #define EXTRACT_IFMT_BCC_W_VARS \
962 SI f_indir_pc__word_pcrel; \
967 /* Contents of trailing part of insn. */ \
970 #define EXTRACT_IFMT_BCC_W_CODE \
972 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
973 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
974 f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \
975 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
976 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
977 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
978 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
980 #define EXTRACT_IFMT_BA_W_VARS \
982 SI f_indir_pc__word_pcrel; \
987 /* Contents of trailing part of insn. */ \
990 #define EXTRACT_IFMT_BA_W_CODE \
992 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
993 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
994 f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \
995 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
996 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
997 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
998 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1000 #define EXTRACT_IFMT_JUMP_C_VARS \
1001 INT f_indir_pc__dword; \
1007 /* Contents of trailing part of insn. */ \
1009 unsigned int length;
1010 #define EXTRACT_IFMT_JUMP_C_CODE \
1012 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
1013 f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
1014 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1015 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1016 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1017 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1018 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1020 #define EXTRACT_IFMT_BREAK_VARS \
1026 unsigned int length;
1027 #define EXTRACT_IFMT_BREAK_CODE \
1029 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1030 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1031 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1032 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1033 f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1035 #define EXTRACT_IFMT_SCC_VARS \
1041 unsigned int length;
1042 #define EXTRACT_IFMT_SCC_CODE \
1044 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1045 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1046 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1047 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1048 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1050 #define EXTRACT_IFMT_ADDOQ_VARS \
1055 unsigned int length;
1056 #define EXTRACT_IFMT_ADDOQ_CODE \
1058 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1059 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1060 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1061 f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
1063 #define EXTRACT_IFMT_BDAPQPC_VARS \
1068 unsigned int length;
1069 #define EXTRACT_IFMT_BDAPQPC_CODE \
1071 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1072 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1073 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1074 f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
1076 /* Collection of various things for the trace handler to use. */
1078 typedef struct trace_record
{
1083 #endif /* CPU_CRISV10F_H */