sim/cris/cpuv32.h

   1 /* CPU family header for crisv32f.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2005 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 3 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21
  22 */
  23
  24 #ifndef CPU_CRISV32F_H
  25 #define CPU_CRISV32F_H
  26
  27 /* Maximum number of instructions that are fetched at a time.
  28    This is for LIW type instructions sets (e.g. m32r).  */
  29 #define MAX_LIW_INSNS 1
  30
  31 /* Maximum number of instructions that can be executed in parallel.  */
  32 #define MAX_PARALLEL_INSNS 1
  33
  34 /* CPU state information.  */
  35 typedef struct {
  36   /* Hardware elements.  */
  37   struct {
  38   /* program counter */
  39   USI h_pc;
  40 #define GET_H_PC() CPU (h_pc)
  41 #define SET_H_PC(x) \
  42 do { \
  43 CPU (h_pc) = ANDSI ((x), (~ (1)));\
  44 ;} while (0)
  45   /* General purpose registers */
  46   SI h_gr_acr[16];
  47 #define GET_H_GR_ACR(a1) CPU (h_gr_acr)[a1]
  48 #define SET_H_GR_ACR(a1, x) (CPU (h_gr_acr)[a1] = (x))
  49   /* Special registers for v32 */
  50   SI h_sr_v32[16];
  51 #define GET_H_SR_V32(index) (ORIF (ORIF (((index) == (((UINT) 0))), ((index) == (((UINT) 4)))), ((index) == (((UINT) 8))))) ? (0) : (((index) == (((UINT) 1)))) ? (32) : (((index) == (((UINT) 13)))) ? (ORSI (ANDSI (CPU (h_sr_v32[((UINT) 13)]), 1073740800), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 1), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 2), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 3), ORSI (SLLSI (ZEXTBISI (CPU (h_xbit)), 4), ORSI (SLLSI (ZEXTBISI (GET_H_IBIT ()), 5), ORSI (SLLSI (ZEXTBISI (GET_H_UBIT ()), 6), ORSI (SLLSI (ZEXTBISI (CPU (h_pbit)), 7), ORSI (SLLSI (ZEXTBISI (CPU (h_rbit)), 8), ORSI (SLLSI (ZEXTBISI (CPU (h_sbit)), 9), ORSI (SLLSI (ZEXTBISI (CPU (h_mbit)), 30), ORSI (SLLSI (ZEXTBISI (CPU (h_qbit)), 31), 0)))))))))))))) : (((index) == (((UINT) 14)))) ? (((GET_H_UBIT ()) ? (CPU (h_gr_acr[((UINT) 14)])) : (CPU (h_sr_v32[((UINT) 14)])))) : (CPU (h_sr_v32[index]))
  52 #define SET_H_SR_V32(index, x) \
  53 do { \
  54 if (ORIF (ORIF ((((index)) == (((UINT) 0))), (((index)) == (((UINT) 4)))), ORIF ((((index)) == (((UINT) 8))), (((index)) == (((UINT) 1)))))) {\
  55 ((void) 0); /*nop*/\
  56 }\
  57  else if ((((index)) == (((UINT) 13)))) {\
  58 {\
  59 CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\
  60 CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\
  61 CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\
  62 CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\
  63 CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\
  64 SET_H_IBIT (((NESI (ANDSI ((x), ((1) << (5))), 0)) ? (1) : (0)));\
  65 SET_H_SBIT (((NESI (ANDSI ((x), ((1) << (9))), 0)) ? (1) : (0)));\
  66 SET_H_MBIT (((NESI (ANDSI ((x), ((1) << (30))), 0)) ? (1) : (0)));\
  67 CPU (h_pbit) = ((NESI (ANDSI ((x), ((1) << (7))), 0)) ? (1) : (0));\
  68 CPU (h_rbit) = ((NESI (ANDSI ((x), ((1) << (8))), 0)) ? (1) : (0));\
  69 SET_H_QBIT (((NESI (ANDSI ((x), ((1) << (31))), 0)) ? (1) : (0)));\
  70 SET_H_UBIT (((NESI (ANDSI ((x), ((1) << (6))), 0)) ? (1) : (0)));\
  71 CPU (h_sr_v32[(index)]) = (x);\
  72 }\
  73 }\
  74  else if ((((index)) == (((UINT) 14)))) {\
  75 {\
  76 if (GET_H_UBIT ()) {\
  77 CPU (h_gr_acr[((UINT) 14)]) = (x);\
  78 }\
  79 CPU (h_sr_v32[((UINT) 14)]) = (x);\
  80 }\
  81 }\
  82  else if ((((index)) == (((UINT) 3)))) {\
  83 if (NOTBI (GET_H_UBIT ())) {\
  84 CPU (h_sr_v32[((UINT) 3)]) = (x);\
  85 }\
  86 }\
  87  else if ((((index)) == (((UINT) 9)))) {\
  88 if (NOTBI (GET_H_UBIT ())) {\
  89 CPU (h_sr_v32[((UINT) 9)]) = (x);\
  90 }\
  91 }\
  92  else if ((((index)) == (((UINT) 2)))) {\
  93 if (NOTBI (GET_H_UBIT ())) {\
  94 {\
  95 crisv32f_write_pid_handler (current_cpu, (x));\
  96 CPU (h_sr_v32[((UINT) 2)]) = (x);\
  97 }\
  98 }\
  99 }\
 100  else if ((((index)) == (((UINT) 15)))) {\
 101 if (NOTBI (GET_H_UBIT ())) {\
 102 CPU (h_sr_v32[((UINT) 15)]) = (x);\
 103 }\
 104 }\
 105  else {\
 106 CPU (h_sr_v32[(index)]) = (x);\
 107 }\
 108 ;} while (0)
 109   /* carry bit */
 110   BI h_cbit;
 111 #define GET_H_CBIT() CPU (h_cbit)
 112 #define SET_H_CBIT(x) (CPU (h_cbit) = (x))
 113   /* overflow bit */
 114   BI h_vbit;
 115 #define GET_H_VBIT() CPU (h_vbit)
 116 #define SET_H_VBIT(x) (CPU (h_vbit) = (x))
 117   /* zero bit */
 118   BI h_zbit;
 119 #define GET_H_ZBIT() CPU (h_zbit)
 120 #define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
 121   /* sign bit */
 122   BI h_nbit;
 123 #define GET_H_NBIT() CPU (h_nbit)
 124 #define SET_H_NBIT(x) (CPU (h_nbit) = (x))
 125   /* extended-arithmetic bit */
 126   BI h_xbit;
 127 #define GET_H_XBIT() CPU (h_xbit)
 128 #define SET_H_XBIT(x) (CPU (h_xbit) = (x))
 129   /* sequence-broken bit */
 130   BI h_pbit;
 131 #define GET_H_PBIT() CPU (h_pbit)
 132 #define SET_H_PBIT(x) (CPU (h_pbit) = (x))
 133   /* carry bit for MCP+restore-p bit */
 134   BI h_rbit;
 135 #define GET_H_RBIT() CPU (h_rbit)
 136 #define SET_H_RBIT(x) (CPU (h_rbit) = (x))
 137   /* guru mode bit */
 138   BI h_gbit;
 139 #define GET_H_GBIT() CPU (h_gbit)
 140 #define SET_H_GBIT(x) (CPU (h_gbit) = (x))
 141   /* Kernel stack pointer during user mode */
 142   SI h_kernel_sp;
 143 #define GET_H_KERNEL_SP() CPU (h_kernel_sp)
 144 #define SET_H_KERNEL_SP(x) (CPU (h_kernel_sp) = (x))
 145   /* User mode bit */
 146   BI h_ubit_v32;
 147 #define GET_H_UBIT_V32() CPU (h_ubit_v32)
 148 #define SET_H_UBIT_V32(x) \
 149 do { \
 150 {\
 151 if (ANDIF ((x), NOTBI (CPU (h_ubit_v32)))) {\
 152 {\
 153 CPU (h_kernel_sp) = CPU (h_gr_acr[((UINT) 14)]);\
 154 CPU (h_gr_acr[((UINT) 14)]) = CPU (h_sr_v32[((UINT) 14)]);\
 155 CPU (h_ubit_v32) = (x);\
 156 crisv32f_usermode_enabled (current_cpu);\
 157 }\
 158 }\
 159 }\
 160 ;} while (0)
 161   /* Interrupt-enable bit */
 162   BI h_ibit_v32;
 163 #define GET_H_IBIT_V32() CPU (h_ibit_v32)
 164 #define SET_H_IBIT_V32(x) \
 165 do { \
 166 {\
 167 if (NOTBI (GET_H_UBIT ())) {\
 168 {\
 169   BI tmp_enabled;\
 170   tmp_enabled = ANDIF ((x), NOTBI (CPU (h_ibit_v32)));\
 171 CPU (h_ibit_v32) = (x);\
 172 if (tmp_enabled) {\
 173 crisv32f_interrupts_enabled (current_cpu);\
 174 }\
 175 }\
 176 }\
 177 }\
 178 ;} while (0)
 179   /* NMI enable bit */
 180   BI h_mbit;
 181 #define GET_H_MBIT() CPU (h_mbit)
 182 #define SET_H_MBIT(x) \
 183 do { \
 184 {\
 185 if (ANDIF ((x), ANDIF (NOTBI (CPU (h_mbit)), NOTBI (GET_H_UBIT ())))) {\
 186 {\
 187 CPU (h_mbit) = 1;\
 188 crisv32f_nmi_enabled (current_cpu);\
 189 }\
 190 }\
 191 }\
 192 ;} while (0)
 193   /* Pending single-step bit */
 194   BI h_qbit;
 195 #define GET_H_QBIT() CPU (h_qbit)
 196 #define SET_H_QBIT(x) \
 197 do { \
 198 {\
 199 if (NOTBI (GET_H_UBIT ())) {\
 200 CPU (h_qbit) = (x);\
 201 }\
 202 }\
 203 ;} while (0)
 204   /* Cause single step exception on ... [see CRISv32 ref] bit */
 205   BI h_sbit;
 206 #define GET_H_SBIT() CPU (h_sbit)
 207 #define SET_H_SBIT(x) \
 208 do { \
 209 {\
 210 if (NOTBI (GET_H_UBIT ())) {\
 211 {\
 212   BI tmp_enabled;\
 213   tmp_enabled = ANDIF ((x), NOTBI (CPU (h_sbit)));\
 214 CPU (h_sbit) = (x);\
 215 if (tmp_enabled) {\
 216 crisv32f_single_step_enabled (current_cpu);\
 217 }\
 218 }\
 219 }\
 220 }\
 221 ;} while (0)
 222   } hardware;
 223 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
 224 } CRISV32F_CPU_DATA;
 225
 226 /* Virtual regs.  */
 227
 228 #define GET_H_V32_V32() 1
 229 #define SET_H_V32_V32(x) \
 230 do { \
 231 cgen_rtx_error (current_cpu, "Can't set h-v32");\
 232 ;} while (0)
 233 #define GET_H_GR(index) CPU (h_gr_acr[index])
 234 #define SET_H_GR(index, x) \
 235 do { \
 236 CPU (h_gr_acr[(index)]) = (x);\
 237 ;} while (0)
 238 #define GET_H_RAW_GR_ACR(index) CPU (h_gr_acr[index])
 239 #define SET_H_RAW_GR_ACR(index, x) \
 240 do { \
 241 CPU (h_gr_acr[(index)]) = (x);\
 242 ;} while (0)
 243 #define GET_H_SR(index) GET_H_SR_V32 (index)
 244 #define SET_H_SR(index, x) \
 245 do { \
 246 SET_H_SR_V32 ((index), (x));\
 247 ;} while (0)
 248 #define GET_H_SUPR(index) crisv32f_read_supr (current_cpu, index)
 249 #define SET_H_SUPR(index, x) \
 250 do { \
 251 crisv32f_write_supr (current_cpu, (index), (x));\
 252 ;} while (0)
 253 #define GET_H_CBIT_MOVE() GET_H_CBIT_MOVE_V32 ()
 254 #define SET_H_CBIT_MOVE(x) \
 255 do { \
 256 SET_H_CBIT_MOVE_V32 ((x));\
 257 ;} while (0)
 258 #define GET_H_CBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-cbit-move on CRISv32"), 0)
 259 #define SET_H_CBIT_MOVE_V32(x) \
 260 do { \
 261 ((void) 0); /*nop*/\
 262 ;} while (0)
 263 #define GET_H_VBIT_MOVE() GET_H_VBIT_MOVE_V32 ()
 264 #define SET_H_VBIT_MOVE(x) \
 265 do { \
 266 SET_H_VBIT_MOVE_V32 ((x));\
 267 ;} while (0)
 268 #define GET_H_VBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-vbit-move on CRISv32"), 0)
 269 #define SET_H_VBIT_MOVE_V32(x) \
 270 do { \
 271 ((void) 0); /*nop*/\
 272 ;} while (0)
 273 #define GET_H_ZBIT_MOVE() GET_H_ZBIT_MOVE_V32 ()
 274 #define SET_H_ZBIT_MOVE(x) \
 275 do { \
 276 SET_H_ZBIT_MOVE_V32 ((x));\
 277 ;} while (0)
 278 #define GET_H_ZBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-zbit-move on CRISv32"), 0)
 279 #define SET_H_ZBIT_MOVE_V32(x) \
 280 do { \
 281 ((void) 0); /*nop*/\
 282 ;} while (0)
 283 #define GET_H_NBIT_MOVE() GET_H_NBIT_MOVE_V32 ()
 284 #define SET_H_NBIT_MOVE(x) \
 285 do { \
 286 SET_H_NBIT_MOVE_V32 ((x));\
 287 ;} while (0)
 288 #define GET_H_NBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-nbit-move on CRISv32"), 0)
 289 #define SET_H_NBIT_MOVE_V32(x) \
 290 do { \
 291 ((void) 0); /*nop*/\
 292 ;} while (0)
 293 #define GET_H_IBIT() CPU (h_ibit_v32)
 294 #define SET_H_IBIT(x) \
 295 do { \
 296 SET_H_IBIT_V32 ((x));\
 297 ;} while (0)
 298 #define GET_H_UBIT() CPU (h_ubit_v32)
 299 #define SET_H_UBIT(x) \
 300 do { \
 301 SET_H_UBIT_V32 ((x));\
 302 ;} while (0)
 303 #define GET_H_INSN_PREFIXED_P() GET_H_INSN_PREFIXED_P_V32 ()
 304 #define SET_H_INSN_PREFIXED_P(x) \
 305 do { \
 306 SET_H_INSN_PREFIXED_P_V32 ((x));\
 307 ;} while (0)
 308 #define GET_H_INSN_PREFIXED_P_V32() 0
 309 #define SET_H_INSN_PREFIXED_P_V32(x) \
 310 do { \
 311 ((void) 0); /*nop*/\
 312 ;} while (0)
 313 #define GET_H_PREFIXREG_V32() GET_H_GR (((UINT) 15))
 314 #define SET_H_PREFIXREG_V32(x) \
 315 do { \
 316 SET_H_GR (((UINT) 15), (x));\
 317 ;} while (0)
 318
 319 /* Cover fns for register access.  */
 320 BI crisv32f_h_v32_v32_get (SIM_CPU *);
 321 void crisv32f_h_v32_v32_set (SIM_CPU *, BI);
 322 USI crisv32f_h_pc_get (SIM_CPU *);
 323 void crisv32f_h_pc_set (SIM_CPU *, USI);
 324 SI crisv32f_h_gr_get (SIM_CPU *, UINT);
 325 void crisv32f_h_gr_set (SIM_CPU *, UINT, SI);
 326 SI crisv32f_h_gr_acr_get (SIM_CPU *, UINT);
 327 void crisv32f_h_gr_acr_set (SIM_CPU *, UINT, SI);
 328 SI crisv32f_h_raw_gr_acr_get (SIM_CPU *, UINT);
 329 void crisv32f_h_raw_gr_acr_set (SIM_CPU *, UINT, SI);
 330 SI crisv32f_h_sr_get (SIM_CPU *, UINT);
 331 void crisv32f_h_sr_set (SIM_CPU *, UINT, SI);
 332 SI crisv32f_h_sr_v32_get (SIM_CPU *, UINT);
 333 void crisv32f_h_sr_v32_set (SIM_CPU *, UINT, SI);
 334 SI crisv32f_h_supr_get (SIM_CPU *, UINT);
 335 void crisv32f_h_supr_set (SIM_CPU *, UINT, SI);
 336 BI crisv32f_h_cbit_get (SIM_CPU *);
 337 void crisv32f_h_cbit_set (SIM_CPU *, BI);
 338 BI crisv32f_h_cbit_move_get (SIM_CPU *);
 339 void crisv32f_h_cbit_move_set (SIM_CPU *, BI);
 340 BI crisv32f_h_cbit_move_v32_get (SIM_CPU *);
 341 void crisv32f_h_cbit_move_v32_set (SIM_CPU *, BI);
 342 BI crisv32f_h_vbit_get (SIM_CPU *);
 343 void crisv32f_h_vbit_set (SIM_CPU *, BI);
 344 BI crisv32f_h_vbit_move_get (SIM_CPU *);
 345 void crisv32f_h_vbit_move_set (SIM_CPU *, BI);
 346 BI crisv32f_h_vbit_move_v32_get (SIM_CPU *);
 347 void crisv32f_h_vbit_move_v32_set (SIM_CPU *, BI);
 348 BI crisv32f_h_zbit_get (SIM_CPU *);
 349 void crisv32f_h_zbit_set (SIM_CPU *, BI);
 350 BI crisv32f_h_zbit_move_get (SIM_CPU *);
 351 void crisv32f_h_zbit_move_set (SIM_CPU *, BI);
 352 BI crisv32f_h_zbit_move_v32_get (SIM_CPU *);
 353 void crisv32f_h_zbit_move_v32_set (SIM_CPU *, BI);
 354 BI crisv32f_h_nbit_get (SIM_CPU *);
 355 void crisv32f_h_nbit_set (SIM_CPU *, BI);
 356 BI crisv32f_h_nbit_move_get (SIM_CPU *);
 357 void crisv32f_h_nbit_move_set (SIM_CPU *, BI);
 358 BI crisv32f_h_nbit_move_v32_get (SIM_CPU *);
 359 void crisv32f_h_nbit_move_v32_set (SIM_CPU *, BI);
 360 BI crisv32f_h_xbit_get (SIM_CPU *);
 361 void crisv32f_h_xbit_set (SIM_CPU *, BI);
 362 BI crisv32f_h_ibit_get (SIM_CPU *);
 363 void crisv32f_h_ibit_set (SIM_CPU *, BI);
 364 BI crisv32f_h_pbit_get (SIM_CPU *);
 365 void crisv32f_h_pbit_set (SIM_CPU *, BI);
 366 BI crisv32f_h_rbit_get (SIM_CPU *);
 367 void crisv32f_h_rbit_set (SIM_CPU *, BI);
 368 BI crisv32f_h_ubit_get (SIM_CPU *);
 369 void crisv32f_h_ubit_set (SIM_CPU *, BI);
 370 BI crisv32f_h_gbit_get (SIM_CPU *);
 371 void crisv32f_h_gbit_set (SIM_CPU *, BI);
 372 SI crisv32f_h_kernel_sp_get (SIM_CPU *);
 373 void crisv32f_h_kernel_sp_set (SIM_CPU *, SI);
 374 BI crisv32f_h_ubit_v32_get (SIM_CPU *);
 375 void crisv32f_h_ubit_v32_set (SIM_CPU *, BI);
 376 BI crisv32f_h_ibit_v32_get (SIM_CPU *);
 377 void crisv32f_h_ibit_v32_set (SIM_CPU *, BI);
 378 BI crisv32f_h_mbit_get (SIM_CPU *);
 379 void crisv32f_h_mbit_set (SIM_CPU *, BI);
 380 BI crisv32f_h_qbit_get (SIM_CPU *);
 381 void crisv32f_h_qbit_set (SIM_CPU *, BI);
 382 BI crisv32f_h_sbit_get (SIM_CPU *);
 383 void crisv32f_h_sbit_set (SIM_CPU *, BI);
 384 BI crisv32f_h_insn_prefixed_p_get (SIM_CPU *);
 385 void crisv32f_h_insn_prefixed_p_set (SIM_CPU *, BI);
 386 BI crisv32f_h_insn_prefixed_p_v32_get (SIM_CPU *);
 387 void crisv32f_h_insn_prefixed_p_v32_set (SIM_CPU *, BI);
 388 SI crisv32f_h_prefixreg_v32_get (SIM_CPU *);
 389 void crisv32f_h_prefixreg_v32_set (SIM_CPU *, SI);
 390
 391 /* These must be hand-written.  */
 392 extern CPUREG_FETCH_FN crisv32f_fetch_register;
 393 extern CPUREG_STORE_FN crisv32f_store_register;
 394
 395 typedef struct {
 396   UINT prev_prev_prev_modf_regs;
 397   UINT prev_prev_modf_regs;
 398   UINT prev_modf_regs;
 399   UINT modf_regs;
 400   UINT prev_prev_prev_movem_dest_regs;
 401   UINT prev_prev_movem_dest_regs;
 402   UINT prev_movem_dest_regs;
 403   UINT movem_dest_regs;
 404 } MODEL_CRISV32_DATA;
 405
 406 /* Instruction argument buffer.  */
 407
 408 union sem_fields {
 409   struct { /* no operands */
 410     int empty;
 411   } fmt_empty;
 412   struct { /*  */
 413     UINT f_u4;
 414   } sfmt_break;
 415   struct { /*  */
 416     UINT f_dstsrc;
 417   } sfmt_setf;
 418   struct { /*  */
 419     IADDR i_o_word_pcrel;
 420     UINT f_operand2;
 421   } sfmt_bcc_w;
 422   struct { /*  */
 423     IADDR i_o_pcrel;
 424     UINT f_operand2;
 425   } sfmt_bcc_b;
 426   struct { /*  */
 427     unsigned char in_h_sr_SI_13;
 428     unsigned char out_h_sr_SI_13;
 429   } sfmt_rfe;
 430   struct { /*  */
 431     INT f_s8;
 432     UINT f_operand2;
 433     unsigned char in_Rd;
 434   } sfmt_addoq;
 435   struct { /*  */
 436     ADDR i_const32_pcrel;
 437     UINT f_operand2;
 438     unsigned char out_Pd;
 439   } sfmt_bas_c;
 440   struct { /*  */
 441     ADDR i_qo;
 442     UINT f_operand2;
 443     unsigned char out_Rd;
 444   } sfmt_lapcq;
 445   struct { /*  */
 446     ADDR i_const32_pcrel;
 447     UINT f_operand2;
 448     unsigned char out_Rd;
 449   } sfmt_lapc_d;
 450   struct { /*  */
 451     INT f_indir_pc__dword;
 452     UINT f_operand2;
 453     unsigned char out_Pd;
 454   } sfmt_move_c_sprv32_p2;
 455   struct { /*  */
 456     INT f_s6;
 457     UINT f_operand2;
 458     unsigned char out_Rd;
 459   } sfmt_moveq;
 460   struct { /*  */
 461     INT f_indir_pc__dword;
 462     UINT f_operand2;
 463     unsigned char in_Rd;
 464     unsigned char out_Rd;
 465   } sfmt_bound_cd;
 466   struct { /*  */
 467     INT f_indir_pc__word;
 468     UINT f_operand2;
 469     unsigned char in_Rd;
 470     unsigned char out_Rd;
 471   } sfmt_bound_cw;
 472   struct { /*  */
 473     INT f_indir_pc__byte;
 474     UINT f_operand2;
 475     unsigned char in_Rd;
 476     unsigned char out_Rd;
 477   } sfmt_bound_cb;
 478   struct { /*  */
 479     UINT f_operand2;
 480     UINT f_u5;
 481     unsigned char in_Rd;
 482     unsigned char out_Rd;
 483   } sfmt_asrq;
 484   struct { /*  */
 485     INT f_s6;
 486     UINT f_operand2;
 487     unsigned char in_Rd;
 488     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 489   } sfmt_andq;
 490   struct { /*  */
 491     INT f_indir_pc__dword;
 492     UINT f_operand2;
 493     unsigned char in_Rd;
 494     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 495   } sfmt_addcdr;
 496   struct { /*  */
 497     INT f_indir_pc__word;
 498     UINT f_operand2;
 499     unsigned char in_Rd;
 500     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 501   } sfmt_addcwr;
 502   struct { /*  */
 503     INT f_indir_pc__byte;
 504     UINT f_operand2;
 505     unsigned char in_Rd;
 506     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 507   } sfmt_addcbr;
 508   struct { /*  */
 509     UINT f_operand2;
 510     UINT f_u6;
 511     unsigned char in_Rd;
 512     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 513   } sfmt_addq;
 514   struct { /*  */
 515     UINT f_operand1;
 516     UINT f_operand2;
 517     unsigned char in_Ps;
 518     unsigned char in_Rs;
 519     unsigned char out_h_gr_SI_index_of__DFLT_Rs;
 520   } sfmt_mcp;
 521   struct { /*  */
 522     UINT f_operand1;
 523     UINT f_operand2;
 524     unsigned char in_Rd;
 525     unsigned char in_Rs;
 526     unsigned char out_Rd;
 527     unsigned char out_h_sr_SI_7;
 528   } sfmt_muls_b;
 529   struct { /*  */
 530     UINT f_memmode;
 531     UINT f_operand1;
 532     UINT f_operand2;
 533     unsigned char in_Ps;
 534     unsigned char in_Rs;
 535     unsigned char out_Rs;
 536   } sfmt_move_spr_mv32;
 537   struct { /*  */
 538     UINT f_memmode;
 539     UINT f_operand1;
 540     UINT f_operand2;
 541     unsigned char in_Rs;
 542     unsigned char out_Pd;
 543     unsigned char out_Rs;
 544   } sfmt_move_m_sprv32;
 545   struct { /*  */
 546     UINT f_memmode;
 547     UINT f_operand1;
 548     UINT f_operand2;
 549     unsigned char in_Rs;
 550     unsigned char out_Rd;
 551     unsigned char out_Rs;
 552   } sfmt_movs_m_b_m;
 553   struct { /*  */
 554     UINT f_memmode;
 555     UINT f_operand1;
 556     UINT f_operand2;
 557     unsigned char in_Rd;
 558     unsigned char in_Rs;
 559     unsigned char out_Rs;
 560     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 561   } sfmt_addc_m;
 562   struct { /*  */
 563     UINT f_memmode;
 564     UINT f_operand1;
 565     UINT f_operand2;
 566     unsigned char in_Rd;
 567     unsigned char in_Rs;
 568     unsigned char out_Rs;
 569     unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd;
 570   } sfmt_add_m_b_m;
 571   struct { /*  */
 572     UINT f_memmode;
 573     UINT f_operand1;
 574     UINT f_operand2;
 575     unsigned char in_Rd;
 576     unsigned char in_Rs;
 577     unsigned char out_Rs;
 578     unsigned char out_h_gr_SI_0;
 579     unsigned char out_h_gr_SI_1;
 580     unsigned char out_h_gr_SI_10;
 581     unsigned char out_h_gr_SI_11;
 582     unsigned char out_h_gr_SI_12;
 583     unsigned char out_h_gr_SI_13;
 584     unsigned char out_h_gr_SI_14;
 585     unsigned char out_h_gr_SI_15;
 586     unsigned char out_h_gr_SI_2;
 587     unsigned char out_h_gr_SI_3;
 588     unsigned char out_h_gr_SI_4;
 589     unsigned char out_h_gr_SI_5;
 590     unsigned char out_h_gr_SI_6;
 591     unsigned char out_h_gr_SI_7;
 592     unsigned char out_h_gr_SI_8;
 593     unsigned char out_h_gr_SI_9;
 594   } sfmt_movem_m_r_v32;
 595   struct { /*  */
 596     UINT f_memmode;
 597     UINT f_operand1;
 598     UINT f_operand2;
 599     unsigned char in_Rd;
 600     unsigned char in_Rs;
 601     unsigned char in_h_gr_SI_0;
 602     unsigned char in_h_gr_SI_1;
 603     unsigned char in_h_gr_SI_10;
 604     unsigned char in_h_gr_SI_11;
 605     unsigned char in_h_gr_SI_12;
 606     unsigned char in_h_gr_SI_13;
 607     unsigned char in_h_gr_SI_14;
 608     unsigned char in_h_gr_SI_15;
 609     unsigned char in_h_gr_SI_2;
 610     unsigned char in_h_gr_SI_3;
 611     unsigned char in_h_gr_SI_4;
 612     unsigned char in_h_gr_SI_5;
 613     unsigned char in_h_gr_SI_6;
 614     unsigned char in_h_gr_SI_7;
 615     unsigned char in_h_gr_SI_8;
 616     unsigned char in_h_gr_SI_9;
 617     unsigned char out_Rs;
 618   } sfmt_movem_r_m_v32;
 619 #if WITH_SCACHE_PBB
 620   /* Writeback handler.  */
 621   struct {
 622     /* Pointer to argbuf entry for insn whose results need writing back.  */
 623     const struct argbuf *abuf;
 624   } write;
 625   /* x-before handler */
 626   struct {
 627     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 628     int first_p;
 629   } before;
 630   /* x-after handler */
 631   struct {
 632     int empty;
 633   } after;
 634   /* This entry is used to terminate each pbb.  */
 635   struct {
 636     /* Number of insns in pbb.  */
 637     int insn_count;
 638     /* Next pbb to execute.  */
 639     SCACHE *next;
 640     SCACHE *branch_target;
 641   } chain;
 642 #endif
 643 };
 644
 645 /* The ARGBUF struct.  */
 646 struct argbuf {
 647   /* These are the baseclass definitions.  */
 648   IADDR addr;
 649   const IDESC *idesc;
 650   char trace_p;
 651   char profile_p;
 652   /* ??? Temporary hack for skip insns.  */
 653   char skip_count;
 654   char unused;
 655   /* cpu specific data follows */
 656   union sem semantic;
 657   int written;
 658   union sem_fields fields;
 659 };
 660
 661 /* A cached insn.
 662
 663    ??? SCACHE used to contain more than just argbuf.  We could delete the
 664    type entirely and always just use ARGBUF, but for future concerns and as
 665    a level of abstraction it is left in.  */
 666
 667 struct scache {
 668   struct argbuf argbuf;
 669 };
 670
 671 /* Macros to simplify extraction, reading and semantic code.
 672    These define and assign the local vars that contain the insn's fields.  */
 673
 674 #define EXTRACT_IFMT_EMPTY_VARS \
 675   unsigned int length;
 676 #define EXTRACT_IFMT_EMPTY_CODE \
 677   length = 0; \
 678
 679 #define EXTRACT_IFMT_MOVE_B_R_VARS \
 680   UINT f_operand2; \
 681   UINT f_mode; \
 682   UINT f_opcode; \
 683   UINT f_size; \
 684   UINT f_operand1; \
 685   unsigned int length;
 686 #define EXTRACT_IFMT_MOVE_B_R_CODE \
 687   length = 2; \
 688   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 689   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 690   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 691   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 692   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 693
 694 #define EXTRACT_IFMT_MOVEQ_VARS \
 695   UINT f_operand2; \
 696   UINT f_mode; \
 697   UINT f_opcode; \
 698   INT f_s6; \
 699   unsigned int length;
 700 #define EXTRACT_IFMT_MOVEQ_CODE \
 701   length = 2; \
 702   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 703   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 704   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 705   f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6); \
 706
 707 #define EXTRACT_IFMT_MOVECBR_VARS \
 708   UINT f_operand2; \
 709   INT f_indir_pc__byte; \
 710   UINT f_mode; \
 711   UINT f_opcode; \
 712   UINT f_size; \
 713   UINT f_operand1; \
 714   /* Contents of trailing part of insn.  */ \
 715   UINT word_1; \
 716   unsigned int length;
 717 #define EXTRACT_IFMT_MOVECBR_CODE \
 718   length = 4; \
 719   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 720   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 721   f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 722   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 723   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 724   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 725   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 726
 727 #define EXTRACT_IFMT_MOVECWR_VARS \
 728   UINT f_operand2; \
 729   INT f_indir_pc__word; \
 730   UINT f_mode; \
 731   UINT f_opcode; \
 732   UINT f_size; \
 733   UINT f_operand1; \
 734   /* Contents of trailing part of insn.  */ \
 735   UINT word_1; \
 736   unsigned int length;
 737 #define EXTRACT_IFMT_MOVECWR_CODE \
 738   length = 4; \
 739   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 740   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 741   f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 742   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 743   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 744   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 745   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 746
 747 #define EXTRACT_IFMT_MOVECDR_VARS \
 748   INT f_indir_pc__dword; \
 749   UINT f_operand2; \
 750   UINT f_mode; \
 751   UINT f_opcode; \
 752   UINT f_size; \
 753   UINT f_operand1; \
 754   /* Contents of trailing part of insn.  */ \
 755   UINT word_1; \
 756   unsigned int length;
 757 #define EXTRACT_IFMT_MOVECDR_CODE \
 758   length = 6; \
 759   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 760   f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
 761   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 762   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 763   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 764   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 765   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 766
 767 #define EXTRACT_IFMT_MOVUCBR_VARS \
 768   UINT f_operand2; \
 769   INT f_indir_pc__byte; \
 770   UINT f_mode; \
 771   UINT f_opcode; \
 772   UINT f_size; \
 773   UINT f_operand1; \
 774   /* Contents of trailing part of insn.  */ \
 775   UINT word_1; \
 776   unsigned int length;
 777 #define EXTRACT_IFMT_MOVUCBR_CODE \
 778   length = 4; \
 779   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 780   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 781   f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 782   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 783   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 784   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 785   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 786
 787 #define EXTRACT_IFMT_MOVUCWR_VARS \
 788   UINT f_operand2; \
 789   INT f_indir_pc__word; \
 790   UINT f_mode; \
 791   UINT f_opcode; \
 792   UINT f_size; \
 793   UINT f_operand1; \
 794   /* Contents of trailing part of insn.  */ \
 795   UINT word_1; \
 796   unsigned int length;
 797 #define EXTRACT_IFMT_MOVUCWR_CODE \
 798   length = 4; \
 799   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 800   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 801   f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 802   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 803   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 804   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 805   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 806
 807 #define EXTRACT_IFMT_ADDQ_VARS \
 808   UINT f_operand2; \
 809   UINT f_mode; \
 810   UINT f_opcode; \
 811   UINT f_u6; \
 812   unsigned int length;
 813 #define EXTRACT_IFMT_ADDQ_CODE \
 814   length = 2; \
 815   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 816   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 817   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 818   f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6); \
 819
 820 #define EXTRACT_IFMT_CMP_M_B_M_VARS \
 821   UINT f_operand2; \
 822   UINT f_membit; \
 823   UINT f_memmode; \
 824   UINT f_opcode; \
 825   UINT f_size; \
 826   UINT f_operand1; \
 827   unsigned int length;
 828 #define EXTRACT_IFMT_CMP_M_B_M_CODE \
 829   length = 2; \
 830   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 831   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 832   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 833   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 834   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 835   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 836
 837 #define EXTRACT_IFMT_MOVE_R_SPRV32_VARS \
 838   UINT f_operand2; \
 839   UINT f_mode; \
 840   UINT f_opcode; \
 841   UINT f_size; \
 842   UINT f_operand1; \
 843   unsigned int length;
 844 #define EXTRACT_IFMT_MOVE_R_SPRV32_CODE \
 845   length = 2; \
 846   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 847   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 848   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 849   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 850   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 851
 852 #define EXTRACT_IFMT_MOVE_SPR_RV32_VARS \
 853   UINT f_operand2; \
 854   UINT f_mode; \
 855   UINT f_opcode; \
 856   UINT f_size; \
 857   UINT f_operand1; \
 858   unsigned int length;
 859 #define EXTRACT_IFMT_MOVE_SPR_RV32_CODE \
 860   length = 2; \
 861   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 862   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 863   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 864   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 865   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 866
 867 #define EXTRACT_IFMT_MOVE_M_SPRV32_VARS \
 868   UINT f_operand2; \
 869   UINT f_membit; \
 870   UINT f_memmode; \
 871   UINT f_opcode; \
 872   UINT f_size; \
 873   UINT f_operand1; \
 874   unsigned int length;
 875 #define EXTRACT_IFMT_MOVE_M_SPRV32_CODE \
 876   length = 2; \
 877   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 878   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 879   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 880   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 881   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 882   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 883
 884 #define EXTRACT_IFMT_MOVE_C_SPRV32_P2_VARS \
 885   INT f_indir_pc__dword; \
 886   UINT f_operand2; \
 887   UINT f_mode; \
 888   UINT f_opcode; \
 889   UINT f_size; \
 890   UINT f_operand1; \
 891   /* Contents of trailing part of insn.  */ \
 892   UINT word_1; \
 893   unsigned int length;
 894 #define EXTRACT_IFMT_MOVE_C_SPRV32_P2_CODE \
 895   length = 6; \
 896   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 897   f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
 898   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 899   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 900   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 901   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 902   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 903
 904 #define EXTRACT_IFMT_MOVE_SPR_MV32_VARS \
 905   UINT f_operand2; \
 906   UINT f_membit; \
 907   UINT f_memmode; \
 908   UINT f_opcode; \
 909   UINT f_size; \
 910   UINT f_operand1; \
 911   unsigned int length;
 912 #define EXTRACT_IFMT_MOVE_SPR_MV32_CODE \
 913   length = 2; \
 914   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 915   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 916   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 917   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 918   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 919   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 920
 921 #define EXTRACT_IFMT_MOVE_SS_R_VARS \
 922   UINT f_operand2; \
 923   UINT f_mode; \
 924   UINT f_opcode; \
 925   UINT f_size; \
 926   UINT f_operand1; \
 927   unsigned int length;
 928 #define EXTRACT_IFMT_MOVE_SS_R_CODE \
 929   length = 2; \
 930   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 931   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 932   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 933   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 934   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 935
 936 #define EXTRACT_IFMT_MOVE_R_SS_VARS \
 937   UINT f_operand2; \
 938   UINT f_mode; \
 939   UINT f_opcode; \
 940   UINT f_size; \
 941   UINT f_operand1; \
 942   unsigned int length;
 943 #define EXTRACT_IFMT_MOVE_R_SS_CODE \
 944   length = 2; \
 945   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 946   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 947   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 948   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 949   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 950
 951 #define EXTRACT_IFMT_LAPC_D_VARS \
 952   SI f_indir_pc__dword_pcrel; \
 953   UINT f_operand2; \
 954   UINT f_mode; \
 955   UINT f_opcode; \
 956   UINT f_size; \
 957   UINT f_operand1; \
 958   /* Contents of trailing part of insn.  */ \
 959   UINT word_1; \
 960   unsigned int length;
 961 #define EXTRACT_IFMT_LAPC_D_CODE \
 962   length = 6; \
 963   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 964   f_indir_pc__dword_pcrel = ((pc) + ((0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)))); \
 965   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 966   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 967   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 968   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 969   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 970
 971 #define EXTRACT_IFMT_LAPCQ_VARS \
 972   UINT f_operand2; \
 973   UINT f_mode; \
 974   UINT f_opcode; \
 975   UINT f_size; \
 976   SI f_qo; \
 977   unsigned int length;
 978 #define EXTRACT_IFMT_LAPCQ_CODE \
 979   length = 2; \
 980   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 981   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 982   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 983   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 984   f_qo = ((pc) + (((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)))); \
 985
 986 #define EXTRACT_IFMT_TEST_M_B_M_VARS \
 987   UINT f_operand2; \
 988   UINT f_membit; \
 989   UINT f_memmode; \
 990   UINT f_opcode; \
 991   UINT f_size; \
 992   UINT f_operand1; \
 993   unsigned int length;
 994 #define EXTRACT_IFMT_TEST_M_B_M_CODE \
 995   length = 2; \
 996   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 997   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 998   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 999   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1000   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1001   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1002
1003 #define EXTRACT_IFMT_SWAP_VARS \
1004   UINT f_operand2; \
1005   UINT f_mode; \
1006   UINT f_opcode; \
1007   UINT f_size; \
1008   UINT f_operand1; \
1009   unsigned int length;
1010 #define EXTRACT_IFMT_SWAP_CODE \
1011   length = 2; \
1012   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1013   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1014   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1015   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1016   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1017
1018 #define EXTRACT_IFMT_ASRQ_VARS \
1019   UINT f_operand2; \
1020   UINT f_mode; \
1021   UINT f_opcode; \
1022   UINT f_b5; \
1023   UINT f_u5; \
1024   unsigned int length;
1025 #define EXTRACT_IFMT_ASRQ_CODE \
1026   length = 2; \
1027   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1028   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1029   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1030   f_b5 = EXTRACT_LSB0_UINT (insn, 16, 5, 1); \
1031   f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5); \
1032
1033 #define EXTRACT_IFMT_SETF_VARS \
1034   UINT f_mode; \
1035   UINT f_opcode; \
1036   UINT f_size; \
1037   UINT f_operand2; \
1038   UINT f_operand1; \
1039   UINT f_dstsrc; \
1040   unsigned int length;
1041 #define EXTRACT_IFMT_SETF_CODE \
1042   length = 2; \
1043   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1044   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1045   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1046   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1047   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1048   f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));\
1049
1050 #define EXTRACT_IFMT_RFE_VARS \
1051   UINT f_operand2; \
1052   UINT f_mode; \
1053   UINT f_opcode; \
1054   UINT f_size; \
1055   UINT f_operand1; \
1056   unsigned int length;
1057 #define EXTRACT_IFMT_RFE_CODE \
1058   length = 2; \
1059   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1060   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1061   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1062   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1063   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1064
1065 #define EXTRACT_IFMT_BCC_B_VARS \
1066   UINT f_operand2; \
1067   UINT f_mode; \
1068   UINT f_opcode_hi; \
1069   INT f_disp9_hi; \
1070   UINT f_disp9_lo; \
1071   INT f_disp9; \
1072   unsigned int length;
1073 #define EXTRACT_IFMT_BCC_B_CODE \
1074   length = 2; \
1075   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1076   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1077   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1078   f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
1079   f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
1080 {\
1081   SI tmp_abslo;\
1082   SI tmp_absval;\
1083   tmp_abslo = ((f_disp9_lo) << (1));\
1084   tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
1085   f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_V32 ()) ? (0) : (2))));\
1086 }\
1087
1088 #define EXTRACT_IFMT_BA_B_VARS \
1089   UINT f_operand2; \
1090   UINT f_mode; \
1091   UINT f_opcode_hi; \
1092   INT f_disp9_hi; \
1093   UINT f_disp9_lo; \
1094   INT f_disp9; \
1095   unsigned int length;
1096 #define EXTRACT_IFMT_BA_B_CODE \
1097   length = 2; \
1098   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1099   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1100   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1101   f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
1102   f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
1103 {\
1104   SI tmp_abslo;\
1105   SI tmp_absval;\
1106   tmp_abslo = ((f_disp9_lo) << (1));\
1107   tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
1108   f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_V32 ()) ? (0) : (2))));\
1109 }\
1110
1111 #define EXTRACT_IFMT_BCC_W_VARS \
1112   UINT f_operand2; \
1113   SI f_indir_pc__word_pcrel; \
1114   UINT f_mode; \
1115   UINT f_opcode; \
1116   UINT f_size; \
1117   UINT f_operand1; \
1118   /* Contents of trailing part of insn.  */ \
1119   UINT word_1; \
1120   unsigned int length;
1121 #define EXTRACT_IFMT_BCC_W_CODE \
1122   length = 4; \
1123   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
1124   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1125   f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4)))))); \
1126   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1127   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1128   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1129   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1130
1131 #define EXTRACT_IFMT_BA_W_VARS \
1132   UINT f_operand2; \
1133   SI f_indir_pc__word_pcrel; \
1134   UINT f_mode; \
1135   UINT f_opcode; \
1136   UINT f_size; \
1137   UINT f_operand1; \
1138   /* Contents of trailing part of insn.  */ \
1139   UINT word_1; \
1140   unsigned int length;
1141 #define EXTRACT_IFMT_BA_W_CODE \
1142   length = 4; \
1143   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
1144   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1145   f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4)))))); \
1146   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1147   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1148   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1149   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1150
1151 #define EXTRACT_IFMT_JAS_C_VARS \
1152   INT f_indir_pc__dword; \
1153   UINT f_operand2; \
1154   UINT f_mode; \
1155   UINT f_opcode; \
1156   UINT f_size; \
1157   UINT f_operand1; \
1158   /* Contents of trailing part of insn.  */ \
1159   UINT word_1; \
1160   unsigned int length;
1161 #define EXTRACT_IFMT_JAS_C_CODE \
1162   length = 6; \
1163   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
1164   f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
1165   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1166   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1167   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1168   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1169   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1170
1171 #define EXTRACT_IFMT_JUMP_P_VARS \
1172   UINT f_operand2; \
1173   UINT f_mode; \
1174   UINT f_opcode; \
1175   UINT f_size; \
1176   UINT f_operand1; \
1177   unsigned int length;
1178 #define EXTRACT_IFMT_JUMP_P_CODE \
1179   length = 2; \
1180   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1181   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1182   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1183   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1184   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1185
1186 #define EXTRACT_IFMT_BAS_C_VARS \
1187   SI f_indir_pc__dword_pcrel; \
1188   UINT f_operand2; \
1189   UINT f_mode; \
1190   UINT f_opcode; \
1191   UINT f_size; \
1192   UINT f_operand1; \
1193   /* Contents of trailing part of insn.  */ \
1194   UINT word_1; \
1195   unsigned int length;
1196 #define EXTRACT_IFMT_BAS_C_CODE \
1197   length = 6; \
1198   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
1199   f_indir_pc__dword_pcrel = ((pc) + ((0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)))); \
1200   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1201   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1202   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1203   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1204   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1205
1206 #define EXTRACT_IFMT_BREAK_VARS \
1207   UINT f_operand2; \
1208   UINT f_mode; \
1209   UINT f_opcode; \
1210   UINT f_size; \
1211   UINT f_u4; \
1212   unsigned int length;
1213 #define EXTRACT_IFMT_BREAK_CODE \
1214   length = 2; \
1215   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1216   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1217   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1218   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1219   f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1220
1221 #define EXTRACT_IFMT_SCC_VARS \
1222   UINT f_operand2; \
1223   UINT f_mode; \
1224   UINT f_opcode; \
1225   UINT f_size; \
1226   UINT f_operand1; \
1227   unsigned int length;
1228 #define EXTRACT_IFMT_SCC_CODE \
1229   length = 2; \
1230   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1231   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1232   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1233   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1234   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1235
1236 #define EXTRACT_IFMT_ADDOQ_VARS \
1237   UINT f_operand2; \
1238   UINT f_mode; \
1239   UINT f_opcode_hi; \
1240   INT f_s8; \
1241   unsigned int length;
1242 #define EXTRACT_IFMT_ADDOQ_CODE \
1243   length = 2; \
1244   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1245   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1246   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1247   f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
1248
1249 #define EXTRACT_IFMT_FIDXI_VARS \
1250   UINT f_operand2; \
1251   UINT f_mode; \
1252   UINT f_opcode; \
1253   UINT f_size; \
1254   UINT f_operand1; \
1255   unsigned int length;
1256 #define EXTRACT_IFMT_FIDXI_CODE \
1257   length = 2; \
1258   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1259   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1260   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1261   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1262   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1263
1264 /* Collection of various things for the trace handler to use.  */
1265
1266 typedef struct trace_record {
1267   IADDR pc;
1268   /* FIXME:wip */
1269 } TRACE_RECORD;
1270
1271 #endif /* CPU_CRISV32F_H */