sim/cris/cris-desc.h

   1 /* CPU data header for cris.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2005 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CRIS_CPU_H
  26 #define CRIS_CPU_H
  27
  28 #define CGEN_ARCH cris
  29
  30 /* Given symbol S, return cris_cgen_<S>.  */
  31 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
  32 #define CGEN_SYM(s) cris##_cgen_##s
  33 #else
  34 #define CGEN_SYM(s) cris/**/_cgen_/**/s
  35 #endif
  36
  37
  38 /* Selected cpu families.  */
  39 #define HAVE_CPU_CRISV0F
  40 #define HAVE_CPU_CRISV3F
  41 #define HAVE_CPU_CRISV8F
  42 #define HAVE_CPU_CRISV10F
  43 #define HAVE_CPU_CRISV32F
  44
  45 #define CGEN_INSN_LSB0_P 1
  46
  47 /* Minimum size of any insn (in bytes).  */
  48 #define CGEN_MIN_INSN_SIZE 2
  49
  50 /* Maximum size of any insn (in bytes).  */
  51 #define CGEN_MAX_INSN_SIZE 6
  52
  53 #define CGEN_INT_INSN_P 0
  54
  55 /* Maximum number of syntax elements in an instruction.  */
  56 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22
  57
  58 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  59    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  60    we can't hash on everything up to the space.  */
  61 #define CGEN_MNEMONIC_OPERANDS
  62
  63 /* Maximum number of fields in an instruction.  */
  64 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 6
  65
  66 /* Enums.  */
  67
  68 /* Enum declaration for .  */
  69 typedef enum gr_names_pcreg {
  70   H_GR_REAL_PC_PC = 15, H_GR_REAL_PC_SP = 14, H_GR_REAL_PC_R0 = 0, H_GR_REAL_PC_R1 = 1
  71  , H_GR_REAL_PC_R2 = 2, H_GR_REAL_PC_R3 = 3, H_GR_REAL_PC_R4 = 4, H_GR_REAL_PC_R5 = 5
  72  , H_GR_REAL_PC_R6 = 6, H_GR_REAL_PC_R7 = 7, H_GR_REAL_PC_R8 = 8, H_GR_REAL_PC_R9 = 9
  73  , H_GR_REAL_PC_R10 = 10, H_GR_REAL_PC_R11 = 11, H_GR_REAL_PC_R12 = 12, H_GR_REAL_PC_R13 = 13
  74  , H_GR_REAL_PC_R14 = 14
  75 } GR_NAMES_PCREG;
  76
  77 /* Enum declaration for .  */
  78 typedef enum gr_names_acr {
  79   H_GR_ACR = 15, H_GR_SP = 14, H_GR_R0 = 0, H_GR_R1 = 1
  80  , H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5
  81  , H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9
  82  , H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13
  83  , H_GR_R14 = 14
  84 } GR_NAMES_ACR;
  85
  86 /* Enum declaration for .  */
  87 typedef enum gr_names_v32 {
  88   H_GR_V32_ACR = 15, H_GR_V32_SP = 14, H_GR_V32_R0 = 0, H_GR_V32_R1 = 1
  89  , H_GR_V32_R2 = 2, H_GR_V32_R3 = 3, H_GR_V32_R4 = 4, H_GR_V32_R5 = 5
  90  , H_GR_V32_R6 = 6, H_GR_V32_R7 = 7, H_GR_V32_R8 = 8, H_GR_V32_R9 = 9
  91  , H_GR_V32_R10 = 10, H_GR_V32_R11 = 11, H_GR_V32_R12 = 12, H_GR_V32_R13 = 13
  92  , H_GR_V32_R14 = 14
  93 } GR_NAMES_V32;
  94
  95 /* Enum declaration for .  */
  96 typedef enum p_names_v10 {
  97   H_SR_PRE_V32_CCR = 5, H_SR_PRE_V32_MOF = 7, H_SR_PRE_V32_IBR = 9, H_SR_PRE_V32_IRP = 10
  98  , H_SR_PRE_V32_BAR = 12, H_SR_PRE_V32_DCCR = 13, H_SR_PRE_V32_BRP = 14, H_SR_PRE_V32_USP = 15
  99  , H_SR_PRE_V32_VR = 1, H_SR_PRE_V32_SRP = 11, H_SR_PRE_V32_P0 = 0, H_SR_PRE_V32_P1 = 1
 100  , H_SR_PRE_V32_P2 = 2, H_SR_PRE_V32_P3 = 3, H_SR_PRE_V32_P4 = 4, H_SR_PRE_V32_P5 = 5
 101  , H_SR_PRE_V32_P6 = 6, H_SR_PRE_V32_P7 = 7, H_SR_PRE_V32_P8 = 8, H_SR_PRE_V32_P9 = 9
 102  , H_SR_PRE_V32_P10 = 10, H_SR_PRE_V32_P11 = 11, H_SR_PRE_V32_P12 = 12, H_SR_PRE_V32_P13 = 13
 103  , H_SR_PRE_V32_P14 = 14
 104 } P_NAMES_V10;
 105
 106 /* Enum declaration for .  */
 107 typedef enum p_names_v32 {
 108   H_SR_BZ = 0, H_SR_PID = 2, H_SR_SRS = 3, H_SR_WZ = 4
 109  , H_SR_EXS = 5, H_SR_EDA = 6, H_SR_MOF = 7, H_SR_DZ = 8
 110  , H_SR_EBP = 9, H_SR_ERP = 10, H_SR_NRP = 12, H_SR_CCS = 13
 111  , H_SR_USP = 14, H_SR_SPC = 15, H_SR_VR = 1, H_SR_SRP = 11
 112  , H_SR_P0 = 0, H_SR_P1 = 1, H_SR_P2 = 2, H_SR_P3 = 3
 113  , H_SR_P4 = 4, H_SR_P5 = 5, H_SR_P6 = 6, H_SR_P7 = 7
 114  , H_SR_P8 = 8, H_SR_P9 = 9, H_SR_P10 = 10, H_SR_P11 = 11
 115  , H_SR_P12 = 12, H_SR_P13 = 13, H_SR_P14 = 14
 116 } P_NAMES_V32;
 117
 118 /* Enum declaration for .  */
 119 typedef enum p_names_v32_x {
 120   H_SR_V32_BZ = 0, H_SR_V32_PID = 2, H_SR_V32_SRS = 3, H_SR_V32_WZ = 4
 121  , H_SR_V32_EXS = 5, H_SR_V32_EDA = 6, H_SR_V32_MOF = 7, H_SR_V32_DZ = 8
 122  , H_SR_V32_EBP = 9, H_SR_V32_ERP = 10, H_SR_V32_NRP = 12, H_SR_V32_CCS = 13
 123  , H_SR_V32_USP = 14, H_SR_V32_SPC = 15, H_SR_V32_VR = 1, H_SR_V32_SRP = 11
 124  , H_SR_V32_P0 = 0, H_SR_V32_P1 = 1, H_SR_V32_P2 = 2, H_SR_V32_P3 = 3
 125  , H_SR_V32_P4 = 4, H_SR_V32_P5 = 5, H_SR_V32_P6 = 6, H_SR_V32_P7 = 7
 126  , H_SR_V32_P8 = 8, H_SR_V32_P9 = 9, H_SR_V32_P10 = 10, H_SR_V32_P11 = 11
 127  , H_SR_V32_P12 = 12, H_SR_V32_P13 = 13, H_SR_V32_P14 = 14
 128 } P_NAMES_V32_X;
 129
 130 /* Enum declaration for Standard instruction operand size.  */
 131 typedef enum insn_size {
 132   SIZE_BYTE, SIZE_WORD, SIZE_DWORD, SIZE_FIXED
 133 } INSN_SIZE;
 134
 135 /* Enum declaration for Standard instruction addressing modes.  */
 136 typedef enum insn_mode {
 137   MODE_QUICK_IMMEDIATE, MODE_REGISTER, MODE_INDIRECT, MODE_AUTOINCREMENT
 138 } INSN_MODE;
 139
 140 /* Enum declaration for Whether the operand is indirect.  */
 141 typedef enum insn_memoryness_mode {
 142   MODEMEMP_NO, MODEMEMP_YES
 143 } INSN_MEMORYNESS_MODE;
 144
 145 /* Enum declaration for Whether the indirect operand is autoincrement.  */
 146 typedef enum insn_memincness_mode {
 147   MODEINCP_NO, MODEINCP_YES
 148 } INSN_MEMINCNESS_MODE;
 149
 150 /* Enum declaration for Signed instruction operand size.  */
 151 typedef enum insn_signed_size {
 152   SIGNED_UNDEF_SIZE_0, SIGNED_UNDEF_SIZE_1, SIGNED_BYTE, SIGNED_WORD
 153 } INSN_SIGNED_SIZE;
 154
 155 /* Enum declaration for Unsigned instruction operand size.  */
 156 typedef enum insn_unsigned_size {
 157   UNSIGNED_BYTE, UNSIGNED_WORD, UNSIGNED_UNDEF_SIZE_2, UNSIGNED_UNDEF_SIZE_3
 158 } INSN_UNSIGNED_SIZE;
 159
 160 /* Enum declaration for Insns for MODE_QUICK_IMMEDIATE.  */
 161 typedef enum insn_qi_opc {
 162   Q_BCC_0, Q_BCC_1, Q_BCC_2, Q_BCC_3
 163  , Q_BDAP_0, Q_BDAP_1, Q_BDAP_2, Q_BDAP_3
 164  , Q_ADDQ, Q_MOVEQ, Q_SUBQ, Q_CMPQ
 165  , Q_ANDQ, Q_ORQ, Q_ASHQ, Q_LSHQ
 166 } INSN_QI_OPC;
 167
 168 /* Enum declaration for Same as insn-qi-opc, though using only the high two bits of the opcode.  */
 169 typedef enum insn_qihi_opc {
 170   QHI_BCC, QHI_BDAP, QHI_OTHER2, QHI_OTHER3
 171 } INSN_QIHI_OPC;
 172
 173 /* Enum declaration for Insns for MODE_REGISTER and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD.  */
 174 typedef enum insn_r_opc {
 175   R_ADDX, R_MOVX, R_SUBX, R_LSL
 176  , R_ADDI, R_BIAP, R_NEG, R_BOUND
 177  , R_ADD, R_MOVE, R_SUB, R_CMP
 178  , R_AND, R_OR, R_ASR, R_LSR
 179 } INSN_R_OPC;
 180
 181 /* Enum declaration for Insns for MODE_REGISTER and SIZE_FIXED.  */
 182 typedef enum insn_rfix_opc {
 183   RFIX_ADDX, RFIX_MOVX, RFIX_SUBX, RFIX_BTST
 184  , RFIX_SCC, RFIX_ADDC, RFIX_SETF, RFIX_CLEARF
 185  , RFIX_MOVE_R_S, RFIX_MOVE_S_R, RFIX_ABS, RFIX_DSTEP
 186  , RFIX_LZ, RFIX_SWAP, RFIX_XOR, RFIX_MSTEP
 187 } INSN_RFIX_OPC;
 188
 189 /* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD.  */
 190 typedef enum insn_indir_opc {
 191   INDIR_ADDX, INDIR_MOVX, INDIR_SUBX, INDIR_CMPX
 192  , INDIR_MUL, INDIR_BDAP_M, INDIR_ADDC, INDIR_BOUND
 193  , INDIR_ADD, INDIR_MOVE_M_R, INDIR_SUB, INDIR_CMP
 194  , INDIR_AND, INDIR_OR, INDIR_TEST, INDIR_MOVE_R_M
 195 } INSN_INDIR_OPC;
 196
 197 /* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and SIZE_FIXED.  */
 198 typedef enum insn_infix_opc {
 199   INFIX_ADDX, INFIX_MOVX, INFIX_SUBX, INFIX_CMPX
 200  , INFIX_JUMP_M, INFIX_DIP, INFIX_JUMP_R, INFIX_BCC_M
 201  , INFIX_MOVE_M_S, INFIX_MOVE_S_M, INFIX_BMOD, INFIX_BSTORE
 202  , INFIX_RBF, INFIX_SBFS, INFIX_MOVEM_M_R, INFIX_MOVEM_R_M
 203 } INSN_INFIX_OPC;
 204
 205 /* Attributes.  */
 206
 207 /* Enum declaration for machine type selection.  */
 208 typedef enum mach_attr {
 209   MACH_BASE, MACH_CRISV0, MACH_CRISV3, MACH_CRISV8
 210  , MACH_CRISV10, MACH_CRISV32, MACH_MAX
 211 } MACH_ATTR;
 212
 213 /* Enum declaration for instruction set selection.  */
 214 typedef enum isa_attr {
 215   ISA_CRIS, ISA_MAX
 216 } ISA_ATTR;
 217
 218 /* Number of architecture variants.  */
 219 #define MAX_ISAS  1
 220 #define MAX_MACHS ((int) MACH_MAX)
 221
 222 /* Ifield support.  */
 223
 224 /* Ifield attribute indices.  */
 225
 226 /* Enum declaration for cgen_ifld attrs.  */
 227 typedef enum cgen_ifld_attr {
 228   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 229  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 230  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 231 } CGEN_IFLD_ATTR;
 232
 233 /* Number of non-boolean elements in cgen_ifld_attr.  */
 234 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 235
 236 /* Enum declaration for cris ifield types.  */
 237 typedef enum ifield_type {
 238   CRIS_F_NIL, CRIS_F_ANYOF, CRIS_F_OPERAND1, CRIS_F_SIZE
 239  , CRIS_F_OPCODE, CRIS_F_MODE, CRIS_F_OPERAND2, CRIS_F_MEMMODE
 240  , CRIS_F_MEMBIT, CRIS_F_B5, CRIS_F_OPCODE_HI, CRIS_F_DSTSRC
 241  , CRIS_F_U6, CRIS_F_S6, CRIS_F_U5, CRIS_F_U4
 242  , CRIS_F_S8, CRIS_F_DISP9_HI, CRIS_F_DISP9_LO, CRIS_F_DISP9
 243  , CRIS_F_QO, CRIS_F_INDIR_PC__BYTE, CRIS_F_INDIR_PC__WORD, CRIS_F_INDIR_PC__WORD_PCREL
 244  , CRIS_F_INDIR_PC__DWORD, CRIS_F_INDIR_PC__DWORD_PCREL, CRIS_F_MAX
 245 } IFIELD_TYPE;
 246
 247 #define MAX_IFLD ((int) CRIS_F_MAX)
 248
 249 /* Hardware attribute indices.  */
 250
 251 /* Enum declaration for cgen_hw attrs.  */
 252 typedef enum cgen_hw_attr {
 253   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 254  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 255 } CGEN_HW_ATTR;
 256
 257 /* Number of non-boolean elements in cgen_hw_attr.  */
 258 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 259
 260 /* Enum declaration for cris hardware types.  */
 261 typedef enum cgen_hw_type {
 262   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 263  , HW_H_IADDR, HW_H_INC, HW_H_CCODE, HW_H_SWAP
 264  , HW_H_FLAGBITS, HW_H_V32, HW_H_PC, HW_H_GR
 265  , HW_H_GR_X, HW_H_GR_REAL_PC, HW_H_RAW_GR, HW_H_SR
 266  , HW_H_SR_X, HW_H_SUPR, HW_H_CBIT, HW_H_CBIT_MOVE
 267  , HW_H_CBIT_MOVE_X, HW_H_VBIT, HW_H_VBIT_MOVE, HW_H_VBIT_MOVE_X
 268  , HW_H_ZBIT, HW_H_ZBIT_MOVE, HW_H_ZBIT_MOVE_X, HW_H_NBIT
 269  , HW_H_NBIT_MOVE, HW_H_NBIT_MOVE_X, HW_H_XBIT, HW_H_IBIT
 270  , HW_H_IBIT_X, HW_H_PBIT, HW_H_RBIT, HW_H_UBIT
 271  , HW_H_UBIT_X, HW_H_GBIT, HW_H_KERNEL_SP, HW_H_MBIT
 272  , HW_H_QBIT, HW_H_SBIT, HW_H_INSN_PREFIXED_P, HW_H_INSN_PREFIXED_P_X
 273  , HW_H_PREFIXREG, HW_MAX
 274 } CGEN_HW_TYPE;
 275
 276 #define MAX_HW ((int) HW_MAX)
 277
 278 /* Operand attribute indices.  */
 279
 280 /* Enum declaration for cgen_operand attrs.  */
 281 typedef enum cgen_operand_attr {
 282   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 283  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 284  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
 285 } CGEN_OPERAND_ATTR;
 286
 287 /* Number of non-boolean elements in cgen_operand_attr.  */
 288 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 289
 290 /* Enum declaration for cris operand types.  */
 291 typedef enum cgen_operand_type {
 292   CRIS_OPERAND_PC, CRIS_OPERAND_CBIT, CRIS_OPERAND_CBIT_MOVE, CRIS_OPERAND_VBIT
 293  , CRIS_OPERAND_VBIT_MOVE, CRIS_OPERAND_ZBIT, CRIS_OPERAND_ZBIT_MOVE, CRIS_OPERAND_NBIT
 294  , CRIS_OPERAND_NBIT_MOVE, CRIS_OPERAND_XBIT, CRIS_OPERAND_IBIT, CRIS_OPERAND_UBIT
 295  , CRIS_OPERAND_PBIT, CRIS_OPERAND_RBIT, CRIS_OPERAND_SBIT, CRIS_OPERAND_MBIT
 296  , CRIS_OPERAND_QBIT, CRIS_OPERAND_PREFIX_SET, CRIS_OPERAND_PREFIXREG, CRIS_OPERAND_RS
 297  , CRIS_OPERAND_INC, CRIS_OPERAND_PS, CRIS_OPERAND_SS, CRIS_OPERAND_SD
 298  , CRIS_OPERAND_I, CRIS_OPERAND_J, CRIS_OPERAND_C, CRIS_OPERAND_QO
 299  , CRIS_OPERAND_RD, CRIS_OPERAND_SCONST8, CRIS_OPERAND_UCONST8, CRIS_OPERAND_SCONST16
 300  , CRIS_OPERAND_UCONST16, CRIS_OPERAND_CONST32, CRIS_OPERAND_CONST32_PCREL, CRIS_OPERAND_PD
 301  , CRIS_OPERAND_O, CRIS_OPERAND_O_PCREL, CRIS_OPERAND_O_WORD_PCREL, CRIS_OPERAND_CC
 302  , CRIS_OPERAND_N, CRIS_OPERAND_SWAPOPTION, CRIS_OPERAND_LIST_OF_FLAGS, CRIS_OPERAND_MAX
 303 } CGEN_OPERAND_TYPE;
 304
 305 /* Number of operands types.  */
 306 #define MAX_OPERANDS 43
 307
 308 /* Maximum number of operands referenced by any insn.  */
 309 #define MAX_OPERAND_INSTANCES 8
 310
 311 /* Insn attribute indices.  */
 312
 313 /* Enum declaration for cgen_insn attrs.  */
 314 typedef enum cgen_insn_attr {
 315   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 316  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
 317  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
 318  , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 319 } CGEN_INSN_ATTR;
 320
 321 /* Number of non-boolean elements in cgen_insn_attr.  */
 322 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 323
 324 /* cgen.h uses things we just defined.  */
 325 #include "opcode/cgen.h"
 326
 327 extern const struct cgen_ifld cris_cgen_ifld_table[];
 328
 329 /* Attributes.  */
 330 extern const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[];
 331 extern const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[];
 332 extern const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[];
 333 extern const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[];
 334
 335 /* Hardware decls.  */
 336
 337 extern CGEN_KEYWORD cris_cgen_opval_h_inc;
 338 extern CGEN_KEYWORD cris_cgen_opval_h_ccode;
 339 extern CGEN_KEYWORD cris_cgen_opval_h_swap;
 340 extern CGEN_KEYWORD cris_cgen_opval_h_flagbits;
 341 extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg;
 342 extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg;
 343 extern CGEN_KEYWORD cris_cgen_opval_gr_names_acr;
 344 extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
 345 extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
 346 extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
 347 extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
 348 extern CGEN_KEYWORD cris_cgen_opval_p_names_v32;
 349 extern CGEN_KEYWORD cris_cgen_opval_h_supr;
 350
 351 extern const CGEN_HW_ENTRY cris_cgen_hw_table[];
 352
 353
 354
 355 #endif /* CRIS_CPU_H */