sim/cris/crisv10f.c

   1 /* CRIS v10 simulator support code
   2    Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009, 2010
   3    Free Software Foundation, Inc.
   4    Contributed by Axis Communications.
   5
   6 This file is part of the GNU simulators.
   7
   8 This program is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3 of the License, or
  11 (at your option) any later version.
  12
  13 This program is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 /* The infrastructure is based on that of i960.c.  */
  22
  23 #define WANT_CPU_CRISV10F
  24
  25 #define BASENUM 10
  26 #define CRIS_TLS_REGISTER 14
  27 #include "cris-tmpl.c"
  28
  29 #if WITH_PROFILE_MODEL_P
  30
  31 /* Model function for u-multiply unit.  */
  32
  33 int
  34 MY (XCONCAT3 (f_model_crisv,BASENUM,
  35               _u_multiply)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
  36                              const IDESC *idesc ATTRIBUTE_UNUSED,
  37                              int unit_num ATTRIBUTE_UNUSED,
  38                              int referenced ATTRIBUTE_UNUSED)
  39 {
  40   return 1;
  41 }
  42
  43 #endif /* WITH_PROFILE_MODEL_P */
  44
  45 /* Do the interrupt sequence if possible, and return 1.  If interrupts
  46    are disabled or some other lockout is active, return 0 and do
  47    nothing.
  48
  49    Beware, the v10 implementation is incomplete and doesn't properly
  50    lock out interrupts e.g. after special-register access and doesn't
  51    handle user-mode.  */
  52
  53 int
  54 MY (deliver_interrupt) (SIM_CPU *current_cpu,
  55                         enum cris_interrupt_type type,
  56                         unsigned int vec)
  57 {
  58   unsigned char entryaddr_le[4];
  59   int was_user;
  60   SIM_DESC sd = CPU_STATE (current_cpu);
  61   unsigned32 entryaddr;
  62
  63   /* We haven't implemented other interrupt-types yet.  */
  64   if (type != CRIS_INT_INT)
  65     abort ();
  66
  67   /* We're supposed to be called outside of prefixes and branch
  68      delay-slots etc, but why not check.  */
  69   if (GET_H_INSN_PREFIXED_P ())
  70     abort ();
  71
  72   if (!GET_H_IBIT ())
  73     return 0;
  74
  75   /* User mode isn't supported for interrupts.  (And we shouldn't see
  76      this as 1 anyway.  The user-mode bit isn't visible from user
  77      mode.  It doesn't make it into the U bit until the next
  78      interrupt/exception.)  */
  79   if (GET_H_UBIT ())
  80     abort ();
  81
  82   SET_H_PBIT (1);
  83
  84   if (sim_core_read_buffer (sd,
  85                             current_cpu,
  86                             read_map, entryaddr_le,
  87                             GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4, 4) == 0)
  88     {
  89       /* Nothing to do actually; either abort or send a signal.  */
  90       sim_core_signal (sd, current_cpu, CIA_GET (current_cpu), 0, 4,
  91                        GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4,
  92                        read_transfer, sim_core_unmapped_signal);
  93       return 0;
  94     }
  95
  96   entryaddr = bfd_getl32 (entryaddr_le);
  97
  98   SET_H_SR (H_SR_PRE_V32_IRP, GET_H_PC ());
  99   SET_H_PC (entryaddr);
 100
 101   return 1;
 102 }