sim/cris/semcrisv10f-switch.c

   1 /* Simulator instruction semantics for crisv10f.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2005 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifdef DEFINE_LABELS
  26
  27   /* The labels have the case they have because the enum of insn types
  28      is all uppercase and in the non-stdc case the insn symbol is built
  29      into the enum name.  */
  30
  31   static struct {
  32     int index;
  33     void *label;
  34   } labels[] = {
  35     { CRISV10F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
  36     { CRISV10F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
  37     { CRISV10F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
  38     { CRISV10F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
  39     { CRISV10F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
  40     { CRISV10F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
  41     { CRISV10F_INSN_NOP, && case_sem_INSN_NOP },
  42     { CRISV10F_INSN_MOVE_B_R, && case_sem_INSN_MOVE_B_R },
  43     { CRISV10F_INSN_MOVE_W_R, && case_sem_INSN_MOVE_W_R },
  44     { CRISV10F_INSN_MOVE_D_R, && case_sem_INSN_MOVE_D_R },
  45     { CRISV10F_INSN_MOVEPCR, && case_sem_INSN_MOVEPCR },
  46     { CRISV10F_INSN_MOVEQ, && case_sem_INSN_MOVEQ },
  47     { CRISV10F_INSN_MOVS_B_R, && case_sem_INSN_MOVS_B_R },
  48     { CRISV10F_INSN_MOVS_W_R, && case_sem_INSN_MOVS_W_R },
  49     { CRISV10F_INSN_MOVU_B_R, && case_sem_INSN_MOVU_B_R },
  50     { CRISV10F_INSN_MOVU_W_R, && case_sem_INSN_MOVU_W_R },
  51     { CRISV10F_INSN_MOVECBR, && case_sem_INSN_MOVECBR },
  52     { CRISV10F_INSN_MOVECWR, && case_sem_INSN_MOVECWR },
  53     { CRISV10F_INSN_MOVECDR, && case_sem_INSN_MOVECDR },
  54     { CRISV10F_INSN_MOVSCBR, && case_sem_INSN_MOVSCBR },
  55     { CRISV10F_INSN_MOVSCWR, && case_sem_INSN_MOVSCWR },
  56     { CRISV10F_INSN_MOVUCBR, && case_sem_INSN_MOVUCBR },
  57     { CRISV10F_INSN_MOVUCWR, && case_sem_INSN_MOVUCWR },
  58     { CRISV10F_INSN_ADDQ, && case_sem_INSN_ADDQ },
  59     { CRISV10F_INSN_SUBQ, && case_sem_INSN_SUBQ },
  60     { CRISV10F_INSN_CMP_R_B_R, && case_sem_INSN_CMP_R_B_R },
  61     { CRISV10F_INSN_CMP_R_W_R, && case_sem_INSN_CMP_R_W_R },
  62     { CRISV10F_INSN_CMP_R_D_R, && case_sem_INSN_CMP_R_D_R },
  63     { CRISV10F_INSN_CMP_M_B_M, && case_sem_INSN_CMP_M_B_M },
  64     { CRISV10F_INSN_CMP_M_W_M, && case_sem_INSN_CMP_M_W_M },
  65     { CRISV10F_INSN_CMP_M_D_M, && case_sem_INSN_CMP_M_D_M },
  66     { CRISV10F_INSN_CMPCBR, && case_sem_INSN_CMPCBR },
  67     { CRISV10F_INSN_CMPCWR, && case_sem_INSN_CMPCWR },
  68     { CRISV10F_INSN_CMPCDR, && case_sem_INSN_CMPCDR },
  69     { CRISV10F_INSN_CMPQ, && case_sem_INSN_CMPQ },
  70     { CRISV10F_INSN_CMPS_M_B_M, && case_sem_INSN_CMPS_M_B_M },
  71     { CRISV10F_INSN_CMPS_M_W_M, && case_sem_INSN_CMPS_M_W_M },
  72     { CRISV10F_INSN_CMPSCBR, && case_sem_INSN_CMPSCBR },
  73     { CRISV10F_INSN_CMPSCWR, && case_sem_INSN_CMPSCWR },
  74     { CRISV10F_INSN_CMPU_M_B_M, && case_sem_INSN_CMPU_M_B_M },
  75     { CRISV10F_INSN_CMPU_M_W_M, && case_sem_INSN_CMPU_M_W_M },
  76     { CRISV10F_INSN_CMPUCBR, && case_sem_INSN_CMPUCBR },
  77     { CRISV10F_INSN_CMPUCWR, && case_sem_INSN_CMPUCWR },
  78     { CRISV10F_INSN_MOVE_M_B_M, && case_sem_INSN_MOVE_M_B_M },
  79     { CRISV10F_INSN_MOVE_M_W_M, && case_sem_INSN_MOVE_M_W_M },
  80     { CRISV10F_INSN_MOVE_M_D_M, && case_sem_INSN_MOVE_M_D_M },
  81     { CRISV10F_INSN_MOVS_M_B_M, && case_sem_INSN_MOVS_M_B_M },
  82     { CRISV10F_INSN_MOVS_M_W_M, && case_sem_INSN_MOVS_M_W_M },
  83     { CRISV10F_INSN_MOVU_M_B_M, && case_sem_INSN_MOVU_M_B_M },
  84     { CRISV10F_INSN_MOVU_M_W_M, && case_sem_INSN_MOVU_M_W_M },
  85     { CRISV10F_INSN_MOVE_R_SPRV10, && case_sem_INSN_MOVE_R_SPRV10 },
  86     { CRISV10F_INSN_MOVE_SPR_RV10, && case_sem_INSN_MOVE_SPR_RV10 },
  87     { CRISV10F_INSN_RET_TYPE, && case_sem_INSN_RET_TYPE },
  88     { CRISV10F_INSN_MOVE_M_SPRV10, && case_sem_INSN_MOVE_M_SPRV10 },
  89     { CRISV10F_INSN_MOVE_C_SPRV10_P5, && case_sem_INSN_MOVE_C_SPRV10_P5 },
  90     { CRISV10F_INSN_MOVE_C_SPRV10_P9, && case_sem_INSN_MOVE_C_SPRV10_P9 },
  91     { CRISV10F_INSN_MOVE_C_SPRV10_P10, && case_sem_INSN_MOVE_C_SPRV10_P10 },
  92     { CRISV10F_INSN_MOVE_C_SPRV10_P11, && case_sem_INSN_MOVE_C_SPRV10_P11 },
  93     { CRISV10F_INSN_MOVE_C_SPRV10_P12, && case_sem_INSN_MOVE_C_SPRV10_P12 },
  94     { CRISV10F_INSN_MOVE_C_SPRV10_P13, && case_sem_INSN_MOVE_C_SPRV10_P13 },
  95     { CRISV10F_INSN_MOVE_C_SPRV10_P7, && case_sem_INSN_MOVE_C_SPRV10_P7 },
  96     { CRISV10F_INSN_MOVE_C_SPRV10_P14, && case_sem_INSN_MOVE_C_SPRV10_P14 },
  97     { CRISV10F_INSN_MOVE_C_SPRV10_P15, && case_sem_INSN_MOVE_C_SPRV10_P15 },
  98     { CRISV10F_INSN_MOVE_SPR_MV10, && case_sem_INSN_MOVE_SPR_MV10 },
  99     { CRISV10F_INSN_SBFS, && case_sem_INSN_SBFS },
 100     { CRISV10F_INSN_MOVEM_R_M, && case_sem_INSN_MOVEM_R_M },
 101     { CRISV10F_INSN_MOVEM_M_R, && case_sem_INSN_MOVEM_M_R },
 102     { CRISV10F_INSN_MOVEM_M_PC, && case_sem_INSN_MOVEM_M_PC },
 103     { CRISV10F_INSN_ADD_B_R, && case_sem_INSN_ADD_B_R },
 104     { CRISV10F_INSN_ADD_W_R, && case_sem_INSN_ADD_W_R },
 105     { CRISV10F_INSN_ADD_D_R, && case_sem_INSN_ADD_D_R },
 106     { CRISV10F_INSN_ADD_M_B_M, && case_sem_INSN_ADD_M_B_M },
 107     { CRISV10F_INSN_ADD_M_W_M, && case_sem_INSN_ADD_M_W_M },
 108     { CRISV10F_INSN_ADD_M_D_M, && case_sem_INSN_ADD_M_D_M },
 109     { CRISV10F_INSN_ADDCBR, && case_sem_INSN_ADDCBR },
 110     { CRISV10F_INSN_ADDCWR, && case_sem_INSN_ADDCWR },
 111     { CRISV10F_INSN_ADDCDR, && case_sem_INSN_ADDCDR },
 112     { CRISV10F_INSN_ADDCPC, && case_sem_INSN_ADDCPC },
 113     { CRISV10F_INSN_ADDS_B_R, && case_sem_INSN_ADDS_B_R },
 114     { CRISV10F_INSN_ADDS_W_R, && case_sem_INSN_ADDS_W_R },
 115     { CRISV10F_INSN_ADDS_M_B_M, && case_sem_INSN_ADDS_M_B_M },
 116     { CRISV10F_INSN_ADDS_M_W_M, && case_sem_INSN_ADDS_M_W_M },
 117     { CRISV10F_INSN_ADDSCBR, && case_sem_INSN_ADDSCBR },
 118     { CRISV10F_INSN_ADDSCWR, && case_sem_INSN_ADDSCWR },
 119     { CRISV10F_INSN_ADDSPCPC, && case_sem_INSN_ADDSPCPC },
 120     { CRISV10F_INSN_ADDU_B_R, && case_sem_INSN_ADDU_B_R },
 121     { CRISV10F_INSN_ADDU_W_R, && case_sem_INSN_ADDU_W_R },
 122     { CRISV10F_INSN_ADDU_M_B_M, && case_sem_INSN_ADDU_M_B_M },
 123     { CRISV10F_INSN_ADDU_M_W_M, && case_sem_INSN_ADDU_M_W_M },
 124     { CRISV10F_INSN_ADDUCBR, && case_sem_INSN_ADDUCBR },
 125     { CRISV10F_INSN_ADDUCWR, && case_sem_INSN_ADDUCWR },
 126     { CRISV10F_INSN_SUB_B_R, && case_sem_INSN_SUB_B_R },
 127     { CRISV10F_INSN_SUB_W_R, && case_sem_INSN_SUB_W_R },
 128     { CRISV10F_INSN_SUB_D_R, && case_sem_INSN_SUB_D_R },
 129     { CRISV10F_INSN_SUB_M_B_M, && case_sem_INSN_SUB_M_B_M },
 130     { CRISV10F_INSN_SUB_M_W_M, && case_sem_INSN_SUB_M_W_M },
 131     { CRISV10F_INSN_SUB_M_D_M, && case_sem_INSN_SUB_M_D_M },
 132     { CRISV10F_INSN_SUBCBR, && case_sem_INSN_SUBCBR },
 133     { CRISV10F_INSN_SUBCWR, && case_sem_INSN_SUBCWR },
 134     { CRISV10F_INSN_SUBCDR, && case_sem_INSN_SUBCDR },
 135     { CRISV10F_INSN_SUBS_B_R, && case_sem_INSN_SUBS_B_R },
 136     { CRISV10F_INSN_SUBS_W_R, && case_sem_INSN_SUBS_W_R },
 137     { CRISV10F_INSN_SUBS_M_B_M, && case_sem_INSN_SUBS_M_B_M },
 138     { CRISV10F_INSN_SUBS_M_W_M, && case_sem_INSN_SUBS_M_W_M },
 139     { CRISV10F_INSN_SUBSCBR, && case_sem_INSN_SUBSCBR },
 140     { CRISV10F_INSN_SUBSCWR, && case_sem_INSN_SUBSCWR },
 141     { CRISV10F_INSN_SUBU_B_R, && case_sem_INSN_SUBU_B_R },
 142     { CRISV10F_INSN_SUBU_W_R, && case_sem_INSN_SUBU_W_R },
 143     { CRISV10F_INSN_SUBU_M_B_M, && case_sem_INSN_SUBU_M_B_M },
 144     { CRISV10F_INSN_SUBU_M_W_M, && case_sem_INSN_SUBU_M_W_M },
 145     { CRISV10F_INSN_SUBUCBR, && case_sem_INSN_SUBUCBR },
 146     { CRISV10F_INSN_SUBUCWR, && case_sem_INSN_SUBUCWR },
 147     { CRISV10F_INSN_ADDI_B_R, && case_sem_INSN_ADDI_B_R },
 148     { CRISV10F_INSN_ADDI_W_R, && case_sem_INSN_ADDI_W_R },
 149     { CRISV10F_INSN_ADDI_D_R, && case_sem_INSN_ADDI_D_R },
 150     { CRISV10F_INSN_NEG_B_R, && case_sem_INSN_NEG_B_R },
 151     { CRISV10F_INSN_NEG_W_R, && case_sem_INSN_NEG_W_R },
 152     { CRISV10F_INSN_NEG_D_R, && case_sem_INSN_NEG_D_R },
 153     { CRISV10F_INSN_TEST_M_B_M, && case_sem_INSN_TEST_M_B_M },
 154     { CRISV10F_INSN_TEST_M_W_M, && case_sem_INSN_TEST_M_W_M },
 155     { CRISV10F_INSN_TEST_M_D_M, && case_sem_INSN_TEST_M_D_M },
 156     { CRISV10F_INSN_MOVE_R_M_B_M, && case_sem_INSN_MOVE_R_M_B_M },
 157     { CRISV10F_INSN_MOVE_R_M_W_M, && case_sem_INSN_MOVE_R_M_W_M },
 158     { CRISV10F_INSN_MOVE_R_M_D_M, && case_sem_INSN_MOVE_R_M_D_M },
 159     { CRISV10F_INSN_MULS_B, && case_sem_INSN_MULS_B },
 160     { CRISV10F_INSN_MULS_W, && case_sem_INSN_MULS_W },
 161     { CRISV10F_INSN_MULS_D, && case_sem_INSN_MULS_D },
 162     { CRISV10F_INSN_MULU_B, && case_sem_INSN_MULU_B },
 163     { CRISV10F_INSN_MULU_W, && case_sem_INSN_MULU_W },
 164     { CRISV10F_INSN_MULU_D, && case_sem_INSN_MULU_D },
 165     { CRISV10F_INSN_MSTEP, && case_sem_INSN_MSTEP },
 166     { CRISV10F_INSN_DSTEP, && case_sem_INSN_DSTEP },
 167     { CRISV10F_INSN_ABS, && case_sem_INSN_ABS },
 168     { CRISV10F_INSN_AND_B_R, && case_sem_INSN_AND_B_R },
 169     { CRISV10F_INSN_AND_W_R, && case_sem_INSN_AND_W_R },
 170     { CRISV10F_INSN_AND_D_R, && case_sem_INSN_AND_D_R },
 171     { CRISV10F_INSN_AND_M_B_M, && case_sem_INSN_AND_M_B_M },
 172     { CRISV10F_INSN_AND_M_W_M, && case_sem_INSN_AND_M_W_M },
 173     { CRISV10F_INSN_AND_M_D_M, && case_sem_INSN_AND_M_D_M },
 174     { CRISV10F_INSN_ANDCBR, && case_sem_INSN_ANDCBR },
 175     { CRISV10F_INSN_ANDCWR, && case_sem_INSN_ANDCWR },
 176     { CRISV10F_INSN_ANDCDR, && case_sem_INSN_ANDCDR },
 177     { CRISV10F_INSN_ANDQ, && case_sem_INSN_ANDQ },
 178     { CRISV10F_INSN_ORR_B_R, && case_sem_INSN_ORR_B_R },
 179     { CRISV10F_INSN_ORR_W_R, && case_sem_INSN_ORR_W_R },
 180     { CRISV10F_INSN_ORR_D_R, && case_sem_INSN_ORR_D_R },
 181     { CRISV10F_INSN_OR_M_B_M, && case_sem_INSN_OR_M_B_M },
 182     { CRISV10F_INSN_OR_M_W_M, && case_sem_INSN_OR_M_W_M },
 183     { CRISV10F_INSN_OR_M_D_M, && case_sem_INSN_OR_M_D_M },
 184     { CRISV10F_INSN_ORCBR, && case_sem_INSN_ORCBR },
 185     { CRISV10F_INSN_ORCWR, && case_sem_INSN_ORCWR },
 186     { CRISV10F_INSN_ORCDR, && case_sem_INSN_ORCDR },
 187     { CRISV10F_INSN_ORQ, && case_sem_INSN_ORQ },
 188     { CRISV10F_INSN_XOR, && case_sem_INSN_XOR },
 189     { CRISV10F_INSN_SWAP, && case_sem_INSN_SWAP },
 190     { CRISV10F_INSN_ASRR_B_R, && case_sem_INSN_ASRR_B_R },
 191     { CRISV10F_INSN_ASRR_W_R, && case_sem_INSN_ASRR_W_R },
 192     { CRISV10F_INSN_ASRR_D_R, && case_sem_INSN_ASRR_D_R },
 193     { CRISV10F_INSN_ASRQ, && case_sem_INSN_ASRQ },
 194     { CRISV10F_INSN_LSRR_B_R, && case_sem_INSN_LSRR_B_R },
 195     { CRISV10F_INSN_LSRR_W_R, && case_sem_INSN_LSRR_W_R },
 196     { CRISV10F_INSN_LSRR_D_R, && case_sem_INSN_LSRR_D_R },
 197     { CRISV10F_INSN_LSRQ, && case_sem_INSN_LSRQ },
 198     { CRISV10F_INSN_LSLR_B_R, && case_sem_INSN_LSLR_B_R },
 199     { CRISV10F_INSN_LSLR_W_R, && case_sem_INSN_LSLR_W_R },
 200     { CRISV10F_INSN_LSLR_D_R, && case_sem_INSN_LSLR_D_R },
 201     { CRISV10F_INSN_LSLQ, && case_sem_INSN_LSLQ },
 202     { CRISV10F_INSN_BTST, && case_sem_INSN_BTST },
 203     { CRISV10F_INSN_BTSTQ, && case_sem_INSN_BTSTQ },
 204     { CRISV10F_INSN_SETF, && case_sem_INSN_SETF },
 205     { CRISV10F_INSN_CLEARF, && case_sem_INSN_CLEARF },
 206     { CRISV10F_INSN_BCC_B, && case_sem_INSN_BCC_B },
 207     { CRISV10F_INSN_BA_B, && case_sem_INSN_BA_B },
 208     { CRISV10F_INSN_BCC_W, && case_sem_INSN_BCC_W },
 209     { CRISV10F_INSN_BA_W, && case_sem_INSN_BA_W },
 210     { CRISV10F_INSN_JUMP_R, && case_sem_INSN_JUMP_R },
 211     { CRISV10F_INSN_JUMP_M, && case_sem_INSN_JUMP_M },
 212     { CRISV10F_INSN_JUMP_C, && case_sem_INSN_JUMP_C },
 213     { CRISV10F_INSN_BREAK, && case_sem_INSN_BREAK },
 214     { CRISV10F_INSN_BOUND_R_B_R, && case_sem_INSN_BOUND_R_B_R },
 215     { CRISV10F_INSN_BOUND_R_W_R, && case_sem_INSN_BOUND_R_W_R },
 216     { CRISV10F_INSN_BOUND_R_D_R, && case_sem_INSN_BOUND_R_D_R },
 217     { CRISV10F_INSN_BOUND_M_B_M, && case_sem_INSN_BOUND_M_B_M },
 218     { CRISV10F_INSN_BOUND_M_W_M, && case_sem_INSN_BOUND_M_W_M },
 219     { CRISV10F_INSN_BOUND_M_D_M, && case_sem_INSN_BOUND_M_D_M },
 220     { CRISV10F_INSN_BOUND_CB, && case_sem_INSN_BOUND_CB },
 221     { CRISV10F_INSN_BOUND_CW, && case_sem_INSN_BOUND_CW },
 222     { CRISV10F_INSN_BOUND_CD, && case_sem_INSN_BOUND_CD },
 223     { CRISV10F_INSN_SCC, && case_sem_INSN_SCC },
 224     { CRISV10F_INSN_LZ, && case_sem_INSN_LZ },
 225     { CRISV10F_INSN_ADDOQ, && case_sem_INSN_ADDOQ },
 226     { CRISV10F_INSN_BDAPQPC, && case_sem_INSN_BDAPQPC },
 227     { CRISV10F_INSN_BDAP_32_PC, && case_sem_INSN_BDAP_32_PC },
 228     { CRISV10F_INSN_MOVE_M_PCPLUS_P0, && case_sem_INSN_MOVE_M_PCPLUS_P0 },
 229     { CRISV10F_INSN_MOVE_M_SPPLUS_P8, && case_sem_INSN_MOVE_M_SPPLUS_P8 },
 230     { CRISV10F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M },
 231     { CRISV10F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M },
 232     { CRISV10F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M },
 233     { CRISV10F_INSN_ADDO_CB, && case_sem_INSN_ADDO_CB },
 234     { CRISV10F_INSN_ADDO_CW, && case_sem_INSN_ADDO_CW },
 235     { CRISV10F_INSN_ADDO_CD, && case_sem_INSN_ADDO_CD },
 236     { CRISV10F_INSN_DIP_M, && case_sem_INSN_DIP_M },
 237     { CRISV10F_INSN_DIP_C, && case_sem_INSN_DIP_C },
 238     { CRISV10F_INSN_ADDI_ACR_B_R, && case_sem_INSN_ADDI_ACR_B_R },
 239     { CRISV10F_INSN_ADDI_ACR_W_R, && case_sem_INSN_ADDI_ACR_W_R },
 240     { CRISV10F_INSN_ADDI_ACR_D_R, && case_sem_INSN_ADDI_ACR_D_R },
 241     { CRISV10F_INSN_BIAP_PC_B_R, && case_sem_INSN_BIAP_PC_B_R },
 242     { CRISV10F_INSN_BIAP_PC_W_R, && case_sem_INSN_BIAP_PC_W_R },
 243     { CRISV10F_INSN_BIAP_PC_D_R, && case_sem_INSN_BIAP_PC_D_R },
 244     { 0, 0 }
 245   };
 246   int i;
 247
 248   for (i = 0; labels[i].label != 0; ++i)
 249     {
 250 #if FAST_P
 251       CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 252 #else
 253       CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 254 #endif
 255     }
 256
 257 #undef DEFINE_LABELS
 258 #endif /* DEFINE_LABELS */
 259
 260 #ifdef DEFINE_SWITCH
 261
 262 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 263    off frills like tracing and profiling.  */
 264 /* FIXME: A better way would be to have TRACE_RESULT check for something
 265    that can cause it to be optimized out.  Another way would be to emit
 266    special handlers into the instruction "stream".  */
 267
 268 #if FAST_P
 269 #undef TRACE_RESULT
 270 #define TRACE_RESULT(cpu, abuf, name, type, val)
 271 #endif
 272
 273 #undef GET_ATTR
 274 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 275 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 276 #else
 277 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
 278 #endif
 279
 280 {
 281
 282 #if WITH_SCACHE_PBB
 283
 284 /* Branch to next handler without going around main loop.  */
 285 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
 286 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 287
 288 #else /* ! WITH_SCACHE_PBB */
 289
 290 #define NEXT(vpc) BREAK (sem)
 291 #ifdef __GNUC__
 292 #if FAST_P
 293   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
 294 #else
 295   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
 296 #endif
 297 #else
 298   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
 299 #endif
 300
 301 #endif /* ! WITH_SCACHE_PBB */
 302
 303     {
 304
 305   CASE (sem, INSN_X_INVALID) : /* --invalid-- */
 306 {
 307   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 308   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 309 #define FLD(f) abuf->fields.fmt_empty.f
 310   int UNUSED written = 0;
 311   IADDR UNUSED pc = abuf->addr;
 312   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 313
 314   {
 315     /* Update the recorded pc in the cpu state struct.
 316        Only necessary for WITH_SCACHE case, but to avoid the
 317        conditional compilation ....  */
 318     SET_H_PC (pc);
 319     /* Virtual insns have zero size.  Overwrite vpc with address of next insn
 320        using the default-insn-bitsize spec.  When executing insns in parallel
 321        we may want to queue the fault and continue execution.  */
 322     vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 323     vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
 324   }
 325
 326 #undef FLD
 327 }
 328   NEXT (vpc);
 329
 330   CASE (sem, INSN_X_AFTER) : /* --after-- */
 331 {
 332   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 333   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 334 #define FLD(f) abuf->fields.fmt_empty.f
 335   int UNUSED written = 0;
 336   IADDR UNUSED pc = abuf->addr;
 337   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 338
 339   {
 340 #if WITH_SCACHE_PBB_CRISV10F
 341     crisv10f_pbb_after (current_cpu, sem_arg);
 342 #endif
 343   }
 344
 345 #undef FLD
 346 }
 347   NEXT (vpc);
 348
 349   CASE (sem, INSN_X_BEFORE) : /* --before-- */
 350 {
 351   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 352   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 353 #define FLD(f) abuf->fields.fmt_empty.f
 354   int UNUSED written = 0;
 355   IADDR UNUSED pc = abuf->addr;
 356   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 357
 358   {
 359 #if WITH_SCACHE_PBB_CRISV10F
 360     crisv10f_pbb_before (current_cpu, sem_arg);
 361 #endif
 362   }
 363
 364 #undef FLD
 365 }
 366   NEXT (vpc);
 367
 368   CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
 369 {
 370   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 371   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 372 #define FLD(f) abuf->fields.fmt_empty.f
 373   int UNUSED written = 0;
 374   IADDR UNUSED pc = abuf->addr;
 375   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 376
 377   {
 378 #if WITH_SCACHE_PBB_CRISV10F
 379 #ifdef DEFINE_SWITCH
 380     vpc = crisv10f_pbb_cti_chain (current_cpu, sem_arg,
 381                                pbb_br_type, pbb_br_npc);
 382     BREAK (sem);
 383 #else
 384     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
 385     vpc = crisv10f_pbb_cti_chain (current_cpu, sem_arg,
 386                                CPU_PBB_BR_TYPE (current_cpu),
 387                                CPU_PBB_BR_NPC (current_cpu));
 388 #endif
 389 #endif
 390   }
 391
 392 #undef FLD
 393 }
 394   NEXT (vpc);
 395
 396   CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 397 {
 398   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 399   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 400 #define FLD(f) abuf->fields.fmt_empty.f
 401   int UNUSED written = 0;
 402   IADDR UNUSED pc = abuf->addr;
 403   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 404
 405   {
 406 #if WITH_SCACHE_PBB_CRISV10F
 407     vpc = crisv10f_pbb_chain (current_cpu, sem_arg);
 408 #ifdef DEFINE_SWITCH
 409     BREAK (sem);
 410 #endif
 411 #endif
 412   }
 413
 414 #undef FLD
 415 }
 416   NEXT (vpc);
 417
 418   CASE (sem, INSN_X_BEGIN) : /* --begin-- */
 419 {
 420   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 421   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 422 #define FLD(f) abuf->fields.fmt_empty.f
 423   int UNUSED written = 0;
 424   IADDR UNUSED pc = abuf->addr;
 425   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 426
 427   {
 428 #if WITH_SCACHE_PBB_CRISV10F
 429 #if defined DEFINE_SWITCH || defined FAST_P
 430     /* In the switch case FAST_P is a constant, allowing several optimizations
 431        in any called inline functions.  */
 432     vpc = crisv10f_pbb_begin (current_cpu, FAST_P);
 433 #else
 434 #if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
 435     vpc = crisv10f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
 436 #else
 437     vpc = crisv10f_pbb_begin (current_cpu, 0);
 438 #endif
 439 #endif
 440 #endif
 441   }
 442
 443 #undef FLD
 444 }
 445   NEXT (vpc);
 446
 447   CASE (sem, INSN_NOP) : /* nop */
 448 {
 449   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 450   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 451 #define FLD(f) abuf->fields.fmt_empty.f
 452   int UNUSED written = 0;
 453   IADDR UNUSED pc = abuf->addr;
 454   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 455
 456 {
 457   {
 458     BI opval = 0;
 459     CPU (h_xbit) = opval;
 460     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 461   }
 462   {
 463     BI opval = 0;
 464     SET_H_INSN_PREFIXED_P (opval);
 465     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 466   }
 467 }
 468
 469 #undef FLD
 470 }
 471   NEXT (vpc);
 472
 473   CASE (sem, INSN_MOVE_B_R) : /* move.b move.m ${Rs},${Rd} */
 474 {
 475   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 476   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 477 #define FLD(f) abuf->fields.sfmt_add_b_r.f
 478   int UNUSED written = 0;
 479   IADDR UNUSED pc = abuf->addr;
 480   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 481
 482 {
 483   QI tmp_newval;
 484   tmp_newval = GET_H_GR (FLD (f_operand1));
 485 {
 486   SI tmp_oldregval;
 487   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 488   {
 489     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 490     SET_H_GR (FLD (f_operand2), opval);
 491     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 492   }
 493 }
 494 {
 495   {
 496     BI opval = LTQI (tmp_newval, 0);
 497     CPU (h_nbit) = opval;
 498     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 499   }
 500   {
 501     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 502     CPU (h_zbit) = opval;
 503     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 504   }
 505 SET_H_CBIT_MOVE (0);
 506 SET_H_VBIT_MOVE (0);
 507 {
 508   {
 509     BI opval = 0;
 510     CPU (h_xbit) = opval;
 511     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 512   }
 513   {
 514     BI opval = 0;
 515     SET_H_INSN_PREFIXED_P (opval);
 516     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 517   }
 518 }
 519 }
 520 }
 521
 522 #undef FLD
 523 }
 524   NEXT (vpc);
 525
 526   CASE (sem, INSN_MOVE_W_R) : /* move.w move.m ${Rs},${Rd} */
 527 {
 528   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 529   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 530 #define FLD(f) abuf->fields.sfmt_add_b_r.f
 531   int UNUSED written = 0;
 532   IADDR UNUSED pc = abuf->addr;
 533   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 534
 535 {
 536   HI tmp_newval;
 537   tmp_newval = GET_H_GR (FLD (f_operand1));
 538 {
 539   SI tmp_oldregval;
 540   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 541   {
 542     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 543     SET_H_GR (FLD (f_operand2), opval);
 544     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 545   }
 546 }
 547 {
 548   {
 549     BI opval = LTHI (tmp_newval, 0);
 550     CPU (h_nbit) = opval;
 551     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 552   }
 553   {
 554     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 555     CPU (h_zbit) = opval;
 556     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 557   }
 558 SET_H_CBIT_MOVE (0);
 559 SET_H_VBIT_MOVE (0);
 560 {
 561   {
 562     BI opval = 0;
 563     CPU (h_xbit) = opval;
 564     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 565   }
 566   {
 567     BI opval = 0;
 568     SET_H_INSN_PREFIXED_P (opval);
 569     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 570   }
 571 }
 572 }
 573 }
 574
 575 #undef FLD
 576 }
 577   NEXT (vpc);
 578
 579   CASE (sem, INSN_MOVE_D_R) : /* move.d move.m ${Rs},${Rd} */
 580 {
 581   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 582   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 583 #define FLD(f) abuf->fields.sfmt_add_b_r.f
 584   int UNUSED written = 0;
 585   IADDR UNUSED pc = abuf->addr;
 586   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 587
 588 {
 589   SI tmp_newval;
 590   tmp_newval = GET_H_GR (FLD (f_operand1));
 591   {
 592     SI opval = tmp_newval;
 593     SET_H_GR (FLD (f_operand2), opval);
 594     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 595   }
 596 {
 597   {
 598     BI opval = LTSI (tmp_newval, 0);
 599     CPU (h_nbit) = opval;
 600     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 601   }
 602   {
 603     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 604     CPU (h_zbit) = opval;
 605     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 606   }
 607 SET_H_CBIT_MOVE (0);
 608 SET_H_VBIT_MOVE (0);
 609 {
 610   {
 611     BI opval = 0;
 612     CPU (h_xbit) = opval;
 613     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 614   }
 615   {
 616     BI opval = 0;
 617     SET_H_INSN_PREFIXED_P (opval);
 618     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 619   }
 620 }
 621 }
 622 }
 623
 624 #undef FLD
 625 }
 626   NEXT (vpc);
 627
 628   CASE (sem, INSN_MOVEPCR) : /* move.d PC,${Rd} */
 629 {
 630   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 631   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 632 #define FLD(f) abuf->fields.sfmt_moveq.f
 633   int UNUSED written = 0;
 634   IADDR UNUSED pc = abuf->addr;
 635   SEM_BRANCH_INIT
 636   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 637
 638 {
 639   SI tmp_pcval;
 640   tmp_pcval = ADDSI (pc, 2);
 641   {
 642     SI opval = tmp_pcval;
 643     SET_H_GR (FLD (f_operand2), opval);
 644     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 645   }
 646 {
 647   {
 648     BI opval = LTSI (tmp_pcval, 0);
 649     CPU (h_nbit) = opval;
 650     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 651   }
 652   {
 653     BI opval = ANDIF (EQSI (tmp_pcval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 654     CPU (h_zbit) = opval;
 655     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 656   }
 657 SET_H_CBIT_MOVE (0);
 658 SET_H_VBIT_MOVE (0);
 659 {
 660   {
 661     BI opval = 0;
 662     CPU (h_xbit) = opval;
 663     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 664   }
 665   {
 666     BI opval = 0;
 667     SET_H_INSN_PREFIXED_P (opval);
 668     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 669   }
 670 }
 671 }
 672 }
 673
 674   SEM_BRANCH_FINI (vpc);
 675 #undef FLD
 676 }
 677   NEXT (vpc);
 678
 679   CASE (sem, INSN_MOVEQ) : /* moveq $i,$Rd */
 680 {
 681   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 682   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 683 #define FLD(f) abuf->fields.sfmt_moveq.f
 684   int UNUSED written = 0;
 685   IADDR UNUSED pc = abuf->addr;
 686   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 687
 688 {
 689   SI tmp_newval;
 690   tmp_newval = FLD (f_s6);
 691   {
 692     SI opval = tmp_newval;
 693     SET_H_GR (FLD (f_operand2), opval);
 694     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 695   }
 696 {
 697 SET_H_NBIT_MOVE (LTSI (tmp_newval, 0));
 698 SET_H_ZBIT_MOVE (ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))));
 699 SET_H_CBIT_MOVE (0);
 700 SET_H_VBIT_MOVE (0);
 701 {
 702   {
 703     BI opval = 0;
 704     CPU (h_xbit) = opval;
 705     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 706   }
 707   {
 708     BI opval = 0;
 709     SET_H_INSN_PREFIXED_P (opval);
 710     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 711   }
 712 }
 713 }
 714 }
 715
 716 #undef FLD
 717 }
 718   NEXT (vpc);
 719
 720   CASE (sem, INSN_MOVS_B_R) : /* movs.b movs.m ${Rs},${Rd} */
 721 {
 722   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 723   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 724 #define FLD(f) abuf->fields.sfmt_muls_b.f
 725   int UNUSED written = 0;
 726   IADDR UNUSED pc = abuf->addr;
 727   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 728
 729 {
 730   QI tmp_newval;
 731   tmp_newval = GET_H_GR (FLD (f_operand1));
 732   {
 733     SI opval = EXTQISI (tmp_newval);
 734     SET_H_GR (FLD (f_operand2), opval);
 735     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 736   }
 737 {
 738   {
 739     BI opval = LTSI (tmp_newval, 0);
 740     CPU (h_nbit) = opval;
 741     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 742   }
 743   {
 744     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 745     CPU (h_zbit) = opval;
 746     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 747   }
 748 SET_H_CBIT_MOVE (0);
 749 SET_H_VBIT_MOVE (0);
 750 {
 751   {
 752     BI opval = 0;
 753     CPU (h_xbit) = opval;
 754     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 755   }
 756   {
 757     BI opval = 0;
 758     SET_H_INSN_PREFIXED_P (opval);
 759     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 760   }
 761 }
 762 }
 763 }
 764
 765 #undef FLD
 766 }
 767   NEXT (vpc);
 768
 769   CASE (sem, INSN_MOVS_W_R) : /* movs.w movs.m ${Rs},${Rd} */
 770 {
 771   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 772   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 773 #define FLD(f) abuf->fields.sfmt_muls_b.f
 774   int UNUSED written = 0;
 775   IADDR UNUSED pc = abuf->addr;
 776   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 777
 778 {
 779   HI tmp_newval;
 780   tmp_newval = GET_H_GR (FLD (f_operand1));
 781   {
 782     SI opval = EXTHISI (tmp_newval);
 783     SET_H_GR (FLD (f_operand2), opval);
 784     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 785   }
 786 {
 787   {
 788     BI opval = LTSI (tmp_newval, 0);
 789     CPU (h_nbit) = opval;
 790     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 791   }
 792   {
 793     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 794     CPU (h_zbit) = opval;
 795     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 796   }
 797 SET_H_CBIT_MOVE (0);
 798 SET_H_VBIT_MOVE (0);
 799 {
 800   {
 801     BI opval = 0;
 802     CPU (h_xbit) = opval;
 803     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 804   }
 805   {
 806     BI opval = 0;
 807     SET_H_INSN_PREFIXED_P (opval);
 808     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 809   }
 810 }
 811 }
 812 }
 813
 814 #undef FLD
 815 }
 816   NEXT (vpc);
 817
 818   CASE (sem, INSN_MOVU_B_R) : /* movu.b movu.m ${Rs},${Rd} */
 819 {
 820   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 821   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 822 #define FLD(f) abuf->fields.sfmt_muls_b.f
 823   int UNUSED written = 0;
 824   IADDR UNUSED pc = abuf->addr;
 825   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 826
 827 {
 828   QI tmp_newval;
 829   tmp_newval = GET_H_GR (FLD (f_operand1));
 830   {
 831     SI opval = ZEXTQISI (tmp_newval);
 832     SET_H_GR (FLD (f_operand2), opval);
 833     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 834   }
 835 {
 836   {
 837     BI opval = LTSI (tmp_newval, 0);
 838     CPU (h_nbit) = opval;
 839     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 840   }
 841   {
 842     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 843     CPU (h_zbit) = opval;
 844     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 845   }
 846 SET_H_CBIT_MOVE (0);
 847 SET_H_VBIT_MOVE (0);
 848 {
 849   {
 850     BI opval = 0;
 851     CPU (h_xbit) = opval;
 852     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 853   }
 854   {
 855     BI opval = 0;
 856     SET_H_INSN_PREFIXED_P (opval);
 857     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 858   }
 859 }
 860 }
 861 }
 862
 863 #undef FLD
 864 }
 865   NEXT (vpc);
 866
 867   CASE (sem, INSN_MOVU_W_R) : /* movu.w movu.m ${Rs},${Rd} */
 868 {
 869   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 870   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 871 #define FLD(f) abuf->fields.sfmt_muls_b.f
 872   int UNUSED written = 0;
 873   IADDR UNUSED pc = abuf->addr;
 874   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 875
 876 {
 877   HI tmp_newval;
 878   tmp_newval = GET_H_GR (FLD (f_operand1));
 879   {
 880     SI opval = ZEXTHISI (tmp_newval);
 881     SET_H_GR (FLD (f_operand2), opval);
 882     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 883   }
 884 {
 885   {
 886     BI opval = LTSI (tmp_newval, 0);
 887     CPU (h_nbit) = opval;
 888     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 889   }
 890   {
 891     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 892     CPU (h_zbit) = opval;
 893     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 894   }
 895 SET_H_CBIT_MOVE (0);
 896 SET_H_VBIT_MOVE (0);
 897 {
 898   {
 899     BI opval = 0;
 900     CPU (h_xbit) = opval;
 901     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 902   }
 903   {
 904     BI opval = 0;
 905     SET_H_INSN_PREFIXED_P (opval);
 906     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 907   }
 908 }
 909 }
 910 }
 911
 912 #undef FLD
 913 }
 914   NEXT (vpc);
 915
 916   CASE (sem, INSN_MOVECBR) : /* move.b ${sconst8},${Rd} */
 917 {
 918   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 919   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 920 #define FLD(f) abuf->fields.sfmt_addcbr.f
 921   int UNUSED written = 0;
 922   IADDR UNUSED pc = abuf->addr;
 923   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 924
 925 {
 926   QI tmp_newval;
 927   tmp_newval = FLD (f_indir_pc__byte);
 928 {
 929   SI tmp_oldregval;
 930   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 931   {
 932     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 933     SET_H_GR (FLD (f_operand2), opval);
 934     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 935   }
 936 }
 937 {
 938   {
 939     BI opval = LTQI (tmp_newval, 0);
 940     CPU (h_nbit) = opval;
 941     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 942   }
 943   {
 944     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 945     CPU (h_zbit) = opval;
 946     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 947   }
 948 SET_H_CBIT_MOVE (0);
 949 SET_H_VBIT_MOVE (0);
 950 {
 951   {
 952     BI opval = 0;
 953     CPU (h_xbit) = opval;
 954     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 955   }
 956   {
 957     BI opval = 0;
 958     SET_H_INSN_PREFIXED_P (opval);
 959     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 960   }
 961 }
 962 }
 963 }
 964
 965 #undef FLD
 966 }
 967   NEXT (vpc);
 968
 969   CASE (sem, INSN_MOVECWR) : /* move.w ${sconst16},${Rd} */
 970 {
 971   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 972   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 973 #define FLD(f) abuf->fields.sfmt_addcwr.f
 974   int UNUSED written = 0;
 975   IADDR UNUSED pc = abuf->addr;
 976   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 977
 978 {
 979   HI tmp_newval;
 980   tmp_newval = FLD (f_indir_pc__word);
 981 {
 982   SI tmp_oldregval;
 983   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 984   {
 985     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 986     SET_H_GR (FLD (f_operand2), opval);
 987     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 988   }
 989 }
 990 {
 991   {
 992     BI opval = LTHI (tmp_newval, 0);
 993     CPU (h_nbit) = opval;
 994     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 995   }
 996   {
 997     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 998     CPU (h_zbit) = opval;
 999     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1000   }
1001 SET_H_CBIT_MOVE (0);
1002 SET_H_VBIT_MOVE (0);
1003 {
1004   {
1005     BI opval = 0;
1006     CPU (h_xbit) = opval;
1007     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1008   }
1009   {
1010     BI opval = 0;
1011     SET_H_INSN_PREFIXED_P (opval);
1012     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1013   }
1014 }
1015 }
1016 }
1017
1018 #undef FLD
1019 }
1020   NEXT (vpc);
1021
1022   CASE (sem, INSN_MOVECDR) : /* move.d ${const32},${Rd} */
1023 {
1024   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1025   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1026 #define FLD(f) abuf->fields.sfmt_bound_cd.f
1027   int UNUSED written = 0;
1028   IADDR UNUSED pc = abuf->addr;
1029   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
1030
1031 {
1032   SI tmp_newval;
1033   tmp_newval = FLD (f_indir_pc__dword);
1034   {
1035     SI opval = tmp_newval;
1036     SET_H_GR (FLD (f_operand2), opval);
1037     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1038   }
1039 {
1040   {
1041     BI opval = LTSI (tmp_newval, 0);
1042     CPU (h_nbit) = opval;
1043     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1044   }
1045   {
1046     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1047     CPU (h_zbit) = opval;
1048     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1049   }
1050 SET_H_CBIT_MOVE (0);
1051 SET_H_VBIT_MOVE (0);
1052 {
1053   {
1054     BI opval = 0;
1055     CPU (h_xbit) = opval;
1056     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1057   }
1058   {
1059     BI opval = 0;
1060     SET_H_INSN_PREFIXED_P (opval);
1061     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1062   }
1063 }
1064 }
1065 }
1066
1067 #undef FLD
1068 }
1069   NEXT (vpc);
1070
1071   CASE (sem, INSN_MOVSCBR) : /* movs.b ${sconst8},${Rd} */
1072 {
1073   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1074   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1075 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1076   int UNUSED written = 0;
1077   IADDR UNUSED pc = abuf->addr;
1078   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1079
1080 {
1081   SI tmp_newval;
1082   tmp_newval = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1083   {
1084     SI opval = tmp_newval;
1085     SET_H_GR (FLD (f_operand2), opval);
1086     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1087   }
1088 {
1089   {
1090     BI opval = LTSI (tmp_newval, 0);
1091     CPU (h_nbit) = opval;
1092     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1093   }
1094   {
1095     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1096     CPU (h_zbit) = opval;
1097     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1098   }
1099 SET_H_CBIT_MOVE (0);
1100 SET_H_VBIT_MOVE (0);
1101 {
1102   {
1103     BI opval = 0;
1104     CPU (h_xbit) = opval;
1105     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1106   }
1107   {
1108     BI opval = 0;
1109     SET_H_INSN_PREFIXED_P (opval);
1110     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1111   }
1112 }
1113 }
1114 }
1115
1116 #undef FLD
1117 }
1118   NEXT (vpc);
1119
1120   CASE (sem, INSN_MOVSCWR) : /* movs.w ${sconst16},${Rd} */
1121 {
1122   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1123   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1124 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1125   int UNUSED written = 0;
1126   IADDR UNUSED pc = abuf->addr;
1127   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1128
1129 {
1130   SI tmp_newval;
1131   tmp_newval = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1132   {
1133     SI opval = tmp_newval;
1134     SET_H_GR (FLD (f_operand2), opval);
1135     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1136   }
1137 {
1138   {
1139     BI opval = LTSI (tmp_newval, 0);
1140     CPU (h_nbit) = opval;
1141     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1142   }
1143   {
1144     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1145     CPU (h_zbit) = opval;
1146     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1147   }
1148 SET_H_CBIT_MOVE (0);
1149 SET_H_VBIT_MOVE (0);
1150 {
1151   {
1152     BI opval = 0;
1153     CPU (h_xbit) = opval;
1154     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1155   }
1156   {
1157     BI opval = 0;
1158     SET_H_INSN_PREFIXED_P (opval);
1159     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1160   }
1161 }
1162 }
1163 }
1164
1165 #undef FLD
1166 }
1167   NEXT (vpc);
1168
1169   CASE (sem, INSN_MOVUCBR) : /* movu.b ${uconst8},${Rd} */
1170 {
1171   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1172   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1173 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1174   int UNUSED written = 0;
1175   IADDR UNUSED pc = abuf->addr;
1176   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1177
1178 {
1179   SI tmp_newval;
1180   tmp_newval = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1181   {
1182     SI opval = tmp_newval;
1183     SET_H_GR (FLD (f_operand2), opval);
1184     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1185   }
1186 {
1187   {
1188     BI opval = LTSI (tmp_newval, 0);
1189     CPU (h_nbit) = opval;
1190     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1191   }
1192   {
1193     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1194     CPU (h_zbit) = opval;
1195     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1196   }
1197 SET_H_CBIT_MOVE (0);
1198 SET_H_VBIT_MOVE (0);
1199 {
1200   {
1201     BI opval = 0;
1202     CPU (h_xbit) = opval;
1203     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1204   }
1205   {
1206     BI opval = 0;
1207     SET_H_INSN_PREFIXED_P (opval);
1208     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1209   }
1210 }
1211 }
1212 }
1213
1214 #undef FLD
1215 }
1216   NEXT (vpc);
1217
1218   CASE (sem, INSN_MOVUCWR) : /* movu.w ${uconst16},${Rd} */
1219 {
1220   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1221   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1222 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1223   int UNUSED written = 0;
1224   IADDR UNUSED pc = abuf->addr;
1225   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1226
1227 {
1228   SI tmp_newval;
1229   tmp_newval = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1230   {
1231     SI opval = tmp_newval;
1232     SET_H_GR (FLD (f_operand2), opval);
1233     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1234   }
1235 {
1236   {
1237     BI opval = LTSI (tmp_newval, 0);
1238     CPU (h_nbit) = opval;
1239     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1240   }
1241   {
1242     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1243     CPU (h_zbit) = opval;
1244     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1245   }
1246 SET_H_CBIT_MOVE (0);
1247 SET_H_VBIT_MOVE (0);
1248 {
1249   {
1250     BI opval = 0;
1251     CPU (h_xbit) = opval;
1252     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1253   }
1254   {
1255     BI opval = 0;
1256     SET_H_INSN_PREFIXED_P (opval);
1257     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1258   }
1259 }
1260 }
1261 }
1262
1263 #undef FLD
1264 }
1265   NEXT (vpc);
1266
1267   CASE (sem, INSN_ADDQ) : /* addq $j,$Rd */
1268 {
1269   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1270   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1271 #define FLD(f) abuf->fields.sfmt_addq.f
1272   int UNUSED written = 0;
1273   IADDR UNUSED pc = abuf->addr;
1274   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1275
1276 {
1277   SI tmp_tmpopd;
1278   SI tmp_tmpops;
1279   BI tmp_carry;
1280   SI tmp_newval;
1281   tmp_tmpops = FLD (f_u6);
1282   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1283   tmp_carry = CPU (h_cbit);
1284   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1285   {
1286     SI opval = tmp_newval;
1287     SET_H_GR (FLD (f_operand2), opval);
1288     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1289   }
1290 {
1291   {
1292     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
1293     CPU (h_cbit) = opval;
1294     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1295   }
1296   {
1297     BI opval = LTSI (tmp_newval, 0);
1298     CPU (h_nbit) = opval;
1299     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1300   }
1301   {
1302     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1303     CPU (h_zbit) = opval;
1304     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1305   }
1306   {
1307     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1308     CPU (h_vbit) = opval;
1309     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1310   }
1311 {
1312   {
1313     BI opval = 0;
1314     CPU (h_xbit) = opval;
1315     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1316   }
1317   {
1318     BI opval = 0;
1319     SET_H_INSN_PREFIXED_P (opval);
1320     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1321   }
1322 }
1323 }
1324 }
1325
1326 #undef FLD
1327 }
1328   NEXT (vpc);
1329
1330   CASE (sem, INSN_SUBQ) : /* subq $j,$Rd */
1331 {
1332   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1333   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1334 #define FLD(f) abuf->fields.sfmt_addq.f
1335   int UNUSED written = 0;
1336   IADDR UNUSED pc = abuf->addr;
1337   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1338
1339 {
1340   SI tmp_tmpopd;
1341   SI tmp_tmpops;
1342   BI tmp_carry;
1343   SI tmp_newval;
1344   tmp_tmpops = FLD (f_u6);
1345   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1346   tmp_carry = CPU (h_cbit);
1347   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1348   {
1349     SI opval = tmp_newval;
1350     SET_H_GR (FLD (f_operand2), opval);
1351     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1352   }
1353 {
1354   {
1355     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1356     CPU (h_cbit) = opval;
1357     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1358   }
1359   {
1360     BI opval = LTSI (tmp_newval, 0);
1361     CPU (h_nbit) = opval;
1362     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1363   }
1364   {
1365     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1366     CPU (h_zbit) = opval;
1367     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1368   }
1369   {
1370     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1371     CPU (h_vbit) = opval;
1372     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1373   }
1374 {
1375   {
1376     BI opval = 0;
1377     CPU (h_xbit) = opval;
1378     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1379   }
1380   {
1381     BI opval = 0;
1382     SET_H_INSN_PREFIXED_P (opval);
1383     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1384   }
1385 }
1386 }
1387 }
1388
1389 #undef FLD
1390 }
1391   NEXT (vpc);
1392
1393   CASE (sem, INSN_CMP_R_B_R) : /* cmp-r.b $Rs,$Rd */
1394 {
1395   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1396   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1397 #define FLD(f) abuf->fields.sfmt_add_b_r.f
1398   int UNUSED written = 0;
1399   IADDR UNUSED pc = abuf->addr;
1400   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1401
1402 {
1403   QI tmp_tmpopd;
1404   QI tmp_tmpops;
1405   BI tmp_carry;
1406   QI tmp_newval;
1407   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1408   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1409   tmp_carry = CPU (h_cbit);
1410   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1411 ((void) 0); /*nop*/
1412 {
1413   {
1414     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1415     CPU (h_cbit) = opval;
1416     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1417   }
1418   {
1419     BI opval = LTQI (tmp_newval, 0);
1420     CPU (h_nbit) = opval;
1421     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1422   }
1423   {
1424     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1425     CPU (h_zbit) = opval;
1426     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1427   }
1428   {
1429     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1430     CPU (h_vbit) = opval;
1431     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1432   }
1433 {
1434   {
1435     BI opval = 0;
1436     CPU (h_xbit) = opval;
1437     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1438   }
1439   {
1440     BI opval = 0;
1441     SET_H_INSN_PREFIXED_P (opval);
1442     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1443   }
1444 }
1445 }
1446 }
1447
1448 #undef FLD
1449 }
1450   NEXT (vpc);
1451
1452   CASE (sem, INSN_CMP_R_W_R) : /* cmp-r.w $Rs,$Rd */
1453 {
1454   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1455   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1456 #define FLD(f) abuf->fields.sfmt_add_b_r.f
1457   int UNUSED written = 0;
1458   IADDR UNUSED pc = abuf->addr;
1459   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1460
1461 {
1462   HI tmp_tmpopd;
1463   HI tmp_tmpops;
1464   BI tmp_carry;
1465   HI tmp_newval;
1466   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1467   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1468   tmp_carry = CPU (h_cbit);
1469   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1470 ((void) 0); /*nop*/
1471 {
1472   {
1473     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1474     CPU (h_cbit) = opval;
1475     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1476   }
1477   {
1478     BI opval = LTHI (tmp_newval, 0);
1479     CPU (h_nbit) = opval;
1480     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1481   }
1482   {
1483     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1484     CPU (h_zbit) = opval;
1485     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1486   }
1487   {
1488     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1489     CPU (h_vbit) = opval;
1490     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1491   }
1492 {
1493   {
1494     BI opval = 0;
1495     CPU (h_xbit) = opval;
1496     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1497   }
1498   {
1499     BI opval = 0;
1500     SET_H_INSN_PREFIXED_P (opval);
1501     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1502   }
1503 }
1504 }
1505 }
1506
1507 #undef FLD
1508 }
1509   NEXT (vpc);
1510
1511   CASE (sem, INSN_CMP_R_D_R) : /* cmp-r.d $Rs,$Rd */
1512 {
1513   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1514   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1515 #define FLD(f) abuf->fields.sfmt_add_b_r.f
1516   int UNUSED written = 0;
1517   IADDR UNUSED pc = abuf->addr;
1518   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1519
1520 {
1521   SI tmp_tmpopd;
1522   SI tmp_tmpops;
1523   BI tmp_carry;
1524   SI tmp_newval;
1525   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1526   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1527   tmp_carry = CPU (h_cbit);
1528   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1529 ((void) 0); /*nop*/
1530 {
1531   {
1532     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1533     CPU (h_cbit) = opval;
1534     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1535   }
1536   {
1537     BI opval = LTSI (tmp_newval, 0);
1538     CPU (h_nbit) = opval;
1539     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1540   }
1541   {
1542     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1543     CPU (h_zbit) = opval;
1544     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1545   }
1546   {
1547     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1548     CPU (h_vbit) = opval;
1549     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1550   }
1551 {
1552   {
1553     BI opval = 0;
1554     CPU (h_xbit) = opval;
1555     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1556   }
1557   {
1558     BI opval = 0;
1559     SET_H_INSN_PREFIXED_P (opval);
1560     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1561   }
1562 }
1563 }
1564 }
1565
1566 #undef FLD
1567 }
1568   NEXT (vpc);
1569
1570   CASE (sem, INSN_CMP_M_B_M) : /* cmp-m.b [${Rs}${inc}],${Rd} */
1571 {
1572   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1573   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1574 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
1575   int UNUSED written = 0;
1576   IADDR UNUSED pc = abuf->addr;
1577   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1578
1579 {
1580   QI tmp_tmpopd;
1581   QI tmp_tmpops;
1582   BI tmp_carry;
1583   QI tmp_newval;
1584   tmp_tmpops = ({   SI tmp_addr;
1585   QI tmp_tmp_mem;
1586   BI tmp_postinc;
1587   tmp_postinc = FLD (f_memmode);
1588 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
1589 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
1590 ; if (NEBI (tmp_postinc, 0)) {
1591 {
1592 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1593   tmp_addr = ADDSI (tmp_addr, 1);
1594 }
1595   {
1596     SI opval = tmp_addr;
1597     SET_H_GR (FLD (f_operand1), opval);
1598     written |= (1 << 9);
1599     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1600   }
1601 }
1602 }
1603 ; tmp_tmp_mem; });
1604   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1605   tmp_carry = CPU (h_cbit);
1606   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1607 ((void) 0); /*nop*/
1608 {
1609   {
1610     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1611     CPU (h_cbit) = opval;
1612     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1613   }
1614   {
1615     BI opval = LTQI (tmp_newval, 0);
1616     CPU (h_nbit) = opval;
1617     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1618   }
1619   {
1620     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1621     CPU (h_zbit) = opval;
1622     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1623   }
1624   {
1625     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1626     CPU (h_vbit) = opval;
1627     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1628   }
1629 {
1630   {
1631     BI opval = 0;
1632     CPU (h_xbit) = opval;
1633     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1634   }
1635   {
1636     BI opval = 0;
1637     SET_H_INSN_PREFIXED_P (opval);
1638     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1639   }
1640 }
1641 }
1642 }
1643
1644   abuf->written = written;
1645 #undef FLD
1646 }
1647   NEXT (vpc);
1648
1649   CASE (sem, INSN_CMP_M_W_M) : /* cmp-m.w [${Rs}${inc}],${Rd} */
1650 {
1651   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1652   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1653 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
1654   int UNUSED written = 0;
1655   IADDR UNUSED pc = abuf->addr;
1656   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1657
1658 {
1659   HI tmp_tmpopd;
1660   HI tmp_tmpops;
1661   BI tmp_carry;
1662   HI tmp_newval;
1663   tmp_tmpops = ({   SI tmp_addr;
1664   HI tmp_tmp_mem;
1665   BI tmp_postinc;
1666   tmp_postinc = FLD (f_memmode);
1667 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
1668 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
1669 ; if (NEBI (tmp_postinc, 0)) {
1670 {
1671 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1672   tmp_addr = ADDSI (tmp_addr, 2);
1673 }
1674   {
1675     SI opval = tmp_addr;
1676     SET_H_GR (FLD (f_operand1), opval);
1677     written |= (1 << 9);
1678     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1679   }
1680 }
1681 }
1682 ; tmp_tmp_mem; });
1683   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1684   tmp_carry = CPU (h_cbit);
1685   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1686 ((void) 0); /*nop*/
1687 {
1688   {
1689     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1690     CPU (h_cbit) = opval;
1691     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1692   }
1693   {
1694     BI opval = LTHI (tmp_newval, 0);
1695     CPU (h_nbit) = opval;
1696     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1697   }
1698   {
1699     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1700     CPU (h_zbit) = opval;
1701     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1702   }
1703   {
1704     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1705     CPU (h_vbit) = opval;
1706     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1707   }
1708 {
1709   {
1710     BI opval = 0;
1711     CPU (h_xbit) = opval;
1712     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1713   }
1714   {
1715     BI opval = 0;
1716     SET_H_INSN_PREFIXED_P (opval);
1717     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1718   }
1719 }
1720 }
1721 }
1722
1723   abuf->written = written;
1724 #undef FLD
1725 }
1726   NEXT (vpc);
1727
1728   CASE (sem, INSN_CMP_M_D_M) : /* cmp-m.d [${Rs}${inc}],${Rd} */
1729 {
1730   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1731   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1732 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
1733   int UNUSED written = 0;
1734   IADDR UNUSED pc = abuf->addr;
1735   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1736
1737 {
1738   SI tmp_tmpopd;
1739   SI tmp_tmpops;
1740   BI tmp_carry;
1741   SI tmp_newval;
1742   tmp_tmpops = ({   SI tmp_addr;
1743   SI tmp_tmp_mem;
1744   BI tmp_postinc;
1745   tmp_postinc = FLD (f_memmode);
1746 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
1747 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
1748 ; if (NEBI (tmp_postinc, 0)) {
1749 {
1750 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1751   tmp_addr = ADDSI (tmp_addr, 4);
1752 }
1753   {
1754     SI opval = tmp_addr;
1755     SET_H_GR (FLD (f_operand1), opval);
1756     written |= (1 << 9);
1757     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1758   }
1759 }
1760 }
1761 ; tmp_tmp_mem; });
1762   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1763   tmp_carry = CPU (h_cbit);
1764   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1765 ((void) 0); /*nop*/
1766 {
1767   {
1768     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1769     CPU (h_cbit) = opval;
1770     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1771   }
1772   {
1773     BI opval = LTSI (tmp_newval, 0);
1774     CPU (h_nbit) = opval;
1775     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1776   }
1777   {
1778     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1779     CPU (h_zbit) = opval;
1780     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1781   }
1782   {
1783     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1784     CPU (h_vbit) = opval;
1785     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1786   }
1787 {
1788   {
1789     BI opval = 0;
1790     CPU (h_xbit) = opval;
1791     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1792   }
1793   {
1794     BI opval = 0;
1795     SET_H_INSN_PREFIXED_P (opval);
1796     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1797   }
1798 }
1799 }
1800 }
1801
1802   abuf->written = written;
1803 #undef FLD
1804 }
1805   NEXT (vpc);
1806
1807   CASE (sem, INSN_CMPCBR) : /* cmp.b $sconst8,$Rd */
1808 {
1809   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1810   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1811 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1812   int UNUSED written = 0;
1813   IADDR UNUSED pc = abuf->addr;
1814   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1815
1816 {
1817   QI tmp_tmpopd;
1818   QI tmp_tmpops;
1819   BI tmp_carry;
1820   QI tmp_newval;
1821   tmp_tmpops = TRUNCSIQI (FLD (f_indir_pc__byte));
1822   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1823   tmp_carry = CPU (h_cbit);
1824   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1825 ((void) 0); /*nop*/
1826 {
1827   {
1828     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1829     CPU (h_cbit) = opval;
1830     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1831   }
1832   {
1833     BI opval = LTQI (tmp_newval, 0);
1834     CPU (h_nbit) = opval;
1835     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1836   }
1837   {
1838     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1839     CPU (h_zbit) = opval;
1840     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1841   }
1842   {
1843     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1844     CPU (h_vbit) = opval;
1845     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1846   }
1847 {
1848   {
1849     BI opval = 0;
1850     CPU (h_xbit) = opval;
1851     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1852   }
1853   {
1854     BI opval = 0;
1855     SET_H_INSN_PREFIXED_P (opval);
1856     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1857   }
1858 }
1859 }
1860 }
1861
1862 #undef FLD
1863 }
1864   NEXT (vpc);
1865
1866   CASE (sem, INSN_CMPCWR) : /* cmp.w $sconst16,$Rd */
1867 {
1868   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1869   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1870 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1871   int UNUSED written = 0;
1872   IADDR UNUSED pc = abuf->addr;
1873   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1874
1875 {
1876   HI tmp_tmpopd;
1877   HI tmp_tmpops;
1878   BI tmp_carry;
1879   HI tmp_newval;
1880   tmp_tmpops = TRUNCSIHI (FLD (f_indir_pc__word));
1881   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1882   tmp_carry = CPU (h_cbit);
1883   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1884 ((void) 0); /*nop*/
1885 {
1886   {
1887     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1888     CPU (h_cbit) = opval;
1889     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1890   }
1891   {
1892     BI opval = LTHI (tmp_newval, 0);
1893     CPU (h_nbit) = opval;
1894     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1895   }
1896   {
1897     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1898     CPU (h_zbit) = opval;
1899     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1900   }
1901   {
1902     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1903     CPU (h_vbit) = opval;
1904     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1905   }
1906 {
1907   {
1908     BI opval = 0;
1909     CPU (h_xbit) = opval;
1910     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1911   }
1912   {
1913     BI opval = 0;
1914     SET_H_INSN_PREFIXED_P (opval);
1915     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1916   }
1917 }
1918 }
1919 }
1920
1921 #undef FLD
1922 }
1923   NEXT (vpc);
1924
1925   CASE (sem, INSN_CMPCDR) : /* cmp.d $const32,$Rd */
1926 {
1927   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1928   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1929 #define FLD(f) abuf->fields.sfmt_bound_cd.f
1930   int UNUSED written = 0;
1931   IADDR UNUSED pc = abuf->addr;
1932   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
1933
1934 {
1935   SI tmp_tmpopd;
1936   SI tmp_tmpops;
1937   BI tmp_carry;
1938   SI tmp_newval;
1939   tmp_tmpops = FLD (f_indir_pc__dword);
1940   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1941   tmp_carry = CPU (h_cbit);
1942   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1943 ((void) 0); /*nop*/
1944 {
1945   {
1946     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1947     CPU (h_cbit) = opval;
1948     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1949   }
1950   {
1951     BI opval = LTSI (tmp_newval, 0);
1952     CPU (h_nbit) = opval;
1953     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1954   }
1955   {
1956     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1957     CPU (h_zbit) = opval;
1958     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1959   }
1960   {
1961     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1962     CPU (h_vbit) = opval;
1963     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1964   }
1965 {
1966   {
1967     BI opval = 0;
1968     CPU (h_xbit) = opval;
1969     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1970   }
1971   {
1972     BI opval = 0;
1973     SET_H_INSN_PREFIXED_P (opval);
1974     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1975   }
1976 }
1977 }
1978 }
1979
1980 #undef FLD
1981 }
1982   NEXT (vpc);
1983
1984   CASE (sem, INSN_CMPQ) : /* cmpq $i,$Rd */
1985 {
1986   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1987   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1988 #define FLD(f) abuf->fields.sfmt_andq.f
1989   int UNUSED written = 0;
1990   IADDR UNUSED pc = abuf->addr;
1991   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1992
1993 {
1994   SI tmp_tmpopd;
1995   SI tmp_tmpops;
1996   BI tmp_carry;
1997   SI tmp_newval;
1998   tmp_tmpops = FLD (f_s6);
1999   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2000   tmp_carry = CPU (h_cbit);
2001   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2002 ((void) 0); /*nop*/
2003 {
2004   {
2005     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2006     CPU (h_cbit) = opval;
2007     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2008   }
2009   {
2010     BI opval = LTSI (tmp_newval, 0);
2011     CPU (h_nbit) = opval;
2012     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2013   }
2014   {
2015     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2016     CPU (h_zbit) = opval;
2017     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2018   }
2019   {
2020     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2021     CPU (h_vbit) = opval;
2022     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2023   }
2024 {
2025   {
2026     BI opval = 0;
2027     CPU (h_xbit) = opval;
2028     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2029   }
2030   {
2031     BI opval = 0;
2032     SET_H_INSN_PREFIXED_P (opval);
2033     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2034   }
2035 }
2036 }
2037 }
2038
2039 #undef FLD
2040 }
2041   NEXT (vpc);
2042
2043   CASE (sem, INSN_CMPS_M_B_M) : /* cmps-m.b [${Rs}${inc}],$Rd */
2044 {
2045   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2046   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2047 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2048   int UNUSED written = 0;
2049   IADDR UNUSED pc = abuf->addr;
2050   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2051
2052 {
2053   SI tmp_tmpopd;
2054   SI tmp_tmpops;
2055   BI tmp_carry;
2056   SI tmp_newval;
2057   tmp_tmpops = EXTQISI (({   SI tmp_addr;
2058   QI tmp_tmp_mem;
2059   BI tmp_postinc;
2060   tmp_postinc = FLD (f_memmode);
2061 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2062 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2063 ; if (NEBI (tmp_postinc, 0)) {
2064 {
2065 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2066   tmp_addr = ADDSI (tmp_addr, 1);
2067 }
2068   {
2069     SI opval = tmp_addr;
2070     SET_H_GR (FLD (f_operand1), opval);
2071     written |= (1 << 9);
2072     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2073   }
2074 }
2075 }
2076 ; tmp_tmp_mem; }));
2077   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2078   tmp_carry = CPU (h_cbit);
2079   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2080 ((void) 0); /*nop*/
2081 {
2082   {
2083     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2084     CPU (h_cbit) = opval;
2085     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2086   }
2087   {
2088     BI opval = LTSI (tmp_newval, 0);
2089     CPU (h_nbit) = opval;
2090     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2091   }
2092   {
2093     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2094     CPU (h_zbit) = opval;
2095     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2096   }
2097   {
2098     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2099     CPU (h_vbit) = opval;
2100     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2101   }
2102 {
2103   {
2104     BI opval = 0;
2105     CPU (h_xbit) = opval;
2106     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2107   }
2108   {
2109     BI opval = 0;
2110     SET_H_INSN_PREFIXED_P (opval);
2111     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2112   }
2113 }
2114 }
2115 }
2116
2117   abuf->written = written;
2118 #undef FLD
2119 }
2120   NEXT (vpc);
2121
2122   CASE (sem, INSN_CMPS_M_W_M) : /* cmps-m.w [${Rs}${inc}],$Rd */
2123 {
2124   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2125   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2126 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2127   int UNUSED written = 0;
2128   IADDR UNUSED pc = abuf->addr;
2129   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2130
2131 {
2132   SI tmp_tmpopd;
2133   SI tmp_tmpops;
2134   BI tmp_carry;
2135   SI tmp_newval;
2136   tmp_tmpops = EXTHISI (({   SI tmp_addr;
2137   HI tmp_tmp_mem;
2138   BI tmp_postinc;
2139   tmp_postinc = FLD (f_memmode);
2140 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2141 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2142 ; if (NEBI (tmp_postinc, 0)) {
2143 {
2144 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2145   tmp_addr = ADDSI (tmp_addr, 2);
2146 }
2147   {
2148     SI opval = tmp_addr;
2149     SET_H_GR (FLD (f_operand1), opval);
2150     written |= (1 << 9);
2151     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2152   }
2153 }
2154 }
2155 ; tmp_tmp_mem; }));
2156   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2157   tmp_carry = CPU (h_cbit);
2158   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2159 ((void) 0); /*nop*/
2160 {
2161   {
2162     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2163     CPU (h_cbit) = opval;
2164     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2165   }
2166   {
2167     BI opval = LTSI (tmp_newval, 0);
2168     CPU (h_nbit) = opval;
2169     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2170   }
2171   {
2172     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2173     CPU (h_zbit) = opval;
2174     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2175   }
2176   {
2177     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2178     CPU (h_vbit) = opval;
2179     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2180   }
2181 {
2182   {
2183     BI opval = 0;
2184     CPU (h_xbit) = opval;
2185     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2186   }
2187   {
2188     BI opval = 0;
2189     SET_H_INSN_PREFIXED_P (opval);
2190     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2191   }
2192 }
2193 }
2194 }
2195
2196   abuf->written = written;
2197 #undef FLD
2198 }
2199   NEXT (vpc);
2200
2201   CASE (sem, INSN_CMPSCBR) : /* [${Rs}${inc}],$Rd */
2202 {
2203   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2204   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2205 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2206   int UNUSED written = 0;
2207   IADDR UNUSED pc = abuf->addr;
2208   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2209
2210 {
2211   SI tmp_tmpopd;
2212   SI tmp_tmpops;
2213   BI tmp_carry;
2214   SI tmp_newval;
2215   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2216   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2217   tmp_carry = CPU (h_cbit);
2218   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2219 ((void) 0); /*nop*/
2220 {
2221   {
2222     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2223     CPU (h_cbit) = opval;
2224     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2225   }
2226   {
2227     BI opval = LTSI (tmp_newval, 0);
2228     CPU (h_nbit) = opval;
2229     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2230   }
2231   {
2232     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2233     CPU (h_zbit) = opval;
2234     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2235   }
2236   {
2237     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2238     CPU (h_vbit) = opval;
2239     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2240   }
2241 {
2242   {
2243     BI opval = 0;
2244     CPU (h_xbit) = opval;
2245     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2246   }
2247   {
2248     BI opval = 0;
2249     SET_H_INSN_PREFIXED_P (opval);
2250     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2251   }
2252 }
2253 }
2254 }
2255
2256 #undef FLD
2257 }
2258   NEXT (vpc);
2259
2260   CASE (sem, INSN_CMPSCWR) : /* [${Rs}${inc}],$Rd */
2261 {
2262   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2263   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2264 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2265   int UNUSED written = 0;
2266   IADDR UNUSED pc = abuf->addr;
2267   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2268
2269 {
2270   SI tmp_tmpopd;
2271   SI tmp_tmpops;
2272   BI tmp_carry;
2273   SI tmp_newval;
2274   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2275   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2276   tmp_carry = CPU (h_cbit);
2277   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2278 ((void) 0); /*nop*/
2279 {
2280   {
2281     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2282     CPU (h_cbit) = opval;
2283     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2284   }
2285   {
2286     BI opval = LTSI (tmp_newval, 0);
2287     CPU (h_nbit) = opval;
2288     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2289   }
2290   {
2291     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2292     CPU (h_zbit) = opval;
2293     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2294   }
2295   {
2296     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2297     CPU (h_vbit) = opval;
2298     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2299   }
2300 {
2301   {
2302     BI opval = 0;
2303     CPU (h_xbit) = opval;
2304     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2305   }
2306   {
2307     BI opval = 0;
2308     SET_H_INSN_PREFIXED_P (opval);
2309     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2310   }
2311 }
2312 }
2313 }
2314
2315 #undef FLD
2316 }
2317   NEXT (vpc);
2318
2319   CASE (sem, INSN_CMPU_M_B_M) : /* cmpu-m.b [${Rs}${inc}],$Rd */
2320 {
2321   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2322   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2323 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2324   int UNUSED written = 0;
2325   IADDR UNUSED pc = abuf->addr;
2326   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2327
2328 {
2329   SI tmp_tmpopd;
2330   SI tmp_tmpops;
2331   BI tmp_carry;
2332   SI tmp_newval;
2333   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
2334   QI tmp_tmp_mem;
2335   BI tmp_postinc;
2336   tmp_postinc = FLD (f_memmode);
2337 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2338 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2339 ; if (NEBI (tmp_postinc, 0)) {
2340 {
2341 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2342   tmp_addr = ADDSI (tmp_addr, 1);
2343 }
2344   {
2345     SI opval = tmp_addr;
2346     SET_H_GR (FLD (f_operand1), opval);
2347     written |= (1 << 9);
2348     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2349   }
2350 }
2351 }
2352 ; tmp_tmp_mem; }));
2353   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2354   tmp_carry = CPU (h_cbit);
2355   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2356 ((void) 0); /*nop*/
2357 {
2358   {
2359     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2360     CPU (h_cbit) = opval;
2361     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2362   }
2363   {
2364     BI opval = LTSI (tmp_newval, 0);
2365     CPU (h_nbit) = opval;
2366     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2367   }
2368   {
2369     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2370     CPU (h_zbit) = opval;
2371     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2372   }
2373   {
2374     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2375     CPU (h_vbit) = opval;
2376     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2377   }
2378 {
2379   {
2380     BI opval = 0;
2381     CPU (h_xbit) = opval;
2382     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2383   }
2384   {
2385     BI opval = 0;
2386     SET_H_INSN_PREFIXED_P (opval);
2387     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2388   }
2389 }
2390 }
2391 }
2392
2393   abuf->written = written;
2394 #undef FLD
2395 }
2396   NEXT (vpc);
2397
2398   CASE (sem, INSN_CMPU_M_W_M) : /* cmpu-m.w [${Rs}${inc}],$Rd */
2399 {
2400   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2401   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2402 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2403   int UNUSED written = 0;
2404   IADDR UNUSED pc = abuf->addr;
2405   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2406
2407 {
2408   SI tmp_tmpopd;
2409   SI tmp_tmpops;
2410   BI tmp_carry;
2411   SI tmp_newval;
2412   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
2413   HI tmp_tmp_mem;
2414   BI tmp_postinc;
2415   tmp_postinc = FLD (f_memmode);
2416 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2417 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2418 ; if (NEBI (tmp_postinc, 0)) {
2419 {
2420 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2421   tmp_addr = ADDSI (tmp_addr, 2);
2422 }
2423   {
2424     SI opval = tmp_addr;
2425     SET_H_GR (FLD (f_operand1), opval);
2426     written |= (1 << 9);
2427     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2428   }
2429 }
2430 }
2431 ; tmp_tmp_mem; }));
2432   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2433   tmp_carry = CPU (h_cbit);
2434   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2435 ((void) 0); /*nop*/
2436 {
2437   {
2438     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2439     CPU (h_cbit) = opval;
2440     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2441   }
2442   {
2443     BI opval = LTSI (tmp_newval, 0);
2444     CPU (h_nbit) = opval;
2445     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2446   }
2447   {
2448     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2449     CPU (h_zbit) = opval;
2450     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2451   }
2452   {
2453     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2454     CPU (h_vbit) = opval;
2455     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2456   }
2457 {
2458   {
2459     BI opval = 0;
2460     CPU (h_xbit) = opval;
2461     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2462   }
2463   {
2464     BI opval = 0;
2465     SET_H_INSN_PREFIXED_P (opval);
2466     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2467   }
2468 }
2469 }
2470 }
2471
2472   abuf->written = written;
2473 #undef FLD
2474 }
2475   NEXT (vpc);
2476
2477   CASE (sem, INSN_CMPUCBR) : /* [${Rs}${inc}],$Rd */
2478 {
2479   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2480   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2481 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2482   int UNUSED written = 0;
2483   IADDR UNUSED pc = abuf->addr;
2484   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2485
2486 {
2487   SI tmp_tmpopd;
2488   SI tmp_tmpops;
2489   BI tmp_carry;
2490   SI tmp_newval;
2491   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2492   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2493   tmp_carry = CPU (h_cbit);
2494   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2495 ((void) 0); /*nop*/
2496 {
2497   {
2498     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2499     CPU (h_cbit) = opval;
2500     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2501   }
2502   {
2503     BI opval = LTSI (tmp_newval, 0);
2504     CPU (h_nbit) = opval;
2505     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2506   }
2507   {
2508     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2509     CPU (h_zbit) = opval;
2510     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2511   }
2512   {
2513     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2514     CPU (h_vbit) = opval;
2515     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2516   }
2517 {
2518   {
2519     BI opval = 0;
2520     CPU (h_xbit) = opval;
2521     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2522   }
2523   {
2524     BI opval = 0;
2525     SET_H_INSN_PREFIXED_P (opval);
2526     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2527   }
2528 }
2529 }
2530 }
2531
2532 #undef FLD
2533 }
2534   NEXT (vpc);
2535
2536   CASE (sem, INSN_CMPUCWR) : /* [${Rs}${inc}],$Rd */
2537 {
2538   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2539   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2540 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2541   int UNUSED written = 0;
2542   IADDR UNUSED pc = abuf->addr;
2543   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2544
2545 {
2546   SI tmp_tmpopd;
2547   SI tmp_tmpops;
2548   BI tmp_carry;
2549   SI tmp_newval;
2550   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2551   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2552   tmp_carry = CPU (h_cbit);
2553   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2554 ((void) 0); /*nop*/
2555 {
2556   {
2557     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2558     CPU (h_cbit) = opval;
2559     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2560   }
2561   {
2562     BI opval = LTSI (tmp_newval, 0);
2563     CPU (h_nbit) = opval;
2564     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2565   }
2566   {
2567     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2568     CPU (h_zbit) = opval;
2569     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2570   }
2571   {
2572     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2573     CPU (h_vbit) = opval;
2574     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2575   }
2576 {
2577   {
2578     BI opval = 0;
2579     CPU (h_xbit) = opval;
2580     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2581   }
2582   {
2583     BI opval = 0;
2584     SET_H_INSN_PREFIXED_P (opval);
2585     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2586   }
2587 }
2588 }
2589 }
2590
2591 #undef FLD
2592 }
2593   NEXT (vpc);
2594
2595   CASE (sem, INSN_MOVE_M_B_M) : /* move-m.b [${Rs}${inc}],${Rd} */
2596 {
2597   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2598   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2599 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2600   int UNUSED written = 0;
2601   IADDR UNUSED pc = abuf->addr;
2602   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2603
2604 {
2605   SI tmp_tmp;
2606   tmp_tmp = ({   SI tmp_addr;
2607   QI tmp_tmp_mem;
2608   BI tmp_postinc;
2609   tmp_postinc = FLD (f_memmode);
2610 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2611 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2612 ; if (NEBI (tmp_postinc, 0)) {
2613 {
2614 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2615   tmp_addr = ADDSI (tmp_addr, 1);
2616 }
2617   {
2618     SI opval = tmp_addr;
2619     SET_H_GR (FLD (f_operand1), opval);
2620     written |= (1 << 10);
2621     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2622   }
2623 }
2624 }
2625 ; tmp_tmp_mem; });
2626 {
2627   SI tmp_oldregval;
2628   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2629   {
2630     SI opval = ORSI (ANDSI (tmp_tmp, 255), ANDSI (tmp_oldregval, 0xffffff00));
2631     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2632     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2633   }
2634 }
2635 {
2636   {
2637     BI opval = LTQI (tmp_tmp, 0);
2638     CPU (h_nbit) = opval;
2639     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2640   }
2641   {
2642     BI opval = ANDIF (EQQI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2643     CPU (h_zbit) = opval;
2644     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2645   }
2646 SET_H_CBIT_MOVE (0);
2647 SET_H_VBIT_MOVE (0);
2648 {
2649   {
2650     BI opval = 0;
2651     CPU (h_xbit) = opval;
2652     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2653   }
2654   {
2655     BI opval = 0;
2656     SET_H_INSN_PREFIXED_P (opval);
2657     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2658   }
2659 }
2660 }
2661 }
2662
2663   abuf->written = written;
2664 #undef FLD
2665 }
2666   NEXT (vpc);
2667
2668   CASE (sem, INSN_MOVE_M_W_M) : /* move-m.w [${Rs}${inc}],${Rd} */
2669 {
2670   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2671   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2672 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2673   int UNUSED written = 0;
2674   IADDR UNUSED pc = abuf->addr;
2675   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2676
2677 {
2678   SI tmp_tmp;
2679   tmp_tmp = ({   SI tmp_addr;
2680   HI tmp_tmp_mem;
2681   BI tmp_postinc;
2682   tmp_postinc = FLD (f_memmode);
2683 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2684 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2685 ; if (NEBI (tmp_postinc, 0)) {
2686 {
2687 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2688   tmp_addr = ADDSI (tmp_addr, 2);
2689 }
2690   {
2691     SI opval = tmp_addr;
2692     SET_H_GR (FLD (f_operand1), opval);
2693     written |= (1 << 10);
2694     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2695   }
2696 }
2697 }
2698 ; tmp_tmp_mem; });
2699 {
2700   SI tmp_oldregval;
2701   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2702   {
2703     SI opval = ORSI (ANDSI (tmp_tmp, 65535), ANDSI (tmp_oldregval, 0xffff0000));
2704     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2705     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2706   }
2707 }
2708 {
2709   {
2710     BI opval = LTHI (tmp_tmp, 0);
2711     CPU (h_nbit) = opval;
2712     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2713   }
2714   {
2715     BI opval = ANDIF (EQHI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2716     CPU (h_zbit) = opval;
2717     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2718   }
2719 SET_H_CBIT_MOVE (0);
2720 SET_H_VBIT_MOVE (0);
2721 {
2722   {
2723     BI opval = 0;
2724     CPU (h_xbit) = opval;
2725     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2726   }
2727   {
2728     BI opval = 0;
2729     SET_H_INSN_PREFIXED_P (opval);
2730     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2731   }
2732 }
2733 }
2734 }
2735
2736   abuf->written = written;
2737 #undef FLD
2738 }
2739   NEXT (vpc);
2740
2741   CASE (sem, INSN_MOVE_M_D_M) : /* move-m.d [${Rs}${inc}],${Rd} */
2742 {
2743   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2744   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2745 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2746   int UNUSED written = 0;
2747   IADDR UNUSED pc = abuf->addr;
2748   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2749
2750 {
2751   SI tmp_tmp;
2752   tmp_tmp = ({   SI tmp_addr;
2753   SI tmp_tmp_mem;
2754   BI tmp_postinc;
2755   tmp_postinc = FLD (f_memmode);
2756 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2757 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
2758 ; if (NEBI (tmp_postinc, 0)) {
2759 {
2760 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2761   tmp_addr = ADDSI (tmp_addr, 4);
2762 }
2763   {
2764     SI opval = tmp_addr;
2765     SET_H_GR (FLD (f_operand1), opval);
2766     written |= (1 << 9);
2767     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2768   }
2769 }
2770 }
2771 ; tmp_tmp_mem; });
2772   {
2773     SI opval = tmp_tmp;
2774     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2775     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2776   }
2777 {
2778   {
2779     BI opval = LTSI (tmp_tmp, 0);
2780     CPU (h_nbit) = opval;
2781     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2782   }
2783   {
2784     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2785     CPU (h_zbit) = opval;
2786     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2787   }
2788 SET_H_CBIT_MOVE (0);
2789 SET_H_VBIT_MOVE (0);
2790 {
2791   {
2792     BI opval = 0;
2793     CPU (h_xbit) = opval;
2794     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2795   }
2796   {
2797     BI opval = 0;
2798     SET_H_INSN_PREFIXED_P (opval);
2799     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2800   }
2801 }
2802 }
2803 }
2804
2805   abuf->written = written;
2806 #undef FLD
2807 }
2808   NEXT (vpc);
2809
2810   CASE (sem, INSN_MOVS_M_B_M) : /* movs-m.b [${Rs}${inc}],${Rd} */
2811 {
2812   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2813   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2814 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2815   int UNUSED written = 0;
2816   IADDR UNUSED pc = abuf->addr;
2817   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2818
2819 {
2820   SI tmp_tmp;
2821   tmp_tmp = EXTQISI (({   SI tmp_addr;
2822   QI tmp_tmp_mem;
2823   BI tmp_postinc;
2824   tmp_postinc = FLD (f_memmode);
2825 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2826 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2827 ; if (NEBI (tmp_postinc, 0)) {
2828 {
2829 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2830   tmp_addr = ADDSI (tmp_addr, 1);
2831 }
2832   {
2833     SI opval = tmp_addr;
2834     SET_H_GR (FLD (f_operand1), opval);
2835     written |= (1 << 8);
2836     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2837   }
2838 }
2839 }
2840 ; tmp_tmp_mem; }));
2841 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2842   {
2843     SI opval = tmp_tmp;
2844     SET_H_GR (FLD (f_operand1), opval);
2845     written |= (1 << 8);
2846     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2847   }
2848 } else {
2849   {
2850     SI opval = tmp_tmp;
2851     SET_H_GR (FLD (f_operand2), opval);
2852     written |= (1 << 7);
2853     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2854   }
2855 }
2856 {
2857   {
2858     BI opval = LTSI (tmp_tmp, 0);
2859     CPU (h_nbit) = opval;
2860     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2861   }
2862   {
2863     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2864     CPU (h_zbit) = opval;
2865     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2866   }
2867 SET_H_CBIT_MOVE (0);
2868 SET_H_VBIT_MOVE (0);
2869 {
2870   {
2871     BI opval = 0;
2872     CPU (h_xbit) = opval;
2873     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2874   }
2875   {
2876     BI opval = 0;
2877     SET_H_INSN_PREFIXED_P (opval);
2878     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2879   }
2880 }
2881 }
2882 }
2883
2884   abuf->written = written;
2885 #undef FLD
2886 }
2887   NEXT (vpc);
2888
2889   CASE (sem, INSN_MOVS_M_W_M) : /* movs-m.w [${Rs}${inc}],${Rd} */
2890 {
2891   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2892   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2893 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2894   int UNUSED written = 0;
2895   IADDR UNUSED pc = abuf->addr;
2896   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2897
2898 {
2899   SI tmp_tmp;
2900   tmp_tmp = EXTHISI (({   SI tmp_addr;
2901   HI tmp_tmp_mem;
2902   BI tmp_postinc;
2903   tmp_postinc = FLD (f_memmode);
2904 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2905 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2906 ; if (NEBI (tmp_postinc, 0)) {
2907 {
2908 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2909   tmp_addr = ADDSI (tmp_addr, 2);
2910 }
2911   {
2912     SI opval = tmp_addr;
2913     SET_H_GR (FLD (f_operand1), opval);
2914     written |= (1 << 8);
2915     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2916   }
2917 }
2918 }
2919 ; tmp_tmp_mem; }));
2920 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2921   {
2922     SI opval = tmp_tmp;
2923     SET_H_GR (FLD (f_operand1), opval);
2924     written |= (1 << 8);
2925     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2926   }
2927 } else {
2928   {
2929     SI opval = tmp_tmp;
2930     SET_H_GR (FLD (f_operand2), opval);
2931     written |= (1 << 7);
2932     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2933   }
2934 }
2935 {
2936   {
2937     BI opval = LTSI (tmp_tmp, 0);
2938     CPU (h_nbit) = opval;
2939     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2940   }
2941   {
2942     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2943     CPU (h_zbit) = opval;
2944     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2945   }
2946 SET_H_CBIT_MOVE (0);
2947 SET_H_VBIT_MOVE (0);
2948 {
2949   {
2950     BI opval = 0;
2951     CPU (h_xbit) = opval;
2952     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2953   }
2954   {
2955     BI opval = 0;
2956     SET_H_INSN_PREFIXED_P (opval);
2957     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2958   }
2959 }
2960 }
2961 }
2962
2963   abuf->written = written;
2964 #undef FLD
2965 }
2966   NEXT (vpc);
2967
2968   CASE (sem, INSN_MOVU_M_B_M) : /* movu-m.b [${Rs}${inc}],${Rd} */
2969 {
2970   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2971   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2972 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2973   int UNUSED written = 0;
2974   IADDR UNUSED pc = abuf->addr;
2975   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2976
2977 {
2978   SI tmp_tmp;
2979   tmp_tmp = ZEXTQISI (({   SI tmp_addr;
2980   QI tmp_tmp_mem;
2981   BI tmp_postinc;
2982   tmp_postinc = FLD (f_memmode);
2983 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2984 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2985 ; if (NEBI (tmp_postinc, 0)) {
2986 {
2987 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2988   tmp_addr = ADDSI (tmp_addr, 1);
2989 }
2990   {
2991     SI opval = tmp_addr;
2992     SET_H_GR (FLD (f_operand1), opval);
2993     written |= (1 << 8);
2994     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2995   }
2996 }
2997 }
2998 ; tmp_tmp_mem; }));
2999 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
3000   {
3001     SI opval = tmp_tmp;
3002     SET_H_GR (FLD (f_operand1), opval);
3003     written |= (1 << 8);
3004     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3005   }
3006 } else {
3007   {
3008     SI opval = tmp_tmp;
3009     SET_H_GR (FLD (f_operand2), opval);
3010     written |= (1 << 7);
3011     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3012   }
3013 }
3014 {
3015   {
3016     BI opval = LTSI (tmp_tmp, 0);
3017     CPU (h_nbit) = opval;
3018     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
3019   }
3020   {
3021     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
3022     CPU (h_zbit) = opval;
3023     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
3024   }
3025 SET_H_CBIT_MOVE (0);
3026 SET_H_VBIT_MOVE (0);
3027 {
3028   {
3029     BI opval = 0;
3030     CPU (h_xbit) = opval;
3031     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3032   }
3033   {
3034     BI opval = 0;
3035     SET_H_INSN_PREFIXED_P (opval);
3036     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3037   }
3038 }
3039 }
3040 }
3041
3042   abuf->written = written;
3043 #undef FLD
3044 }
3045   NEXT (vpc);
3046
3047   CASE (sem, INSN_MOVU_M_W_M) : /* movu-m.w [${Rs}${inc}],${Rd} */
3048 {
3049   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3050   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3051 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
3052   int UNUSED written = 0;
3053   IADDR UNUSED pc = abuf->addr;
3054   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3055
3056 {
3057   SI tmp_tmp;
3058   tmp_tmp = ZEXTHISI (({   SI tmp_addr;
3059   HI tmp_tmp_mem;
3060   BI tmp_postinc;
3061   tmp_postinc = FLD (f_memmode);
3062 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3063 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
3064 ; if (NEBI (tmp_postinc, 0)) {
3065 {
3066 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3067   tmp_addr = ADDSI (tmp_addr, 2);
3068 }
3069   {
3070     SI opval = tmp_addr;
3071     SET_H_GR (FLD (f_operand1), opval);
3072     written |= (1 << 8);
3073     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3074   }
3075 }
3076 }
3077 ; tmp_tmp_mem; }));
3078 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
3079   {
3080     SI opval = tmp_tmp;
3081     SET_H_GR (FLD (f_operand1), opval);
3082     written |= (1 << 8);
3083     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3084   }
3085 } else {
3086   {
3087     SI opval = tmp_tmp;
3088     SET_H_GR (FLD (f_operand2), opval);
3089     written |= (1 << 7);
3090     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3091   }
3092 }
3093 {
3094   {
3095     BI opval = LTSI (tmp_tmp, 0);
3096     CPU (h_nbit) = opval;
3097     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
3098   }
3099   {
3100     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
3101     CPU (h_zbit) = opval;
3102     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
3103   }
3104 SET_H_CBIT_MOVE (0);
3105 SET_H_VBIT_MOVE (0);
3106 {
3107   {
3108     BI opval = 0;
3109     CPU (h_xbit) = opval;
3110     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3111   }
3112   {
3113     BI opval = 0;
3114     SET_H_INSN_PREFIXED_P (opval);
3115     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3116   }
3117 }
3118 }
3119 }
3120
3121   abuf->written = written;
3122 #undef FLD
3123 }
3124   NEXT (vpc);
3125
3126   CASE (sem, INSN_MOVE_R_SPRV10) : /* move ${Rs},${Pd} */
3127 {
3128   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3129   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3130 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
3131   int UNUSED written = 0;
3132   IADDR UNUSED pc = abuf->addr;
3133   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3134
3135 {
3136   SI tmp_tmp;
3137   SI tmp_rno;
3138   tmp_tmp = GET_H_GR (FLD (f_operand1));
3139   tmp_rno = FLD (f_operand2);
3140 if (ORIF (ORIF (EQSI (tmp_rno, 0), EQSI (tmp_rno, 1)), ORIF (EQSI (tmp_rno, 4), EQSI (tmp_rno, 8)))) {
3141 cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special register");
3142 }
3143  else {
3144   {
3145     SI opval = tmp_tmp;
3146     SET_H_SR (FLD (f_operand2), opval);
3147     written |= (1 << 2);
3148     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3149   }
3150 }
3151 {
3152   {
3153     BI opval = 0;
3154     CPU (h_xbit) = opval;
3155     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3156   }
3157   {
3158     BI opval = 0;
3159     SET_H_INSN_PREFIXED_P (opval);
3160     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3161   }
3162 }
3163 }
3164
3165   abuf->written = written;
3166 #undef FLD
3167 }
3168   NEXT (vpc);
3169
3170   CASE (sem, INSN_MOVE_SPR_RV10) : /* move ${Ps},${Rd-sfield} */
3171 {
3172   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3173   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3174 #define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
3175   int UNUSED written = 0;
3176   IADDR UNUSED pc = abuf->addr;
3177   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3178
3179 {
3180   SI tmp_grno;
3181   SI tmp_prno;
3182   SI tmp_newval;
3183   tmp_prno = FLD (f_operand2);
3184   tmp_newval = GET_H_SR (FLD (f_operand2));
3185 if (EQSI (tmp_prno, 5)) {
3186 {
3187   SI tmp_oldregval;
3188   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3189   {
3190     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
3191     SET_H_GR (FLD (f_operand1), opval);
3192     written |= (1 << 4);
3193     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3194   }
3195 }
3196 }
3197  else if (EQSI (tmp_prno, 9)) {
3198   {
3199     SI opval = tmp_newval;
3200     SET_H_GR (FLD (f_operand1), opval);
3201     written |= (1 << 4);
3202     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3203   }
3204 }
3205  else if (EQSI (tmp_prno, 10)) {
3206   {
3207     SI opval = tmp_newval;
3208     SET_H_GR (FLD (f_operand1), opval);
3209     written |= (1 << 4);
3210     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3211   }
3212 }
3213  else if (EQSI (tmp_prno, 11)) {
3214   {
3215     SI opval = tmp_newval;
3216     SET_H_GR (FLD (f_operand1), opval);
3217     written |= (1 << 4);
3218     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3219   }
3220 }
3221  else if (EQSI (tmp_prno, 12)) {
3222   {
3223     SI opval = tmp_newval;
3224     SET_H_GR (FLD (f_operand1), opval);
3225     written |= (1 << 4);
3226     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3227   }
3228 }
3229  else if (EQSI (tmp_prno, 13)) {
3230   {
3231     SI opval = tmp_newval;
3232     SET_H_GR (FLD (f_operand1), opval);
3233     written |= (1 << 4);
3234     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3235   }
3236 }
3237  else if (EQSI (tmp_prno, 0)) {
3238 {
3239   SI tmp_oldregval;
3240   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3241   {
3242     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3243     SET_H_GR (FLD (f_operand1), opval);
3244     written |= (1 << 4);
3245     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3246   }
3247 }
3248 }
3249  else if (EQSI (tmp_prno, 1)) {
3250 {
3251   SI tmp_oldregval;
3252   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3253   {
3254     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3255     SET_H_GR (FLD (f_operand1), opval);
3256     written |= (1 << 4);
3257     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3258   }
3259 }
3260 }
3261  else if (EQSI (tmp_prno, 4)) {
3262 {
3263   SI tmp_oldregval;
3264   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3265   {
3266     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
3267     SET_H_GR (FLD (f_operand1), opval);
3268     written |= (1 << 4);
3269     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3270   }
3271 }
3272 }
3273  else if (EQSI (tmp_prno, 8)) {
3274   {
3275     SI opval = tmp_newval;
3276     SET_H_GR (FLD (f_operand1), opval);
3277     written |= (1 << 4);
3278     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3279   }
3280 }
3281  else if (EQSI (tmp_prno, 7)) {
3282   {
3283     SI opval = tmp_newval;
3284     SET_H_GR (FLD (f_operand1), opval);
3285     written |= (1 << 4);
3286     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3287   }
3288 }
3289  else if (EQSI (tmp_prno, 14)) {
3290   {
3291     SI opval = tmp_newval;
3292     SET_H_GR (FLD (f_operand1), opval);
3293     written |= (1 << 4);
3294     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3295   }
3296 }
3297  else if (EQSI (tmp_prno, 15)) {
3298   {
3299     SI opval = tmp_newval;
3300     SET_H_GR (FLD (f_operand1), opval);
3301     written |= (1 << 4);
3302     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3303   }
3304 }
3305  else {
3306 cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
3307 }
3308 {
3309   {
3310     BI opval = 0;
3311     CPU (h_xbit) = opval;
3312     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3313   }
3314   {
3315     BI opval = 0;
3316     SET_H_INSN_PREFIXED_P (opval);
3317     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3318   }
3319 }
3320 }
3321
3322   abuf->written = written;
3323 #undef FLD
3324 }
3325   NEXT (vpc);
3326
3327   CASE (sem, INSN_RET_TYPE) : /* ret/reti/retb */
3328 {
3329   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3330   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3331 #define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
3332   int UNUSED written = 0;
3333   IADDR UNUSED pc = abuf->addr;
3334   SEM_BRANCH_INIT
3335   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3336
3337 {
3338   SI tmp_retaddr;
3339   tmp_retaddr = GET_H_SR (FLD (f_operand2));
3340 {
3341   {
3342     BI opval = 0;
3343     CPU (h_xbit) = opval;
3344     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3345   }
3346   {
3347     BI opval = 0;
3348     SET_H_INSN_PREFIXED_P (opval);
3349     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3350   }
3351 }
3352 {
3353   {
3354     USI opval = tmp_retaddr;
3355     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3356     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3357   }
3358 }
3359 }
3360
3361   SEM_BRANCH_FINI (vpc);
3362 #undef FLD
3363 }
3364   NEXT (vpc);
3365
3366   CASE (sem, INSN_MOVE_M_SPRV10) : /* move [${Rs}${inc}],${Pd} */
3367 {
3368   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3369   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3370 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
3371   int UNUSED written = 0;
3372   IADDR UNUSED pc = abuf->addr;
3373   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3374
3375 {
3376   SI tmp_rno;
3377   SI tmp_newval;
3378   tmp_rno = FLD (f_operand2);
3379 if (EQSI (tmp_rno, 5)) {
3380   tmp_newval = EXTHISI (({   SI tmp_addr;
3381   HI tmp_tmp_mem;
3382   BI tmp_postinc;
3383   tmp_postinc = FLD (f_memmode);
3384 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3385 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
3386 ; if (NEBI (tmp_postinc, 0)) {
3387 {
3388 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3389   tmp_addr = ADDSI (tmp_addr, 2);
3390 }
3391   {
3392     SI opval = tmp_addr;
3393     SET_H_GR (FLD (f_operand1), opval);
3394     written |= (1 << 8);
3395     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3396   }
3397 }
3398 }
3399 ; tmp_tmp_mem; }));
3400 }
3401  else if (EQSI (tmp_rno, 9)) {
3402   tmp_newval = ({   SI tmp_addr;
3403   SI tmp_tmp_mem;
3404   BI tmp_postinc;
3405   tmp_postinc = FLD (f_memmode);
3406 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3407 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3408 ; if (NEBI (tmp_postinc, 0)) {
3409 {
3410 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3411   tmp_addr = ADDSI (tmp_addr, 4);
3412 }
3413   {
3414     SI opval = tmp_addr;
3415     SET_H_GR (FLD (f_operand1), opval);
3416     written |= (1 << 8);
3417     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3418   }
3419 }
3420 }
3421 ; tmp_tmp_mem; });
3422 }
3423  else if (EQSI (tmp_rno, 10)) {
3424   tmp_newval = ({   SI tmp_addr;
3425   SI tmp_tmp_mem;
3426   BI tmp_postinc;
3427   tmp_postinc = FLD (f_memmode);
3428 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3429 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3430 ; if (NEBI (tmp_postinc, 0)) {
3431 {
3432 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3433   tmp_addr = ADDSI (tmp_addr, 4);
3434 }
3435   {
3436     SI opval = tmp_addr;
3437     SET_H_GR (FLD (f_operand1), opval);
3438     written |= (1 << 8);
3439     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3440   }
3441 }
3442 }
3443 ; tmp_tmp_mem; });
3444 }
3445  else if (EQSI (tmp_rno, 11)) {
3446   tmp_newval = ({   SI tmp_addr;
3447   SI tmp_tmp_mem;
3448   BI tmp_postinc;
3449   tmp_postinc = FLD (f_memmode);
3450 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3451 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3452 ; if (NEBI (tmp_postinc, 0)) {
3453 {
3454 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3455   tmp_addr = ADDSI (tmp_addr, 4);
3456 }
3457   {
3458     SI opval = tmp_addr;
3459     SET_H_GR (FLD (f_operand1), opval);
3460     written |= (1 << 8);
3461     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3462   }
3463 }
3464 }
3465 ; tmp_tmp_mem; });
3466 }
3467  else if (EQSI (tmp_rno, 12)) {
3468   tmp_newval = ({   SI tmp_addr;
3469   SI tmp_tmp_mem;
3470   BI tmp_postinc;
3471   tmp_postinc = FLD (f_memmode);
3472 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3473 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3474 ; if (NEBI (tmp_postinc, 0)) {
3475 {
3476 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3477   tmp_addr = ADDSI (tmp_addr, 4);
3478 }
3479   {
3480     SI opval = tmp_addr;
3481     SET_H_GR (FLD (f_operand1), opval);
3482     written |= (1 << 8);
3483     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3484   }
3485 }
3486 }
3487 ; tmp_tmp_mem; });
3488 }
3489  else if (EQSI (tmp_rno, 13)) {
3490   tmp_newval = ({   SI tmp_addr;
3491   SI tmp_tmp_mem;
3492   BI tmp_postinc;
3493   tmp_postinc = FLD (f_memmode);
3494 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3495 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3496 ; if (NEBI (tmp_postinc, 0)) {
3497 {
3498 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3499   tmp_addr = ADDSI (tmp_addr, 4);
3500 }
3501   {
3502     SI opval = tmp_addr;
3503     SET_H_GR (FLD (f_operand1), opval);
3504     written |= (1 << 8);
3505     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3506   }
3507 }
3508 }
3509 ; tmp_tmp_mem; });
3510 }
3511  else if (EQSI (tmp_rno, 7)) {
3512   tmp_newval = ({   SI tmp_addr;
3513   SI tmp_tmp_mem;
3514   BI tmp_postinc;
3515   tmp_postinc = FLD (f_memmode);
3516 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3517 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3518 ; if (NEBI (tmp_postinc, 0)) {
3519 {
3520 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3521   tmp_addr = ADDSI (tmp_addr, 4);
3522 }
3523   {
3524     SI opval = tmp_addr;
3525     SET_H_GR (FLD (f_operand1), opval);
3526     written |= (1 << 8);
3527     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3528   }
3529 }
3530 }
3531 ; tmp_tmp_mem; });
3532 }
3533  else if (EQSI (tmp_rno, 14)) {
3534   tmp_newval = ({   SI tmp_addr;
3535   SI tmp_tmp_mem;
3536   BI tmp_postinc;
3537   tmp_postinc = FLD (f_memmode);
3538 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3539 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3540 ; if (NEBI (tmp_postinc, 0)) {
3541 {
3542 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3543   tmp_addr = ADDSI (tmp_addr, 4);
3544 }
3545   {
3546     SI opval = tmp_addr;
3547     SET_H_GR (FLD (f_operand1), opval);
3548     written |= (1 << 8);
3549     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3550   }
3551 }
3552 }
3553 ; tmp_tmp_mem; });
3554 }
3555  else if (EQSI (tmp_rno, 15)) {
3556   tmp_newval = ({   SI tmp_addr;
3557   SI tmp_tmp_mem;
3558   BI tmp_postinc;
3559   tmp_postinc = FLD (f_memmode);
3560 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3561 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3562 ; if (NEBI (tmp_postinc, 0)) {
3563 {
3564 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3565   tmp_addr = ADDSI (tmp_addr, 4);
3566 }
3567   {
3568     SI opval = tmp_addr;
3569     SET_H_GR (FLD (f_operand1), opval);
3570     written |= (1 << 8);
3571     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3572   }
3573 }
3574 }
3575 ; tmp_tmp_mem; });
3576 }
3577  else {
3578 cgen_rtx_error (current_cpu, "Trying to set unimplemented special register");
3579 }
3580   {
3581     SI opval = tmp_newval;
3582     SET_H_SR (FLD (f_operand2), opval);
3583     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3584   }
3585 {
3586   {
3587     BI opval = 0;
3588     CPU (h_xbit) = opval;
3589     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3590   }
3591   {
3592     BI opval = 0;
3593     SET_H_INSN_PREFIXED_P (opval);
3594     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3595   }
3596 }
3597 }
3598
3599   abuf->written = written;
3600 #undef FLD
3601 }
3602   NEXT (vpc);
3603
3604   CASE (sem, INSN_MOVE_C_SPRV10_P5) : /* move ${sconst16},${Pd} */
3605 {
3606   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3607   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3608 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p5.f
3609   int UNUSED written = 0;
3610   IADDR UNUSED pc = abuf->addr;
3611   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3612
3613 {
3614   {
3615     SI opval = FLD (f_indir_pc__word);
3616     SET_H_SR (FLD (f_operand2), opval);
3617     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3618   }
3619 {
3620   {
3621     BI opval = 0;
3622     CPU (h_xbit) = opval;
3623     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3624   }
3625   {
3626     BI opval = 0;
3627     SET_H_INSN_PREFIXED_P (opval);
3628     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3629   }
3630 }
3631 }
3632
3633 #undef FLD
3634 }
3635   NEXT (vpc);
3636
3637   CASE (sem, INSN_MOVE_C_SPRV10_P9) : /* move ${const32},${Pd} */
3638 {
3639   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3640   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3641 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3642   int UNUSED written = 0;
3643   IADDR UNUSED pc = abuf->addr;
3644   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3645
3646 {
3647   {
3648     SI opval = FLD (f_indir_pc__dword);
3649     SET_H_SR (FLD (f_operand2), opval);
3650     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3651   }
3652 {
3653   {
3654     BI opval = 0;
3655     CPU (h_xbit) = opval;
3656     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3657   }
3658   {
3659     BI opval = 0;
3660     SET_H_INSN_PREFIXED_P (opval);
3661     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3662   }
3663 }
3664 }
3665
3666 #undef FLD
3667 }
3668   NEXT (vpc);
3669
3670   CASE (sem, INSN_MOVE_C_SPRV10_P10) : /* move ${const32},${Pd} */
3671 {
3672   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3673   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3674 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3675   int UNUSED written = 0;
3676   IADDR UNUSED pc = abuf->addr;
3677   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3678
3679 {
3680   {
3681     SI opval = FLD (f_indir_pc__dword);
3682     SET_H_SR (FLD (f_operand2), opval);
3683     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3684   }
3685 {
3686   {
3687     BI opval = 0;
3688     CPU (h_xbit) = opval;
3689     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3690   }
3691   {
3692     BI opval = 0;
3693     SET_H_INSN_PREFIXED_P (opval);
3694     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3695   }
3696 }
3697 }
3698
3699 #undef FLD
3700 }
3701   NEXT (vpc);
3702
3703   CASE (sem, INSN_MOVE_C_SPRV10_P11) : /* move ${const32},${Pd} */
3704 {
3705   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3706   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3707 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3708   int UNUSED written = 0;
3709   IADDR UNUSED pc = abuf->addr;
3710   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3711
3712 {
3713   {
3714     SI opval = FLD (f_indir_pc__dword);
3715     SET_H_SR (FLD (f_operand2), opval);
3716     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3717   }
3718 {
3719   {
3720     BI opval = 0;
3721     CPU (h_xbit) = opval;
3722     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3723   }
3724   {
3725     BI opval = 0;
3726     SET_H_INSN_PREFIXED_P (opval);
3727     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3728   }
3729 }
3730 }
3731
3732 #undef FLD
3733 }
3734   NEXT (vpc);
3735
3736   CASE (sem, INSN_MOVE_C_SPRV10_P12) : /* move ${const32},${Pd} */
3737 {
3738   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3739   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3740 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3741   int UNUSED written = 0;
3742   IADDR UNUSED pc = abuf->addr;
3743   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3744
3745 {
3746   {
3747     SI opval = FLD (f_indir_pc__dword);
3748     SET_H_SR (FLD (f_operand2), opval);
3749     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3750   }
3751 {
3752   {
3753     BI opval = 0;
3754     CPU (h_xbit) = opval;
3755     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3756   }
3757   {
3758     BI opval = 0;
3759     SET_H_INSN_PREFIXED_P (opval);
3760     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3761   }
3762 }
3763 }
3764
3765 #undef FLD
3766 }
3767   NEXT (vpc);
3768
3769   CASE (sem, INSN_MOVE_C_SPRV10_P13) : /* move ${const32},${Pd} */
3770 {
3771   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3772   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3773 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3774   int UNUSED written = 0;
3775   IADDR UNUSED pc = abuf->addr;
3776   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3777
3778 {
3779   {
3780     SI opval = FLD (f_indir_pc__dword);
3781     SET_H_SR (FLD (f_operand2), opval);
3782     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3783   }
3784 {
3785   {
3786     BI opval = 0;
3787     CPU (h_xbit) = opval;
3788     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3789   }
3790   {
3791     BI opval = 0;
3792     SET_H_INSN_PREFIXED_P (opval);
3793     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3794   }
3795 }
3796 }
3797
3798 #undef FLD
3799 }
3800   NEXT (vpc);
3801
3802   CASE (sem, INSN_MOVE_C_SPRV10_P7) : /* move ${const32},${Pd} */
3803 {
3804   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3805   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3806 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3807   int UNUSED written = 0;
3808   IADDR UNUSED pc = abuf->addr;
3809   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3810
3811 {
3812   {
3813     SI opval = FLD (f_indir_pc__dword);
3814     SET_H_SR (FLD (f_operand2), opval);
3815     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3816   }
3817 {
3818   {
3819     BI opval = 0;
3820     CPU (h_xbit) = opval;
3821     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3822   }
3823   {
3824     BI opval = 0;
3825     SET_H_INSN_PREFIXED_P (opval);
3826     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3827   }
3828 }
3829 }
3830
3831 #undef FLD
3832 }
3833   NEXT (vpc);
3834
3835   CASE (sem, INSN_MOVE_C_SPRV10_P14) : /* move ${const32},${Pd} */
3836 {
3837   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3838   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3839 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3840   int UNUSED written = 0;
3841   IADDR UNUSED pc = abuf->addr;
3842   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3843
3844 {
3845   {
3846     SI opval = FLD (f_indir_pc__dword);
3847     SET_H_SR (FLD (f_operand2), opval);
3848     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3849   }
3850 {
3851   {
3852     BI opval = 0;
3853     CPU (h_xbit) = opval;
3854     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3855   }
3856   {
3857     BI opval = 0;
3858     SET_H_INSN_PREFIXED_P (opval);
3859     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3860   }
3861 }
3862 }
3863
3864 #undef FLD
3865 }
3866   NEXT (vpc);
3867
3868   CASE (sem, INSN_MOVE_C_SPRV10_P15) : /* move ${const32},${Pd} */
3869 {
3870   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3871   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3872 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3873   int UNUSED written = 0;
3874   IADDR UNUSED pc = abuf->addr;
3875   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3876
3877 {
3878   {
3879     SI opval = FLD (f_indir_pc__dword);
3880     SET_H_SR (FLD (f_operand2), opval);
3881     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3882   }
3883 {
3884   {
3885     BI opval = 0;
3886     CPU (h_xbit) = opval;
3887     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3888   }
3889   {
3890     BI opval = 0;
3891     SET_H_INSN_PREFIXED_P (opval);
3892     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3893   }
3894 }
3895 }
3896
3897 #undef FLD
3898 }
3899   NEXT (vpc);
3900
3901   CASE (sem, INSN_MOVE_SPR_MV10) : /* move ${Ps},[${Rd-sfield}${inc}] */
3902 {
3903   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3904   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3905 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
3906   int UNUSED written = 0;
3907   IADDR UNUSED pc = abuf->addr;
3908   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3909
3910 {
3911   SI tmp_rno;
3912   tmp_rno = FLD (f_operand2);
3913 if (EQSI (tmp_rno, 5)) {
3914 {
3915   SI tmp_addr;
3916   BI tmp_postinc;
3917   tmp_postinc = FLD (f_memmode);
3918   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3919 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
3920 if (EQBI (CPU (h_pbit), 0)) {
3921 {
3922   {
3923     HI opval = GET_H_SR (FLD (f_operand2));
3924     SETMEMHI (current_cpu, pc, tmp_addr, opval);
3925     written |= (1 << 11);
3926     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
3927   }
3928   {
3929     BI opval = CPU (h_pbit);
3930     CPU (h_cbit) = opval;
3931     written |= (1 << 10);
3932     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
3933   }
3934 }
3935 } else {
3936   {
3937     BI opval = 1;
3938     CPU (h_cbit) = opval;
3939     written |= (1 << 10);
3940     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
3941   }
3942 }
3943 } else {
3944   {
3945     HI opval = GET_H_SR (FLD (f_operand2));
3946     SETMEMHI (current_cpu, pc, tmp_addr, opval);
3947     written |= (1 << 11);
3948     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
3949   }
3950 }
3951 if (NEBI (tmp_postinc, 0)) {
3952 {
3953 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3954   tmp_addr = ADDSI (tmp_addr, 2);
3955 }
3956   {
3957     SI opval = tmp_addr;
3958     SET_H_GR (FLD (f_operand1), opval);
3959     written |= (1 << 9);
3960     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3961   }
3962 }
3963 }
3964 }
3965 }
3966  else if (EQSI (tmp_rno, 9)) {
3967 {
3968   SI tmp_addr;
3969   BI tmp_postinc;
3970   tmp_postinc = FLD (f_memmode);
3971   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3972 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
3973 if (EQBI (CPU (h_pbit), 0)) {
3974 {
3975   {
3976     SI opval = GET_H_SR (FLD (f_operand2));
3977     SETMEMSI (current_cpu, pc, tmp_addr, opval);
3978     written |= (1 << 13);
3979     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
3980   }
3981   {
3982     BI opval = CPU (h_pbit);
3983     CPU (h_cbit) = opval;
3984     written |= (1 << 10);
3985     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
3986   }
3987 }
3988 } else {
3989   {
3990     BI opval = 1;
3991     CPU (h_cbit) = opval;
3992     written |= (1 << 10);
3993     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
3994   }
3995 }
3996 } else {
3997   {
3998     SI opval = GET_H_SR (FLD (f_operand2));
3999     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4000     written |= (1 << 13);
4001     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4002   }
4003 }
4004 if (NEBI (tmp_postinc, 0)) {
4005 {
4006 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4007   tmp_addr = ADDSI (tmp_addr, 4);
4008 }
4009   {
4010     SI opval = tmp_addr;
4011     SET_H_GR (FLD (f_operand1), opval);
4012     written |= (1 << 9);
4013     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4014   }
4015 }
4016 }
4017 }
4018 }
4019  else if (EQSI (tmp_rno, 10)) {
4020 {
4021   SI tmp_addr;
4022   BI tmp_postinc;
4023   tmp_postinc = FLD (f_memmode);
4024   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4025 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4026 if (EQBI (CPU (h_pbit), 0)) {
4027 {
4028   {
4029     SI opval = GET_H_SR (FLD (f_operand2));
4030     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4031     written |= (1 << 13);
4032     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4033   }
4034   {
4035     BI opval = CPU (h_pbit);
4036     CPU (h_cbit) = opval;
4037     written |= (1 << 10);
4038     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4039   }
4040 }
4041 } else {
4042   {
4043     BI opval = 1;
4044     CPU (h_cbit) = opval;
4045     written |= (1 << 10);
4046     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4047   }
4048 }
4049 } else {
4050   {
4051     SI opval = GET_H_SR (FLD (f_operand2));
4052     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4053     written |= (1 << 13);
4054     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4055   }
4056 }
4057 if (NEBI (tmp_postinc, 0)) {
4058 {
4059 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4060   tmp_addr = ADDSI (tmp_addr, 4);
4061 }
4062   {
4063     SI opval = tmp_addr;
4064     SET_H_GR (FLD (f_operand1), opval);
4065     written |= (1 << 9);
4066     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4067   }
4068 }
4069 }
4070 }
4071 }
4072  else if (EQSI (tmp_rno, 11)) {
4073 {
4074   SI tmp_addr;
4075   BI tmp_postinc;
4076   tmp_postinc = FLD (f_memmode);
4077   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4078 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4079 if (EQBI (CPU (h_pbit), 0)) {
4080 {
4081   {
4082     SI opval = GET_H_SR (FLD (f_operand2));
4083     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4084     written |= (1 << 13);
4085     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4086   }
4087   {
4088     BI opval = CPU (h_pbit);
4089     CPU (h_cbit) = opval;
4090     written |= (1 << 10);
4091     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4092   }
4093 }
4094 } else {
4095   {
4096     BI opval = 1;
4097     CPU (h_cbit) = opval;
4098     written |= (1 << 10);
4099     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4100   }
4101 }
4102 } else {
4103   {
4104     SI opval = GET_H_SR (FLD (f_operand2));
4105     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4106     written |= (1 << 13);
4107     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4108   }
4109 }
4110 if (NEBI (tmp_postinc, 0)) {
4111 {
4112 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4113   tmp_addr = ADDSI (tmp_addr, 4);
4114 }
4115   {
4116     SI opval = tmp_addr;
4117     SET_H_GR (FLD (f_operand1), opval);
4118     written |= (1 << 9);
4119     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4120   }
4121 }
4122 }
4123 }
4124 }
4125  else if (EQSI (tmp_rno, 12)) {
4126 {
4127   SI tmp_addr;
4128   BI tmp_postinc;
4129   tmp_postinc = FLD (f_memmode);
4130   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4131 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4132 if (EQBI (CPU (h_pbit), 0)) {
4133 {
4134   {
4135     SI opval = GET_H_SR (FLD (f_operand2));
4136     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4137     written |= (1 << 13);
4138     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4139   }
4140   {
4141     BI opval = CPU (h_pbit);
4142     CPU (h_cbit) = opval;
4143     written |= (1 << 10);
4144     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4145   }
4146 }
4147 } else {
4148   {
4149     BI opval = 1;
4150     CPU (h_cbit) = opval;
4151     written |= (1 << 10);
4152     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4153   }
4154 }
4155 } else {
4156   {
4157     SI opval = GET_H_SR (FLD (f_operand2));
4158     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4159     written |= (1 << 13);
4160     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4161   }
4162 }
4163 if (NEBI (tmp_postinc, 0)) {
4164 {
4165 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4166   tmp_addr = ADDSI (tmp_addr, 4);
4167 }
4168   {
4169     SI opval = tmp_addr;
4170     SET_H_GR (FLD (f_operand1), opval);
4171     written |= (1 << 9);
4172     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4173   }
4174 }
4175 }
4176 }
4177 }
4178  else if (EQSI (tmp_rno, 13)) {
4179 {
4180   SI tmp_addr;
4181   BI tmp_postinc;
4182   tmp_postinc = FLD (f_memmode);
4183   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4184 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4185 if (EQBI (CPU (h_pbit), 0)) {
4186 {
4187   {
4188     SI opval = GET_H_SR (FLD (f_operand2));
4189     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4190     written |= (1 << 13);
4191     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4192   }
4193   {
4194     BI opval = CPU (h_pbit);
4195     CPU (h_cbit) = opval;
4196     written |= (1 << 10);
4197     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4198   }
4199 }
4200 } else {
4201   {
4202     BI opval = 1;
4203     CPU (h_cbit) = opval;
4204     written |= (1 << 10);
4205     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4206   }
4207 }
4208 } else {
4209   {
4210     SI opval = GET_H_SR (FLD (f_operand2));
4211     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4212     written |= (1 << 13);
4213     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4214   }
4215 }
4216 if (NEBI (tmp_postinc, 0)) {
4217 {
4218 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4219   tmp_addr = ADDSI (tmp_addr, 4);
4220 }
4221   {
4222     SI opval = tmp_addr;
4223     SET_H_GR (FLD (f_operand1), opval);
4224     written |= (1 << 9);
4225     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4226   }
4227 }
4228 }
4229 }
4230 }
4231  else if (EQSI (tmp_rno, 0)) {
4232 {
4233   SI tmp_addr;
4234   BI tmp_postinc;
4235   tmp_postinc = FLD (f_memmode);
4236   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4237 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4238 if (EQBI (CPU (h_pbit), 0)) {
4239 {
4240   {
4241     QI opval = GET_H_SR (FLD (f_operand2));
4242     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4243     written |= (1 << 12);
4244     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4245   }
4246   {
4247     BI opval = CPU (h_pbit);
4248     CPU (h_cbit) = opval;
4249     written |= (1 << 10);
4250     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4251   }
4252 }
4253 } else {
4254   {
4255     BI opval = 1;
4256     CPU (h_cbit) = opval;
4257     written |= (1 << 10);
4258     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4259   }
4260 }
4261 } else {
4262   {
4263     QI opval = GET_H_SR (FLD (f_operand2));
4264     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4265     written |= (1 << 12);
4266     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4267   }
4268 }
4269 if (NEBI (tmp_postinc, 0)) {
4270 {
4271 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4272   tmp_addr = ADDSI (tmp_addr, 1);
4273 }
4274   {
4275     SI opval = tmp_addr;
4276     SET_H_GR (FLD (f_operand1), opval);
4277     written |= (1 << 9);
4278     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4279   }
4280 }
4281 }
4282 }
4283 }
4284  else if (EQSI (tmp_rno, 1)) {
4285 {
4286   SI tmp_addr;
4287   BI tmp_postinc;
4288   tmp_postinc = FLD (f_memmode);
4289   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4290 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4291 if (EQBI (CPU (h_pbit), 0)) {
4292 {
4293   {
4294     QI opval = GET_H_SR (FLD (f_operand2));
4295     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4296     written |= (1 << 12);
4297     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4298   }
4299   {
4300     BI opval = CPU (h_pbit);
4301     CPU (h_cbit) = opval;
4302     written |= (1 << 10);
4303     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4304   }
4305 }
4306 } else {
4307   {
4308     BI opval = 1;
4309     CPU (h_cbit) = opval;
4310     written |= (1 << 10);
4311     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4312   }
4313 }
4314 } else {
4315   {
4316     QI opval = GET_H_SR (FLD (f_operand2));
4317     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4318     written |= (1 << 12);
4319     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4320   }
4321 }
4322 if (NEBI (tmp_postinc, 0)) {
4323 {
4324 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4325   tmp_addr = ADDSI (tmp_addr, 1);
4326 }
4327   {
4328     SI opval = tmp_addr;
4329     SET_H_GR (FLD (f_operand1), opval);
4330     written |= (1 << 9);
4331     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4332   }
4333 }
4334 }
4335 }
4336 }
4337  else if (EQSI (tmp_rno, 4)) {
4338 {
4339   SI tmp_addr;
4340   BI tmp_postinc;
4341   tmp_postinc = FLD (f_memmode);
4342   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4343 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4344 if (EQBI (CPU (h_pbit), 0)) {
4345 {
4346   {
4347     HI opval = GET_H_SR (FLD (f_operand2));
4348     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4349     written |= (1 << 11);
4350     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4351   }
4352   {
4353     BI opval = CPU (h_pbit);
4354     CPU (h_cbit) = opval;
4355     written |= (1 << 10);
4356     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4357   }
4358 }
4359 } else {
4360   {
4361     BI opval = 1;
4362     CPU (h_cbit) = opval;
4363     written |= (1 << 10);
4364     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4365   }
4366 }
4367 } else {
4368   {
4369     HI opval = GET_H_SR (FLD (f_operand2));
4370     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4371     written |= (1 << 11);
4372     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4373   }
4374 }
4375 if (NEBI (tmp_postinc, 0)) {
4376 {
4377 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4378   tmp_addr = ADDSI (tmp_addr, 2);
4379 }
4380   {
4381     SI opval = tmp_addr;
4382     SET_H_GR (FLD (f_operand1), opval);
4383     written |= (1 << 9);
4384     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4385   }
4386 }
4387 }
4388 }
4389 }
4390  else if (EQSI (tmp_rno, 8)) {
4391 {
4392   SI tmp_addr;
4393   BI tmp_postinc;
4394   tmp_postinc = FLD (f_memmode);
4395   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4396 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4397 if (EQBI (CPU (h_pbit), 0)) {
4398 {
4399   {
4400     SI opval = GET_H_SR (FLD (f_operand2));
4401     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4402     written |= (1 << 13);
4403     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4404   }
4405   {
4406     BI opval = CPU (h_pbit);
4407     CPU (h_cbit) = opval;
4408     written |= (1 << 10);
4409     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4410   }
4411 }
4412 } else {
4413   {
4414     BI opval = 1;
4415     CPU (h_cbit) = opval;
4416     written |= (1 << 10);
4417     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4418   }
4419 }
4420 } else {
4421   {
4422     SI opval = GET_H_SR (FLD (f_operand2));
4423     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4424     written |= (1 << 13);
4425     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4426   }
4427 }
4428 if (NEBI (tmp_postinc, 0)) {
4429 {
4430 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4431   tmp_addr = ADDSI (tmp_addr, 4);
4432 }
4433   {
4434     SI opval = tmp_addr;
4435     SET_H_GR (FLD (f_operand1), opval);
4436     written |= (1 << 9);
4437     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4438   }
4439 }
4440 }
4441 }
4442 }
4443  else if (EQSI (tmp_rno, 7)) {
4444 {
4445   SI tmp_addr;
4446   BI tmp_postinc;
4447   tmp_postinc = FLD (f_memmode);
4448   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4449 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4450 if (EQBI (CPU (h_pbit), 0)) {
4451 {
4452   {
4453     SI opval = GET_H_SR (FLD (f_operand2));
4454     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4455     written |= (1 << 13);
4456     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4457   }
4458   {
4459     BI opval = CPU (h_pbit);
4460     CPU (h_cbit) = opval;
4461     written |= (1 << 10);
4462     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4463   }
4464 }
4465 } else {
4466   {
4467     BI opval = 1;
4468     CPU (h_cbit) = opval;
4469     written |= (1 << 10);
4470     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4471   }
4472 }
4473 } else {
4474   {
4475     SI opval = GET_H_SR (FLD (f_operand2));
4476     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4477     written |= (1 << 13);
4478     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4479   }
4480 }
4481 if (NEBI (tmp_postinc, 0)) {
4482 {
4483 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4484   tmp_addr = ADDSI (tmp_addr, 4);
4485 }
4486   {
4487     SI opval = tmp_addr;
4488     SET_H_GR (FLD (f_operand1), opval);
4489     written |= (1 << 9);
4490     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4491   }
4492 }
4493 }
4494 }
4495 }
4496  else if (EQSI (tmp_rno, 14)) {
4497 {
4498   SI tmp_addr;
4499   BI tmp_postinc;
4500   tmp_postinc = FLD (f_memmode);
4501   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4502 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4503 if (EQBI (CPU (h_pbit), 0)) {
4504 {
4505   {
4506     SI opval = GET_H_SR (FLD (f_operand2));
4507     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4508     written |= (1 << 13);
4509     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4510   }
4511   {
4512     BI opval = CPU (h_pbit);
4513     CPU (h_cbit) = opval;
4514     written |= (1 << 10);
4515     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4516   }
4517 }
4518 } else {
4519   {
4520     BI opval = 1;
4521     CPU (h_cbit) = opval;
4522     written |= (1 << 10);
4523     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4524   }
4525 }
4526 } else {
4527   {
4528     SI opval = GET_H_SR (FLD (f_operand2));
4529     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4530     written |= (1 << 13);
4531     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4532   }
4533 }
4534 if (NEBI (tmp_postinc, 0)) {
4535 {
4536 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4537   tmp_addr = ADDSI (tmp_addr, 4);
4538 }
4539   {
4540     SI opval = tmp_addr;
4541     SET_H_GR (FLD (f_operand1), opval);
4542     written |= (1 << 9);
4543     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4544   }
4545 }
4546 }
4547 }
4548 }
4549  else if (EQSI (tmp_rno, 15)) {
4550 {
4551   SI tmp_addr;
4552   BI tmp_postinc;
4553   tmp_postinc = FLD (f_memmode);
4554   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4555 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4556 if (EQBI (CPU (h_pbit), 0)) {
4557 {
4558   {
4559     SI opval = GET_H_SR (FLD (f_operand2));
4560     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4561     written |= (1 << 13);
4562     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4563   }
4564   {
4565     BI opval = CPU (h_pbit);
4566     CPU (h_cbit) = opval;
4567     written |= (1 << 10);
4568     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4569   }
4570 }
4571 } else {
4572   {
4573     BI opval = 1;
4574     CPU (h_cbit) = opval;
4575     written |= (1 << 10);
4576     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4577   }
4578 }
4579 } else {
4580   {
4581     SI opval = GET_H_SR (FLD (f_operand2));
4582     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4583     written |= (1 << 13);
4584     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4585   }
4586 }
4587 if (NEBI (tmp_postinc, 0)) {
4588 {
4589 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4590   tmp_addr = ADDSI (tmp_addr, 4);
4591 }
4592   {
4593     SI opval = tmp_addr;
4594     SET_H_GR (FLD (f_operand1), opval);
4595     written |= (1 << 9);
4596     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4597   }
4598 }
4599 }
4600 }
4601 }
4602  else {
4603 cgen_rtx_error (current_cpu, "write from unimplemented special register");
4604 }
4605 {
4606   {
4607     BI opval = 0;
4608     CPU (h_xbit) = opval;
4609     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4610   }
4611   {
4612     BI opval = 0;
4613     SET_H_INSN_PREFIXED_P (opval);
4614     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4615   }
4616 }
4617 }
4618
4619   abuf->written = written;
4620 #undef FLD
4621 }
4622   NEXT (vpc);
4623
4624   CASE (sem, INSN_SBFS) : /* sbfs [${Rd-sfield}${inc}] */
4625 {
4626   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4627   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4628 #define FLD(f) abuf->fields.fmt_empty.f
4629   int UNUSED written = 0;
4630   IADDR UNUSED pc = abuf->addr;
4631   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4632
4633 cgen_rtx_error (current_cpu, "SBFS isn't implemented");
4634
4635 #undef FLD
4636 }
4637   NEXT (vpc);
4638
4639   CASE (sem, INSN_MOVEM_R_M) : /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
4640 {
4641   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4642   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4643 #define FLD(f) abuf->fields.sfmt_movem_r_m.f
4644   int UNUSED written = 0;
4645   IADDR UNUSED pc = abuf->addr;
4646   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4647
4648 {
4649   SI tmp_addr;
4650   BI tmp_postinc;
4651   tmp_postinc = FLD (f_memmode);
4652 {
4653   SI tmp_dummy;
4654   tmp_dummy = GET_H_GR (FLD (f_operand2));
4655 }
4656   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4657 {
4658 if (GESI (FLD (f_operand2), 15)) {
4659 {
4660   SI tmp_tmp;
4661   tmp_tmp = GET_H_GR (((UINT) 15));
4662   {
4663     SI opval = tmp_tmp;
4664     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4665     written |= (1 << 23);
4666     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4667   }
4668   tmp_addr = ADDSI (tmp_addr, 4);
4669 }
4670 }
4671 if (GESI (FLD (f_operand2), 14)) {
4672 {
4673   SI tmp_tmp;
4674   tmp_tmp = GET_H_GR (((UINT) 14));
4675   {
4676     SI opval = tmp_tmp;
4677     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4678     written |= (1 << 23);
4679     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4680   }
4681   tmp_addr = ADDSI (tmp_addr, 4);
4682 }
4683 }
4684 if (GESI (FLD (f_operand2), 13)) {
4685 {
4686   SI tmp_tmp;
4687   tmp_tmp = GET_H_GR (((UINT) 13));
4688   {
4689     SI opval = tmp_tmp;
4690     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4691     written |= (1 << 23);
4692     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4693   }
4694   tmp_addr = ADDSI (tmp_addr, 4);
4695 }
4696 }
4697 if (GESI (FLD (f_operand2), 12)) {
4698 {
4699   SI tmp_tmp;
4700   tmp_tmp = GET_H_GR (((UINT) 12));
4701   {
4702     SI opval = tmp_tmp;
4703     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4704     written |= (1 << 23);
4705     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4706   }
4707   tmp_addr = ADDSI (tmp_addr, 4);
4708 }
4709 }
4710 if (GESI (FLD (f_operand2), 11)) {
4711 {
4712   SI tmp_tmp;
4713   tmp_tmp = GET_H_GR (((UINT) 11));
4714   {
4715     SI opval = tmp_tmp;
4716     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4717     written |= (1 << 23);
4718     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4719   }
4720   tmp_addr = ADDSI (tmp_addr, 4);
4721 }
4722 }
4723 if (GESI (FLD (f_operand2), 10)) {
4724 {
4725   SI tmp_tmp;
4726   tmp_tmp = GET_H_GR (((UINT) 10));
4727   {
4728     SI opval = tmp_tmp;
4729     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4730     written |= (1 << 23);
4731     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4732   }
4733   tmp_addr = ADDSI (tmp_addr, 4);
4734 }
4735 }
4736 if (GESI (FLD (f_operand2), 9)) {
4737 {
4738   SI tmp_tmp;
4739   tmp_tmp = GET_H_GR (((UINT) 9));
4740   {
4741     SI opval = tmp_tmp;
4742     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4743     written |= (1 << 23);
4744     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4745   }
4746   tmp_addr = ADDSI (tmp_addr, 4);
4747 }
4748 }
4749 if (GESI (FLD (f_operand2), 8)) {
4750 {
4751   SI tmp_tmp;
4752   tmp_tmp = GET_H_GR (((UINT) 8));
4753   {
4754     SI opval = tmp_tmp;
4755     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4756     written |= (1 << 23);
4757     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4758   }
4759   tmp_addr = ADDSI (tmp_addr, 4);
4760 }
4761 }
4762 if (GESI (FLD (f_operand2), 7)) {
4763 {
4764   SI tmp_tmp;
4765   tmp_tmp = GET_H_GR (((UINT) 7));
4766   {
4767     SI opval = tmp_tmp;
4768     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4769     written |= (1 << 23);
4770     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4771   }
4772   tmp_addr = ADDSI (tmp_addr, 4);
4773 }
4774 }
4775 if (GESI (FLD (f_operand2), 6)) {
4776 {
4777   SI tmp_tmp;
4778   tmp_tmp = GET_H_GR (((UINT) 6));
4779   {
4780     SI opval = tmp_tmp;
4781     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4782     written |= (1 << 23);
4783     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4784   }
4785   tmp_addr = ADDSI (tmp_addr, 4);
4786 }
4787 }
4788 if (GESI (FLD (f_operand2), 5)) {
4789 {
4790   SI tmp_tmp;
4791   tmp_tmp = GET_H_GR (((UINT) 5));
4792   {
4793     SI opval = tmp_tmp;
4794     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4795     written |= (1 << 23);
4796     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4797   }
4798   tmp_addr = ADDSI (tmp_addr, 4);
4799 }
4800 }
4801 if (GESI (FLD (f_operand2), 4)) {
4802 {
4803   SI tmp_tmp;
4804   tmp_tmp = GET_H_GR (((UINT) 4));
4805   {
4806     SI opval = tmp_tmp;
4807     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4808     written |= (1 << 23);
4809     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4810   }
4811   tmp_addr = ADDSI (tmp_addr, 4);
4812 }
4813 }
4814 if (GESI (FLD (f_operand2), 3)) {
4815 {
4816   SI tmp_tmp;
4817   tmp_tmp = GET_H_GR (((UINT) 3));
4818   {
4819     SI opval = tmp_tmp;
4820     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4821     written |= (1 << 23);
4822     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4823   }
4824   tmp_addr = ADDSI (tmp_addr, 4);
4825 }
4826 }
4827 if (GESI (FLD (f_operand2), 2)) {
4828 {
4829   SI tmp_tmp;
4830   tmp_tmp = GET_H_GR (((UINT) 2));
4831   {
4832     SI opval = tmp_tmp;
4833     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4834     written |= (1 << 23);
4835     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4836   }
4837   tmp_addr = ADDSI (tmp_addr, 4);
4838 }
4839 }
4840 if (GESI (FLD (f_operand2), 1)) {
4841 {
4842   SI tmp_tmp;
4843   tmp_tmp = GET_H_GR (((UINT) 1));
4844   {
4845     SI opval = tmp_tmp;
4846     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4847     written |= (1 << 23);
4848     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4849   }
4850   tmp_addr = ADDSI (tmp_addr, 4);
4851 }
4852 }
4853 if (GESI (FLD (f_operand2), 0)) {
4854 {
4855   SI tmp_tmp;
4856   tmp_tmp = GET_H_GR (((UINT) 0));
4857   {
4858     SI opval = tmp_tmp;
4859     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4860     written |= (1 << 23);
4861     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4862   }
4863   tmp_addr = ADDSI (tmp_addr, 4);
4864 }
4865 }
4866 }
4867 if (NEBI (tmp_postinc, 0)) {
4868   {
4869     SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
4870     SET_H_GR (FLD (f_operand1), opval);
4871     written |= (1 << 22);
4872     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4873   }
4874 }
4875 {
4876   {
4877     BI opval = 0;
4878     CPU (h_xbit) = opval;
4879     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4880   }
4881   {
4882     BI opval = 0;
4883     SET_H_INSN_PREFIXED_P (opval);
4884     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4885   }
4886 }
4887 }
4888
4889   abuf->written = written;
4890 #undef FLD
4891 }
4892   NEXT (vpc);
4893
4894   CASE (sem, INSN_MOVEM_M_R) : /* movem [${Rs}${inc}],${Rd} */
4895 {
4896   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4897   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4898 #define FLD(f) abuf->fields.sfmt_movem_m_r.f
4899   int UNUSED written = 0;
4900   IADDR UNUSED pc = abuf->addr;
4901   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4902
4903 {
4904   SI tmp_addr;
4905   BI tmp_postinc;
4906   tmp_postinc = FLD (f_memmode);
4907   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4908 {
4909   SI tmp_dummy;
4910   tmp_dummy = GET_H_GR (FLD (f_operand2));
4911 }
4912 {
4913 if (GESI (FLD (f_operand2), 14)) {
4914 {
4915   SI tmp_tmp;
4916   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4917   {
4918     SI opval = tmp_tmp;
4919     SET_H_GR (((UINT) 14), opval);
4920     written |= (1 << 14);
4921     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4922   }
4923   tmp_addr = ADDSI (tmp_addr, 4);
4924 }
4925 }
4926 if (GESI (FLD (f_operand2), 13)) {
4927 {
4928   SI tmp_tmp;
4929   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4930   {
4931     SI opval = tmp_tmp;
4932     SET_H_GR (((UINT) 13), opval);
4933     written |= (1 << 13);
4934     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4935   }
4936   tmp_addr = ADDSI (tmp_addr, 4);
4937 }
4938 }
4939 if (GESI (FLD (f_operand2), 12)) {
4940 {
4941   SI tmp_tmp;
4942   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4943   {
4944     SI opval = tmp_tmp;
4945     SET_H_GR (((UINT) 12), opval);
4946     written |= (1 << 12);
4947     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4948   }
4949   tmp_addr = ADDSI (tmp_addr, 4);
4950 }
4951 }
4952 if (GESI (FLD (f_operand2), 11)) {
4953 {
4954   SI tmp_tmp;
4955   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4956   {
4957     SI opval = tmp_tmp;
4958     SET_H_GR (((UINT) 11), opval);
4959     written |= (1 << 11);
4960     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4961   }
4962   tmp_addr = ADDSI (tmp_addr, 4);
4963 }
4964 }
4965 if (GESI (FLD (f_operand2), 10)) {
4966 {
4967   SI tmp_tmp;
4968   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4969   {
4970     SI opval = tmp_tmp;
4971     SET_H_GR (((UINT) 10), opval);
4972     written |= (1 << 10);
4973     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4974   }
4975   tmp_addr = ADDSI (tmp_addr, 4);
4976 }
4977 }
4978 if (GESI (FLD (f_operand2), 9)) {
4979 {
4980   SI tmp_tmp;
4981   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4982   {
4983     SI opval = tmp_tmp;
4984     SET_H_GR (((UINT) 9), opval);
4985     written |= (1 << 22);
4986     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4987   }
4988   tmp_addr = ADDSI (tmp_addr, 4);
4989 }
4990 }
4991 if (GESI (FLD (f_operand2), 8)) {
4992 {
4993   SI tmp_tmp;
4994   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4995   {
4996     SI opval = tmp_tmp;
4997     SET_H_GR (((UINT) 8), opval);
4998     written |= (1 << 21);
4999     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5000   }
5001   tmp_addr = ADDSI (tmp_addr, 4);
5002 }
5003 }
5004 if (GESI (FLD (f_operand2), 7)) {
5005 {
5006   SI tmp_tmp;
5007   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5008   {
5009     SI opval = tmp_tmp;
5010     SET_H_GR (((UINT) 7), opval);
5011     written |= (1 << 20);
5012     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5013   }
5014   tmp_addr = ADDSI (tmp_addr, 4);
5015 }
5016 }
5017 if (GESI (FLD (f_operand2), 6)) {
5018 {
5019   SI tmp_tmp;
5020   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5021   {
5022     SI opval = tmp_tmp;
5023     SET_H_GR (((UINT) 6), opval);
5024     written |= (1 << 19);
5025     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5026   }
5027   tmp_addr = ADDSI (tmp_addr, 4);
5028 }
5029 }
5030 if (GESI (FLD (f_operand2), 5)) {
5031 {
5032   SI tmp_tmp;
5033   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5034   {
5035     SI opval = tmp_tmp;
5036     SET_H_GR (((UINT) 5), opval);
5037     written |= (1 << 18);
5038     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5039   }
5040   tmp_addr = ADDSI (tmp_addr, 4);
5041 }
5042 }
5043 if (GESI (FLD (f_operand2), 4)) {
5044 {
5045   SI tmp_tmp;
5046   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5047   {
5048     SI opval = tmp_tmp;
5049     SET_H_GR (((UINT) 4), opval);
5050     written |= (1 << 17);
5051     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5052   }
5053   tmp_addr = ADDSI (tmp_addr, 4);
5054 }
5055 }
5056 if (GESI (FLD (f_operand2), 3)) {
5057 {
5058   SI tmp_tmp;
5059   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5060   {
5061     SI opval = tmp_tmp;
5062     SET_H_GR (((UINT) 3), opval);
5063     written |= (1 << 16);
5064     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5065   }
5066   tmp_addr = ADDSI (tmp_addr, 4);
5067 }
5068 }
5069 if (GESI (FLD (f_operand2), 2)) {
5070 {
5071   SI tmp_tmp;
5072   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5073   {
5074     SI opval = tmp_tmp;
5075     SET_H_GR (((UINT) 2), opval);
5076     written |= (1 << 15);
5077     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5078   }
5079   tmp_addr = ADDSI (tmp_addr, 4);
5080 }
5081 }
5082 if (GESI (FLD (f_operand2), 1)) {
5083 {
5084   SI tmp_tmp;
5085   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5086   {
5087     SI opval = tmp_tmp;
5088     SET_H_GR (((UINT) 1), opval);
5089     written |= (1 << 9);
5090     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5091   }
5092   tmp_addr = ADDSI (tmp_addr, 4);
5093 }
5094 }
5095 if (GESI (FLD (f_operand2), 0)) {
5096 {
5097   SI tmp_tmp;
5098   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5099   {
5100     SI opval = tmp_tmp;
5101     SET_H_GR (((UINT) 0), opval);
5102     written |= (1 << 8);
5103     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5104   }
5105   tmp_addr = ADDSI (tmp_addr, 4);
5106 }
5107 }
5108 }
5109 if (NEBI (tmp_postinc, 0)) {
5110   {
5111     SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
5112     SET_H_GR (FLD (f_operand1), opval);
5113     written |= (1 << 7);
5114     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5115   }
5116 }
5117 {
5118   {
5119     BI opval = 0;
5120     CPU (h_xbit) = opval;
5121     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5122   }
5123   {
5124     BI opval = 0;
5125     SET_H_INSN_PREFIXED_P (opval);
5126     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5127   }
5128 }
5129 }
5130
5131   abuf->written = written;
5132 #undef FLD
5133 }
5134   NEXT (vpc);
5135
5136   CASE (sem, INSN_MOVEM_M_PC) : /* movem [${Rs}${inc}],${Rd} */
5137 {
5138   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5139   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5140 #define FLD(f) abuf->fields.sfmt_movem_m_r.f
5141   int UNUSED written = 0;
5142   IADDR UNUSED pc = abuf->addr;
5143   SEM_BRANCH_INIT
5144   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5145
5146 {
5147   SI tmp_addr;
5148   BI tmp_postinc;
5149   tmp_postinc = FLD (f_memmode);
5150   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5151 {
5152   {
5153     USI opval = GETMEMSI (current_cpu, pc, tmp_addr);
5154     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
5155     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
5156   }
5157   tmp_addr = ADDSI (tmp_addr, 4);
5158 {
5159   SI tmp_tmp;
5160   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5161   {
5162     SI opval = tmp_tmp;
5163     SET_H_GR (((UINT) 14), opval);
5164     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5165   }
5166   tmp_addr = ADDSI (tmp_addr, 4);
5167 }
5168 {
5169   SI tmp_tmp;
5170   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5171   {
5172     SI opval = tmp_tmp;
5173     SET_H_GR (((UINT) 13), opval);
5174     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5175   }
5176   tmp_addr = ADDSI (tmp_addr, 4);
5177 }
5178 {
5179   SI tmp_tmp;
5180   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5181   {
5182     SI opval = tmp_tmp;
5183     SET_H_GR (((UINT) 12), opval);
5184     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5185   }
5186   tmp_addr = ADDSI (tmp_addr, 4);
5187 }
5188 {
5189   SI tmp_tmp;
5190   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5191   {
5192     SI opval = tmp_tmp;
5193     SET_H_GR (((UINT) 11), opval);
5194     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5195   }
5196   tmp_addr = ADDSI (tmp_addr, 4);
5197 }
5198 {
5199   SI tmp_tmp;
5200   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5201   {
5202     SI opval = tmp_tmp;
5203     SET_H_GR (((UINT) 10), opval);
5204     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5205   }
5206   tmp_addr = ADDSI (tmp_addr, 4);
5207 }
5208 {
5209   SI tmp_tmp;
5210   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5211   {
5212     SI opval = tmp_tmp;
5213     SET_H_GR (((UINT) 9), opval);
5214     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5215   }
5216   tmp_addr = ADDSI (tmp_addr, 4);
5217 }
5218 {
5219   SI tmp_tmp;
5220   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5221   {
5222     SI opval = tmp_tmp;
5223     SET_H_GR (((UINT) 8), opval);
5224     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5225   }
5226   tmp_addr = ADDSI (tmp_addr, 4);
5227 }
5228 {
5229   SI tmp_tmp;
5230   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5231   {
5232     SI opval = tmp_tmp;
5233     SET_H_GR (((UINT) 7), opval);
5234     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5235   }
5236   tmp_addr = ADDSI (tmp_addr, 4);
5237 }
5238 {
5239   SI tmp_tmp;
5240   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5241   {
5242     SI opval = tmp_tmp;
5243     SET_H_GR (((UINT) 6), opval);
5244     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5245   }
5246   tmp_addr = ADDSI (tmp_addr, 4);
5247 }
5248 {
5249   SI tmp_tmp;
5250   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5251   {
5252     SI opval = tmp_tmp;
5253     SET_H_GR (((UINT) 5), opval);
5254     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5255   }
5256   tmp_addr = ADDSI (tmp_addr, 4);
5257 }
5258 {
5259   SI tmp_tmp;
5260   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5261   {
5262     SI opval = tmp_tmp;
5263     SET_H_GR (((UINT) 4), opval);
5264     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5265   }
5266   tmp_addr = ADDSI (tmp_addr, 4);
5267 }
5268 {
5269   SI tmp_tmp;
5270   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5271   {
5272     SI opval = tmp_tmp;
5273     SET_H_GR (((UINT) 3), opval);
5274     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5275   }
5276   tmp_addr = ADDSI (tmp_addr, 4);
5277 }
5278 {
5279   SI tmp_tmp;
5280   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5281   {
5282     SI opval = tmp_tmp;
5283     SET_H_GR (((UINT) 2), opval);
5284     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5285   }
5286   tmp_addr = ADDSI (tmp_addr, 4);
5287 }
5288 {
5289   SI tmp_tmp;
5290   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5291   {
5292     SI opval = tmp_tmp;
5293     SET_H_GR (((UINT) 1), opval);
5294     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5295   }
5296   tmp_addr = ADDSI (tmp_addr, 4);
5297 }
5298 {
5299   SI tmp_tmp;
5300   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5301   {
5302     SI opval = tmp_tmp;
5303     SET_H_GR (((UINT) 0), opval);
5304     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5305   }
5306   tmp_addr = ADDSI (tmp_addr, 4);
5307 }
5308 }
5309 if (NEBI (tmp_postinc, 0)) {
5310   {
5311     SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
5312     SET_H_GR (FLD (f_operand1), opval);
5313     written |= (1 << 5);
5314     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5315   }
5316 }
5317 {
5318   {
5319     BI opval = 0;
5320     CPU (h_xbit) = opval;
5321     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5322   }
5323   {
5324     BI opval = 0;
5325     SET_H_INSN_PREFIXED_P (opval);
5326     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5327   }
5328 }
5329 }
5330
5331   abuf->written = written;
5332   SEM_BRANCH_FINI (vpc);
5333 #undef FLD
5334 }
5335   NEXT (vpc);
5336
5337   CASE (sem, INSN_ADD_B_R) : /* add.b $Rs,$Rd */
5338 {
5339   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5340   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5341 #define FLD(f) abuf->fields.sfmt_add_b_r.f
5342   int UNUSED written = 0;
5343   IADDR UNUSED pc = abuf->addr;
5344   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5345
5346 {
5347   QI tmp_tmpopd;
5348   QI tmp_tmpops;
5349   BI tmp_carry;
5350   QI tmp_newval;
5351   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5352   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5353   tmp_carry = CPU (h_cbit);
5354   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5355 {
5356   SI tmp_oldregval;
5357   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5358   {
5359     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5360     SET_H_GR (FLD (f_operand2), opval);
5361     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5362   }
5363 }
5364 {
5365   {
5366     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5367     CPU (h_cbit) = opval;
5368     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5369   }
5370   {
5371     BI opval = LTQI (tmp_newval, 0);
5372     CPU (h_nbit) = opval;
5373     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5374   }
5375   {
5376     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5377     CPU (h_zbit) = opval;
5378     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5379   }
5380   {
5381     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5382     CPU (h_vbit) = opval;
5383     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5384   }
5385 {
5386   {
5387     BI opval = 0;
5388     CPU (h_xbit) = opval;
5389     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5390   }
5391   {
5392     BI opval = 0;
5393     SET_H_INSN_PREFIXED_P (opval);
5394     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5395   }
5396 }
5397 }
5398 }
5399
5400 #undef FLD
5401 }
5402   NEXT (vpc);
5403
5404   CASE (sem, INSN_ADD_W_R) : /* add.w $Rs,$Rd */
5405 {
5406   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5407   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5408 #define FLD(f) abuf->fields.sfmt_add_b_r.f
5409   int UNUSED written = 0;
5410   IADDR UNUSED pc = abuf->addr;
5411   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5412
5413 {
5414   HI tmp_tmpopd;
5415   HI tmp_tmpops;
5416   BI tmp_carry;
5417   HI tmp_newval;
5418   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5419   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5420   tmp_carry = CPU (h_cbit);
5421   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5422 {
5423   SI tmp_oldregval;
5424   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5425   {
5426     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5427     SET_H_GR (FLD (f_operand2), opval);
5428     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5429   }
5430 }
5431 {
5432   {
5433     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5434     CPU (h_cbit) = opval;
5435     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5436   }
5437   {
5438     BI opval = LTHI (tmp_newval, 0);
5439     CPU (h_nbit) = opval;
5440     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5441   }
5442   {
5443     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5444     CPU (h_zbit) = opval;
5445     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5446   }
5447   {
5448     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5449     CPU (h_vbit) = opval;
5450     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5451   }
5452 {
5453   {
5454     BI opval = 0;
5455     CPU (h_xbit) = opval;
5456     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5457   }
5458   {
5459     BI opval = 0;
5460     SET_H_INSN_PREFIXED_P (opval);
5461     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5462   }
5463 }
5464 }
5465 }
5466
5467 #undef FLD
5468 }
5469   NEXT (vpc);
5470
5471   CASE (sem, INSN_ADD_D_R) : /* add.d $Rs,$Rd */
5472 {
5473   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5474   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5475 #define FLD(f) abuf->fields.sfmt_add_b_r.f
5476   int UNUSED written = 0;
5477   IADDR UNUSED pc = abuf->addr;
5478   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5479
5480 {
5481   SI tmp_tmpopd;
5482   SI tmp_tmpops;
5483   BI tmp_carry;
5484   SI tmp_newval;
5485   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5486   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5487   tmp_carry = CPU (h_cbit);
5488   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5489   {
5490     SI opval = tmp_newval;
5491     SET_H_GR (FLD (f_operand2), opval);
5492     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5493   }
5494 {
5495   {
5496     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5497     CPU (h_cbit) = opval;
5498     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5499   }
5500   {
5501     BI opval = LTSI (tmp_newval, 0);
5502     CPU (h_nbit) = opval;
5503     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5504   }
5505   {
5506     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5507     CPU (h_zbit) = opval;
5508     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5509   }
5510   {
5511     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5512     CPU (h_vbit) = opval;
5513     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5514   }
5515 {
5516   {
5517     BI opval = 0;
5518     CPU (h_xbit) = opval;
5519     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5520   }
5521   {
5522     BI opval = 0;
5523     SET_H_INSN_PREFIXED_P (opval);
5524     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5525   }
5526 }
5527 }
5528 }
5529
5530 #undef FLD
5531 }
5532   NEXT (vpc);
5533
5534   CASE (sem, INSN_ADD_M_B_M) : /* add-m.b [${Rs}${inc}],${Rd} */
5535 {
5536   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5537   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5538 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5539   int UNUSED written = 0;
5540   IADDR UNUSED pc = abuf->addr;
5541   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5542
5543 {
5544   QI tmp_tmpopd;
5545   QI tmp_tmpops;
5546   BI tmp_carry;
5547   QI tmp_newval;
5548   tmp_tmpops = ({   SI tmp_addr;
5549   QI tmp_tmp_mem;
5550   BI tmp_postinc;
5551   tmp_postinc = FLD (f_memmode);
5552 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5553 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
5554 ; if (NEBI (tmp_postinc, 0)) {
5555 {
5556 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5557   tmp_addr = ADDSI (tmp_addr, 1);
5558 }
5559   {
5560     SI opval = tmp_addr;
5561     SET_H_GR (FLD (f_operand1), opval);
5562     written |= (1 << 12);
5563     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5564   }
5565 }
5566 }
5567 ; tmp_tmp_mem; });
5568   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5569   tmp_carry = CPU (h_cbit);
5570   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5571 {
5572   SI tmp_oldregval;
5573   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5574   {
5575     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5576     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5577     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5578   }
5579 }
5580 {
5581   {
5582     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5583     CPU (h_cbit) = opval;
5584     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5585   }
5586   {
5587     BI opval = LTQI (tmp_newval, 0);
5588     CPU (h_nbit) = opval;
5589     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5590   }
5591   {
5592     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5593     CPU (h_zbit) = opval;
5594     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5595   }
5596   {
5597     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5598     CPU (h_vbit) = opval;
5599     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5600   }
5601 {
5602   {
5603     BI opval = 0;
5604     CPU (h_xbit) = opval;
5605     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5606   }
5607   {
5608     BI opval = 0;
5609     SET_H_INSN_PREFIXED_P (opval);
5610     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5611   }
5612 }
5613 }
5614 }
5615
5616   abuf->written = written;
5617 #undef FLD
5618 }
5619   NEXT (vpc);
5620
5621   CASE (sem, INSN_ADD_M_W_M) : /* add-m.w [${Rs}${inc}],${Rd} */
5622 {
5623   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5624   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5625 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5626   int UNUSED written = 0;
5627   IADDR UNUSED pc = abuf->addr;
5628   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5629
5630 {
5631   HI tmp_tmpopd;
5632   HI tmp_tmpops;
5633   BI tmp_carry;
5634   HI tmp_newval;
5635   tmp_tmpops = ({   SI tmp_addr;
5636   HI tmp_tmp_mem;
5637   BI tmp_postinc;
5638   tmp_postinc = FLD (f_memmode);
5639 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5640 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
5641 ; if (NEBI (tmp_postinc, 0)) {
5642 {
5643 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5644   tmp_addr = ADDSI (tmp_addr, 2);
5645 }
5646   {
5647     SI opval = tmp_addr;
5648     SET_H_GR (FLD (f_operand1), opval);
5649     written |= (1 << 12);
5650     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5651   }
5652 }
5653 }
5654 ; tmp_tmp_mem; });
5655   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5656   tmp_carry = CPU (h_cbit);
5657   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5658 {
5659   SI tmp_oldregval;
5660   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5661   {
5662     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5663     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5664     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5665   }
5666 }
5667 {
5668   {
5669     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5670     CPU (h_cbit) = opval;
5671     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5672   }
5673   {
5674     BI opval = LTHI (tmp_newval, 0);
5675     CPU (h_nbit) = opval;
5676     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5677   }
5678   {
5679     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5680     CPU (h_zbit) = opval;
5681     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5682   }
5683   {
5684     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5685     CPU (h_vbit) = opval;
5686     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5687   }
5688 {
5689   {
5690     BI opval = 0;
5691     CPU (h_xbit) = opval;
5692     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5693   }
5694   {
5695     BI opval = 0;
5696     SET_H_INSN_PREFIXED_P (opval);
5697     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5698   }
5699 }
5700 }
5701 }
5702
5703   abuf->written = written;
5704 #undef FLD
5705 }
5706   NEXT (vpc);
5707
5708   CASE (sem, INSN_ADD_M_D_M) : /* add-m.d [${Rs}${inc}],${Rd} */
5709 {
5710   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5711   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5712 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5713   int UNUSED written = 0;
5714   IADDR UNUSED pc = abuf->addr;
5715   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5716
5717 {
5718   SI tmp_tmpopd;
5719   SI tmp_tmpops;
5720   BI tmp_carry;
5721   SI tmp_newval;
5722   tmp_tmpops = ({   SI tmp_addr;
5723   SI tmp_tmp_mem;
5724   BI tmp_postinc;
5725   tmp_postinc = FLD (f_memmode);
5726 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5727 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
5728 ; if (NEBI (tmp_postinc, 0)) {
5729 {
5730 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5731   tmp_addr = ADDSI (tmp_addr, 4);
5732 }
5733   {
5734     SI opval = tmp_addr;
5735     SET_H_GR (FLD (f_operand1), opval);
5736     written |= (1 << 11);
5737     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5738   }
5739 }
5740 }
5741 ; tmp_tmp_mem; });
5742   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5743   tmp_carry = CPU (h_cbit);
5744   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5745   {
5746     SI opval = tmp_newval;
5747     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5748     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5749   }
5750 {
5751   {
5752     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5753     CPU (h_cbit) = opval;
5754     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5755   }
5756   {
5757     BI opval = LTSI (tmp_newval, 0);
5758     CPU (h_nbit) = opval;
5759     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5760   }
5761   {
5762     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5763     CPU (h_zbit) = opval;
5764     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5765   }
5766   {
5767     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5768     CPU (h_vbit) = opval;
5769     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5770   }
5771 {
5772   {
5773     BI opval = 0;
5774     CPU (h_xbit) = opval;
5775     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5776   }
5777   {
5778     BI opval = 0;
5779     SET_H_INSN_PREFIXED_P (opval);
5780     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5781   }
5782 }
5783 }
5784 }
5785
5786   abuf->written = written;
5787 #undef FLD
5788 }
5789   NEXT (vpc);
5790
5791   CASE (sem, INSN_ADDCBR) : /* add.b ${sconst8}],${Rd} */
5792 {
5793   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5794   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5795 #define FLD(f) abuf->fields.sfmt_addcbr.f
5796   int UNUSED written = 0;
5797   IADDR UNUSED pc = abuf->addr;
5798   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
5799
5800 {
5801   QI tmp_tmpopd;
5802   QI tmp_tmpops;
5803   BI tmp_carry;
5804   QI tmp_newval;
5805   tmp_tmpops = FLD (f_indir_pc__byte);
5806   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5807   tmp_carry = CPU (h_cbit);
5808   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5809 {
5810   SI tmp_oldregval;
5811   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5812   {
5813     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5814     SET_H_GR (FLD (f_operand2), opval);
5815     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5816   }
5817 }
5818 {
5819   {
5820     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5821     CPU (h_cbit) = opval;
5822     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5823   }
5824   {
5825     BI opval = LTQI (tmp_newval, 0);
5826     CPU (h_nbit) = opval;
5827     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5828   }
5829   {
5830     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5831     CPU (h_zbit) = opval;
5832     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5833   }
5834   {
5835     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5836     CPU (h_vbit) = opval;
5837     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5838   }
5839 {
5840   {
5841     BI opval = 0;
5842     CPU (h_xbit) = opval;
5843     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5844   }
5845   {
5846     BI opval = 0;
5847     SET_H_INSN_PREFIXED_P (opval);
5848     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5849   }
5850 }
5851 }
5852 }
5853
5854 #undef FLD
5855 }
5856   NEXT (vpc);
5857
5858   CASE (sem, INSN_ADDCWR) : /* add.w ${sconst16}],${Rd} */
5859 {
5860   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5861   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5862 #define FLD(f) abuf->fields.sfmt_addcwr.f
5863   int UNUSED written = 0;
5864   IADDR UNUSED pc = abuf->addr;
5865   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
5866
5867 {
5868   HI tmp_tmpopd;
5869   HI tmp_tmpops;
5870   BI tmp_carry;
5871   HI tmp_newval;
5872   tmp_tmpops = FLD (f_indir_pc__word);
5873   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5874   tmp_carry = CPU (h_cbit);
5875   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5876 {
5877   SI tmp_oldregval;
5878   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5879   {
5880     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5881     SET_H_GR (FLD (f_operand2), opval);
5882     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5883   }
5884 }
5885 {
5886   {
5887     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5888     CPU (h_cbit) = opval;
5889     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5890   }
5891   {
5892     BI opval = LTHI (tmp_newval, 0);
5893     CPU (h_nbit) = opval;
5894     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5895   }
5896   {
5897     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5898     CPU (h_zbit) = opval;
5899     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5900   }
5901   {
5902     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5903     CPU (h_vbit) = opval;
5904     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5905   }
5906 {
5907   {
5908     BI opval = 0;
5909     CPU (h_xbit) = opval;
5910     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5911   }
5912   {
5913     BI opval = 0;
5914     SET_H_INSN_PREFIXED_P (opval);
5915     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5916   }
5917 }
5918 }
5919 }
5920
5921 #undef FLD
5922 }
5923   NEXT (vpc);
5924
5925   CASE (sem, INSN_ADDCDR) : /* add.d ${const32}],${Rd} */
5926 {
5927   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5928   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5929 #define FLD(f) abuf->fields.sfmt_addcdr.f
5930   int UNUSED written = 0;
5931   IADDR UNUSED pc = abuf->addr;
5932   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
5933
5934 {
5935   SI tmp_tmpopd;
5936   SI tmp_tmpops;
5937   BI tmp_carry;
5938   SI tmp_newval;
5939   tmp_tmpops = FLD (f_indir_pc__dword);
5940   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5941   tmp_carry = CPU (h_cbit);
5942   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5943   {
5944     SI opval = tmp_newval;
5945     SET_H_GR (FLD (f_operand2), opval);
5946     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5947   }
5948 {
5949   {
5950     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5951     CPU (h_cbit) = opval;
5952     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5953   }
5954   {
5955     BI opval = LTSI (tmp_newval, 0);
5956     CPU (h_nbit) = opval;
5957     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5958   }
5959   {
5960     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5961     CPU (h_zbit) = opval;
5962     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5963   }
5964   {
5965     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5966     CPU (h_vbit) = opval;
5967     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5968   }
5969 {
5970   {
5971     BI opval = 0;
5972     CPU (h_xbit) = opval;
5973     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5974   }
5975   {
5976     BI opval = 0;
5977     SET_H_INSN_PREFIXED_P (opval);
5978     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5979   }
5980 }
5981 }
5982 }
5983
5984 #undef FLD
5985 }
5986   NEXT (vpc);
5987
5988   CASE (sem, INSN_ADDCPC) : /* add.d ${sconst32},PC */
5989 {
5990   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5991   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5992 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
5993   int UNUSED written = 0;
5994   IADDR UNUSED pc = abuf->addr;
5995   SEM_BRANCH_INIT
5996   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
5997
5998 {
5999   SI tmp_newpc;
6000   SI tmp_oldpc;
6001   SI tmp_offs;
6002   tmp_offs = FLD (f_indir_pc__dword);
6003   tmp_oldpc = ADDSI (pc, 6);
6004   tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
6005   {
6006     USI opval = tmp_newpc;
6007     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
6008     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
6009   }
6010 {
6011   {
6012     BI opval = ORIF (ANDIF (LTSI (tmp_offs, 0), LTSI (tmp_oldpc, 0)), ORIF (ANDIF (LTSI (tmp_oldpc, 0), GESI (tmp_newpc, 0)), ANDIF (LTSI (tmp_offs, 0), GESI (tmp_newpc, 0))));
6013     CPU (h_cbit) = opval;
6014     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6015   }
6016   {
6017     BI opval = LTSI (tmp_newpc, 0);
6018     CPU (h_nbit) = opval;
6019     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6020   }
6021   {
6022     BI opval = ANDIF (EQSI (tmp_newpc, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6023     CPU (h_zbit) = opval;
6024     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6025   }
6026   {
6027     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_offs, 0), LTSI (tmp_oldpc, 0)), GESI (tmp_newpc, 0)), ANDIF (ANDIF (GESI (tmp_offs, 0), GESI (tmp_oldpc, 0)), LTSI (tmp_newpc, 0)));
6028     CPU (h_vbit) = opval;
6029     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6030   }
6031 {
6032   {
6033     BI opval = 0;
6034     CPU (h_xbit) = opval;
6035     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6036   }
6037   {
6038     BI opval = 0;
6039     SET_H_INSN_PREFIXED_P (opval);
6040     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6041   }
6042 }
6043 }
6044 }
6045
6046   SEM_BRANCH_FINI (vpc);
6047 #undef FLD
6048 }
6049   NEXT (vpc);
6050
6051   CASE (sem, INSN_ADDS_B_R) : /* adds.b $Rs,$Rd */
6052 {
6053   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6054   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6055 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6056   int UNUSED written = 0;
6057   IADDR UNUSED pc = abuf->addr;
6058   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6059
6060 {
6061   SI tmp_tmpopd;
6062   SI tmp_tmpops;
6063   BI tmp_carry;
6064   SI tmp_newval;
6065   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6066   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6067   tmp_carry = CPU (h_cbit);
6068   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6069   {
6070     SI opval = tmp_newval;
6071     SET_H_GR (FLD (f_operand2), opval);
6072     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6073   }
6074 {
6075   {
6076     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6077     CPU (h_cbit) = opval;
6078     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6079   }
6080   {
6081     BI opval = LTSI (tmp_newval, 0);
6082     CPU (h_nbit) = opval;
6083     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6084   }
6085   {
6086     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6087     CPU (h_zbit) = opval;
6088     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6089   }
6090   {
6091     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6092     CPU (h_vbit) = opval;
6093     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6094   }
6095 {
6096   {
6097     BI opval = 0;
6098     CPU (h_xbit) = opval;
6099     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6100   }
6101   {
6102     BI opval = 0;
6103     SET_H_INSN_PREFIXED_P (opval);
6104     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6105   }
6106 }
6107 }
6108 }
6109
6110 #undef FLD
6111 }
6112   NEXT (vpc);
6113
6114   CASE (sem, INSN_ADDS_W_R) : /* adds.w $Rs,$Rd */
6115 {
6116   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6117   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6118 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6119   int UNUSED written = 0;
6120   IADDR UNUSED pc = abuf->addr;
6121   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6122
6123 {
6124   SI tmp_tmpopd;
6125   SI tmp_tmpops;
6126   BI tmp_carry;
6127   SI tmp_newval;
6128   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6129   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6130   tmp_carry = CPU (h_cbit);
6131   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6132   {
6133     SI opval = tmp_newval;
6134     SET_H_GR (FLD (f_operand2), opval);
6135     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6136   }
6137 {
6138   {
6139     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6140     CPU (h_cbit) = opval;
6141     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6142   }
6143   {
6144     BI opval = LTSI (tmp_newval, 0);
6145     CPU (h_nbit) = opval;
6146     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6147   }
6148   {
6149     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6150     CPU (h_zbit) = opval;
6151     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6152   }
6153   {
6154     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6155     CPU (h_vbit) = opval;
6156     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6157   }
6158 {
6159   {
6160     BI opval = 0;
6161     CPU (h_xbit) = opval;
6162     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6163   }
6164   {
6165     BI opval = 0;
6166     SET_H_INSN_PREFIXED_P (opval);
6167     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6168   }
6169 }
6170 }
6171 }
6172
6173 #undef FLD
6174 }
6175   NEXT (vpc);
6176
6177   CASE (sem, INSN_ADDS_M_B_M) : /* adds-m.b [${Rs}${inc}],$Rd */
6178 {
6179   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6180   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6181 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6182   int UNUSED written = 0;
6183   IADDR UNUSED pc = abuf->addr;
6184   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6185
6186 {
6187   SI tmp_tmpopd;
6188   SI tmp_tmpops;
6189   BI tmp_carry;
6190   SI tmp_newval;
6191   tmp_tmpops = EXTQISI (({   SI tmp_addr;
6192   QI tmp_tmp_mem;
6193   BI tmp_postinc;
6194   tmp_postinc = FLD (f_memmode);
6195 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6196 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6197 ; if (NEBI (tmp_postinc, 0)) {
6198 {
6199 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6200   tmp_addr = ADDSI (tmp_addr, 1);
6201 }
6202   {
6203     SI opval = tmp_addr;
6204     SET_H_GR (FLD (f_operand1), opval);
6205     written |= (1 << 11);
6206     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6207   }
6208 }
6209 }
6210 ; tmp_tmp_mem; }));
6211   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6212   tmp_carry = CPU (h_cbit);
6213   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6214   {
6215     SI opval = tmp_newval;
6216     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6217     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6218   }
6219 {
6220   {
6221     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6222     CPU (h_cbit) = opval;
6223     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6224   }
6225   {
6226     BI opval = LTSI (tmp_newval, 0);
6227     CPU (h_nbit) = opval;
6228     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6229   }
6230   {
6231     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6232     CPU (h_zbit) = opval;
6233     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6234   }
6235   {
6236     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6237     CPU (h_vbit) = opval;
6238     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6239   }
6240 {
6241   {
6242     BI opval = 0;
6243     CPU (h_xbit) = opval;
6244     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6245   }
6246   {
6247     BI opval = 0;
6248     SET_H_INSN_PREFIXED_P (opval);
6249     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6250   }
6251 }
6252 }
6253 }
6254
6255   abuf->written = written;
6256 #undef FLD
6257 }
6258   NEXT (vpc);
6259
6260   CASE (sem, INSN_ADDS_M_W_M) : /* adds-m.w [${Rs}${inc}],$Rd */
6261 {
6262   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6263   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6264 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6265   int UNUSED written = 0;
6266   IADDR UNUSED pc = abuf->addr;
6267   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6268
6269 {
6270   SI tmp_tmpopd;
6271   SI tmp_tmpops;
6272   BI tmp_carry;
6273   SI tmp_newval;
6274   tmp_tmpops = EXTHISI (({   SI tmp_addr;
6275   HI tmp_tmp_mem;
6276   BI tmp_postinc;
6277   tmp_postinc = FLD (f_memmode);
6278 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6279 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6280 ; if (NEBI (tmp_postinc, 0)) {
6281 {
6282 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6283   tmp_addr = ADDSI (tmp_addr, 2);
6284 }
6285   {
6286     SI opval = tmp_addr;
6287     SET_H_GR (FLD (f_operand1), opval);
6288     written |= (1 << 11);
6289     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6290   }
6291 }
6292 }
6293 ; tmp_tmp_mem; }));
6294   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6295   tmp_carry = CPU (h_cbit);
6296   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6297   {
6298     SI opval = tmp_newval;
6299     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6300     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6301   }
6302 {
6303   {
6304     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6305     CPU (h_cbit) = opval;
6306     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6307   }
6308   {
6309     BI opval = LTSI (tmp_newval, 0);
6310     CPU (h_nbit) = opval;
6311     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6312   }
6313   {
6314     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6315     CPU (h_zbit) = opval;
6316     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6317   }
6318   {
6319     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6320     CPU (h_vbit) = opval;
6321     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6322   }
6323 {
6324   {
6325     BI opval = 0;
6326     CPU (h_xbit) = opval;
6327     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6328   }
6329   {
6330     BI opval = 0;
6331     SET_H_INSN_PREFIXED_P (opval);
6332     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6333   }
6334 }
6335 }
6336 }
6337
6338   abuf->written = written;
6339 #undef FLD
6340 }
6341   NEXT (vpc);
6342
6343   CASE (sem, INSN_ADDSCBR) : /* [${Rs}${inc}],$Rd */
6344 {
6345   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6346   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6347 #define FLD(f) abuf->fields.sfmt_addcbr.f
6348   int UNUSED written = 0;
6349   IADDR UNUSED pc = abuf->addr;
6350   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6351
6352 {
6353   SI tmp_tmpopd;
6354   SI tmp_tmpops;
6355   BI tmp_carry;
6356   SI tmp_newval;
6357   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6358   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6359   tmp_carry = CPU (h_cbit);
6360   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6361   {
6362     SI opval = tmp_newval;
6363     SET_H_GR (FLD (f_operand2), opval);
6364     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6365   }
6366 {
6367   {
6368     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6369     CPU (h_cbit) = opval;
6370     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6371   }
6372   {
6373     BI opval = LTSI (tmp_newval, 0);
6374     CPU (h_nbit) = opval;
6375     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6376   }
6377   {
6378     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6379     CPU (h_zbit) = opval;
6380     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6381   }
6382   {
6383     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6384     CPU (h_vbit) = opval;
6385     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6386   }
6387 {
6388   {
6389     BI opval = 0;
6390     CPU (h_xbit) = opval;
6391     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6392   }
6393   {
6394     BI opval = 0;
6395     SET_H_INSN_PREFIXED_P (opval);
6396     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6397   }
6398 }
6399 }
6400 }
6401
6402 #undef FLD
6403 }
6404   NEXT (vpc);
6405
6406   CASE (sem, INSN_ADDSCWR) : /* [${Rs}${inc}],$Rd */
6407 {
6408   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6409   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6410 #define FLD(f) abuf->fields.sfmt_addcwr.f
6411   int UNUSED written = 0;
6412   IADDR UNUSED pc = abuf->addr;
6413   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6414
6415 {
6416   SI tmp_tmpopd;
6417   SI tmp_tmpops;
6418   BI tmp_carry;
6419   SI tmp_newval;
6420   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6421   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6422   tmp_carry = CPU (h_cbit);
6423   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6424   {
6425     SI opval = tmp_newval;
6426     SET_H_GR (FLD (f_operand2), opval);
6427     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6428   }
6429 {
6430   {
6431     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6432     CPU (h_cbit) = opval;
6433     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6434   }
6435   {
6436     BI opval = LTSI (tmp_newval, 0);
6437     CPU (h_nbit) = opval;
6438     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6439   }
6440   {
6441     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6442     CPU (h_zbit) = opval;
6443     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6444   }
6445   {
6446     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6447     CPU (h_vbit) = opval;
6448     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6449   }
6450 {
6451   {
6452     BI opval = 0;
6453     CPU (h_xbit) = opval;
6454     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6455   }
6456   {
6457     BI opval = 0;
6458     SET_H_INSN_PREFIXED_P (opval);
6459     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6460   }
6461 }
6462 }
6463 }
6464
6465 #undef FLD
6466 }
6467   NEXT (vpc);
6468
6469   CASE (sem, INSN_ADDSPCPC) : /* adds.w [PC],PC */
6470 {
6471   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6472   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6473 #define FLD(f) abuf->fields.fmt_empty.f
6474   int UNUSED written = 0;
6475   IADDR UNUSED pc = abuf->addr;
6476   SEM_BRANCH_INIT
6477   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6478
6479 {
6480   SI tmp_newpc;
6481   SI tmp_oldpc;
6482   HI tmp_offs;
6483 if (NOTBI (GET_H_INSN_PREFIXED_P ())) {
6484 cgen_rtx_error (current_cpu, "Unexpected adds.w [PC],PC without prefix");
6485 }
6486   tmp_offs = GETMEMHI (current_cpu, pc, CPU (h_prefixreg_pre_v32));
6487   tmp_oldpc = ADDSI (pc, 2);
6488   tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
6489   {
6490     USI opval = tmp_newpc;
6491     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
6492     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
6493   }
6494 {
6495   {
6496     BI opval = ORIF (ANDIF (LTSI (EXTHISI (tmp_offs), 0), LTSI (tmp_oldpc, 0)), ORIF (ANDIF (LTSI (tmp_oldpc, 0), GESI (tmp_newpc, 0)), ANDIF (LTSI (EXTHISI (tmp_offs), 0), GESI (tmp_newpc, 0))));
6497     CPU (h_cbit) = opval;
6498     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6499   }
6500   {
6501     BI opval = LTSI (tmp_newpc, 0);
6502     CPU (h_nbit) = opval;
6503     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6504   }
6505   {
6506     BI opval = ANDIF (EQSI (tmp_newpc, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6507     CPU (h_zbit) = opval;
6508     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6509   }
6510   {
6511     BI opval = ORIF (ANDIF (ANDIF (LTSI (EXTHISI (tmp_offs), 0), LTSI (tmp_oldpc, 0)), GESI (tmp_newpc, 0)), ANDIF (ANDIF (GESI (EXTHISI (tmp_offs), 0), GESI (tmp_oldpc, 0)), LTSI (tmp_newpc, 0)));
6512     CPU (h_vbit) = opval;
6513     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6514   }
6515 {
6516   {
6517     BI opval = 0;
6518     CPU (h_xbit) = opval;
6519     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6520   }
6521   {
6522     BI opval = 0;
6523     SET_H_INSN_PREFIXED_P (opval);
6524     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6525   }
6526 }
6527 }
6528 }
6529
6530   SEM_BRANCH_FINI (vpc);
6531 #undef FLD
6532 }
6533   NEXT (vpc);
6534
6535   CASE (sem, INSN_ADDU_B_R) : /* addu.b $Rs,$Rd */
6536 {
6537   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6538   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6539 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6540   int UNUSED written = 0;
6541   IADDR UNUSED pc = abuf->addr;
6542   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6543
6544 {
6545   SI tmp_tmpopd;
6546   SI tmp_tmpops;
6547   BI tmp_carry;
6548   SI tmp_newval;
6549   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6550   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6551   tmp_carry = CPU (h_cbit);
6552   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6553   {
6554     SI opval = tmp_newval;
6555     SET_H_GR (FLD (f_operand2), opval);
6556     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6557   }
6558 {
6559   {
6560     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6561     CPU (h_cbit) = opval;
6562     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6563   }
6564   {
6565     BI opval = LTSI (tmp_newval, 0);
6566     CPU (h_nbit) = opval;
6567     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6568   }
6569   {
6570     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6571     CPU (h_zbit) = opval;
6572     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6573   }
6574   {
6575     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6576     CPU (h_vbit) = opval;
6577     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6578   }
6579 {
6580   {
6581     BI opval = 0;
6582     CPU (h_xbit) = opval;
6583     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6584   }
6585   {
6586     BI opval = 0;
6587     SET_H_INSN_PREFIXED_P (opval);
6588     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6589   }
6590 }
6591 }
6592 }
6593
6594 #undef FLD
6595 }
6596   NEXT (vpc);
6597
6598   CASE (sem, INSN_ADDU_W_R) : /* addu.w $Rs,$Rd */
6599 {
6600   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6601   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6602 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6603   int UNUSED written = 0;
6604   IADDR UNUSED pc = abuf->addr;
6605   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6606
6607 {
6608   SI tmp_tmpopd;
6609   SI tmp_tmpops;
6610   BI tmp_carry;
6611   SI tmp_newval;
6612   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6613   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6614   tmp_carry = CPU (h_cbit);
6615   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6616   {
6617     SI opval = tmp_newval;
6618     SET_H_GR (FLD (f_operand2), opval);
6619     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6620   }
6621 {
6622   {
6623     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6624     CPU (h_cbit) = opval;
6625     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6626   }
6627   {
6628     BI opval = LTSI (tmp_newval, 0);
6629     CPU (h_nbit) = opval;
6630     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6631   }
6632   {
6633     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6634     CPU (h_zbit) = opval;
6635     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6636   }
6637   {
6638     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6639     CPU (h_vbit) = opval;
6640     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6641   }
6642 {
6643   {
6644     BI opval = 0;
6645     CPU (h_xbit) = opval;
6646     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6647   }
6648   {
6649     BI opval = 0;
6650     SET_H_INSN_PREFIXED_P (opval);
6651     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6652   }
6653 }
6654 }
6655 }
6656
6657 #undef FLD
6658 }
6659   NEXT (vpc);
6660
6661   CASE (sem, INSN_ADDU_M_B_M) : /* addu-m.b [${Rs}${inc}],$Rd */
6662 {
6663   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6664   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6665 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6666   int UNUSED written = 0;
6667   IADDR UNUSED pc = abuf->addr;
6668   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6669
6670 {
6671   SI tmp_tmpopd;
6672   SI tmp_tmpops;
6673   BI tmp_carry;
6674   SI tmp_newval;
6675   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
6676   QI tmp_tmp_mem;
6677   BI tmp_postinc;
6678   tmp_postinc = FLD (f_memmode);
6679 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6680 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6681 ; if (NEBI (tmp_postinc, 0)) {
6682 {
6683 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6684   tmp_addr = ADDSI (tmp_addr, 1);
6685 }
6686   {
6687     SI opval = tmp_addr;
6688     SET_H_GR (FLD (f_operand1), opval);
6689     written |= (1 << 11);
6690     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6691   }
6692 }
6693 }
6694 ; tmp_tmp_mem; }));
6695   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6696   tmp_carry = CPU (h_cbit);
6697   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6698   {
6699     SI opval = tmp_newval;
6700     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6701     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6702   }
6703 {
6704   {
6705     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6706     CPU (h_cbit) = opval;
6707     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6708   }
6709   {
6710     BI opval = LTSI (tmp_newval, 0);
6711     CPU (h_nbit) = opval;
6712     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6713   }
6714   {
6715     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6716     CPU (h_zbit) = opval;
6717     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6718   }
6719   {
6720     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6721     CPU (h_vbit) = opval;
6722     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6723   }
6724 {
6725   {
6726     BI opval = 0;
6727     CPU (h_xbit) = opval;
6728     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6729   }
6730   {
6731     BI opval = 0;
6732     SET_H_INSN_PREFIXED_P (opval);
6733     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6734   }
6735 }
6736 }
6737 }
6738
6739   abuf->written = written;
6740 #undef FLD
6741 }
6742   NEXT (vpc);
6743
6744   CASE (sem, INSN_ADDU_M_W_M) : /* addu-m.w [${Rs}${inc}],$Rd */
6745 {
6746   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6747   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6748 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6749   int UNUSED written = 0;
6750   IADDR UNUSED pc = abuf->addr;
6751   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6752
6753 {
6754   SI tmp_tmpopd;
6755   SI tmp_tmpops;
6756   BI tmp_carry;
6757   SI tmp_newval;
6758   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
6759   HI tmp_tmp_mem;
6760   BI tmp_postinc;
6761   tmp_postinc = FLD (f_memmode);
6762 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6763 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6764 ; if (NEBI (tmp_postinc, 0)) {
6765 {
6766 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6767   tmp_addr = ADDSI (tmp_addr, 2);
6768 }
6769   {
6770     SI opval = tmp_addr;
6771     SET_H_GR (FLD (f_operand1), opval);
6772     written |= (1 << 11);
6773     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6774   }
6775 }
6776 }
6777 ; tmp_tmp_mem; }));
6778   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6779   tmp_carry = CPU (h_cbit);
6780   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6781   {
6782     SI opval = tmp_newval;
6783     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6784     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6785   }
6786 {
6787   {
6788     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6789     CPU (h_cbit) = opval;
6790     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6791   }
6792   {
6793     BI opval = LTSI (tmp_newval, 0);
6794     CPU (h_nbit) = opval;
6795     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6796   }
6797   {
6798     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6799     CPU (h_zbit) = opval;
6800     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6801   }
6802   {
6803     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6804     CPU (h_vbit) = opval;
6805     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6806   }
6807 {
6808   {
6809     BI opval = 0;
6810     CPU (h_xbit) = opval;
6811     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6812   }
6813   {
6814     BI opval = 0;
6815     SET_H_INSN_PREFIXED_P (opval);
6816     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6817   }
6818 }
6819 }
6820 }
6821
6822   abuf->written = written;
6823 #undef FLD
6824 }
6825   NEXT (vpc);
6826
6827   CASE (sem, INSN_ADDUCBR) : /* [${Rs}${inc}],$Rd */
6828 {
6829   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6830   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6831 #define FLD(f) abuf->fields.sfmt_addcbr.f
6832   int UNUSED written = 0;
6833   IADDR UNUSED pc = abuf->addr;
6834   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6835
6836 {
6837   SI tmp_tmpopd;
6838   SI tmp_tmpops;
6839   BI tmp_carry;
6840   SI tmp_newval;
6841   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6842   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6843   tmp_carry = CPU (h_cbit);
6844   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6845   {
6846     SI opval = tmp_newval;
6847     SET_H_GR (FLD (f_operand2), opval);
6848     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6849   }
6850 {
6851   {
6852     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6853     CPU (h_cbit) = opval;
6854     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6855   }
6856   {
6857     BI opval = LTSI (tmp_newval, 0);
6858     CPU (h_nbit) = opval;
6859     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6860   }
6861   {
6862     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6863     CPU (h_zbit) = opval;
6864     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6865   }
6866   {
6867     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6868     CPU (h_vbit) = opval;
6869     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6870   }
6871 {
6872   {
6873     BI opval = 0;
6874     CPU (h_xbit) = opval;
6875     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6876   }
6877   {
6878     BI opval = 0;
6879     SET_H_INSN_PREFIXED_P (opval);
6880     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6881   }
6882 }
6883 }
6884 }
6885
6886 #undef FLD
6887 }
6888   NEXT (vpc);
6889
6890   CASE (sem, INSN_ADDUCWR) : /* [${Rs}${inc}],$Rd */
6891 {
6892   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6893   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6894 #define FLD(f) abuf->fields.sfmt_addcwr.f
6895   int UNUSED written = 0;
6896   IADDR UNUSED pc = abuf->addr;
6897   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6898
6899 {
6900   SI tmp_tmpopd;
6901   SI tmp_tmpops;
6902   BI tmp_carry;
6903   SI tmp_newval;
6904   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6905   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6906   tmp_carry = CPU (h_cbit);
6907   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6908   {
6909     SI opval = tmp_newval;
6910     SET_H_GR (FLD (f_operand2), opval);
6911     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6912   }
6913 {
6914   {
6915     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6916     CPU (h_cbit) = opval;
6917     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6918   }
6919   {
6920     BI opval = LTSI (tmp_newval, 0);
6921     CPU (h_nbit) = opval;
6922     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6923   }
6924   {
6925     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6926     CPU (h_zbit) = opval;
6927     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6928   }
6929   {
6930     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6931     CPU (h_vbit) = opval;
6932     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6933   }
6934 {
6935   {
6936     BI opval = 0;
6937     CPU (h_xbit) = opval;
6938     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6939   }
6940   {
6941     BI opval = 0;
6942     SET_H_INSN_PREFIXED_P (opval);
6943     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6944   }
6945 }
6946 }
6947 }
6948
6949 #undef FLD
6950 }
6951   NEXT (vpc);
6952
6953   CASE (sem, INSN_SUB_B_R) : /* sub.b $Rs,$Rd */
6954 {
6955   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6956   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6957 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6958   int UNUSED written = 0;
6959   IADDR UNUSED pc = abuf->addr;
6960   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6961
6962 {
6963   QI tmp_tmpopd;
6964   QI tmp_tmpops;
6965   BI tmp_carry;
6966   QI tmp_newval;
6967   tmp_tmpops = GET_H_GR (FLD (f_operand1));
6968   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6969   tmp_carry = CPU (h_cbit);
6970   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6971 {
6972   SI tmp_oldregval;
6973   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
6974   {
6975     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
6976     SET_H_GR (FLD (f_operand2), opval);
6977     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6978   }
6979 }
6980 {
6981   {
6982     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
6983     CPU (h_cbit) = opval;
6984     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6985   }
6986   {
6987     BI opval = LTQI (tmp_newval, 0);
6988     CPU (h_nbit) = opval;
6989     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6990   }
6991   {
6992     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6993     CPU (h_zbit) = opval;
6994     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6995   }
6996   {
6997     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
6998     CPU (h_vbit) = opval;
6999     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7000   }
7001 {
7002   {
7003     BI opval = 0;
7004     CPU (h_xbit) = opval;
7005     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7006   }
7007   {
7008     BI opval = 0;
7009     SET_H_INSN_PREFIXED_P (opval);
7010     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7011   }
7012 }
7013 }
7014 }
7015
7016 #undef FLD
7017 }
7018   NEXT (vpc);
7019
7020   CASE (sem, INSN_SUB_W_R) : /* sub.w $Rs,$Rd */
7021 {
7022   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7023   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7024 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7025   int UNUSED written = 0;
7026   IADDR UNUSED pc = abuf->addr;
7027   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7028
7029 {
7030   HI tmp_tmpopd;
7031   HI tmp_tmpops;
7032   BI tmp_carry;
7033   HI tmp_newval;
7034   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7035   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7036   tmp_carry = CPU (h_cbit);
7037   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7038 {
7039   SI tmp_oldregval;
7040   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
7041   {
7042     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7043     SET_H_GR (FLD (f_operand2), opval);
7044     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7045   }
7046 }
7047 {
7048   {
7049     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7050     CPU (h_cbit) = opval;
7051     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7052   }
7053   {
7054     BI opval = LTHI (tmp_newval, 0);
7055     CPU (h_nbit) = opval;
7056     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7057   }
7058   {
7059     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7060     CPU (h_zbit) = opval;
7061     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7062   }
7063   {
7064     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7065     CPU (h_vbit) = opval;
7066     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7067   }
7068 {
7069   {
7070     BI opval = 0;
7071     CPU (h_xbit) = opval;
7072     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7073   }
7074   {
7075     BI opval = 0;
7076     SET_H_INSN_PREFIXED_P (opval);
7077     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7078   }
7079 }
7080 }
7081 }
7082
7083 #undef FLD
7084 }
7085   NEXT (vpc);
7086
7087   CASE (sem, INSN_SUB_D_R) : /* sub.d $Rs,$Rd */
7088 {
7089   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7090   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7091 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7092   int UNUSED written = 0;
7093   IADDR UNUSED pc = abuf->addr;
7094   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7095
7096 {
7097   SI tmp_tmpopd;
7098   SI tmp_tmpops;
7099   BI tmp_carry;
7100   SI tmp_newval;
7101   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7102   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7103   tmp_carry = CPU (h_cbit);
7104   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7105   {
7106     SI opval = tmp_newval;
7107     SET_H_GR (FLD (f_operand2), opval);
7108     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7109   }
7110 {
7111   {
7112     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7113     CPU (h_cbit) = opval;
7114     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7115   }
7116   {
7117     BI opval = LTSI (tmp_newval, 0);
7118     CPU (h_nbit) = opval;
7119     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7120   }
7121   {
7122     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7123     CPU (h_zbit) = opval;
7124     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7125   }
7126   {
7127     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7128     CPU (h_vbit) = opval;
7129     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7130   }
7131 {
7132   {
7133     BI opval = 0;
7134     CPU (h_xbit) = opval;
7135     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7136   }
7137   {
7138     BI opval = 0;
7139     SET_H_INSN_PREFIXED_P (opval);
7140     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7141   }
7142 }
7143 }
7144 }
7145
7146 #undef FLD
7147 }
7148   NEXT (vpc);
7149
7150   CASE (sem, INSN_SUB_M_B_M) : /* sub-m.b [${Rs}${inc}],${Rd} */
7151 {
7152   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7153   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7154 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7155   int UNUSED written = 0;
7156   IADDR UNUSED pc = abuf->addr;
7157   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7158
7159 {
7160   QI tmp_tmpopd;
7161   QI tmp_tmpops;
7162   BI tmp_carry;
7163   QI tmp_newval;
7164   tmp_tmpops = ({   SI tmp_addr;
7165   QI tmp_tmp_mem;
7166   BI tmp_postinc;
7167   tmp_postinc = FLD (f_memmode);
7168 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7169 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7170 ; if (NEBI (tmp_postinc, 0)) {
7171 {
7172 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7173   tmp_addr = ADDSI (tmp_addr, 1);
7174 }
7175   {
7176     SI opval = tmp_addr;
7177     SET_H_GR (FLD (f_operand1), opval);
7178     written |= (1 << 12);
7179     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7180   }
7181 }
7182 }
7183 ; tmp_tmp_mem; });
7184   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7185   tmp_carry = CPU (h_cbit);
7186   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7187 {
7188   SI tmp_oldregval;
7189   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7190   {
7191     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7192     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7193     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7194   }
7195 }
7196 {
7197   {
7198     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7199     CPU (h_cbit) = opval;
7200     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7201   }
7202   {
7203     BI opval = LTQI (tmp_newval, 0);
7204     CPU (h_nbit) = opval;
7205     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7206   }
7207   {
7208     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7209     CPU (h_zbit) = opval;
7210     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7211   }
7212   {
7213     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7214     CPU (h_vbit) = opval;
7215     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7216   }
7217 {
7218   {
7219     BI opval = 0;
7220     CPU (h_xbit) = opval;
7221     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7222   }
7223   {
7224     BI opval = 0;
7225     SET_H_INSN_PREFIXED_P (opval);
7226     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7227   }
7228 }
7229 }
7230 }
7231
7232   abuf->written = written;
7233 #undef FLD
7234 }
7235   NEXT (vpc);
7236
7237   CASE (sem, INSN_SUB_M_W_M) : /* sub-m.w [${Rs}${inc}],${Rd} */
7238 {
7239   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7240   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7241 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7242   int UNUSED written = 0;
7243   IADDR UNUSED pc = abuf->addr;
7244   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7245
7246 {
7247   HI tmp_tmpopd;
7248   HI tmp_tmpops;
7249   BI tmp_carry;
7250   HI tmp_newval;
7251   tmp_tmpops = ({   SI tmp_addr;
7252   HI tmp_tmp_mem;
7253   BI tmp_postinc;
7254   tmp_postinc = FLD (f_memmode);
7255 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7256 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7257 ; if (NEBI (tmp_postinc, 0)) {
7258 {
7259 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7260   tmp_addr = ADDSI (tmp_addr, 2);
7261 }
7262   {
7263     SI opval = tmp_addr;
7264     SET_H_GR (FLD (f_operand1), opval);
7265     written |= (1 << 12);
7266     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7267   }
7268 }
7269 }
7270 ; tmp_tmp_mem; });
7271   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7272   tmp_carry = CPU (h_cbit);
7273   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7274 {
7275   SI tmp_oldregval;
7276   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7277   {
7278     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7279     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7280     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7281   }
7282 }
7283 {
7284   {
7285     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7286     CPU (h_cbit) = opval;
7287     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7288   }
7289   {
7290     BI opval = LTHI (tmp_newval, 0);
7291     CPU (h_nbit) = opval;
7292     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7293   }
7294   {
7295     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7296     CPU (h_zbit) = opval;
7297     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7298   }
7299   {
7300     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7301     CPU (h_vbit) = opval;
7302     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7303   }
7304 {
7305   {
7306     BI opval = 0;
7307     CPU (h_xbit) = opval;
7308     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7309   }
7310   {
7311     BI opval = 0;
7312     SET_H_INSN_PREFIXED_P (opval);
7313     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7314   }
7315 }
7316 }
7317 }
7318
7319   abuf->written = written;
7320 #undef FLD
7321 }
7322   NEXT (vpc);
7323
7324   CASE (sem, INSN_SUB_M_D_M) : /* sub-m.d [${Rs}${inc}],${Rd} */
7325 {
7326   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7327   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7328 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7329   int UNUSED written = 0;
7330   IADDR UNUSED pc = abuf->addr;
7331   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7332
7333 {
7334   SI tmp_tmpopd;
7335   SI tmp_tmpops;
7336   BI tmp_carry;
7337   SI tmp_newval;
7338   tmp_tmpops = ({   SI tmp_addr;
7339   SI tmp_tmp_mem;
7340   BI tmp_postinc;
7341   tmp_postinc = FLD (f_memmode);
7342 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7343 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
7344 ; if (NEBI (tmp_postinc, 0)) {
7345 {
7346 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7347   tmp_addr = ADDSI (tmp_addr, 4);
7348 }
7349   {
7350     SI opval = tmp_addr;
7351     SET_H_GR (FLD (f_operand1), opval);
7352     written |= (1 << 11);
7353     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7354   }
7355 }
7356 }
7357 ; tmp_tmp_mem; });
7358   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7359   tmp_carry = CPU (h_cbit);
7360   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7361   {
7362     SI opval = tmp_newval;
7363     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7364     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7365   }
7366 {
7367   {
7368     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7369     CPU (h_cbit) = opval;
7370     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7371   }
7372   {
7373     BI opval = LTSI (tmp_newval, 0);
7374     CPU (h_nbit) = opval;
7375     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7376   }
7377   {
7378     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7379     CPU (h_zbit) = opval;
7380     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7381   }
7382   {
7383     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7384     CPU (h_vbit) = opval;
7385     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7386   }
7387 {
7388   {
7389     BI opval = 0;
7390     CPU (h_xbit) = opval;
7391     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7392   }
7393   {
7394     BI opval = 0;
7395     SET_H_INSN_PREFIXED_P (opval);
7396     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7397   }
7398 }
7399 }
7400 }
7401
7402   abuf->written = written;
7403 #undef FLD
7404 }
7405   NEXT (vpc);
7406
7407   CASE (sem, INSN_SUBCBR) : /* sub.b ${sconst8}],${Rd} */
7408 {
7409   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7410   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7411 #define FLD(f) abuf->fields.sfmt_addcbr.f
7412   int UNUSED written = 0;
7413   IADDR UNUSED pc = abuf->addr;
7414   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7415
7416 {
7417   QI tmp_tmpopd;
7418   QI tmp_tmpops;
7419   BI tmp_carry;
7420   QI tmp_newval;
7421   tmp_tmpops = FLD (f_indir_pc__byte);
7422   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7423   tmp_carry = CPU (h_cbit);
7424   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7425 {
7426   SI tmp_oldregval;
7427   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
7428   {
7429     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7430     SET_H_GR (FLD (f_operand2), opval);
7431     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7432   }
7433 }
7434 {
7435   {
7436     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7437     CPU (h_cbit) = opval;
7438     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7439   }
7440   {
7441     BI opval = LTQI (tmp_newval, 0);
7442     CPU (h_nbit) = opval;
7443     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7444   }
7445   {
7446     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7447     CPU (h_zbit) = opval;
7448     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7449   }
7450   {
7451     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7452     CPU (h_vbit) = opval;
7453     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7454   }
7455 {
7456   {
7457     BI opval = 0;
7458     CPU (h_xbit) = opval;
7459     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7460   }
7461   {
7462     BI opval = 0;
7463     SET_H_INSN_PREFIXED_P (opval);
7464     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7465   }
7466 }
7467 }
7468 }
7469
7470 #undef FLD
7471 }
7472   NEXT (vpc);
7473
7474   CASE (sem, INSN_SUBCWR) : /* sub.w ${sconst16}],${Rd} */
7475 {
7476   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7477   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7478 #define FLD(f) abuf->fields.sfmt_addcwr.f
7479   int UNUSED written = 0;
7480   IADDR UNUSED pc = abuf->addr;
7481   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7482
7483 {
7484   HI tmp_tmpopd;
7485   HI tmp_tmpops;
7486   BI tmp_carry;
7487   HI tmp_newval;
7488   tmp_tmpops = FLD (f_indir_pc__word);
7489   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7490   tmp_carry = CPU (h_cbit);
7491   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7492 {
7493   SI tmp_oldregval;
7494   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
7495   {
7496     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7497     SET_H_GR (FLD (f_operand2), opval);
7498     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7499   }
7500 }
7501 {
7502   {
7503     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7504     CPU (h_cbit) = opval;
7505     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7506   }
7507   {
7508     BI opval = LTHI (tmp_newval, 0);
7509     CPU (h_nbit) = opval;
7510     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7511   }
7512   {
7513     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7514     CPU (h_zbit) = opval;
7515     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7516   }
7517   {
7518     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7519     CPU (h_vbit) = opval;
7520     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7521   }
7522 {
7523   {
7524     BI opval = 0;
7525     CPU (h_xbit) = opval;
7526     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7527   }
7528   {
7529     BI opval = 0;
7530     SET_H_INSN_PREFIXED_P (opval);
7531     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7532   }
7533 }
7534 }
7535 }
7536
7537 #undef FLD
7538 }
7539   NEXT (vpc);
7540
7541   CASE (sem, INSN_SUBCDR) : /* sub.d ${const32}],${Rd} */
7542 {
7543   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7544   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7545 #define FLD(f) abuf->fields.sfmt_addcdr.f
7546   int UNUSED written = 0;
7547   IADDR UNUSED pc = abuf->addr;
7548   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
7549
7550 {
7551   SI tmp_tmpopd;
7552   SI tmp_tmpops;
7553   BI tmp_carry;
7554   SI tmp_newval;
7555   tmp_tmpops = FLD (f_indir_pc__dword);
7556   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7557   tmp_carry = CPU (h_cbit);
7558   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7559   {
7560     SI opval = tmp_newval;
7561     SET_H_GR (FLD (f_operand2), opval);
7562     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7563   }
7564 {
7565   {
7566     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7567     CPU (h_cbit) = opval;
7568     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7569   }
7570   {
7571     BI opval = LTSI (tmp_newval, 0);
7572     CPU (h_nbit) = opval;
7573     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7574   }
7575   {
7576     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7577     CPU (h_zbit) = opval;
7578     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7579   }
7580   {
7581     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7582     CPU (h_vbit) = opval;
7583     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7584   }
7585 {
7586   {
7587     BI opval = 0;
7588     CPU (h_xbit) = opval;
7589     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7590   }
7591   {
7592     BI opval = 0;
7593     SET_H_INSN_PREFIXED_P (opval);
7594     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7595   }
7596 }
7597 }
7598 }
7599
7600 #undef FLD
7601 }
7602   NEXT (vpc);
7603
7604   CASE (sem, INSN_SUBS_B_R) : /* subs.b $Rs,$Rd */
7605 {
7606   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7607   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7608 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7609   int UNUSED written = 0;
7610   IADDR UNUSED pc = abuf->addr;
7611   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7612
7613 {
7614   SI tmp_tmpopd;
7615   SI tmp_tmpops;
7616   BI tmp_carry;
7617   SI tmp_newval;
7618   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
7619   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7620   tmp_carry = CPU (h_cbit);
7621   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7622   {
7623     SI opval = tmp_newval;
7624     SET_H_GR (FLD (f_operand2), opval);
7625     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7626   }
7627 {
7628   {
7629     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7630     CPU (h_cbit) = opval;
7631     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7632   }
7633   {
7634     BI opval = LTSI (tmp_newval, 0);
7635     CPU (h_nbit) = opval;
7636     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7637   }
7638   {
7639     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7640     CPU (h_zbit) = opval;
7641     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7642   }
7643   {
7644     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7645     CPU (h_vbit) = opval;
7646     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7647   }
7648 {
7649   {
7650     BI opval = 0;
7651     CPU (h_xbit) = opval;
7652     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7653   }
7654   {
7655     BI opval = 0;
7656     SET_H_INSN_PREFIXED_P (opval);
7657     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7658   }
7659 }
7660 }
7661 }
7662
7663 #undef FLD
7664 }
7665   NEXT (vpc);
7666
7667   CASE (sem, INSN_SUBS_W_R) : /* subs.w $Rs,$Rd */
7668 {
7669   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7670   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7671 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7672   int UNUSED written = 0;
7673   IADDR UNUSED pc = abuf->addr;
7674   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7675
7676 {
7677   SI tmp_tmpopd;
7678   SI tmp_tmpops;
7679   BI tmp_carry;
7680   SI tmp_newval;
7681   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
7682   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7683   tmp_carry = CPU (h_cbit);
7684   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7685   {
7686     SI opval = tmp_newval;
7687     SET_H_GR (FLD (f_operand2), opval);
7688     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7689   }
7690 {
7691   {
7692     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7693     CPU (h_cbit) = opval;
7694     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7695   }
7696   {
7697     BI opval = LTSI (tmp_newval, 0);
7698     CPU (h_nbit) = opval;
7699     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7700   }
7701   {
7702     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7703     CPU (h_zbit) = opval;
7704     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7705   }
7706   {
7707     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7708     CPU (h_vbit) = opval;
7709     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7710   }
7711 {
7712   {
7713     BI opval = 0;
7714     CPU (h_xbit) = opval;
7715     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7716   }
7717   {
7718     BI opval = 0;
7719     SET_H_INSN_PREFIXED_P (opval);
7720     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7721   }
7722 }
7723 }
7724 }
7725
7726 #undef FLD
7727 }
7728   NEXT (vpc);
7729
7730   CASE (sem, INSN_SUBS_M_B_M) : /* subs-m.b [${Rs}${inc}],$Rd */
7731 {
7732   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7733   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7734 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7735   int UNUSED written = 0;
7736   IADDR UNUSED pc = abuf->addr;
7737   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7738
7739 {
7740   SI tmp_tmpopd;
7741   SI tmp_tmpops;
7742   BI tmp_carry;
7743   SI tmp_newval;
7744   tmp_tmpops = EXTQISI (({   SI tmp_addr;
7745   QI tmp_tmp_mem;
7746   BI tmp_postinc;
7747   tmp_postinc = FLD (f_memmode);
7748 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7749 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7750 ; if (NEBI (tmp_postinc, 0)) {
7751 {
7752 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7753   tmp_addr = ADDSI (tmp_addr, 1);
7754 }
7755   {
7756     SI opval = tmp_addr;
7757     SET_H_GR (FLD (f_operand1), opval);
7758     written |= (1 << 11);
7759     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7760   }
7761 }
7762 }
7763 ; tmp_tmp_mem; }));
7764   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7765   tmp_carry = CPU (h_cbit);
7766   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7767   {
7768     SI opval = tmp_newval;
7769     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7770     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7771   }
7772 {
7773   {
7774     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7775     CPU (h_cbit) = opval;
7776     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7777   }
7778   {
7779     BI opval = LTSI (tmp_newval, 0);
7780     CPU (h_nbit) = opval;
7781     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7782   }
7783   {
7784     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7785     CPU (h_zbit) = opval;
7786     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7787   }
7788   {
7789     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7790     CPU (h_vbit) = opval;
7791     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7792   }
7793 {
7794   {
7795     BI opval = 0;
7796     CPU (h_xbit) = opval;
7797     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7798   }
7799   {
7800     BI opval = 0;
7801     SET_H_INSN_PREFIXED_P (opval);
7802     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7803   }
7804 }
7805 }
7806 }
7807
7808   abuf->written = written;
7809 #undef FLD
7810 }
7811   NEXT (vpc);
7812
7813   CASE (sem, INSN_SUBS_M_W_M) : /* subs-m.w [${Rs}${inc}],$Rd */
7814 {
7815   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7816   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7817 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7818   int UNUSED written = 0;
7819   IADDR UNUSED pc = abuf->addr;
7820   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7821
7822 {
7823   SI tmp_tmpopd;
7824   SI tmp_tmpops;
7825   BI tmp_carry;
7826   SI tmp_newval;
7827   tmp_tmpops = EXTHISI (({   SI tmp_addr;
7828   HI tmp_tmp_mem;
7829   BI tmp_postinc;
7830   tmp_postinc = FLD (f_memmode);
7831 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7832 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7833 ; if (NEBI (tmp_postinc, 0)) {
7834 {
7835 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7836   tmp_addr = ADDSI (tmp_addr, 2);
7837 }
7838   {
7839     SI opval = tmp_addr;
7840     SET_H_GR (FLD (f_operand1), opval);
7841     written |= (1 << 11);
7842     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7843   }
7844 }
7845 }
7846 ; tmp_tmp_mem; }));
7847   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7848   tmp_carry = CPU (h_cbit);
7849   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7850   {
7851     SI opval = tmp_newval;
7852     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7853     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7854   }
7855 {
7856   {
7857     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7858     CPU (h_cbit) = opval;
7859     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7860   }
7861   {
7862     BI opval = LTSI (tmp_newval, 0);
7863     CPU (h_nbit) = opval;
7864     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7865   }
7866   {
7867     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7868     CPU (h_zbit) = opval;
7869     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7870   }
7871   {
7872     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7873     CPU (h_vbit) = opval;
7874     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7875   }
7876 {
7877   {
7878     BI opval = 0;
7879     CPU (h_xbit) = opval;
7880     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7881   }
7882   {
7883     BI opval = 0;
7884     SET_H_INSN_PREFIXED_P (opval);
7885     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7886   }
7887 }
7888 }
7889 }
7890
7891   abuf->written = written;
7892 #undef FLD
7893 }
7894   NEXT (vpc);
7895
7896   CASE (sem, INSN_SUBSCBR) : /* [${Rs}${inc}],$Rd */
7897 {
7898   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7899   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7900 #define FLD(f) abuf->fields.sfmt_addcbr.f
7901   int UNUSED written = 0;
7902   IADDR UNUSED pc = abuf->addr;
7903   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7904
7905 {
7906   SI tmp_tmpopd;
7907   SI tmp_tmpops;
7908   BI tmp_carry;
7909   SI tmp_newval;
7910   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
7911   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7912   tmp_carry = CPU (h_cbit);
7913   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7914   {
7915     SI opval = tmp_newval;
7916     SET_H_GR (FLD (f_operand2), opval);
7917     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7918   }
7919 {
7920   {
7921     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7922     CPU (h_cbit) = opval;
7923     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7924   }
7925   {
7926     BI opval = LTSI (tmp_newval, 0);
7927     CPU (h_nbit) = opval;
7928     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7929   }
7930   {
7931     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7932     CPU (h_zbit) = opval;
7933     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7934   }
7935   {
7936     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7937     CPU (h_vbit) = opval;
7938     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7939   }
7940 {
7941   {
7942     BI opval = 0;
7943     CPU (h_xbit) = opval;
7944     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7945   }
7946   {
7947     BI opval = 0;
7948     SET_H_INSN_PREFIXED_P (opval);
7949     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7950   }
7951 }
7952 }
7953 }
7954
7955 #undef FLD
7956 }
7957   NEXT (vpc);
7958
7959   CASE (sem, INSN_SUBSCWR) : /* [${Rs}${inc}],$Rd */
7960 {
7961   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7962   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7963 #define FLD(f) abuf->fields.sfmt_addcwr.f
7964   int UNUSED written = 0;
7965   IADDR UNUSED pc = abuf->addr;
7966   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7967
7968 {
7969   SI tmp_tmpopd;
7970   SI tmp_tmpops;
7971   BI tmp_carry;
7972   SI tmp_newval;
7973   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
7974   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7975   tmp_carry = CPU (h_cbit);
7976   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7977   {
7978     SI opval = tmp_newval;
7979     SET_H_GR (FLD (f_operand2), opval);
7980     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7981   }
7982 {
7983   {
7984     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7985     CPU (h_cbit) = opval;
7986     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7987   }
7988   {
7989     BI opval = LTSI (tmp_newval, 0);
7990     CPU (h_nbit) = opval;
7991     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7992   }
7993   {
7994     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7995     CPU (h_zbit) = opval;
7996     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7997   }
7998   {
7999     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8000     CPU (h_vbit) = opval;
8001     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8002   }
8003 {
8004   {
8005     BI opval = 0;
8006     CPU (h_xbit) = opval;
8007     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8008   }
8009   {
8010     BI opval = 0;
8011     SET_H_INSN_PREFIXED_P (opval);
8012     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8013   }
8014 }
8015 }
8016 }
8017
8018 #undef FLD
8019 }
8020   NEXT (vpc);
8021
8022   CASE (sem, INSN_SUBU_B_R) : /* subu.b $Rs,$Rd */
8023 {
8024   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8025   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8026 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8027   int UNUSED written = 0;
8028   IADDR UNUSED pc = abuf->addr;
8029   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8030
8031 {
8032   SI tmp_tmpopd;
8033   SI tmp_tmpops;
8034   BI tmp_carry;
8035   SI tmp_newval;
8036   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
8037   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8038   tmp_carry = CPU (h_cbit);
8039   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8040   {
8041     SI opval = tmp_newval;
8042     SET_H_GR (FLD (f_operand2), opval);
8043     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8044   }
8045 {
8046   {
8047     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8048     CPU (h_cbit) = opval;
8049     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8050   }
8051   {
8052     BI opval = LTSI (tmp_newval, 0);
8053     CPU (h_nbit) = opval;
8054     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8055   }
8056   {
8057     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8058     CPU (h_zbit) = opval;
8059     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8060   }
8061   {
8062     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8063     CPU (h_vbit) = opval;
8064     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8065   }
8066 {
8067   {
8068     BI opval = 0;
8069     CPU (h_xbit) = opval;
8070     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8071   }
8072   {
8073     BI opval = 0;
8074     SET_H_INSN_PREFIXED_P (opval);
8075     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8076   }
8077 }
8078 }
8079 }
8080
8081 #undef FLD
8082 }
8083   NEXT (vpc);
8084
8085   CASE (sem, INSN_SUBU_W_R) : /* subu.w $Rs,$Rd */
8086 {
8087   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8088   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8089 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8090   int UNUSED written = 0;
8091   IADDR UNUSED pc = abuf->addr;
8092   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8093
8094 {
8095   SI tmp_tmpopd;
8096   SI tmp_tmpops;
8097   BI tmp_carry;
8098   SI tmp_newval;
8099   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
8100   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8101   tmp_carry = CPU (h_cbit);
8102   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8103   {
8104     SI opval = tmp_newval;
8105     SET_H_GR (FLD (f_operand2), opval);
8106     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8107   }
8108 {
8109   {
8110     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8111     CPU (h_cbit) = opval;
8112     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8113   }
8114   {
8115     BI opval = LTSI (tmp_newval, 0);
8116     CPU (h_nbit) = opval;
8117     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8118   }
8119   {
8120     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8121     CPU (h_zbit) = opval;
8122     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8123   }
8124   {
8125     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8126     CPU (h_vbit) = opval;
8127     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8128   }
8129 {
8130   {
8131     BI opval = 0;
8132     CPU (h_xbit) = opval;
8133     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8134   }
8135   {
8136     BI opval = 0;
8137     SET_H_INSN_PREFIXED_P (opval);
8138     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8139   }
8140 }
8141 }
8142 }
8143
8144 #undef FLD
8145 }
8146   NEXT (vpc);
8147
8148   CASE (sem, INSN_SUBU_M_B_M) : /* subu-m.b [${Rs}${inc}],$Rd */
8149 {
8150   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8151   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8152 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8153   int UNUSED written = 0;
8154   IADDR UNUSED pc = abuf->addr;
8155   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8156
8157 {
8158   SI tmp_tmpopd;
8159   SI tmp_tmpops;
8160   BI tmp_carry;
8161   SI tmp_newval;
8162   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
8163   QI tmp_tmp_mem;
8164   BI tmp_postinc;
8165   tmp_postinc = FLD (f_memmode);
8166 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8167 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
8168 ; if (NEBI (tmp_postinc, 0)) {
8169 {
8170 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8171   tmp_addr = ADDSI (tmp_addr, 1);
8172 }
8173   {
8174     SI opval = tmp_addr;
8175     SET_H_GR (FLD (f_operand1), opval);
8176     written |= (1 << 11);
8177     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8178   }
8179 }
8180 }
8181 ; tmp_tmp_mem; }));
8182   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8183   tmp_carry = CPU (h_cbit);
8184   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8185   {
8186     SI opval = tmp_newval;
8187     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8188     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8189   }
8190 {
8191   {
8192     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8193     CPU (h_cbit) = opval;
8194     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8195   }
8196   {
8197     BI opval = LTSI (tmp_newval, 0);
8198     CPU (h_nbit) = opval;
8199     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8200   }
8201   {
8202     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8203     CPU (h_zbit) = opval;
8204     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8205   }
8206   {
8207     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8208     CPU (h_vbit) = opval;
8209     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8210   }
8211 {
8212   {
8213     BI opval = 0;
8214     CPU (h_xbit) = opval;
8215     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8216   }
8217   {
8218     BI opval = 0;
8219     SET_H_INSN_PREFIXED_P (opval);
8220     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8221   }
8222 }
8223 }
8224 }
8225
8226   abuf->written = written;
8227 #undef FLD
8228 }
8229   NEXT (vpc);
8230
8231   CASE (sem, INSN_SUBU_M_W_M) : /* subu-m.w [${Rs}${inc}],$Rd */
8232 {
8233   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8234   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8235 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8236   int UNUSED written = 0;
8237   IADDR UNUSED pc = abuf->addr;
8238   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8239
8240 {
8241   SI tmp_tmpopd;
8242   SI tmp_tmpops;
8243   BI tmp_carry;
8244   SI tmp_newval;
8245   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
8246   HI tmp_tmp_mem;
8247   BI tmp_postinc;
8248   tmp_postinc = FLD (f_memmode);
8249 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8250 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
8251 ; if (NEBI (tmp_postinc, 0)) {
8252 {
8253 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8254   tmp_addr = ADDSI (tmp_addr, 2);
8255 }
8256   {
8257     SI opval = tmp_addr;
8258     SET_H_GR (FLD (f_operand1), opval);
8259     written |= (1 << 11);
8260     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8261   }
8262 }
8263 }
8264 ; tmp_tmp_mem; }));
8265   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8266   tmp_carry = CPU (h_cbit);
8267   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8268   {
8269     SI opval = tmp_newval;
8270     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8271     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8272   }
8273 {
8274   {
8275     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8276     CPU (h_cbit) = opval;
8277     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8278   }
8279   {
8280     BI opval = LTSI (tmp_newval, 0);
8281     CPU (h_nbit) = opval;
8282     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8283   }
8284   {
8285     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8286     CPU (h_zbit) = opval;
8287     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8288   }
8289   {
8290     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8291     CPU (h_vbit) = opval;
8292     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8293   }
8294 {
8295   {
8296     BI opval = 0;
8297     CPU (h_xbit) = opval;
8298     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8299   }
8300   {
8301     BI opval = 0;
8302     SET_H_INSN_PREFIXED_P (opval);
8303     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8304   }
8305 }
8306 }
8307 }
8308
8309   abuf->written = written;
8310 #undef FLD
8311 }
8312   NEXT (vpc);
8313
8314   CASE (sem, INSN_SUBUCBR) : /* [${Rs}${inc}],$Rd */
8315 {
8316   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8317   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8318 #define FLD(f) abuf->fields.sfmt_addcbr.f
8319   int UNUSED written = 0;
8320   IADDR UNUSED pc = abuf->addr;
8321   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8322
8323 {
8324   SI tmp_tmpopd;
8325   SI tmp_tmpops;
8326   BI tmp_carry;
8327   SI tmp_newval;
8328   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
8329   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8330   tmp_carry = CPU (h_cbit);
8331   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8332   {
8333     SI opval = tmp_newval;
8334     SET_H_GR (FLD (f_operand2), opval);
8335     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8336   }
8337 {
8338   {
8339     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8340     CPU (h_cbit) = opval;
8341     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8342   }
8343   {
8344     BI opval = LTSI (tmp_newval, 0);
8345     CPU (h_nbit) = opval;
8346     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8347   }
8348   {
8349     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8350     CPU (h_zbit) = opval;
8351     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8352   }
8353   {
8354     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8355     CPU (h_vbit) = opval;
8356     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8357   }
8358 {
8359   {
8360     BI opval = 0;
8361     CPU (h_xbit) = opval;
8362     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8363   }
8364   {
8365     BI opval = 0;
8366     SET_H_INSN_PREFIXED_P (opval);
8367     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8368   }
8369 }
8370 }
8371 }
8372
8373 #undef FLD
8374 }
8375   NEXT (vpc);
8376
8377   CASE (sem, INSN_SUBUCWR) : /* [${Rs}${inc}],$Rd */
8378 {
8379   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8380   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8381 #define FLD(f) abuf->fields.sfmt_addcwr.f
8382   int UNUSED written = 0;
8383   IADDR UNUSED pc = abuf->addr;
8384   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8385
8386 {
8387   SI tmp_tmpopd;
8388   SI tmp_tmpops;
8389   BI tmp_carry;
8390   SI tmp_newval;
8391   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
8392   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8393   tmp_carry = CPU (h_cbit);
8394   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8395   {
8396     SI opval = tmp_newval;
8397     SET_H_GR (FLD (f_operand2), opval);
8398     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8399   }
8400 {
8401   {
8402     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8403     CPU (h_cbit) = opval;
8404     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8405   }
8406   {
8407     BI opval = LTSI (tmp_newval, 0);
8408     CPU (h_nbit) = opval;
8409     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8410   }
8411   {
8412     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8413     CPU (h_zbit) = opval;
8414     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8415   }
8416   {
8417     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8418     CPU (h_vbit) = opval;
8419     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8420   }
8421 {
8422   {
8423     BI opval = 0;
8424     CPU (h_xbit) = opval;
8425     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8426   }
8427   {
8428     BI opval = 0;
8429     SET_H_INSN_PREFIXED_P (opval);
8430     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8431   }
8432 }
8433 }
8434 }
8435
8436 #undef FLD
8437 }
8438   NEXT (vpc);
8439
8440   CASE (sem, INSN_ADDI_B_R) : /* addi.b ${Rs-dfield}.m,${Rd-sfield} */
8441 {
8442   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8443   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8444 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8445   int UNUSED written = 0;
8446   IADDR UNUSED pc = abuf->addr;
8447   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8448
8449 {
8450   {
8451     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
8452     SET_H_GR (FLD (f_operand1), opval);
8453     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8454   }
8455 {
8456   {
8457     BI opval = 0;
8458     CPU (h_xbit) = opval;
8459     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8460   }
8461   {
8462     BI opval = 0;
8463     SET_H_INSN_PREFIXED_P (opval);
8464     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8465   }
8466 }
8467 }
8468
8469 #undef FLD
8470 }
8471   NEXT (vpc);
8472
8473   CASE (sem, INSN_ADDI_W_R) : /* addi.w ${Rs-dfield}.m,${Rd-sfield} */
8474 {
8475   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8476   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8477 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8478   int UNUSED written = 0;
8479   IADDR UNUSED pc = abuf->addr;
8480   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8481
8482 {
8483   {
8484     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
8485     SET_H_GR (FLD (f_operand1), opval);
8486     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8487   }
8488 {
8489   {
8490     BI opval = 0;
8491     CPU (h_xbit) = opval;
8492     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8493   }
8494   {
8495     BI opval = 0;
8496     SET_H_INSN_PREFIXED_P (opval);
8497     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8498   }
8499 }
8500 }
8501
8502 #undef FLD
8503 }
8504   NEXT (vpc);
8505
8506   CASE (sem, INSN_ADDI_D_R) : /* addi.d ${Rs-dfield}.m,${Rd-sfield} */
8507 {
8508   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8509   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8510 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8511   int UNUSED written = 0;
8512   IADDR UNUSED pc = abuf->addr;
8513   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8514
8515 {
8516   {
8517     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
8518     SET_H_GR (FLD (f_operand1), opval);
8519     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8520   }
8521 {
8522   {
8523     BI opval = 0;
8524     CPU (h_xbit) = opval;
8525     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8526   }
8527   {
8528     BI opval = 0;
8529     SET_H_INSN_PREFIXED_P (opval);
8530     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8531   }
8532 }
8533 }
8534
8535 #undef FLD
8536 }
8537   NEXT (vpc);
8538
8539   CASE (sem, INSN_NEG_B_R) : /* neg.b $Rs,$Rd */
8540 {
8541   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8542   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8543 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8544   int UNUSED written = 0;
8545   IADDR UNUSED pc = abuf->addr;
8546   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8547
8548 {
8549   QI tmp_tmpopd;
8550   QI tmp_tmpops;
8551   BI tmp_carry;
8552   QI tmp_newval;
8553   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8554   tmp_tmpopd = 0;
8555   tmp_carry = CPU (h_cbit);
8556   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8557 {
8558   SI tmp_oldregval;
8559   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
8560   {
8561     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
8562     SET_H_GR (FLD (f_operand2), opval);
8563     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8564   }
8565 }
8566 {
8567   {
8568     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
8569     CPU (h_cbit) = opval;
8570     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8571   }
8572   {
8573     BI opval = LTQI (tmp_newval, 0);
8574     CPU (h_nbit) = opval;
8575     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8576   }
8577   {
8578     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8579     CPU (h_zbit) = opval;
8580     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8581   }
8582   {
8583     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
8584     CPU (h_vbit) = opval;
8585     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8586   }
8587 {
8588   {
8589     BI opval = 0;
8590     CPU (h_xbit) = opval;
8591     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8592   }
8593   {
8594     BI opval = 0;
8595     SET_H_INSN_PREFIXED_P (opval);
8596     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8597   }
8598 }
8599 }
8600 }
8601
8602 #undef FLD
8603 }
8604   NEXT (vpc);
8605
8606   CASE (sem, INSN_NEG_W_R) : /* neg.w $Rs,$Rd */
8607 {
8608   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8609   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8610 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8611   int UNUSED written = 0;
8612   IADDR UNUSED pc = abuf->addr;
8613   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8614
8615 {
8616   HI tmp_tmpopd;
8617   HI tmp_tmpops;
8618   BI tmp_carry;
8619   HI tmp_newval;
8620   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8621   tmp_tmpopd = 0;
8622   tmp_carry = CPU (h_cbit);
8623   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8624 {
8625   SI tmp_oldregval;
8626   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
8627   {
8628     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
8629     SET_H_GR (FLD (f_operand2), opval);
8630     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8631   }
8632 }
8633 {
8634   {
8635     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
8636     CPU (h_cbit) = opval;
8637     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8638   }
8639   {
8640     BI opval = LTHI (tmp_newval, 0);
8641     CPU (h_nbit) = opval;
8642     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8643   }
8644   {
8645     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8646     CPU (h_zbit) = opval;
8647     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8648   }
8649   {
8650     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
8651     CPU (h_vbit) = opval;
8652     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8653   }
8654 {
8655   {
8656     BI opval = 0;
8657     CPU (h_xbit) = opval;
8658     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8659   }
8660   {
8661     BI opval = 0;
8662     SET_H_INSN_PREFIXED_P (opval);
8663     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8664   }
8665 }
8666 }
8667 }
8668
8669 #undef FLD
8670 }
8671   NEXT (vpc);
8672
8673   CASE (sem, INSN_NEG_D_R) : /* neg.d $Rs,$Rd */
8674 {
8675   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8676   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8677 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8678   int UNUSED written = 0;
8679   IADDR UNUSED pc = abuf->addr;
8680   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8681
8682 {
8683   SI tmp_tmpopd;
8684   SI tmp_tmpops;
8685   BI tmp_carry;
8686   SI tmp_newval;
8687   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8688   tmp_tmpopd = 0;
8689   tmp_carry = CPU (h_cbit);
8690   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8691   {
8692     SI opval = tmp_newval;
8693     SET_H_GR (FLD (f_operand2), opval);
8694     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8695   }
8696 {
8697   {
8698     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8699     CPU (h_cbit) = opval;
8700     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8701   }
8702   {
8703     BI opval = LTSI (tmp_newval, 0);
8704     CPU (h_nbit) = opval;
8705     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8706   }
8707   {
8708     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8709     CPU (h_zbit) = opval;
8710     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8711   }
8712   {
8713     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8714     CPU (h_vbit) = opval;
8715     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8716   }
8717 {
8718   {
8719     BI opval = 0;
8720     CPU (h_xbit) = opval;
8721     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8722   }
8723   {
8724     BI opval = 0;
8725     SET_H_INSN_PREFIXED_P (opval);
8726     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8727   }
8728 }
8729 }
8730 }
8731
8732 #undef FLD
8733 }
8734   NEXT (vpc);
8735
8736   CASE (sem, INSN_TEST_M_B_M) : /* test-m.b [${Rs}${inc}] */
8737 {
8738   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8739   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8740 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
8741   int UNUSED written = 0;
8742   IADDR UNUSED pc = abuf->addr;
8743   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8744
8745 {
8746   QI tmp_tmpd;
8747   tmp_tmpd = ({   SI tmp_addr;
8748   QI tmp_tmp_mem;
8749   BI tmp_postinc;
8750   tmp_postinc = FLD (f_memmode);
8751 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8752 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
8753 ; if (NEBI (tmp_postinc, 0)) {
8754 {
8755 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8756   tmp_addr = ADDSI (tmp_addr, 1);
8757 }
8758   {
8759     SI opval = tmp_addr;
8760     SET_H_GR (FLD (f_operand1), opval);
8761     written |= (1 << 8);
8762     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8763   }
8764 }
8765 }
8766 ; tmp_tmp_mem; });
8767 {
8768   QI tmp_tmpopd;
8769   QI tmp_tmpops;
8770   BI tmp_carry;
8771   QI tmp_newval;
8772   tmp_tmpops = 0;
8773   tmp_tmpopd = tmp_tmpd;
8774   tmp_carry = CPU (h_cbit);
8775   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8776 ((void) 0); /*nop*/
8777 {
8778   {
8779     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
8780     CPU (h_cbit) = opval;
8781     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8782   }
8783   {
8784     BI opval = LTQI (tmp_newval, 0);
8785     CPU (h_nbit) = opval;
8786     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8787   }
8788   {
8789     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8790     CPU (h_zbit) = opval;
8791     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8792   }
8793   {
8794     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
8795     CPU (h_vbit) = opval;
8796     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8797   }
8798 {
8799   {
8800     BI opval = 0;
8801     CPU (h_xbit) = opval;
8802     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8803   }
8804   {
8805     BI opval = 0;
8806     SET_H_INSN_PREFIXED_P (opval);
8807     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8808   }
8809 }
8810 }
8811 }
8812 }
8813
8814   abuf->written = written;
8815 #undef FLD
8816 }
8817   NEXT (vpc);
8818
8819   CASE (sem, INSN_TEST_M_W_M) : /* test-m.w [${Rs}${inc}] */
8820 {
8821   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8822   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8823 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
8824   int UNUSED written = 0;
8825   IADDR UNUSED pc = abuf->addr;
8826   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8827
8828 {
8829   HI tmp_tmpd;
8830   tmp_tmpd = ({   SI tmp_addr;
8831   HI tmp_tmp_mem;
8832   BI tmp_postinc;
8833   tmp_postinc = FLD (f_memmode);
8834 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8835 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
8836 ; if (NEBI (tmp_postinc, 0)) {
8837 {
8838 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8839   tmp_addr = ADDSI (tmp_addr, 2);
8840 }
8841   {
8842     SI opval = tmp_addr;
8843     SET_H_GR (FLD (f_operand1), opval);
8844     written |= (1 << 8);
8845     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8846   }
8847 }
8848 }
8849 ; tmp_tmp_mem; });
8850 {
8851   HI tmp_tmpopd;
8852   HI tmp_tmpops;
8853   BI tmp_carry;
8854   HI tmp_newval;
8855   tmp_tmpops = 0;
8856   tmp_tmpopd = tmp_tmpd;
8857   tmp_carry = CPU (h_cbit);
8858   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8859 ((void) 0); /*nop*/
8860 {
8861   {
8862     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
8863     CPU (h_cbit) = opval;
8864     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8865   }
8866   {
8867     BI opval = LTHI (tmp_newval, 0);
8868     CPU (h_nbit) = opval;
8869     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8870   }
8871   {
8872     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8873     CPU (h_zbit) = opval;
8874     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8875   }
8876   {
8877     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
8878     CPU (h_vbit) = opval;
8879     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8880   }
8881 {
8882   {
8883     BI opval = 0;
8884     CPU (h_xbit) = opval;
8885     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8886   }
8887   {
8888     BI opval = 0;
8889     SET_H_INSN_PREFIXED_P (opval);
8890     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8891   }
8892 }
8893 }
8894 }
8895 }
8896
8897   abuf->written = written;
8898 #undef FLD
8899 }
8900   NEXT (vpc);
8901
8902   CASE (sem, INSN_TEST_M_D_M) : /* test-m.d [${Rs}${inc}] */
8903 {
8904   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8905   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8906 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
8907   int UNUSED written = 0;
8908   IADDR UNUSED pc = abuf->addr;
8909   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8910
8911 {
8912   SI tmp_tmpd;
8913   tmp_tmpd = ({   SI tmp_addr;
8914   SI tmp_tmp_mem;
8915   BI tmp_postinc;
8916   tmp_postinc = FLD (f_memmode);
8917 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8918 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
8919 ; if (NEBI (tmp_postinc, 0)) {
8920 {
8921 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8922   tmp_addr = ADDSI (tmp_addr, 4);
8923 }
8924   {
8925     SI opval = tmp_addr;
8926     SET_H_GR (FLD (f_operand1), opval);
8927     written |= (1 << 8);
8928     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8929   }
8930 }
8931 }
8932 ; tmp_tmp_mem; });
8933 {
8934   SI tmp_tmpopd;
8935   SI tmp_tmpops;
8936   BI tmp_carry;
8937   SI tmp_newval;
8938   tmp_tmpops = 0;
8939   tmp_tmpopd = tmp_tmpd;
8940   tmp_carry = CPU (h_cbit);
8941   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8942 ((void) 0); /*nop*/
8943 {
8944   {
8945     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8946     CPU (h_cbit) = opval;
8947     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8948   }
8949   {
8950     BI opval = LTSI (tmp_newval, 0);
8951     CPU (h_nbit) = opval;
8952     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8953   }
8954   {
8955     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8956     CPU (h_zbit) = opval;
8957     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8958   }
8959   {
8960     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8961     CPU (h_vbit) = opval;
8962     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8963   }
8964 {
8965   {
8966     BI opval = 0;
8967     CPU (h_xbit) = opval;
8968     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8969   }
8970   {
8971     BI opval = 0;
8972     SET_H_INSN_PREFIXED_P (opval);
8973     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8974   }
8975 }
8976 }
8977 }
8978 }
8979
8980   abuf->written = written;
8981 #undef FLD
8982 }
8983   NEXT (vpc);
8984
8985   CASE (sem, INSN_MOVE_R_M_B_M) : /* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
8986 {
8987   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8988   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8989 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8990   int UNUSED written = 0;
8991   IADDR UNUSED pc = abuf->addr;
8992   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8993
8994 {
8995   QI tmp_tmpd;
8996   tmp_tmpd = GET_H_GR (FLD (f_operand2));
8997 {
8998   SI tmp_addr;
8999   BI tmp_postinc;
9000   tmp_postinc = FLD (f_memmode);
9001   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9002 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
9003 if (EQBI (CPU (h_pbit), 0)) {
9004 {
9005   {
9006     QI opval = tmp_tmpd;
9007     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9008     written |= (1 << 10);
9009     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9010   }
9011   {
9012     BI opval = CPU (h_pbit);
9013     CPU (h_cbit) = opval;
9014     written |= (1 << 9);
9015     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9016   }
9017 }
9018 } else {
9019   {
9020     BI opval = 1;
9021     CPU (h_cbit) = opval;
9022     written |= (1 << 9);
9023     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9024   }
9025 }
9026 } else {
9027   {
9028     QI opval = tmp_tmpd;
9029     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9030     written |= (1 << 10);
9031     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9032   }
9033 }
9034 if (NEBI (tmp_postinc, 0)) {
9035 {
9036 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9037   tmp_addr = ADDSI (tmp_addr, 1);
9038 }
9039   {
9040     SI opval = tmp_addr;
9041     SET_H_GR (FLD (f_operand1), opval);
9042     written |= (1 << 8);
9043     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9044   }
9045 }
9046 }
9047 }
9048 {
9049   {
9050     BI opval = 0;
9051     CPU (h_xbit) = opval;
9052     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9053   }
9054   {
9055     BI opval = 0;
9056     SET_H_INSN_PREFIXED_P (opval);
9057     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9058   }
9059 }
9060 }
9061
9062   abuf->written = written;
9063 #undef FLD
9064 }
9065   NEXT (vpc);
9066
9067   CASE (sem, INSN_MOVE_R_M_W_M) : /* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
9068 {
9069   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9070   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9071 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
9072   int UNUSED written = 0;
9073   IADDR UNUSED pc = abuf->addr;
9074   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9075
9076 {
9077   HI tmp_tmpd;
9078   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9079 {
9080   SI tmp_addr;
9081   BI tmp_postinc;
9082   tmp_postinc = FLD (f_memmode);
9083   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9084 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
9085 if (EQBI (CPU (h_pbit), 0)) {
9086 {
9087   {
9088     HI opval = tmp_tmpd;
9089     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9090     written |= (1 << 10);
9091     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9092   }
9093   {
9094     BI opval = CPU (h_pbit);
9095     CPU (h_cbit) = opval;
9096     written |= (1 << 9);
9097     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9098   }
9099 }
9100 } else {
9101   {
9102     BI opval = 1;
9103     CPU (h_cbit) = opval;
9104     written |= (1 << 9);
9105     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9106   }
9107 }
9108 } else {
9109   {
9110     HI opval = tmp_tmpd;
9111     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9112     written |= (1 << 10);
9113     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9114   }
9115 }
9116 if (NEBI (tmp_postinc, 0)) {
9117 {
9118 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9119   tmp_addr = ADDSI (tmp_addr, 2);
9120 }
9121   {
9122     SI opval = tmp_addr;
9123     SET_H_GR (FLD (f_operand1), opval);
9124     written |= (1 << 8);
9125     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9126   }
9127 }
9128 }
9129 }
9130 {
9131   {
9132     BI opval = 0;
9133     CPU (h_xbit) = opval;
9134     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9135   }
9136   {
9137     BI opval = 0;
9138     SET_H_INSN_PREFIXED_P (opval);
9139     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9140   }
9141 }
9142 }
9143
9144   abuf->written = written;
9145 #undef FLD
9146 }
9147   NEXT (vpc);
9148
9149   CASE (sem, INSN_MOVE_R_M_D_M) : /* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
9150 {
9151   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9152   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9153 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
9154   int UNUSED written = 0;
9155   IADDR UNUSED pc = abuf->addr;
9156   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9157
9158 {
9159   SI tmp_tmpd;
9160   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9161 {
9162   SI tmp_addr;
9163   BI tmp_postinc;
9164   tmp_postinc = FLD (f_memmode);
9165   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9166 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
9167 if (EQBI (CPU (h_pbit), 0)) {
9168 {
9169   {
9170     SI opval = tmp_tmpd;
9171     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9172     written |= (1 << 10);
9173     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9174   }
9175   {
9176     BI opval = CPU (h_pbit);
9177     CPU (h_cbit) = opval;
9178     written |= (1 << 9);
9179     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9180   }
9181 }
9182 } else {
9183   {
9184     BI opval = 1;
9185     CPU (h_cbit) = opval;
9186     written |= (1 << 9);
9187     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9188   }
9189 }
9190 } else {
9191   {
9192     SI opval = tmp_tmpd;
9193     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9194     written |= (1 << 10);
9195     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9196   }
9197 }
9198 if (NEBI (tmp_postinc, 0)) {
9199 {
9200 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9201   tmp_addr = ADDSI (tmp_addr, 4);
9202 }
9203   {
9204     SI opval = tmp_addr;
9205     SET_H_GR (FLD (f_operand1), opval);
9206     written |= (1 << 8);
9207     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9208   }
9209 }
9210 }
9211 }
9212 {
9213   {
9214     BI opval = 0;
9215     CPU (h_xbit) = opval;
9216     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9217   }
9218   {
9219     BI opval = 0;
9220     SET_H_INSN_PREFIXED_P (opval);
9221     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9222   }
9223 }
9224 }
9225
9226   abuf->written = written;
9227 #undef FLD
9228 }
9229   NEXT (vpc);
9230
9231   CASE (sem, INSN_MULS_B) : /* muls.b $Rs,$Rd */
9232 {
9233   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9234   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9235 #define FLD(f) abuf->fields.sfmt_muls_b.f
9236   int UNUSED written = 0;
9237   IADDR UNUSED pc = abuf->addr;
9238   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9239
9240 {
9241   DI tmp_src1;
9242   DI tmp_src2;
9243   DI tmp_tmpr;
9244   tmp_src1 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9245   tmp_src2 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9246   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9247   {
9248     SI opval = TRUNCDISI (tmp_tmpr);
9249     SET_H_GR (FLD (f_operand2), opval);
9250     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9251   }
9252   {
9253     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9254     SET_H_SR (((UINT) 7), opval);
9255     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9256   }
9257 {
9258   {
9259     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9260     CPU (h_cbit) = opval;
9261     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9262   }
9263   {
9264     BI opval = LTDI (tmp_tmpr, 0);
9265     CPU (h_nbit) = opval;
9266     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9267   }
9268   {
9269     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9270     CPU (h_zbit) = opval;
9271     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9272   }
9273   {
9274     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9275     CPU (h_vbit) = opval;
9276     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9277   }
9278 {
9279   {
9280     BI opval = 0;
9281     CPU (h_xbit) = opval;
9282     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9283   }
9284   {
9285     BI opval = 0;
9286     SET_H_INSN_PREFIXED_P (opval);
9287     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9288   }
9289 }
9290 }
9291 }
9292
9293 #undef FLD
9294 }
9295   NEXT (vpc);
9296
9297   CASE (sem, INSN_MULS_W) : /* muls.w $Rs,$Rd */
9298 {
9299   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9300   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9301 #define FLD(f) abuf->fields.sfmt_muls_b.f
9302   int UNUSED written = 0;
9303   IADDR UNUSED pc = abuf->addr;
9304   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9305
9306 {
9307   DI tmp_src1;
9308   DI tmp_src2;
9309   DI tmp_tmpr;
9310   tmp_src1 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9311   tmp_src2 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9312   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9313   {
9314     SI opval = TRUNCDISI (tmp_tmpr);
9315     SET_H_GR (FLD (f_operand2), opval);
9316     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9317   }
9318   {
9319     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9320     SET_H_SR (((UINT) 7), opval);
9321     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9322   }
9323 {
9324   {
9325     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9326     CPU (h_cbit) = opval;
9327     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9328   }
9329   {
9330     BI opval = LTDI (tmp_tmpr, 0);
9331     CPU (h_nbit) = opval;
9332     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9333   }
9334   {
9335     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9336     CPU (h_zbit) = opval;
9337     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9338   }
9339   {
9340     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9341     CPU (h_vbit) = opval;
9342     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9343   }
9344 {
9345   {
9346     BI opval = 0;
9347     CPU (h_xbit) = opval;
9348     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9349   }
9350   {
9351     BI opval = 0;
9352     SET_H_INSN_PREFIXED_P (opval);
9353     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9354   }
9355 }
9356 }
9357 }
9358
9359 #undef FLD
9360 }
9361   NEXT (vpc);
9362
9363   CASE (sem, INSN_MULS_D) : /* muls.d $Rs,$Rd */
9364 {
9365   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9366   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9367 #define FLD(f) abuf->fields.sfmt_muls_b.f
9368   int UNUSED written = 0;
9369   IADDR UNUSED pc = abuf->addr;
9370   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9371
9372 {
9373   DI tmp_src1;
9374   DI tmp_src2;
9375   DI tmp_tmpr;
9376   tmp_src1 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9377   tmp_src2 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9378   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9379   {
9380     SI opval = TRUNCDISI (tmp_tmpr);
9381     SET_H_GR (FLD (f_operand2), opval);
9382     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9383   }
9384   {
9385     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9386     SET_H_SR (((UINT) 7), opval);
9387     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9388   }
9389 {
9390   {
9391     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9392     CPU (h_cbit) = opval;
9393     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9394   }
9395   {
9396     BI opval = LTDI (tmp_tmpr, 0);
9397     CPU (h_nbit) = opval;
9398     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9399   }
9400   {
9401     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9402     CPU (h_zbit) = opval;
9403     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9404   }
9405   {
9406     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9407     CPU (h_vbit) = opval;
9408     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9409   }
9410 {
9411   {
9412     BI opval = 0;
9413     CPU (h_xbit) = opval;
9414     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9415   }
9416   {
9417     BI opval = 0;
9418     SET_H_INSN_PREFIXED_P (opval);
9419     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9420   }
9421 }
9422 }
9423 }
9424
9425 #undef FLD
9426 }
9427   NEXT (vpc);
9428
9429   CASE (sem, INSN_MULU_B) : /* mulu.b $Rs,$Rd */
9430 {
9431   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9432   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9433 #define FLD(f) abuf->fields.sfmt_muls_b.f
9434   int UNUSED written = 0;
9435   IADDR UNUSED pc = abuf->addr;
9436   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9437
9438 {
9439   DI tmp_src1;
9440   DI tmp_src2;
9441   DI tmp_tmpr;
9442   tmp_src1 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9443   tmp_src2 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9444   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9445   {
9446     SI opval = TRUNCDISI (tmp_tmpr);
9447     SET_H_GR (FLD (f_operand2), opval);
9448     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9449   }
9450   {
9451     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9452     SET_H_SR (((UINT) 7), opval);
9453     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9454   }
9455 {
9456   {
9457     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9458     CPU (h_cbit) = opval;
9459     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9460   }
9461   {
9462     BI opval = LTDI (tmp_tmpr, 0);
9463     CPU (h_nbit) = opval;
9464     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9465   }
9466   {
9467     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9468     CPU (h_zbit) = opval;
9469     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9470   }
9471   {
9472     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9473     CPU (h_vbit) = opval;
9474     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9475   }
9476 {
9477   {
9478     BI opval = 0;
9479     CPU (h_xbit) = opval;
9480     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9481   }
9482   {
9483     BI opval = 0;
9484     SET_H_INSN_PREFIXED_P (opval);
9485     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9486   }
9487 }
9488 }
9489 }
9490
9491 #undef FLD
9492 }
9493   NEXT (vpc);
9494
9495   CASE (sem, INSN_MULU_W) : /* mulu.w $Rs,$Rd */
9496 {
9497   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9498   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9499 #define FLD(f) abuf->fields.sfmt_muls_b.f
9500   int UNUSED written = 0;
9501   IADDR UNUSED pc = abuf->addr;
9502   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9503
9504 {
9505   DI tmp_src1;
9506   DI tmp_src2;
9507   DI tmp_tmpr;
9508   tmp_src1 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9509   tmp_src2 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9510   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9511   {
9512     SI opval = TRUNCDISI (tmp_tmpr);
9513     SET_H_GR (FLD (f_operand2), opval);
9514     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9515   }
9516   {
9517     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9518     SET_H_SR (((UINT) 7), opval);
9519     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9520   }
9521 {
9522   {
9523     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9524     CPU (h_cbit) = opval;
9525     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9526   }
9527   {
9528     BI opval = LTDI (tmp_tmpr, 0);
9529     CPU (h_nbit) = opval;
9530     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9531   }
9532   {
9533     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9534     CPU (h_zbit) = opval;
9535     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9536   }
9537   {
9538     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9539     CPU (h_vbit) = opval;
9540     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9541   }
9542 {
9543   {
9544     BI opval = 0;
9545     CPU (h_xbit) = opval;
9546     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9547   }
9548   {
9549     BI opval = 0;
9550     SET_H_INSN_PREFIXED_P (opval);
9551     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9552   }
9553 }
9554 }
9555 }
9556
9557 #undef FLD
9558 }
9559   NEXT (vpc);
9560
9561   CASE (sem, INSN_MULU_D) : /* mulu.d $Rs,$Rd */
9562 {
9563   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9564   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9565 #define FLD(f) abuf->fields.sfmt_muls_b.f
9566   int UNUSED written = 0;
9567   IADDR UNUSED pc = abuf->addr;
9568   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9569
9570 {
9571   DI tmp_src1;
9572   DI tmp_src2;
9573   DI tmp_tmpr;
9574   tmp_src1 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9575   tmp_src2 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9576   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9577   {
9578     SI opval = TRUNCDISI (tmp_tmpr);
9579     SET_H_GR (FLD (f_operand2), opval);
9580     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9581   }
9582   {
9583     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9584     SET_H_SR (((UINT) 7), opval);
9585     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9586   }
9587 {
9588   {
9589     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9590     CPU (h_cbit) = opval;
9591     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9592   }
9593   {
9594     BI opval = LTDI (tmp_tmpr, 0);
9595     CPU (h_nbit) = opval;
9596     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9597   }
9598   {
9599     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9600     CPU (h_zbit) = opval;
9601     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9602   }
9603   {
9604     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9605     CPU (h_vbit) = opval;
9606     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9607   }
9608 {
9609   {
9610     BI opval = 0;
9611     CPU (h_xbit) = opval;
9612     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9613   }
9614   {
9615     BI opval = 0;
9616     SET_H_INSN_PREFIXED_P (opval);
9617     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9618   }
9619 }
9620 }
9621 }
9622
9623 #undef FLD
9624 }
9625   NEXT (vpc);
9626
9627   CASE (sem, INSN_MSTEP) : /* mstep $Rs,$Rd */
9628 {
9629   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9630   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9631 #define FLD(f) abuf->fields.sfmt_muls_b.f
9632   int UNUSED written = 0;
9633   IADDR UNUSED pc = abuf->addr;
9634   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9635
9636 {
9637   SI tmp_tmpd;
9638   SI tmp_tmps;
9639   tmp_tmps = GET_H_GR (FLD (f_operand1));
9640   tmp_tmpd = ADDSI (SLLSI (GET_H_GR (FLD (f_operand2)), 1), ((CPU (h_nbit)) ? (tmp_tmps) : (0)));
9641   {
9642     SI opval = tmp_tmpd;
9643     SET_H_GR (FLD (f_operand2), opval);
9644     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9645   }
9646 {
9647   {
9648     BI opval = LTSI (tmp_tmpd, 0);
9649     CPU (h_nbit) = opval;
9650     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9651   }
9652   {
9653     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9654     CPU (h_zbit) = opval;
9655     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9656   }
9657 SET_H_CBIT_MOVE (0);
9658 SET_H_VBIT_MOVE (0);
9659 {
9660   {
9661     BI opval = 0;
9662     CPU (h_xbit) = opval;
9663     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9664   }
9665   {
9666     BI opval = 0;
9667     SET_H_INSN_PREFIXED_P (opval);
9668     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9669   }
9670 }
9671 }
9672 }
9673
9674 #undef FLD
9675 }
9676   NEXT (vpc);
9677
9678   CASE (sem, INSN_DSTEP) : /* dstep $Rs,$Rd */
9679 {
9680   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9681   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9682 #define FLD(f) abuf->fields.sfmt_muls_b.f
9683   int UNUSED written = 0;
9684   IADDR UNUSED pc = abuf->addr;
9685   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9686
9687 {
9688   SI tmp_tmp;
9689   SI tmp_tmps;
9690   SI tmp_tmpd;
9691   tmp_tmps = GET_H_GR (FLD (f_operand1));
9692   tmp_tmp = SLLSI (GET_H_GR (FLD (f_operand2)), 1);
9693   tmp_tmpd = ((GEUSI (tmp_tmp, tmp_tmps)) ? (SUBSI (tmp_tmp, tmp_tmps)) : (tmp_tmp));
9694   {
9695     SI opval = tmp_tmpd;
9696     SET_H_GR (FLD (f_operand2), opval);
9697     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9698   }
9699 {
9700   {
9701     BI opval = LTSI (tmp_tmpd, 0);
9702     CPU (h_nbit) = opval;
9703     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9704   }
9705   {
9706     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9707     CPU (h_zbit) = opval;
9708     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9709   }
9710 SET_H_CBIT_MOVE (0);
9711 SET_H_VBIT_MOVE (0);
9712 {
9713   {
9714     BI opval = 0;
9715     CPU (h_xbit) = opval;
9716     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9717   }
9718   {
9719     BI opval = 0;
9720     SET_H_INSN_PREFIXED_P (opval);
9721     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9722   }
9723 }
9724 }
9725 }
9726
9727 #undef FLD
9728 }
9729   NEXT (vpc);
9730
9731   CASE (sem, INSN_ABS) : /* abs $Rs,$Rd */
9732 {
9733   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9734   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9735 #define FLD(f) abuf->fields.sfmt_muls_b.f
9736   int UNUSED written = 0;
9737   IADDR UNUSED pc = abuf->addr;
9738   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9739
9740 {
9741   SI tmp_tmpd;
9742   tmp_tmpd = ABSSI (GET_H_GR (FLD (f_operand1)));
9743   {
9744     SI opval = tmp_tmpd;
9745     SET_H_GR (FLD (f_operand2), opval);
9746     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9747   }
9748 {
9749   {
9750     BI opval = LTSI (tmp_tmpd, 0);
9751     CPU (h_nbit) = opval;
9752     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9753   }
9754   {
9755     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9756     CPU (h_zbit) = opval;
9757     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9758   }
9759 SET_H_CBIT_MOVE (0);
9760 SET_H_VBIT_MOVE (0);
9761 {
9762   {
9763     BI opval = 0;
9764     CPU (h_xbit) = opval;
9765     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9766   }
9767   {
9768     BI opval = 0;
9769     SET_H_INSN_PREFIXED_P (opval);
9770     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9771   }
9772 }
9773 }
9774 }
9775
9776 #undef FLD
9777 }
9778   NEXT (vpc);
9779
9780   CASE (sem, INSN_AND_B_R) : /* and.b $Rs,$Rd */
9781 {
9782   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9783   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9784 #define FLD(f) abuf->fields.sfmt_add_b_r.f
9785   int UNUSED written = 0;
9786   IADDR UNUSED pc = abuf->addr;
9787   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9788
9789 {
9790   QI tmp_tmpd;
9791   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
9792 {
9793   SI tmp_oldregval;
9794   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
9795   {
9796     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
9797     SET_H_GR (FLD (f_operand2), opval);
9798     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9799   }
9800 }
9801 {
9802   {
9803     BI opval = LTQI (tmp_tmpd, 0);
9804     CPU (h_nbit) = opval;
9805     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9806   }
9807   {
9808     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9809     CPU (h_zbit) = opval;
9810     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9811   }
9812 SET_H_CBIT_MOVE (0);
9813 SET_H_VBIT_MOVE (0);
9814 {
9815   {
9816     BI opval = 0;
9817     CPU (h_xbit) = opval;
9818     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9819   }
9820   {
9821     BI opval = 0;
9822     SET_H_INSN_PREFIXED_P (opval);
9823     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9824   }
9825 }
9826 }
9827 }
9828
9829 #undef FLD
9830 }
9831   NEXT (vpc);
9832
9833   CASE (sem, INSN_AND_W_R) : /* and.w $Rs,$Rd */
9834 {
9835   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9836   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9837 #define FLD(f) abuf->fields.sfmt_add_b_r.f
9838   int UNUSED written = 0;
9839   IADDR UNUSED pc = abuf->addr;
9840   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9841
9842 {
9843   HI tmp_tmpd;
9844   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
9845 {
9846   SI tmp_oldregval;
9847   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
9848   {
9849     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
9850     SET_H_GR (FLD (f_operand2), opval);
9851     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9852   }
9853 }
9854 {
9855   {
9856     BI opval = LTHI (tmp_tmpd, 0);
9857     CPU (h_nbit) = opval;
9858     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9859   }
9860   {
9861     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9862     CPU (h_zbit) = opval;
9863     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9864   }
9865 SET_H_CBIT_MOVE (0);
9866 SET_H_VBIT_MOVE (0);
9867 {
9868   {
9869     BI opval = 0;
9870     CPU (h_xbit) = opval;
9871     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9872   }
9873   {
9874     BI opval = 0;
9875     SET_H_INSN_PREFIXED_P (opval);
9876     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9877   }
9878 }
9879 }
9880 }
9881
9882 #undef FLD
9883 }
9884   NEXT (vpc);
9885
9886   CASE (sem, INSN_AND_D_R) : /* and.d $Rs,$Rd */
9887 {
9888   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9889   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9890 #define FLD(f) abuf->fields.sfmt_add_b_r.f
9891   int UNUSED written = 0;
9892   IADDR UNUSED pc = abuf->addr;
9893   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9894
9895 {
9896   SI tmp_tmpd;
9897   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
9898   {
9899     SI opval = tmp_tmpd;
9900     SET_H_GR (FLD (f_operand2), opval);
9901     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9902   }
9903 {
9904   {
9905     BI opval = LTSI (tmp_tmpd, 0);
9906     CPU (h_nbit) = opval;
9907     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9908   }
9909   {
9910     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9911     CPU (h_zbit) = opval;
9912     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9913   }
9914 SET_H_CBIT_MOVE (0);
9915 SET_H_VBIT_MOVE (0);
9916 {
9917   {
9918     BI opval = 0;
9919     CPU (h_xbit) = opval;
9920     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9921   }
9922   {
9923     BI opval = 0;
9924     SET_H_INSN_PREFIXED_P (opval);
9925     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9926   }
9927 }
9928 }
9929 }
9930
9931 #undef FLD
9932 }
9933   NEXT (vpc);
9934
9935   CASE (sem, INSN_AND_M_B_M) : /* and-m.b [${Rs}${inc}],${Rd} */
9936 {
9937   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9938   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9939 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
9940   int UNUSED written = 0;
9941   IADDR UNUSED pc = abuf->addr;
9942   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9943
9944 {
9945   QI tmp_tmpd;
9946   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
9947   QI tmp_tmp_mem;
9948   BI tmp_postinc;
9949   tmp_postinc = FLD (f_memmode);
9950 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9951 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
9952 ; if (NEBI (tmp_postinc, 0)) {
9953 {
9954 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9955   tmp_addr = ADDSI (tmp_addr, 1);
9956 }
9957   {
9958     SI opval = tmp_addr;
9959     SET_H_GR (FLD (f_operand1), opval);
9960     written |= (1 << 11);
9961     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9962   }
9963 }
9964 }
9965 ; tmp_tmp_mem; }));
9966 {
9967   SI tmp_oldregval;
9968   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
9969   {
9970     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
9971     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
9972     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9973   }
9974 }
9975 {
9976   {
9977     BI opval = LTQI (tmp_tmpd, 0);
9978     CPU (h_nbit) = opval;
9979     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9980   }
9981   {
9982     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9983     CPU (h_zbit) = opval;
9984     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9985   }
9986 SET_H_CBIT_MOVE (0);
9987 SET_H_VBIT_MOVE (0);
9988 {
9989   {
9990     BI opval = 0;
9991     CPU (h_xbit) = opval;
9992     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9993   }
9994   {
9995     BI opval = 0;
9996     SET_H_INSN_PREFIXED_P (opval);
9997     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9998   }
9999 }
10000 }
10001 }
10002
10003   abuf->written = written;
10004 #undef FLD
10005 }
10006   NEXT (vpc);
10007
10008   CASE (sem, INSN_AND_M_W_M) : /* and-m.w [${Rs}${inc}],${Rd} */
10009 {
10010   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10011   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10012 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10013   int UNUSED written = 0;
10014   IADDR UNUSED pc = abuf->addr;
10015   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10016
10017 {
10018   HI tmp_tmpd;
10019   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10020   HI tmp_tmp_mem;
10021   BI tmp_postinc;
10022   tmp_postinc = FLD (f_memmode);
10023 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10024 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10025 ; if (NEBI (tmp_postinc, 0)) {
10026 {
10027 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10028   tmp_addr = ADDSI (tmp_addr, 2);
10029 }
10030   {
10031     SI opval = tmp_addr;
10032     SET_H_GR (FLD (f_operand1), opval);
10033     written |= (1 << 11);
10034     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10035   }
10036 }
10037 }
10038 ; tmp_tmp_mem; }));
10039 {
10040   SI tmp_oldregval;
10041   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10042   {
10043     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10044     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10045     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10046   }
10047 }
10048 {
10049   {
10050     BI opval = LTHI (tmp_tmpd, 0);
10051     CPU (h_nbit) = opval;
10052     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10053   }
10054   {
10055     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10056     CPU (h_zbit) = opval;
10057     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10058   }
10059 SET_H_CBIT_MOVE (0);
10060 SET_H_VBIT_MOVE (0);
10061 {
10062   {
10063     BI opval = 0;
10064     CPU (h_xbit) = opval;
10065     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10066   }
10067   {
10068     BI opval = 0;
10069     SET_H_INSN_PREFIXED_P (opval);
10070     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10071   }
10072 }
10073 }
10074 }
10075
10076   abuf->written = written;
10077 #undef FLD
10078 }
10079   NEXT (vpc);
10080
10081   CASE (sem, INSN_AND_M_D_M) : /* and-m.d [${Rs}${inc}],${Rd} */
10082 {
10083   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10084   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10085 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10086   int UNUSED written = 0;
10087   IADDR UNUSED pc = abuf->addr;
10088   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10089
10090 {
10091   SI tmp_tmpd;
10092   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10093   SI tmp_tmp_mem;
10094   BI tmp_postinc;
10095   tmp_postinc = FLD (f_memmode);
10096 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10097 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10098 ; if (NEBI (tmp_postinc, 0)) {
10099 {
10100 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10101   tmp_addr = ADDSI (tmp_addr, 4);
10102 }
10103   {
10104     SI opval = tmp_addr;
10105     SET_H_GR (FLD (f_operand1), opval);
10106     written |= (1 << 10);
10107     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10108   }
10109 }
10110 }
10111 ; tmp_tmp_mem; }));
10112   {
10113     SI opval = tmp_tmpd;
10114     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10115     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10116   }
10117 {
10118   {
10119     BI opval = LTSI (tmp_tmpd, 0);
10120     CPU (h_nbit) = opval;
10121     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10122   }
10123   {
10124     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10125     CPU (h_zbit) = opval;
10126     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10127   }
10128 SET_H_CBIT_MOVE (0);
10129 SET_H_VBIT_MOVE (0);
10130 {
10131   {
10132     BI opval = 0;
10133     CPU (h_xbit) = opval;
10134     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10135   }
10136   {
10137     BI opval = 0;
10138     SET_H_INSN_PREFIXED_P (opval);
10139     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10140   }
10141 }
10142 }
10143 }
10144
10145   abuf->written = written;
10146 #undef FLD
10147 }
10148   NEXT (vpc);
10149
10150   CASE (sem, INSN_ANDCBR) : /* and.b ${sconst8}],${Rd} */
10151 {
10152   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10153   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10154 #define FLD(f) abuf->fields.sfmt_addcbr.f
10155   int UNUSED written = 0;
10156   IADDR UNUSED pc = abuf->addr;
10157   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10158
10159 {
10160   QI tmp_tmpd;
10161   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
10162 {
10163   SI tmp_oldregval;
10164   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10165   {
10166     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10167     SET_H_GR (FLD (f_operand2), opval);
10168     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10169   }
10170 }
10171 {
10172   {
10173     BI opval = LTQI (tmp_tmpd, 0);
10174     CPU (h_nbit) = opval;
10175     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10176   }
10177   {
10178     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10179     CPU (h_zbit) = opval;
10180     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10181   }
10182 SET_H_CBIT_MOVE (0);
10183 SET_H_VBIT_MOVE (0);
10184 {
10185   {
10186     BI opval = 0;
10187     CPU (h_xbit) = opval;
10188     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10189   }
10190   {
10191     BI opval = 0;
10192     SET_H_INSN_PREFIXED_P (opval);
10193     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10194   }
10195 }
10196 }
10197 }
10198
10199 #undef FLD
10200 }
10201   NEXT (vpc);
10202
10203   CASE (sem, INSN_ANDCWR) : /* and.w ${sconst16}],${Rd} */
10204 {
10205   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10206   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10207 #define FLD(f) abuf->fields.sfmt_addcwr.f
10208   int UNUSED written = 0;
10209   IADDR UNUSED pc = abuf->addr;
10210   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10211
10212 {
10213   HI tmp_tmpd;
10214   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
10215 {
10216   SI tmp_oldregval;
10217   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10218   {
10219     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10220     SET_H_GR (FLD (f_operand2), opval);
10221     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10222   }
10223 }
10224 {
10225   {
10226     BI opval = LTHI (tmp_tmpd, 0);
10227     CPU (h_nbit) = opval;
10228     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10229   }
10230   {
10231     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10232     CPU (h_zbit) = opval;
10233     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10234   }
10235 SET_H_CBIT_MOVE (0);
10236 SET_H_VBIT_MOVE (0);
10237 {
10238   {
10239     BI opval = 0;
10240     CPU (h_xbit) = opval;
10241     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10242   }
10243   {
10244     BI opval = 0;
10245     SET_H_INSN_PREFIXED_P (opval);
10246     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10247   }
10248 }
10249 }
10250 }
10251
10252 #undef FLD
10253 }
10254   NEXT (vpc);
10255
10256   CASE (sem, INSN_ANDCDR) : /* and.d ${const32}],${Rd} */
10257 {
10258   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10259   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10260 #define FLD(f) abuf->fields.sfmt_addcdr.f
10261   int UNUSED written = 0;
10262   IADDR UNUSED pc = abuf->addr;
10263   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
10264
10265 {
10266   SI tmp_tmpd;
10267   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
10268   {
10269     SI opval = tmp_tmpd;
10270     SET_H_GR (FLD (f_operand2), opval);
10271     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10272   }
10273 {
10274   {
10275     BI opval = LTSI (tmp_tmpd, 0);
10276     CPU (h_nbit) = opval;
10277     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10278   }
10279   {
10280     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10281     CPU (h_zbit) = opval;
10282     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10283   }
10284 SET_H_CBIT_MOVE (0);
10285 SET_H_VBIT_MOVE (0);
10286 {
10287   {
10288     BI opval = 0;
10289     CPU (h_xbit) = opval;
10290     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10291   }
10292   {
10293     BI opval = 0;
10294     SET_H_INSN_PREFIXED_P (opval);
10295     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10296   }
10297 }
10298 }
10299 }
10300
10301 #undef FLD
10302 }
10303   NEXT (vpc);
10304
10305   CASE (sem, INSN_ANDQ) : /* andq $i,$Rd */
10306 {
10307   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10308   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10309 #define FLD(f) abuf->fields.sfmt_andq.f
10310   int UNUSED written = 0;
10311   IADDR UNUSED pc = abuf->addr;
10312   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10313
10314 {
10315   SI tmp_tmpd;
10316   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
10317   {
10318     SI opval = tmp_tmpd;
10319     SET_H_GR (FLD (f_operand2), opval);
10320     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10321   }
10322 {
10323   {
10324     BI opval = LTSI (tmp_tmpd, 0);
10325     CPU (h_nbit) = opval;
10326     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10327   }
10328   {
10329     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10330     CPU (h_zbit) = opval;
10331     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10332   }
10333 SET_H_CBIT_MOVE (0);
10334 SET_H_VBIT_MOVE (0);
10335 {
10336   {
10337     BI opval = 0;
10338     CPU (h_xbit) = opval;
10339     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10340   }
10341   {
10342     BI opval = 0;
10343     SET_H_INSN_PREFIXED_P (opval);
10344     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10345   }
10346 }
10347 }
10348 }
10349
10350 #undef FLD
10351 }
10352   NEXT (vpc);
10353
10354   CASE (sem, INSN_ORR_B_R) : /* orr.b $Rs,$Rd */
10355 {
10356   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10357   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10358 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10359   int UNUSED written = 0;
10360   IADDR UNUSED pc = abuf->addr;
10361   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10362
10363 {
10364   QI tmp_tmpd;
10365   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10366 {
10367   SI tmp_oldregval;
10368   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10369   {
10370     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10371     SET_H_GR (FLD (f_operand2), opval);
10372     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10373   }
10374 }
10375 {
10376   {
10377     BI opval = LTQI (tmp_tmpd, 0);
10378     CPU (h_nbit) = opval;
10379     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10380   }
10381   {
10382     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10383     CPU (h_zbit) = opval;
10384     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10385   }
10386 SET_H_CBIT_MOVE (0);
10387 SET_H_VBIT_MOVE (0);
10388 {
10389   {
10390     BI opval = 0;
10391     CPU (h_xbit) = opval;
10392     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10393   }
10394   {
10395     BI opval = 0;
10396     SET_H_INSN_PREFIXED_P (opval);
10397     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10398   }
10399 }
10400 }
10401 }
10402
10403 #undef FLD
10404 }
10405   NEXT (vpc);
10406
10407   CASE (sem, INSN_ORR_W_R) : /* orr.w $Rs,$Rd */
10408 {
10409   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10410   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10411 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10412   int UNUSED written = 0;
10413   IADDR UNUSED pc = abuf->addr;
10414   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10415
10416 {
10417   HI tmp_tmpd;
10418   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10419 {
10420   SI tmp_oldregval;
10421   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10422   {
10423     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10424     SET_H_GR (FLD (f_operand2), opval);
10425     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10426   }
10427 }
10428 {
10429   {
10430     BI opval = LTHI (tmp_tmpd, 0);
10431     CPU (h_nbit) = opval;
10432     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10433   }
10434   {
10435     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10436     CPU (h_zbit) = opval;
10437     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10438   }
10439 SET_H_CBIT_MOVE (0);
10440 SET_H_VBIT_MOVE (0);
10441 {
10442   {
10443     BI opval = 0;
10444     CPU (h_xbit) = opval;
10445     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10446   }
10447   {
10448     BI opval = 0;
10449     SET_H_INSN_PREFIXED_P (opval);
10450     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10451   }
10452 }
10453 }
10454 }
10455
10456 #undef FLD
10457 }
10458   NEXT (vpc);
10459
10460   CASE (sem, INSN_ORR_D_R) : /* orr.d $Rs,$Rd */
10461 {
10462   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10463   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10464 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10465   int UNUSED written = 0;
10466   IADDR UNUSED pc = abuf->addr;
10467   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10468
10469 {
10470   SI tmp_tmpd;
10471   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10472   {
10473     SI opval = tmp_tmpd;
10474     SET_H_GR (FLD (f_operand2), opval);
10475     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10476   }
10477 {
10478   {
10479     BI opval = LTSI (tmp_tmpd, 0);
10480     CPU (h_nbit) = opval;
10481     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10482   }
10483   {
10484     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10485     CPU (h_zbit) = opval;
10486     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10487   }
10488 SET_H_CBIT_MOVE (0);
10489 SET_H_VBIT_MOVE (0);
10490 {
10491   {
10492     BI opval = 0;
10493     CPU (h_xbit) = opval;
10494     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10495   }
10496   {
10497     BI opval = 0;
10498     SET_H_INSN_PREFIXED_P (opval);
10499     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10500   }
10501 }
10502 }
10503 }
10504
10505 #undef FLD
10506 }
10507   NEXT (vpc);
10508
10509   CASE (sem, INSN_OR_M_B_M) : /* or-m.b [${Rs}${inc}],${Rd} */
10510 {
10511   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10512   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10513 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10514   int UNUSED written = 0;
10515   IADDR UNUSED pc = abuf->addr;
10516   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10517
10518 {
10519   QI tmp_tmpd;
10520   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10521   QI tmp_tmp_mem;
10522   BI tmp_postinc;
10523   tmp_postinc = FLD (f_memmode);
10524 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10525 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
10526 ; if (NEBI (tmp_postinc, 0)) {
10527 {
10528 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10529   tmp_addr = ADDSI (tmp_addr, 1);
10530 }
10531   {
10532     SI opval = tmp_addr;
10533     SET_H_GR (FLD (f_operand1), opval);
10534     written |= (1 << 11);
10535     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10536   }
10537 }
10538 }
10539 ; tmp_tmp_mem; }));
10540 {
10541   SI tmp_oldregval;
10542   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10543   {
10544     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10545     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10546     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10547   }
10548 }
10549 {
10550   {
10551     BI opval = LTQI (tmp_tmpd, 0);
10552     CPU (h_nbit) = opval;
10553     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10554   }
10555   {
10556     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10557     CPU (h_zbit) = opval;
10558     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10559   }
10560 SET_H_CBIT_MOVE (0);
10561 SET_H_VBIT_MOVE (0);
10562 {
10563   {
10564     BI opval = 0;
10565     CPU (h_xbit) = opval;
10566     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10567   }
10568   {
10569     BI opval = 0;
10570     SET_H_INSN_PREFIXED_P (opval);
10571     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10572   }
10573 }
10574 }
10575 }
10576
10577   abuf->written = written;
10578 #undef FLD
10579 }
10580   NEXT (vpc);
10581
10582   CASE (sem, INSN_OR_M_W_M) : /* or-m.w [${Rs}${inc}],${Rd} */
10583 {
10584   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10585   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10586 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10587   int UNUSED written = 0;
10588   IADDR UNUSED pc = abuf->addr;
10589   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10590
10591 {
10592   HI tmp_tmpd;
10593   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10594   HI tmp_tmp_mem;
10595   BI tmp_postinc;
10596   tmp_postinc = FLD (f_memmode);
10597 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10598 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10599 ; if (NEBI (tmp_postinc, 0)) {
10600 {
10601 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10602   tmp_addr = ADDSI (tmp_addr, 2);
10603 }
10604   {
10605     SI opval = tmp_addr;
10606     SET_H_GR (FLD (f_operand1), opval);
10607     written |= (1 << 11);
10608     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10609   }
10610 }
10611 }
10612 ; tmp_tmp_mem; }));
10613 {
10614   SI tmp_oldregval;
10615   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10616   {
10617     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10618     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10619     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10620   }
10621 }
10622 {
10623   {
10624     BI opval = LTHI (tmp_tmpd, 0);
10625     CPU (h_nbit) = opval;
10626     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10627   }
10628   {
10629     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10630     CPU (h_zbit) = opval;
10631     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10632   }
10633 SET_H_CBIT_MOVE (0);
10634 SET_H_VBIT_MOVE (0);
10635 {
10636   {
10637     BI opval = 0;
10638     CPU (h_xbit) = opval;
10639     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10640   }
10641   {
10642     BI opval = 0;
10643     SET_H_INSN_PREFIXED_P (opval);
10644     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10645   }
10646 }
10647 }
10648 }
10649
10650   abuf->written = written;
10651 #undef FLD
10652 }
10653   NEXT (vpc);
10654
10655   CASE (sem, INSN_OR_M_D_M) : /* or-m.d [${Rs}${inc}],${Rd} */
10656 {
10657   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10658   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10659 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10660   int UNUSED written = 0;
10661   IADDR UNUSED pc = abuf->addr;
10662   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10663
10664 {
10665   SI tmp_tmpd;
10666   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10667   SI tmp_tmp_mem;
10668   BI tmp_postinc;
10669   tmp_postinc = FLD (f_memmode);
10670 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10671 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10672 ; if (NEBI (tmp_postinc, 0)) {
10673 {
10674 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10675   tmp_addr = ADDSI (tmp_addr, 4);
10676 }
10677   {
10678     SI opval = tmp_addr;
10679     SET_H_GR (FLD (f_operand1), opval);
10680     written |= (1 << 10);
10681     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10682   }
10683 }
10684 }
10685 ; tmp_tmp_mem; }));
10686   {
10687     SI opval = tmp_tmpd;
10688     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10689     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10690   }
10691 {
10692   {
10693     BI opval = LTSI (tmp_tmpd, 0);
10694     CPU (h_nbit) = opval;
10695     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10696   }
10697   {
10698     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10699     CPU (h_zbit) = opval;
10700     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10701   }
10702 SET_H_CBIT_MOVE (0);
10703 SET_H_VBIT_MOVE (0);
10704 {
10705   {
10706     BI opval = 0;
10707     CPU (h_xbit) = opval;
10708     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10709   }
10710   {
10711     BI opval = 0;
10712     SET_H_INSN_PREFIXED_P (opval);
10713     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10714   }
10715 }
10716 }
10717 }
10718
10719   abuf->written = written;
10720 #undef FLD
10721 }
10722   NEXT (vpc);
10723
10724   CASE (sem, INSN_ORCBR) : /* or.b ${sconst8}],${Rd} */
10725 {
10726   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10727   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10728 #define FLD(f) abuf->fields.sfmt_addcbr.f
10729   int UNUSED written = 0;
10730   IADDR UNUSED pc = abuf->addr;
10731   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10732
10733 {
10734   QI tmp_tmpd;
10735   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
10736 {
10737   SI tmp_oldregval;
10738   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10739   {
10740     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10741     SET_H_GR (FLD (f_operand2), opval);
10742     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10743   }
10744 }
10745 {
10746   {
10747     BI opval = LTQI (tmp_tmpd, 0);
10748     CPU (h_nbit) = opval;
10749     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10750   }
10751   {
10752     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10753     CPU (h_zbit) = opval;
10754     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10755   }
10756 SET_H_CBIT_MOVE (0);
10757 SET_H_VBIT_MOVE (0);
10758 {
10759   {
10760     BI opval = 0;
10761     CPU (h_xbit) = opval;
10762     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10763   }
10764   {
10765     BI opval = 0;
10766     SET_H_INSN_PREFIXED_P (opval);
10767     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10768   }
10769 }
10770 }
10771 }
10772
10773 #undef FLD
10774 }
10775   NEXT (vpc);
10776
10777   CASE (sem, INSN_ORCWR) : /* or.w ${sconst16}],${Rd} */
10778 {
10779   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10780   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10781 #define FLD(f) abuf->fields.sfmt_addcwr.f
10782   int UNUSED written = 0;
10783   IADDR UNUSED pc = abuf->addr;
10784   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10785
10786 {
10787   HI tmp_tmpd;
10788   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
10789 {
10790   SI tmp_oldregval;
10791   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10792   {
10793     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10794     SET_H_GR (FLD (f_operand2), opval);
10795     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10796   }
10797 }
10798 {
10799   {
10800     BI opval = LTHI (tmp_tmpd, 0);
10801     CPU (h_nbit) = opval;
10802     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10803   }
10804   {
10805     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10806     CPU (h_zbit) = opval;
10807     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10808   }
10809 SET_H_CBIT_MOVE (0);
10810 SET_H_VBIT_MOVE (0);
10811 {
10812   {
10813     BI opval = 0;
10814     CPU (h_xbit) = opval;
10815     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10816   }
10817   {
10818     BI opval = 0;
10819     SET_H_INSN_PREFIXED_P (opval);
10820     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10821   }
10822 }
10823 }
10824 }
10825
10826 #undef FLD
10827 }
10828   NEXT (vpc);
10829
10830   CASE (sem, INSN_ORCDR) : /* or.d ${const32}],${Rd} */
10831 {
10832   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10833   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10834 #define FLD(f) abuf->fields.sfmt_addcdr.f
10835   int UNUSED written = 0;
10836   IADDR UNUSED pc = abuf->addr;
10837   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
10838
10839 {
10840   SI tmp_tmpd;
10841   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
10842   {
10843     SI opval = tmp_tmpd;
10844     SET_H_GR (FLD (f_operand2), opval);
10845     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10846   }
10847 {
10848   {
10849     BI opval = LTSI (tmp_tmpd, 0);
10850     CPU (h_nbit) = opval;
10851     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10852   }
10853   {
10854     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10855     CPU (h_zbit) = opval;
10856     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10857   }
10858 SET_H_CBIT_MOVE (0);
10859 SET_H_VBIT_MOVE (0);
10860 {
10861   {
10862     BI opval = 0;
10863     CPU (h_xbit) = opval;
10864     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10865   }
10866   {
10867     BI opval = 0;
10868     SET_H_INSN_PREFIXED_P (opval);
10869     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10870   }
10871 }
10872 }
10873 }
10874
10875 #undef FLD
10876 }
10877   NEXT (vpc);
10878
10879   CASE (sem, INSN_ORQ) : /* orq $i,$Rd */
10880 {
10881   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10882   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10883 #define FLD(f) abuf->fields.sfmt_andq.f
10884   int UNUSED written = 0;
10885   IADDR UNUSED pc = abuf->addr;
10886   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10887
10888 {
10889   SI tmp_tmpd;
10890   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
10891   {
10892     SI opval = tmp_tmpd;
10893     SET_H_GR (FLD (f_operand2), opval);
10894     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10895   }
10896 {
10897   {
10898     BI opval = LTSI (tmp_tmpd, 0);
10899     CPU (h_nbit) = opval;
10900     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10901   }
10902   {
10903     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10904     CPU (h_zbit) = opval;
10905     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10906   }
10907 SET_H_CBIT_MOVE (0);
10908 SET_H_VBIT_MOVE (0);
10909 {
10910   {
10911     BI opval = 0;
10912     CPU (h_xbit) = opval;
10913     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10914   }
10915   {
10916     BI opval = 0;
10917     SET_H_INSN_PREFIXED_P (opval);
10918     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10919   }
10920 }
10921 }
10922 }
10923
10924 #undef FLD
10925 }
10926   NEXT (vpc);
10927
10928   CASE (sem, INSN_XOR) : /* xor $Rs,$Rd */
10929 {
10930   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10931   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10932 #define FLD(f) abuf->fields.sfmt_muls_b.f
10933   int UNUSED written = 0;
10934   IADDR UNUSED pc = abuf->addr;
10935   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10936
10937 {
10938   SI tmp_tmpd;
10939   tmp_tmpd = XORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10940   {
10941     SI opval = tmp_tmpd;
10942     SET_H_GR (FLD (f_operand2), opval);
10943     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10944   }
10945 {
10946   {
10947     BI opval = LTSI (tmp_tmpd, 0);
10948     CPU (h_nbit) = opval;
10949     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10950   }
10951   {
10952     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10953     CPU (h_zbit) = opval;
10954     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10955   }
10956 SET_H_CBIT_MOVE (0);
10957 SET_H_VBIT_MOVE (0);
10958 {
10959   {
10960     BI opval = 0;
10961     CPU (h_xbit) = opval;
10962     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10963   }
10964   {
10965     BI opval = 0;
10966     SET_H_INSN_PREFIXED_P (opval);
10967     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10968   }
10969 }
10970 }
10971 }
10972
10973 #undef FLD
10974 }
10975   NEXT (vpc);
10976
10977   CASE (sem, INSN_SWAP) : /* swap${swapoption} ${Rs} */
10978 {
10979   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10980   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10981 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
10982   int UNUSED written = 0;
10983   IADDR UNUSED pc = abuf->addr;
10984   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10985
10986 {
10987   SI tmp_tmps;
10988   SI tmp_tmpd;
10989   tmp_tmps = GET_H_GR (FLD (f_operand1));
10990   tmp_tmpd = ({   SI tmp_tmpcode;
10991   SI tmp_tmpval;
10992   SI tmp_tmpres;
10993   tmp_tmpcode = FLD (f_operand2);
10994 ;   tmp_tmpval = tmp_tmps;
10995 ; if (EQSI (tmp_tmpcode, 0)) {
10996   tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
10997 }
10998  else if (EQSI (tmp_tmpcode, 1)) {
10999   tmp_tmpres = ({   SI tmp_tmpr;
11000   tmp_tmpr = tmp_tmpval;
11001 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11002 }
11003  else if (EQSI (tmp_tmpcode, 2)) {
11004   tmp_tmpres = ({   SI tmp_tmpb;
11005   tmp_tmpb = tmp_tmpval;
11006 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11007 }
11008  else if (EQSI (tmp_tmpcode, 3)) {
11009   tmp_tmpres = ({   SI tmp_tmpr;
11010   tmp_tmpr = ({   SI tmp_tmpb;
11011   tmp_tmpb = tmp_tmpval;
11012 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11013 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11014 }
11015  else if (EQSI (tmp_tmpcode, 4)) {
11016   tmp_tmpres = ({   SI tmp_tmpb;
11017   tmp_tmpb = tmp_tmpval;
11018 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11019 }
11020  else if (EQSI (tmp_tmpcode, 5)) {
11021   tmp_tmpres = ({   SI tmp_tmpr;
11022   tmp_tmpr = ({   SI tmp_tmpb;
11023   tmp_tmpb = tmp_tmpval;
11024 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11025 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11026 }
11027  else if (EQSI (tmp_tmpcode, 6)) {
11028   tmp_tmpres = ({   SI tmp_tmpb;
11029   tmp_tmpb = ({   SI tmp_tmpb;
11030   tmp_tmpb = tmp_tmpval;
11031 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11032 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11033 }
11034  else if (EQSI (tmp_tmpcode, 7)) {
11035   tmp_tmpres = ({   SI tmp_tmpr;
11036   tmp_tmpr = ({   SI tmp_tmpb;
11037   tmp_tmpb = ({   SI tmp_tmpb;
11038   tmp_tmpb = tmp_tmpval;
11039 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11040 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11041 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11042 }
11043  else if (EQSI (tmp_tmpcode, 8)) {
11044   tmp_tmpres = INVSI (tmp_tmpval);
11045 }
11046  else if (EQSI (tmp_tmpcode, 9)) {
11047   tmp_tmpres = ({   SI tmp_tmpr;
11048   tmp_tmpr = INVSI (tmp_tmpval);
11049 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11050 }
11051  else if (EQSI (tmp_tmpcode, 10)) {
11052   tmp_tmpres = ({   SI tmp_tmpb;
11053   tmp_tmpb = INVSI (tmp_tmpval);
11054 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11055 }
11056  else if (EQSI (tmp_tmpcode, 11)) {
11057   tmp_tmpres = ({   SI tmp_tmpr;
11058   tmp_tmpr = ({   SI tmp_tmpb;
11059   tmp_tmpb = INVSI (tmp_tmpval);
11060 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11061 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11062 }
11063  else if (EQSI (tmp_tmpcode, 12)) {
11064   tmp_tmpres = ({   SI tmp_tmpb;
11065   tmp_tmpb = INVSI (tmp_tmpval);
11066 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11067 }
11068  else if (EQSI (tmp_tmpcode, 13)) {
11069   tmp_tmpres = ({   SI tmp_tmpr;
11070   tmp_tmpr = ({   SI tmp_tmpb;
11071   tmp_tmpb = INVSI (tmp_tmpval);
11072 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11073 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11074 }
11075  else if (EQSI (tmp_tmpcode, 14)) {
11076   tmp_tmpres = ({   SI tmp_tmpb;
11077   tmp_tmpb = ({   SI tmp_tmpb;
11078   tmp_tmpb = INVSI (tmp_tmpval);
11079 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11080 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11081 }
11082  else if (EQSI (tmp_tmpcode, 15)) {
11083   tmp_tmpres = ({   SI tmp_tmpr;
11084   tmp_tmpr = ({   SI tmp_tmpb;
11085   tmp_tmpb = ({   SI tmp_tmpb;
11086   tmp_tmpb = INVSI (tmp_tmpval);
11087 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11088 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11089 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11090 }
11091 ; tmp_tmpres; });
11092   {
11093     SI opval = tmp_tmpd;
11094     SET_H_GR (FLD (f_operand1), opval);
11095     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11096   }
11097 {
11098   {
11099     BI opval = LTSI (tmp_tmpd, 0);
11100     CPU (h_nbit) = opval;
11101     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11102   }
11103   {
11104     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11105     CPU (h_zbit) = opval;
11106     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11107   }
11108 SET_H_CBIT_MOVE (0);
11109 SET_H_VBIT_MOVE (0);
11110 {
11111   {
11112     BI opval = 0;
11113     CPU (h_xbit) = opval;
11114     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11115   }
11116   {
11117     BI opval = 0;
11118     SET_H_INSN_PREFIXED_P (opval);
11119     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11120   }
11121 }
11122 }
11123 }
11124
11125 #undef FLD
11126 }
11127   NEXT (vpc);
11128
11129   CASE (sem, INSN_ASRR_B_R) : /* asrr.b $Rs,$Rd */
11130 {
11131   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11132   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11133 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11134   int UNUSED written = 0;
11135   IADDR UNUSED pc = abuf->addr;
11136   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11137
11138 {
11139   QI tmp_tmpd;
11140   SI tmp_cnt1;
11141   SI tmp_cnt2;
11142   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11143   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11144   tmp_tmpd = SRASI (EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11145 {
11146   SI tmp_oldregval;
11147   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11148   {
11149     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11150     SET_H_GR (FLD (f_operand2), opval);
11151     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11152   }
11153 }
11154 {
11155   {
11156     BI opval = LTQI (tmp_tmpd, 0);
11157     CPU (h_nbit) = opval;
11158     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11159   }
11160   {
11161     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11162     CPU (h_zbit) = opval;
11163     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11164   }
11165 SET_H_CBIT_MOVE (0);
11166 SET_H_VBIT_MOVE (0);
11167 {
11168   {
11169     BI opval = 0;
11170     CPU (h_xbit) = opval;
11171     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11172   }
11173   {
11174     BI opval = 0;
11175     SET_H_INSN_PREFIXED_P (opval);
11176     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11177   }
11178 }
11179 }
11180 }
11181
11182 #undef FLD
11183 }
11184   NEXT (vpc);
11185
11186   CASE (sem, INSN_ASRR_W_R) : /* asrr.w $Rs,$Rd */
11187 {
11188   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11189   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11190 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11191   int UNUSED written = 0;
11192   IADDR UNUSED pc = abuf->addr;
11193   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11194
11195 {
11196   HI tmp_tmpd;
11197   SI tmp_cnt1;
11198   SI tmp_cnt2;
11199   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11200   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11201   tmp_tmpd = SRASI (EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11202 {
11203   SI tmp_oldregval;
11204   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11205   {
11206     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11207     SET_H_GR (FLD (f_operand2), opval);
11208     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11209   }
11210 }
11211 {
11212   {
11213     BI opval = LTHI (tmp_tmpd, 0);
11214     CPU (h_nbit) = opval;
11215     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11216   }
11217   {
11218     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11219     CPU (h_zbit) = opval;
11220     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11221   }
11222 SET_H_CBIT_MOVE (0);
11223 SET_H_VBIT_MOVE (0);
11224 {
11225   {
11226     BI opval = 0;
11227     CPU (h_xbit) = opval;
11228     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11229   }
11230   {
11231     BI opval = 0;
11232     SET_H_INSN_PREFIXED_P (opval);
11233     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11234   }
11235 }
11236 }
11237 }
11238
11239 #undef FLD
11240 }
11241   NEXT (vpc);
11242
11243   CASE (sem, INSN_ASRR_D_R) : /* asrr.d $Rs,$Rd */
11244 {
11245   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11246   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11247 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11248   int UNUSED written = 0;
11249   IADDR UNUSED pc = abuf->addr;
11250   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11251
11252 {
11253   SI tmp_tmpd;
11254   SI tmp_cnt1;
11255   SI tmp_cnt2;
11256   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11257   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11258   tmp_tmpd = SRASI (EXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11259   {
11260     SI opval = tmp_tmpd;
11261     SET_H_GR (FLD (f_operand2), opval);
11262     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11263   }
11264 {
11265   {
11266     BI opval = LTSI (tmp_tmpd, 0);
11267     CPU (h_nbit) = opval;
11268     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11269   }
11270   {
11271     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11272     CPU (h_zbit) = opval;
11273     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11274   }
11275 SET_H_CBIT_MOVE (0);
11276 SET_H_VBIT_MOVE (0);
11277 {
11278   {
11279     BI opval = 0;
11280     CPU (h_xbit) = opval;
11281     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11282   }
11283   {
11284     BI opval = 0;
11285     SET_H_INSN_PREFIXED_P (opval);
11286     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11287   }
11288 }
11289 }
11290 }
11291
11292 #undef FLD
11293 }
11294   NEXT (vpc);
11295
11296   CASE (sem, INSN_ASRQ) : /* asrq $c,${Rd} */
11297 {
11298   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11299   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11300 #define FLD(f) abuf->fields.sfmt_asrq.f
11301   int UNUSED written = 0;
11302   IADDR UNUSED pc = abuf->addr;
11303   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11304
11305 {
11306   SI tmp_tmpd;
11307   tmp_tmpd = SRASI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11308   {
11309     SI opval = tmp_tmpd;
11310     SET_H_GR (FLD (f_operand2), opval);
11311     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11312   }
11313 {
11314   {
11315     BI opval = LTSI (tmp_tmpd, 0);
11316     CPU (h_nbit) = opval;
11317     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11318   }
11319   {
11320     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11321     CPU (h_zbit) = opval;
11322     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11323   }
11324 SET_H_CBIT_MOVE (0);
11325 SET_H_VBIT_MOVE (0);
11326 {
11327   {
11328     BI opval = 0;
11329     CPU (h_xbit) = opval;
11330     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11331   }
11332   {
11333     BI opval = 0;
11334     SET_H_INSN_PREFIXED_P (opval);
11335     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11336   }
11337 }
11338 }
11339 }
11340
11341 #undef FLD
11342 }
11343   NEXT (vpc);
11344
11345   CASE (sem, INSN_LSRR_B_R) : /* lsrr.b $Rs,$Rd */
11346 {
11347   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11348   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11349 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11350   int UNUSED written = 0;
11351   IADDR UNUSED pc = abuf->addr;
11352   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11353
11354 {
11355   SI tmp_tmpd;
11356   SI tmp_cnt;
11357   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11358   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11359 {
11360   SI tmp_oldregval;
11361   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11362   {
11363     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11364     SET_H_GR (FLD (f_operand2), opval);
11365     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11366   }
11367 }
11368 {
11369   {
11370     BI opval = LTQI (tmp_tmpd, 0);
11371     CPU (h_nbit) = opval;
11372     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11373   }
11374   {
11375     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11376     CPU (h_zbit) = opval;
11377     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11378   }
11379 SET_H_CBIT_MOVE (0);
11380 SET_H_VBIT_MOVE (0);
11381 {
11382   {
11383     BI opval = 0;
11384     CPU (h_xbit) = opval;
11385     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11386   }
11387   {
11388     BI opval = 0;
11389     SET_H_INSN_PREFIXED_P (opval);
11390     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11391   }
11392 }
11393 }
11394 }
11395
11396 #undef FLD
11397 }
11398   NEXT (vpc);
11399
11400   CASE (sem, INSN_LSRR_W_R) : /* lsrr.w $Rs,$Rd */
11401 {
11402   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11403   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11404 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11405   int UNUSED written = 0;
11406   IADDR UNUSED pc = abuf->addr;
11407   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11408
11409 {
11410   SI tmp_tmpd;
11411   SI tmp_cnt;
11412   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11413   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11414 {
11415   SI tmp_oldregval;
11416   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11417   {
11418     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11419     SET_H_GR (FLD (f_operand2), opval);
11420     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11421   }
11422 }
11423 {
11424   {
11425     BI opval = LTHI (tmp_tmpd, 0);
11426     CPU (h_nbit) = opval;
11427     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11428   }
11429   {
11430     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11431     CPU (h_zbit) = opval;
11432     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11433   }
11434 SET_H_CBIT_MOVE (0);
11435 SET_H_VBIT_MOVE (0);
11436 {
11437   {
11438     BI opval = 0;
11439     CPU (h_xbit) = opval;
11440     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11441   }
11442   {
11443     BI opval = 0;
11444     SET_H_INSN_PREFIXED_P (opval);
11445     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11446   }
11447 }
11448 }
11449 }
11450
11451 #undef FLD
11452 }
11453   NEXT (vpc);
11454
11455   CASE (sem, INSN_LSRR_D_R) : /* lsrr.d $Rs,$Rd */
11456 {
11457   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11458   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11459 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11460   int UNUSED written = 0;
11461   IADDR UNUSED pc = abuf->addr;
11462   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11463
11464 {
11465   SI tmp_tmpd;
11466   SI tmp_cnt;
11467   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11468   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11469   {
11470     SI opval = tmp_tmpd;
11471     SET_H_GR (FLD (f_operand2), opval);
11472     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11473   }
11474 {
11475   {
11476     BI opval = LTSI (tmp_tmpd, 0);
11477     CPU (h_nbit) = opval;
11478     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11479   }
11480   {
11481     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11482     CPU (h_zbit) = opval;
11483     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11484   }
11485 SET_H_CBIT_MOVE (0);
11486 SET_H_VBIT_MOVE (0);
11487 {
11488   {
11489     BI opval = 0;
11490     CPU (h_xbit) = opval;
11491     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11492   }
11493   {
11494     BI opval = 0;
11495     SET_H_INSN_PREFIXED_P (opval);
11496     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11497   }
11498 }
11499 }
11500 }
11501
11502 #undef FLD
11503 }
11504   NEXT (vpc);
11505
11506   CASE (sem, INSN_LSRQ) : /* lsrq $c,${Rd} */
11507 {
11508   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11509   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11510 #define FLD(f) abuf->fields.sfmt_asrq.f
11511   int UNUSED written = 0;
11512   IADDR UNUSED pc = abuf->addr;
11513   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11514
11515 {
11516   SI tmp_tmpd;
11517   tmp_tmpd = SRLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11518   {
11519     SI opval = tmp_tmpd;
11520     SET_H_GR (FLD (f_operand2), opval);
11521     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11522   }
11523 {
11524   {
11525     BI opval = LTSI (tmp_tmpd, 0);
11526     CPU (h_nbit) = opval;
11527     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11528   }
11529   {
11530     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11531     CPU (h_zbit) = opval;
11532     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11533   }
11534 SET_H_CBIT_MOVE (0);
11535 SET_H_VBIT_MOVE (0);
11536 {
11537   {
11538     BI opval = 0;
11539     CPU (h_xbit) = opval;
11540     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11541   }
11542   {
11543     BI opval = 0;
11544     SET_H_INSN_PREFIXED_P (opval);
11545     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11546   }
11547 }
11548 }
11549 }
11550
11551 #undef FLD
11552 }
11553   NEXT (vpc);
11554
11555   CASE (sem, INSN_LSLR_B_R) : /* lslr.b $Rs,$Rd */
11556 {
11557   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11558   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11559 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11560   int UNUSED written = 0;
11561   IADDR UNUSED pc = abuf->addr;
11562   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11563
11564 {
11565   SI tmp_tmpd;
11566   SI tmp_cnt;
11567   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11568   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11569 {
11570   SI tmp_oldregval;
11571   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11572   {
11573     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11574     SET_H_GR (FLD (f_operand2), opval);
11575     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11576   }
11577 }
11578 {
11579   {
11580     BI opval = LTQI (tmp_tmpd, 0);
11581     CPU (h_nbit) = opval;
11582     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11583   }
11584   {
11585     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11586     CPU (h_zbit) = opval;
11587     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11588   }
11589 SET_H_CBIT_MOVE (0);
11590 SET_H_VBIT_MOVE (0);
11591 {
11592   {
11593     BI opval = 0;
11594     CPU (h_xbit) = opval;
11595     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11596   }
11597   {
11598     BI opval = 0;
11599     SET_H_INSN_PREFIXED_P (opval);
11600     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11601   }
11602 }
11603 }
11604 }
11605
11606 #undef FLD
11607 }
11608   NEXT (vpc);
11609
11610   CASE (sem, INSN_LSLR_W_R) : /* lslr.w $Rs,$Rd */
11611 {
11612   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11613   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11614 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11615   int UNUSED written = 0;
11616   IADDR UNUSED pc = abuf->addr;
11617   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11618
11619 {
11620   SI tmp_tmpd;
11621   SI tmp_cnt;
11622   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11623   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11624 {
11625   SI tmp_oldregval;
11626   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11627   {
11628     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11629     SET_H_GR (FLD (f_operand2), opval);
11630     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11631   }
11632 }
11633 {
11634   {
11635     BI opval = LTHI (tmp_tmpd, 0);
11636     CPU (h_nbit) = opval;
11637     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11638   }
11639   {
11640     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11641     CPU (h_zbit) = opval;
11642     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11643   }
11644 SET_H_CBIT_MOVE (0);
11645 SET_H_VBIT_MOVE (0);
11646 {
11647   {
11648     BI opval = 0;
11649     CPU (h_xbit) = opval;
11650     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11651   }
11652   {
11653     BI opval = 0;
11654     SET_H_INSN_PREFIXED_P (opval);
11655     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11656   }
11657 }
11658 }
11659 }
11660
11661 #undef FLD
11662 }
11663   NEXT (vpc);
11664
11665   CASE (sem, INSN_LSLR_D_R) : /* lslr.d $Rs,$Rd */
11666 {
11667   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11668   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11669 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11670   int UNUSED written = 0;
11671   IADDR UNUSED pc = abuf->addr;
11672   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11673
11674 {
11675   SI tmp_tmpd;
11676   SI tmp_cnt;
11677   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11678   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11679   {
11680     SI opval = tmp_tmpd;
11681     SET_H_GR (FLD (f_operand2), opval);
11682     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11683   }
11684 {
11685   {
11686     BI opval = LTSI (tmp_tmpd, 0);
11687     CPU (h_nbit) = opval;
11688     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11689   }
11690   {
11691     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11692     CPU (h_zbit) = opval;
11693     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11694   }
11695 SET_H_CBIT_MOVE (0);
11696 SET_H_VBIT_MOVE (0);
11697 {
11698   {
11699     BI opval = 0;
11700     CPU (h_xbit) = opval;
11701     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11702   }
11703   {
11704     BI opval = 0;
11705     SET_H_INSN_PREFIXED_P (opval);
11706     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11707   }
11708 }
11709 }
11710 }
11711
11712 #undef FLD
11713 }
11714   NEXT (vpc);
11715
11716   CASE (sem, INSN_LSLQ) : /* lslq $c,${Rd} */
11717 {
11718   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11719   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11720 #define FLD(f) abuf->fields.sfmt_asrq.f
11721   int UNUSED written = 0;
11722   IADDR UNUSED pc = abuf->addr;
11723   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11724
11725 {
11726   SI tmp_tmpd;
11727   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11728   {
11729     SI opval = tmp_tmpd;
11730     SET_H_GR (FLD (f_operand2), opval);
11731     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11732   }
11733 {
11734   {
11735     BI opval = LTSI (tmp_tmpd, 0);
11736     CPU (h_nbit) = opval;
11737     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11738   }
11739   {
11740     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11741     CPU (h_zbit) = opval;
11742     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11743   }
11744 SET_H_CBIT_MOVE (0);
11745 SET_H_VBIT_MOVE (0);
11746 {
11747   {
11748     BI opval = 0;
11749     CPU (h_xbit) = opval;
11750     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11751   }
11752   {
11753     BI opval = 0;
11754     SET_H_INSN_PREFIXED_P (opval);
11755     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11756   }
11757 }
11758 }
11759 }
11760
11761 #undef FLD
11762 }
11763   NEXT (vpc);
11764
11765   CASE (sem, INSN_BTST) : /* $Rs,$Rd */
11766 {
11767   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11768   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11769 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11770   int UNUSED written = 0;
11771   IADDR UNUSED pc = abuf->addr;
11772   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11773
11774 {
11775   SI tmp_tmpd;
11776   SI tmp_cnt;
11777   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, ANDSI (GET_H_GR (FLD (f_operand1)), 31)));
11778 {
11779   {
11780     BI opval = LTSI (tmp_tmpd, 0);
11781     CPU (h_nbit) = opval;
11782     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11783   }
11784   {
11785     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11786     CPU (h_zbit) = opval;
11787     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11788   }
11789 SET_H_CBIT_MOVE (0);
11790 SET_H_VBIT_MOVE (0);
11791 {
11792   {
11793     BI opval = 0;
11794     CPU (h_xbit) = opval;
11795     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11796   }
11797   {
11798     BI opval = 0;
11799     SET_H_INSN_PREFIXED_P (opval);
11800     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11801   }
11802 }
11803 }
11804 }
11805
11806 #undef FLD
11807 }
11808   NEXT (vpc);
11809
11810   CASE (sem, INSN_BTSTQ) : /* btstq $c,${Rd} */
11811 {
11812   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11813   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11814 #define FLD(f) abuf->fields.sfmt_asrq.f
11815   int UNUSED written = 0;
11816   IADDR UNUSED pc = abuf->addr;
11817   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11818
11819 {
11820   SI tmp_tmpd;
11821   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, FLD (f_u5)));
11822 {
11823   {
11824     BI opval = LTSI (tmp_tmpd, 0);
11825     CPU (h_nbit) = opval;
11826     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11827   }
11828   {
11829     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11830     CPU (h_zbit) = opval;
11831     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11832   }
11833 SET_H_CBIT_MOVE (0);
11834 SET_H_VBIT_MOVE (0);
11835 {
11836   {
11837     BI opval = 0;
11838     CPU (h_xbit) = opval;
11839     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11840   }
11841   {
11842     BI opval = 0;
11843     SET_H_INSN_PREFIXED_P (opval);
11844     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11845   }
11846 }
11847 }
11848 }
11849
11850 #undef FLD
11851 }
11852   NEXT (vpc);
11853
11854   CASE (sem, INSN_SETF) : /* setf ${list-of-flags} */
11855 {
11856   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11857   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11858 #define FLD(f) abuf->fields.sfmt_setf.f
11859   int UNUSED written = 0;
11860   IADDR UNUSED pc = abuf->addr;
11861   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11862
11863 {
11864   SI tmp_tmp;
11865   tmp_tmp = FLD (f_dstsrc);
11866 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
11867   {
11868     BI opval = 1;
11869     CPU (h_cbit) = opval;
11870     written |= (1 << 1);
11871     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
11872   }
11873 }
11874 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
11875   {
11876     BI opval = 1;
11877     CPU (h_vbit) = opval;
11878     written |= (1 << 7);
11879     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
11880   }
11881 }
11882 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
11883   {
11884     BI opval = 1;
11885     CPU (h_zbit) = opval;
11886     written |= (1 << 9);
11887     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11888   }
11889 }
11890 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
11891   {
11892     BI opval = 1;
11893     CPU (h_nbit) = opval;
11894     written |= (1 << 3);
11895     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11896   }
11897 }
11898 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
11899   {
11900     BI opval = 1;
11901     CPU (h_xbit) = opval;
11902     written |= (1 << 8);
11903     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11904   }
11905 }
11906 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
11907   {
11908     BI opval = 1;
11909     SET_H_IBIT (opval);
11910     written |= (1 << 2);
11911     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
11912   }
11913 }
11914 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
11915   {
11916     BI opval = 1;
11917     SET_H_UBIT (opval);
11918     written |= (1 << 6);
11919     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
11920   }
11921 }
11922 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
11923   {
11924     BI opval = 1;
11925     CPU (h_pbit) = opval;
11926     written |= (1 << 4);
11927     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
11928   }
11929 }
11930   {
11931     BI opval = 0;
11932     SET_H_INSN_PREFIXED_P (opval);
11933     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11934   }
11935 if (EQSI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
11936   {
11937     BI opval = 0;
11938     CPU (h_xbit) = opval;
11939     written |= (1 << 8);
11940     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11941   }
11942 }
11943 }
11944
11945   abuf->written = written;
11946 #undef FLD
11947 }
11948   NEXT (vpc);
11949
11950   CASE (sem, INSN_CLEARF) : /* clearf ${list-of-flags} */
11951 {
11952   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11953   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11954 #define FLD(f) abuf->fields.sfmt_setf.f
11955   int UNUSED written = 0;
11956   IADDR UNUSED pc = abuf->addr;
11957   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11958
11959 {
11960   SI tmp_tmp;
11961   tmp_tmp = FLD (f_dstsrc);
11962 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
11963   {
11964     BI opval = 0;
11965     CPU (h_cbit) = opval;
11966     written |= (1 << 1);
11967     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
11968   }
11969 }
11970 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
11971   {
11972     BI opval = 0;
11973     CPU (h_vbit) = opval;
11974     written |= (1 << 7);
11975     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
11976   }
11977 }
11978 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
11979   {
11980     BI opval = 0;
11981     CPU (h_zbit) = opval;
11982     written |= (1 << 9);
11983     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11984   }
11985 }
11986 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
11987   {
11988     BI opval = 0;
11989     CPU (h_nbit) = opval;
11990     written |= (1 << 3);
11991     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11992   }
11993 }
11994 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
11995   {
11996     BI opval = 0;
11997     CPU (h_xbit) = opval;
11998     written |= (1 << 8);
11999     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12000   }
12001 }
12002 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
12003   {
12004     BI opval = 0;
12005     SET_H_IBIT (opval);
12006     written |= (1 << 2);
12007     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
12008   }
12009 }
12010 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
12011   {
12012     BI opval = 0;
12013     SET_H_UBIT (opval);
12014     written |= (1 << 6);
12015     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
12016   }
12017 }
12018 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
12019   {
12020     BI opval = 0;
12021     CPU (h_pbit) = opval;
12022     written |= (1 << 4);
12023     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
12024   }
12025 }
12026 {
12027   {
12028     BI opval = 0;
12029     CPU (h_xbit) = opval;
12030     written |= (1 << 8);
12031     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12032   }
12033   {
12034     BI opval = 0;
12035     SET_H_INSN_PREFIXED_P (opval);
12036     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12037   }
12038 }
12039 }
12040
12041   abuf->written = written;
12042 #undef FLD
12043 }
12044   NEXT (vpc);
12045
12046   CASE (sem, INSN_BCC_B) : /* b${cc} ${o-pcrel} */
12047 {
12048   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12049   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12050 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12051   int UNUSED written = 0;
12052   IADDR UNUSED pc = abuf->addr;
12053   SEM_BRANCH_INIT
12054   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12055
12056 {
12057   BI tmp_truthval;
12058   tmp_truthval = ({   SI tmp_tmpcond;
12059   BI tmp_condres;
12060   tmp_tmpcond = FLD (f_operand2);
12061 ; if (EQSI (tmp_tmpcond, 0)) {
12062   tmp_condres = NOTBI (CPU (h_cbit));
12063 }
12064  else if (EQSI (tmp_tmpcond, 1)) {
12065   tmp_condres = CPU (h_cbit);
12066 }
12067  else if (EQSI (tmp_tmpcond, 2)) {
12068   tmp_condres = NOTBI (CPU (h_zbit));
12069 }
12070  else if (EQSI (tmp_tmpcond, 3)) {
12071   tmp_condres = CPU (h_zbit);
12072 }
12073  else if (EQSI (tmp_tmpcond, 4)) {
12074   tmp_condres = NOTBI (CPU (h_vbit));
12075 }
12076  else if (EQSI (tmp_tmpcond, 5)) {
12077   tmp_condres = CPU (h_vbit);
12078 }
12079  else if (EQSI (tmp_tmpcond, 6)) {
12080   tmp_condres = NOTBI (CPU (h_nbit));
12081 }
12082  else if (EQSI (tmp_tmpcond, 7)) {
12083   tmp_condres = CPU (h_nbit);
12084 }
12085  else if (EQSI (tmp_tmpcond, 8)) {
12086   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12087 }
12088  else if (EQSI (tmp_tmpcond, 9)) {
12089   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12090 }
12091  else if (EQSI (tmp_tmpcond, 10)) {
12092   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12093 }
12094  else if (EQSI (tmp_tmpcond, 11)) {
12095   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12096 }
12097  else if (EQSI (tmp_tmpcond, 12)) {
12098   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12099 }
12100  else if (EQSI (tmp_tmpcond, 13)) {
12101   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12102 }
12103  else if (EQSI (tmp_tmpcond, 14)) {
12104   tmp_condres = 1;
12105 }
12106  else if (EQSI (tmp_tmpcond, 15)) {
12107   tmp_condres = CPU (h_pbit);
12108 }
12109 ; tmp_condres; });
12110 crisv10f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval);
12111 {
12112   {
12113     BI opval = 0;
12114     CPU (h_xbit) = opval;
12115     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12116   }
12117   {
12118     BI opval = 0;
12119     SET_H_INSN_PREFIXED_P (opval);
12120     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12121   }
12122 }
12123 if (tmp_truthval) {
12124 {
12125   {
12126     USI opval = FLD (i_o_pcrel);
12127     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12128     written |= (1 << 8);
12129     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12130   }
12131 }
12132 }
12133 }
12134
12135   abuf->written = written;
12136   SEM_BRANCH_FINI (vpc);
12137 #undef FLD
12138 }
12139   NEXT (vpc);
12140
12141   CASE (sem, INSN_BA_B) : /* ba ${o-pcrel} */
12142 {
12143   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12144   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12145 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12146   int UNUSED written = 0;
12147   IADDR UNUSED pc = abuf->addr;
12148   SEM_BRANCH_INIT
12149   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12150
12151 {
12152 {
12153   {
12154     BI opval = 0;
12155     CPU (h_xbit) = opval;
12156     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12157   }
12158   {
12159     BI opval = 0;
12160     SET_H_INSN_PREFIXED_P (opval);
12161     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12162   }
12163 }
12164 {
12165   {
12166     USI opval = FLD (i_o_pcrel);
12167     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12168     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12169   }
12170 }
12171 }
12172
12173   SEM_BRANCH_FINI (vpc);
12174 #undef FLD
12175 }
12176   NEXT (vpc);
12177
12178   CASE (sem, INSN_BCC_W) : /* b${cc} ${o-word-pcrel} */
12179 {
12180   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12181   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12182 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12183   int UNUSED written = 0;
12184   IADDR UNUSED pc = abuf->addr;
12185   SEM_BRANCH_INIT
12186   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12187
12188 {
12189   BI tmp_truthval;
12190   tmp_truthval = ({   SI tmp_tmpcond;
12191   BI tmp_condres;
12192   tmp_tmpcond = FLD (f_operand2);
12193 ; if (EQSI (tmp_tmpcond, 0)) {
12194   tmp_condres = NOTBI (CPU (h_cbit));
12195 }
12196  else if (EQSI (tmp_tmpcond, 1)) {
12197   tmp_condres = CPU (h_cbit);
12198 }
12199  else if (EQSI (tmp_tmpcond, 2)) {
12200   tmp_condres = NOTBI (CPU (h_zbit));
12201 }
12202  else if (EQSI (tmp_tmpcond, 3)) {
12203   tmp_condres = CPU (h_zbit);
12204 }
12205  else if (EQSI (tmp_tmpcond, 4)) {
12206   tmp_condres = NOTBI (CPU (h_vbit));
12207 }
12208  else if (EQSI (tmp_tmpcond, 5)) {
12209   tmp_condres = CPU (h_vbit);
12210 }
12211  else if (EQSI (tmp_tmpcond, 6)) {
12212   tmp_condres = NOTBI (CPU (h_nbit));
12213 }
12214  else if (EQSI (tmp_tmpcond, 7)) {
12215   tmp_condres = CPU (h_nbit);
12216 }
12217  else if (EQSI (tmp_tmpcond, 8)) {
12218   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12219 }
12220  else if (EQSI (tmp_tmpcond, 9)) {
12221   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12222 }
12223  else if (EQSI (tmp_tmpcond, 10)) {
12224   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12225 }
12226  else if (EQSI (tmp_tmpcond, 11)) {
12227   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12228 }
12229  else if (EQSI (tmp_tmpcond, 12)) {
12230   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12231 }
12232  else if (EQSI (tmp_tmpcond, 13)) {
12233   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12234 }
12235  else if (EQSI (tmp_tmpcond, 14)) {
12236   tmp_condres = 1;
12237 }
12238  else if (EQSI (tmp_tmpcond, 15)) {
12239   tmp_condres = CPU (h_pbit);
12240 }
12241 ; tmp_condres; });
12242 crisv10f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval);
12243 {
12244   {
12245     BI opval = 0;
12246     CPU (h_xbit) = opval;
12247     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12248   }
12249   {
12250     BI opval = 0;
12251     SET_H_INSN_PREFIXED_P (opval);
12252     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12253   }
12254 }
12255 if (tmp_truthval) {
12256 {
12257   {
12258     USI opval = FLD (i_o_word_pcrel);
12259     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12260     written |= (1 << 8);
12261     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12262   }
12263 }
12264 }
12265 }
12266
12267   abuf->written = written;
12268   SEM_BRANCH_FINI (vpc);
12269 #undef FLD
12270 }
12271   NEXT (vpc);
12272
12273   CASE (sem, INSN_BA_W) : /* ba ${o-word-pcrel} */
12274 {
12275   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12276   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12277 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12278   int UNUSED written = 0;
12279   IADDR UNUSED pc = abuf->addr;
12280   SEM_BRANCH_INIT
12281   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12282
12283 {
12284 {
12285   {
12286     BI opval = 0;
12287     CPU (h_xbit) = opval;
12288     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12289   }
12290   {
12291     BI opval = 0;
12292     SET_H_INSN_PREFIXED_P (opval);
12293     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12294   }
12295 }
12296 {
12297   {
12298     USI opval = FLD (i_o_word_pcrel);
12299     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12300     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12301   }
12302 }
12303 }
12304
12305   SEM_BRANCH_FINI (vpc);
12306 #undef FLD
12307 }
12308   NEXT (vpc);
12309
12310   CASE (sem, INSN_JUMP_R) : /* jump/jsr/jir ${Rs} */
12311 {
12312   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12313   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12314 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
12315   int UNUSED written = 0;
12316   IADDR UNUSED pc = abuf->addr;
12317   SEM_BRANCH_INIT
12318   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12319
12320 {
12321   {
12322     SI opval = ADDSI (pc, 2);
12323     SET_H_SR (FLD (f_operand2), opval);
12324     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12325   }
12326   {
12327     USI opval = GET_H_GR (FLD (f_operand1));
12328     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12329     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12330   }
12331 {
12332   {
12333     BI opval = 0;
12334     CPU (h_xbit) = opval;
12335     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12336   }
12337   {
12338     BI opval = 0;
12339     SET_H_INSN_PREFIXED_P (opval);
12340     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12341   }
12342 }
12343 }
12344
12345   SEM_BRANCH_FINI (vpc);
12346 #undef FLD
12347 }
12348   NEXT (vpc);
12349
12350   CASE (sem, INSN_JUMP_M) : /* jump/jsr/jir [${Rs}${inc}] */
12351 {
12352   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12353   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12354 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
12355   int UNUSED written = 0;
12356   IADDR UNUSED pc = abuf->addr;
12357   SEM_BRANCH_INIT
12358   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12359
12360 {
12361   {
12362     SI opval = ADDSI (pc, 2);
12363     SET_H_SR (FLD (f_operand2), opval);
12364     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12365   }
12366   {
12367     USI opval = ({   SI tmp_addr;
12368   SI tmp_tmp_mem;
12369   BI tmp_postinc;
12370   tmp_postinc = FLD (f_memmode);
12371 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12372 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
12373 ; if (NEBI (tmp_postinc, 0)) {
12374 {
12375 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12376   tmp_addr = ADDSI (tmp_addr, 4);
12377 }
12378   {
12379     SI opval = tmp_addr;
12380     SET_H_GR (FLD (f_operand1), opval);
12381     written |= (1 << 7);
12382     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12383   }
12384 }
12385 }
12386 ; tmp_tmp_mem; });
12387     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12388     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12389   }
12390 {
12391   {
12392     BI opval = 0;
12393     CPU (h_xbit) = opval;
12394     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12395   }
12396   {
12397     BI opval = 0;
12398     SET_H_INSN_PREFIXED_P (opval);
12399     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12400   }
12401 }
12402 }
12403
12404   abuf->written = written;
12405   SEM_BRANCH_FINI (vpc);
12406 #undef FLD
12407 }
12408   NEXT (vpc);
12409
12410   CASE (sem, INSN_JUMP_C) : /* jump/jsr/jir ${const32} */
12411 {
12412   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12413   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12414 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
12415   int UNUSED written = 0;
12416   IADDR UNUSED pc = abuf->addr;
12417   SEM_BRANCH_INIT
12418   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12419
12420 {
12421   {
12422     SI opval = ADDSI (pc, 6);
12423     SET_H_SR (FLD (f_operand2), opval);
12424     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12425   }
12426   {
12427     USI opval = FLD (f_indir_pc__dword);
12428     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12429     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12430   }
12431 {
12432   {
12433     BI opval = 0;
12434     CPU (h_xbit) = opval;
12435     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12436   }
12437   {
12438     BI opval = 0;
12439     SET_H_INSN_PREFIXED_P (opval);
12440     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12441   }
12442 }
12443 }
12444
12445   SEM_BRANCH_FINI (vpc);
12446 #undef FLD
12447 }
12448   NEXT (vpc);
12449
12450   CASE (sem, INSN_BREAK) : /* break $n */
12451 {
12452   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12453   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12454 #define FLD(f) abuf->fields.sfmt_break.f
12455   int UNUSED written = 0;
12456   IADDR UNUSED pc = abuf->addr;
12457   SEM_BRANCH_INIT
12458   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12459
12460 {
12461 {
12462   {
12463     BI opval = 0;
12464     CPU (h_xbit) = opval;
12465     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12466   }
12467   {
12468     BI opval = 0;
12469     SET_H_INSN_PREFIXED_P (opval);
12470     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12471   }
12472 }
12473   {
12474     USI opval = crisv10f_break_handler (current_cpu, FLD (f_u4), pc);
12475     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12476     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12477   }
12478 }
12479
12480   SEM_BRANCH_FINI (vpc);
12481 #undef FLD
12482 }
12483   NEXT (vpc);
12484
12485   CASE (sem, INSN_BOUND_R_B_R) : /* bound-r.b ${Rs},${Rd} */
12486 {
12487   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12488   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12489 #define FLD(f) abuf->fields.sfmt_muls_b.f
12490   int UNUSED written = 0;
12491   IADDR UNUSED pc = abuf->addr;
12492   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12493
12494 {
12495   SI tmp_tmpopd;
12496   SI tmp_tmpops;
12497   SI tmp_newval;
12498   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
12499   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12500   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12501   {
12502     SI opval = tmp_newval;
12503     SET_H_GR (FLD (f_operand2), opval);
12504     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12505   }
12506 {
12507   {
12508     BI opval = LTSI (tmp_newval, 0);
12509     CPU (h_nbit) = opval;
12510     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12511   }
12512   {
12513     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12514     CPU (h_zbit) = opval;
12515     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12516   }
12517 SET_H_CBIT_MOVE (0);
12518 SET_H_VBIT_MOVE (0);
12519 {
12520   {
12521     BI opval = 0;
12522     CPU (h_xbit) = opval;
12523     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12524   }
12525   {
12526     BI opval = 0;
12527     SET_H_INSN_PREFIXED_P (opval);
12528     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12529   }
12530 }
12531 }
12532 }
12533
12534 #undef FLD
12535 }
12536   NEXT (vpc);
12537
12538   CASE (sem, INSN_BOUND_R_W_R) : /* bound-r.w ${Rs},${Rd} */
12539 {
12540   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12541   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12542 #define FLD(f) abuf->fields.sfmt_muls_b.f
12543   int UNUSED written = 0;
12544   IADDR UNUSED pc = abuf->addr;
12545   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12546
12547 {
12548   SI tmp_tmpopd;
12549   SI tmp_tmpops;
12550   SI tmp_newval;
12551   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
12552   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12553   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12554   {
12555     SI opval = tmp_newval;
12556     SET_H_GR (FLD (f_operand2), opval);
12557     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12558   }
12559 {
12560   {
12561     BI opval = LTSI (tmp_newval, 0);
12562     CPU (h_nbit) = opval;
12563     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12564   }
12565   {
12566     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12567     CPU (h_zbit) = opval;
12568     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12569   }
12570 SET_H_CBIT_MOVE (0);
12571 SET_H_VBIT_MOVE (0);
12572 {
12573   {
12574     BI opval = 0;
12575     CPU (h_xbit) = opval;
12576     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12577   }
12578   {
12579     BI opval = 0;
12580     SET_H_INSN_PREFIXED_P (opval);
12581     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12582   }
12583 }
12584 }
12585 }
12586
12587 #undef FLD
12588 }
12589   NEXT (vpc);
12590
12591   CASE (sem, INSN_BOUND_R_D_R) : /* bound-r.d ${Rs},${Rd} */
12592 {
12593   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12594   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12595 #define FLD(f) abuf->fields.sfmt_muls_b.f
12596   int UNUSED written = 0;
12597   IADDR UNUSED pc = abuf->addr;
12598   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12599
12600 {
12601   SI tmp_tmpopd;
12602   SI tmp_tmpops;
12603   SI tmp_newval;
12604   tmp_tmpops = TRUNCSISI (GET_H_GR (FLD (f_operand1)));
12605   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12606   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12607   {
12608     SI opval = tmp_newval;
12609     SET_H_GR (FLD (f_operand2), opval);
12610     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12611   }
12612 {
12613   {
12614     BI opval = LTSI (tmp_newval, 0);
12615     CPU (h_nbit) = opval;
12616     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12617   }
12618   {
12619     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12620     CPU (h_zbit) = opval;
12621     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12622   }
12623 SET_H_CBIT_MOVE (0);
12624 SET_H_VBIT_MOVE (0);
12625 {
12626   {
12627     BI opval = 0;
12628     CPU (h_xbit) = opval;
12629     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12630   }
12631   {
12632     BI opval = 0;
12633     SET_H_INSN_PREFIXED_P (opval);
12634     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12635   }
12636 }
12637 }
12638 }
12639
12640 #undef FLD
12641 }
12642   NEXT (vpc);
12643
12644   CASE (sem, INSN_BOUND_M_B_M) : /* bound-m.b [${Rs}${inc}],${Rd} */
12645 {
12646   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12647   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12648 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
12649   int UNUSED written = 0;
12650   IADDR UNUSED pc = abuf->addr;
12651   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12652
12653 {
12654   SI tmp_tmpopd;
12655   SI tmp_tmpops;
12656   SI tmp_newval;
12657   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
12658   QI tmp_tmp_mem;
12659   BI tmp_postinc;
12660   tmp_postinc = FLD (f_memmode);
12661 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12662 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
12663 ; if (NEBI (tmp_postinc, 0)) {
12664 {
12665 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12666   tmp_addr = ADDSI (tmp_addr, 1);
12667 }
12668   {
12669     SI opval = tmp_addr;
12670     SET_H_GR (FLD (f_operand1), opval);
12671     written |= (1 << 9);
12672     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12673   }
12674 }
12675 }
12676 ; tmp_tmp_mem; }));
12677   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12678   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12679 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
12680   {
12681     SI opval = tmp_newval;
12682     SET_H_GR (FLD (f_operand1), opval);
12683     written |= (1 << 9);
12684     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12685   }
12686 } else {
12687   {
12688     SI opval = tmp_newval;
12689     SET_H_GR (FLD (f_operand2), opval);
12690     written |= (1 << 8);
12691     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12692   }
12693 }
12694 {
12695   {
12696     BI opval = LTSI (tmp_newval, 0);
12697     CPU (h_nbit) = opval;
12698     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12699   }
12700   {
12701     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12702     CPU (h_zbit) = opval;
12703     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12704   }
12705 SET_H_CBIT_MOVE (0);
12706 SET_H_VBIT_MOVE (0);
12707 {
12708   {
12709     BI opval = 0;
12710     CPU (h_xbit) = opval;
12711     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12712   }
12713   {
12714     BI opval = 0;
12715     SET_H_INSN_PREFIXED_P (opval);
12716     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12717   }
12718 }
12719 }
12720 }
12721
12722   abuf->written = written;
12723 #undef FLD
12724 }
12725   NEXT (vpc);
12726
12727   CASE (sem, INSN_BOUND_M_W_M) : /* bound-m.w [${Rs}${inc}],${Rd} */
12728 {
12729   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12730   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12731 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
12732   int UNUSED written = 0;
12733   IADDR UNUSED pc = abuf->addr;
12734   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12735
12736 {
12737   SI tmp_tmpopd;
12738   SI tmp_tmpops;
12739   SI tmp_newval;
12740   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
12741   HI tmp_tmp_mem;
12742   BI tmp_postinc;
12743   tmp_postinc = FLD (f_memmode);
12744 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12745 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
12746 ; if (NEBI (tmp_postinc, 0)) {
12747 {
12748 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12749   tmp_addr = ADDSI (tmp_addr, 2);
12750 }
12751   {
12752     SI opval = tmp_addr;
12753     SET_H_GR (FLD (f_operand1), opval);
12754     written |= (1 << 9);
12755     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12756   }
12757 }
12758 }
12759 ; tmp_tmp_mem; }));
12760   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12761   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12762 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
12763   {
12764     SI opval = tmp_newval;
12765     SET_H_GR (FLD (f_operand1), opval);
12766     written |= (1 << 9);
12767     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12768   }
12769 } else {
12770   {
12771     SI opval = tmp_newval;
12772     SET_H_GR (FLD (f_operand2), opval);
12773     written |= (1 << 8);
12774     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12775   }
12776 }
12777 {
12778   {
12779     BI opval = LTSI (tmp_newval, 0);
12780     CPU (h_nbit) = opval;
12781     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12782   }
12783   {
12784     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12785     CPU (h_zbit) = opval;
12786     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12787   }
12788 SET_H_CBIT_MOVE (0);
12789 SET_H_VBIT_MOVE (0);
12790 {
12791   {
12792     BI opval = 0;
12793     CPU (h_xbit) = opval;
12794     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12795   }
12796   {
12797     BI opval = 0;
12798     SET_H_INSN_PREFIXED_P (opval);
12799     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12800   }
12801 }
12802 }
12803 }
12804
12805   abuf->written = written;
12806 #undef FLD
12807 }
12808   NEXT (vpc);
12809
12810   CASE (sem, INSN_BOUND_M_D_M) : /* bound-m.d [${Rs}${inc}],${Rd} */
12811 {
12812   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12813   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12814 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
12815   int UNUSED written = 0;
12816   IADDR UNUSED pc = abuf->addr;
12817   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12818
12819 {
12820   SI tmp_tmpopd;
12821   SI tmp_tmpops;
12822   SI tmp_newval;
12823   tmp_tmpops = ({   SI tmp_addr;
12824   SI tmp_tmp_mem;
12825   BI tmp_postinc;
12826   tmp_postinc = FLD (f_memmode);
12827 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12828 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
12829 ; if (NEBI (tmp_postinc, 0)) {
12830 {
12831 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12832   tmp_addr = ADDSI (tmp_addr, 4);
12833 }
12834   {
12835     SI opval = tmp_addr;
12836     SET_H_GR (FLD (f_operand1), opval);
12837     written |= (1 << 9);
12838     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12839   }
12840 }
12841 }
12842 ; tmp_tmp_mem; });
12843   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12844   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12845 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
12846   {
12847     SI opval = tmp_newval;
12848     SET_H_GR (FLD (f_operand1), opval);
12849     written |= (1 << 9);
12850     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12851   }
12852 } else {
12853   {
12854     SI opval = tmp_newval;
12855     SET_H_GR (FLD (f_operand2), opval);
12856     written |= (1 << 8);
12857     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12858   }
12859 }
12860 {
12861   {
12862     BI opval = LTSI (tmp_newval, 0);
12863     CPU (h_nbit) = opval;
12864     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12865   }
12866   {
12867     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12868     CPU (h_zbit) = opval;
12869     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12870   }
12871 SET_H_CBIT_MOVE (0);
12872 SET_H_VBIT_MOVE (0);
12873 {
12874   {
12875     BI opval = 0;
12876     CPU (h_xbit) = opval;
12877     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12878   }
12879   {
12880     BI opval = 0;
12881     SET_H_INSN_PREFIXED_P (opval);
12882     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12883   }
12884 }
12885 }
12886 }
12887
12888   abuf->written = written;
12889 #undef FLD
12890 }
12891   NEXT (vpc);
12892
12893   CASE (sem, INSN_BOUND_CB) : /* bound.b [PC+],${Rd} */
12894 {
12895   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12896   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12897 #define FLD(f) abuf->fields.sfmt_bound_cb.f
12898   int UNUSED written = 0;
12899   IADDR UNUSED pc = abuf->addr;
12900   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12901
12902 {
12903   SI tmp_tmpopd;
12904   SI tmp_tmpops;
12905   SI tmp_newval;
12906   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
12907   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12908   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12909   {
12910     SI opval = tmp_newval;
12911     SET_H_GR (FLD (f_operand2), opval);
12912     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12913   }
12914 {
12915   {
12916     BI opval = LTSI (tmp_newval, 0);
12917     CPU (h_nbit) = opval;
12918     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12919   }
12920   {
12921     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12922     CPU (h_zbit) = opval;
12923     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12924   }
12925 SET_H_CBIT_MOVE (0);
12926 SET_H_VBIT_MOVE (0);
12927 {
12928   {
12929     BI opval = 0;
12930     CPU (h_xbit) = opval;
12931     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12932   }
12933   {
12934     BI opval = 0;
12935     SET_H_INSN_PREFIXED_P (opval);
12936     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12937   }
12938 }
12939 }
12940 }
12941
12942 #undef FLD
12943 }
12944   NEXT (vpc);
12945
12946   CASE (sem, INSN_BOUND_CW) : /* bound.w [PC+],${Rd} */
12947 {
12948   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12949   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12950 #define FLD(f) abuf->fields.sfmt_bound_cw.f
12951   int UNUSED written = 0;
12952   IADDR UNUSED pc = abuf->addr;
12953   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12954
12955 {
12956   SI tmp_tmpopd;
12957   SI tmp_tmpops;
12958   SI tmp_newval;
12959   tmp_tmpops = ZEXTSISI (FLD (f_indir_pc__word));
12960   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12961   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12962   {
12963     SI opval = tmp_newval;
12964     SET_H_GR (FLD (f_operand2), opval);
12965     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12966   }
12967 {
12968   {
12969     BI opval = LTSI (tmp_newval, 0);
12970     CPU (h_nbit) = opval;
12971     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12972   }
12973   {
12974     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12975     CPU (h_zbit) = opval;
12976     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12977   }
12978 SET_H_CBIT_MOVE (0);
12979 SET_H_VBIT_MOVE (0);
12980 {
12981   {
12982     BI opval = 0;
12983     CPU (h_xbit) = opval;
12984     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12985   }
12986   {
12987     BI opval = 0;
12988     SET_H_INSN_PREFIXED_P (opval);
12989     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12990   }
12991 }
12992 }
12993 }
12994
12995 #undef FLD
12996 }
12997   NEXT (vpc);
12998
12999   CASE (sem, INSN_BOUND_CD) : /* bound.d [PC+],${Rd} */
13000 {
13001   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13002   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13003 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13004   int UNUSED written = 0;
13005   IADDR UNUSED pc = abuf->addr;
13006   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13007
13008 {
13009   SI tmp_tmpopd;
13010   SI tmp_tmpops;
13011   SI tmp_newval;
13012   tmp_tmpops = FLD (f_indir_pc__dword);
13013   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13014   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13015   {
13016     SI opval = tmp_newval;
13017     SET_H_GR (FLD (f_operand2), opval);
13018     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13019   }
13020 {
13021   {
13022     BI opval = LTSI (tmp_newval, 0);
13023     CPU (h_nbit) = opval;
13024     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13025   }
13026   {
13027     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13028     CPU (h_zbit) = opval;
13029     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13030   }
13031 SET_H_CBIT_MOVE (0);
13032 SET_H_VBIT_MOVE (0);
13033 {
13034   {
13035     BI opval = 0;
13036     CPU (h_xbit) = opval;
13037     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13038   }
13039   {
13040     BI opval = 0;
13041     SET_H_INSN_PREFIXED_P (opval);
13042     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13043   }
13044 }
13045 }
13046 }
13047
13048 #undef FLD
13049 }
13050   NEXT (vpc);
13051
13052   CASE (sem, INSN_SCC) : /* s${cc} ${Rd-sfield} */
13053 {
13054   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13055   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13056 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
13057   int UNUSED written = 0;
13058   IADDR UNUSED pc = abuf->addr;
13059   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13060
13061 {
13062   BI tmp_truthval;
13063   tmp_truthval = ({   SI tmp_tmpcond;
13064   BI tmp_condres;
13065   tmp_tmpcond = FLD (f_operand2);
13066 ; if (EQSI (tmp_tmpcond, 0)) {
13067   tmp_condres = NOTBI (CPU (h_cbit));
13068 }
13069  else if (EQSI (tmp_tmpcond, 1)) {
13070   tmp_condres = CPU (h_cbit);
13071 }
13072  else if (EQSI (tmp_tmpcond, 2)) {
13073   tmp_condres = NOTBI (CPU (h_zbit));
13074 }
13075  else if (EQSI (tmp_tmpcond, 3)) {
13076   tmp_condres = CPU (h_zbit);
13077 }
13078  else if (EQSI (tmp_tmpcond, 4)) {
13079   tmp_condres = NOTBI (CPU (h_vbit));
13080 }
13081  else if (EQSI (tmp_tmpcond, 5)) {
13082   tmp_condres = CPU (h_vbit);
13083 }
13084  else if (EQSI (tmp_tmpcond, 6)) {
13085   tmp_condres = NOTBI (CPU (h_nbit));
13086 }
13087  else if (EQSI (tmp_tmpcond, 7)) {
13088   tmp_condres = CPU (h_nbit);
13089 }
13090  else if (EQSI (tmp_tmpcond, 8)) {
13091   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
13092 }
13093  else if (EQSI (tmp_tmpcond, 9)) {
13094   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
13095 }
13096  else if (EQSI (tmp_tmpcond, 10)) {
13097   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
13098 }
13099  else if (EQSI (tmp_tmpcond, 11)) {
13100   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
13101 }
13102  else if (EQSI (tmp_tmpcond, 12)) {
13103   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
13104 }
13105  else if (EQSI (tmp_tmpcond, 13)) {
13106   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
13107 }
13108  else if (EQSI (tmp_tmpcond, 14)) {
13109   tmp_condres = 1;
13110 }
13111  else if (EQSI (tmp_tmpcond, 15)) {
13112   tmp_condres = CPU (h_pbit);
13113 }
13114 ; tmp_condres; });
13115   {
13116     SI opval = ZEXTBISI (tmp_truthval);
13117     SET_H_GR (FLD (f_operand1), opval);
13118     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13119   }
13120 {
13121   {
13122     BI opval = 0;
13123     CPU (h_xbit) = opval;
13124     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13125   }
13126   {
13127     BI opval = 0;
13128     SET_H_INSN_PREFIXED_P (opval);
13129     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13130   }
13131 }
13132 }
13133
13134 #undef FLD
13135 }
13136   NEXT (vpc);
13137
13138   CASE (sem, INSN_LZ) : /* lz ${Rs},${Rd} */
13139 {
13140   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13141   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13142 #define FLD(f) abuf->fields.sfmt_muls_b.f
13143   int UNUSED written = 0;
13144   IADDR UNUSED pc = abuf->addr;
13145   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13146
13147 {
13148   SI tmp_tmpd;
13149   SI tmp_tmp;
13150   tmp_tmp = GET_H_GR (FLD (f_operand1));
13151   tmp_tmpd = 0;
13152 {
13153 if (GESI (tmp_tmp, 0)) {
13154 {
13155   tmp_tmp = SLLSI (tmp_tmp, 1);
13156   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13157 }
13158 }
13159 if (GESI (tmp_tmp, 0)) {
13160 {
13161   tmp_tmp = SLLSI (tmp_tmp, 1);
13162   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13163 }
13164 }
13165 if (GESI (tmp_tmp, 0)) {
13166 {
13167   tmp_tmp = SLLSI (tmp_tmp, 1);
13168   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13169 }
13170 }
13171 if (GESI (tmp_tmp, 0)) {
13172 {
13173   tmp_tmp = SLLSI (tmp_tmp, 1);
13174   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13175 }
13176 }
13177 if (GESI (tmp_tmp, 0)) {
13178 {
13179   tmp_tmp = SLLSI (tmp_tmp, 1);
13180   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13181 }
13182 }
13183 if (GESI (tmp_tmp, 0)) {
13184 {
13185   tmp_tmp = SLLSI (tmp_tmp, 1);
13186   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13187 }
13188 }
13189 if (GESI (tmp_tmp, 0)) {
13190 {
13191   tmp_tmp = SLLSI (tmp_tmp, 1);
13192   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13193 }
13194 }
13195 if (GESI (tmp_tmp, 0)) {
13196 {
13197   tmp_tmp = SLLSI (tmp_tmp, 1);
13198   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13199 }
13200 }
13201 if (GESI (tmp_tmp, 0)) {
13202 {
13203   tmp_tmp = SLLSI (tmp_tmp, 1);
13204   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13205 }
13206 }
13207 if (GESI (tmp_tmp, 0)) {
13208 {
13209   tmp_tmp = SLLSI (tmp_tmp, 1);
13210   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13211 }
13212 }
13213 if (GESI (tmp_tmp, 0)) {
13214 {
13215   tmp_tmp = SLLSI (tmp_tmp, 1);
13216   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13217 }
13218 }
13219 if (GESI (tmp_tmp, 0)) {
13220 {
13221   tmp_tmp = SLLSI (tmp_tmp, 1);
13222   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13223 }
13224 }
13225 if (GESI (tmp_tmp, 0)) {
13226 {
13227   tmp_tmp = SLLSI (tmp_tmp, 1);
13228   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13229 }
13230 }
13231 if (GESI (tmp_tmp, 0)) {
13232 {
13233   tmp_tmp = SLLSI (tmp_tmp, 1);
13234   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13235 }
13236 }
13237 if (GESI (tmp_tmp, 0)) {
13238 {
13239   tmp_tmp = SLLSI (tmp_tmp, 1);
13240   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13241 }
13242 }
13243 if (GESI (tmp_tmp, 0)) {
13244 {
13245   tmp_tmp = SLLSI (tmp_tmp, 1);
13246   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13247 }
13248 }
13249 if (GESI (tmp_tmp, 0)) {
13250 {
13251   tmp_tmp = SLLSI (tmp_tmp, 1);
13252   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13253 }
13254 }
13255 if (GESI (tmp_tmp, 0)) {
13256 {
13257   tmp_tmp = SLLSI (tmp_tmp, 1);
13258   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13259 }
13260 }
13261 if (GESI (tmp_tmp, 0)) {
13262 {
13263   tmp_tmp = SLLSI (tmp_tmp, 1);
13264   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13265 }
13266 }
13267 if (GESI (tmp_tmp, 0)) {
13268 {
13269   tmp_tmp = SLLSI (tmp_tmp, 1);
13270   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13271 }
13272 }
13273 if (GESI (tmp_tmp, 0)) {
13274 {
13275   tmp_tmp = SLLSI (tmp_tmp, 1);
13276   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13277 }
13278 }
13279 if (GESI (tmp_tmp, 0)) {
13280 {
13281   tmp_tmp = SLLSI (tmp_tmp, 1);
13282   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13283 }
13284 }
13285 if (GESI (tmp_tmp, 0)) {
13286 {
13287   tmp_tmp = SLLSI (tmp_tmp, 1);
13288   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13289 }
13290 }
13291 if (GESI (tmp_tmp, 0)) {
13292 {
13293   tmp_tmp = SLLSI (tmp_tmp, 1);
13294   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13295 }
13296 }
13297 if (GESI (tmp_tmp, 0)) {
13298 {
13299   tmp_tmp = SLLSI (tmp_tmp, 1);
13300   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13301 }
13302 }
13303 if (GESI (tmp_tmp, 0)) {
13304 {
13305   tmp_tmp = SLLSI (tmp_tmp, 1);
13306   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13307 }
13308 }
13309 if (GESI (tmp_tmp, 0)) {
13310 {
13311   tmp_tmp = SLLSI (tmp_tmp, 1);
13312   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13313 }
13314 }
13315 if (GESI (tmp_tmp, 0)) {
13316 {
13317   tmp_tmp = SLLSI (tmp_tmp, 1);
13318   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13319 }
13320 }
13321 if (GESI (tmp_tmp, 0)) {
13322 {
13323   tmp_tmp = SLLSI (tmp_tmp, 1);
13324   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13325 }
13326 }
13327 if (GESI (tmp_tmp, 0)) {
13328 {
13329   tmp_tmp = SLLSI (tmp_tmp, 1);
13330   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13331 }
13332 }
13333 if (GESI (tmp_tmp, 0)) {
13334 {
13335   tmp_tmp = SLLSI (tmp_tmp, 1);
13336   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13337 }
13338 }
13339 if (GESI (tmp_tmp, 0)) {
13340 {
13341   tmp_tmp = SLLSI (tmp_tmp, 1);
13342   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13343 }
13344 }
13345 }
13346   {
13347     SI opval = tmp_tmpd;
13348     SET_H_GR (FLD (f_operand2), opval);
13349     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13350   }
13351 {
13352   {
13353     BI opval = LTSI (tmp_tmpd, 0);
13354     CPU (h_nbit) = opval;
13355     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13356   }
13357   {
13358     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13359     CPU (h_zbit) = opval;
13360     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13361   }
13362 SET_H_CBIT_MOVE (0);
13363 SET_H_VBIT_MOVE (0);
13364 {
13365   {
13366     BI opval = 0;
13367     CPU (h_xbit) = opval;
13368     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13369   }
13370   {
13371     BI opval = 0;
13372     SET_H_INSN_PREFIXED_P (opval);
13373     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13374   }
13375 }
13376 }
13377 }
13378
13379 #undef FLD
13380 }
13381   NEXT (vpc);
13382
13383   CASE (sem, INSN_ADDOQ) : /* addoq $o,$Rs,ACR */
13384 {
13385   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13386   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13387 #define FLD(f) abuf->fields.sfmt_addoq.f
13388   int UNUSED written = 0;
13389   IADDR UNUSED pc = abuf->addr;
13390   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13391
13392 {
13393   {
13394     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s8));
13395     CPU (h_prefixreg_pre_v32) = opval;
13396     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13397   }
13398   {
13399     BI opval = 1;
13400     SET_H_INSN_PREFIXED_P (opval);
13401     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13402   }
13403 }
13404
13405 #undef FLD
13406 }
13407   NEXT (vpc);
13408
13409   CASE (sem, INSN_BDAPQPC) : /* bdapq $o,PC */
13410 {
13411   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13412   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13413 #define FLD(f) abuf->fields.sfmt_addoq.f
13414   int UNUSED written = 0;
13415   IADDR UNUSED pc = abuf->addr;
13416   SEM_BRANCH_INIT
13417   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13418
13419 {
13420   {
13421     SI opval = ADDSI (ADDSI (pc, 2), FLD (f_s8));
13422     CPU (h_prefixreg_pre_v32) = opval;
13423     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13424   }
13425   {
13426     BI opval = 1;
13427     SET_H_INSN_PREFIXED_P (opval);
13428     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13429   }
13430 cris_flush_simulator_decode_cache (current_cpu, pc);
13431 }
13432
13433   SEM_BRANCH_FINI (vpc);
13434 #undef FLD
13435 }
13436   NEXT (vpc);
13437
13438   CASE (sem, INSN_BDAP_32_PC) : /* bdap ${sconst32},PC */
13439 {
13440   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13441   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13442 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
13443   int UNUSED written = 0;
13444   IADDR UNUSED pc = abuf->addr;
13445   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13446
13447 {
13448   SI tmp_newpc;
13449   SI tmp_oldpc;
13450   SI tmp_offs;
13451   tmp_offs = FLD (f_indir_pc__dword);
13452   tmp_oldpc = ADDSI (pc, 6);
13453   tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
13454   {
13455     SI opval = tmp_newpc;
13456     CPU (h_prefixreg_pre_v32) = opval;
13457     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13458   }
13459   {
13460     BI opval = 1;
13461     SET_H_INSN_PREFIXED_P (opval);
13462     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13463   }
13464 }
13465
13466 #undef FLD
13467 }
13468   NEXT (vpc);
13469
13470   CASE (sem, INSN_MOVE_M_PCPLUS_P0) : /* move [PC+],P0 */
13471 {
13472   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13473   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13474 #define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f
13475   int UNUSED written = 0;
13476   IADDR UNUSED pc = abuf->addr;
13477   SEM_BRANCH_INIT
13478   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13479
13480 if (GET_H_INSN_PREFIXED_P ()) {
13481 {
13482   QI tmp_dummy;
13483   tmp_dummy = ({   SI tmp_addr;
13484   QI tmp_tmp_mem;
13485   BI tmp_postinc;
13486   tmp_postinc = FLD (f_memmode);
13487 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (pc) : (CPU (h_prefixreg_pre_v32)));
13488 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
13489 ; if (NEBI (tmp_postinc, 0)) {
13490 {
13491 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13492   tmp_addr = ADDSI (tmp_addr, 1);
13493 }
13494   {
13495     USI opval = tmp_addr;
13496     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13497     written |= (1 << 5);
13498     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13499   }
13500 }
13501 }
13502 ; tmp_tmp_mem; });
13503 {
13504   {
13505     BI opval = 0;
13506     CPU (h_xbit) = opval;
13507     written |= (1 << 7);
13508     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13509   }
13510   {
13511     BI opval = 0;
13512     SET_H_INSN_PREFIXED_P (opval);
13513     written |= (1 << 6);
13514     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13515   }
13516 }
13517 }
13518 } else {
13519 cgen_rtx_error (current_cpu, "move [PC+],P0 without prefix is not implemented");
13520 }
13521
13522   abuf->written = written;
13523   SEM_BRANCH_FINI (vpc);
13524 #undef FLD
13525 }
13526   NEXT (vpc);
13527
13528   CASE (sem, INSN_MOVE_M_SPPLUS_P8) : /* move [SP+],P8 */
13529 {
13530   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13531   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13532 #define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f
13533   int UNUSED written = 0;
13534   IADDR UNUSED pc = abuf->addr;
13535   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13536
13537 if (GET_H_INSN_PREFIXED_P ()) {
13538 {
13539   SI tmp_dummy;
13540   tmp_dummy = ({   SI tmp_addr;
13541   SI tmp_tmp_mem;
13542   BI tmp_postinc;
13543   tmp_postinc = FLD (f_memmode);
13544 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (((UINT) 14))) : (CPU (h_prefixreg_pre_v32)));
13545 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13546 ; if (NEBI (tmp_postinc, 0)) {
13547 {
13548 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13549   tmp_addr = ADDSI (tmp_addr, 4);
13550 }
13551   {
13552     SI opval = tmp_addr;
13553     SET_H_GR (((UINT) 14), opval);
13554     written |= (1 << 5);
13555     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13556   }
13557 }
13558 }
13559 ; tmp_tmp_mem; });
13560 {
13561   {
13562     BI opval = 0;
13563     CPU (h_xbit) = opval;
13564     written |= (1 << 7);
13565     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13566   }
13567   {
13568     BI opval = 0;
13569     SET_H_INSN_PREFIXED_P (opval);
13570     written |= (1 << 6);
13571     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13572   }
13573 }
13574 }
13575 } else {
13576 cgen_rtx_error (current_cpu, "move [SP+],P8 without prefix is not implemented");
13577 }
13578
13579   abuf->written = written;
13580 #undef FLD
13581 }
13582   NEXT (vpc);
13583
13584   CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */
13585 {
13586   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13587   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13588 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
13589   int UNUSED written = 0;
13590   IADDR UNUSED pc = abuf->addr;
13591   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13592
13593 {
13594   QI tmp_tmps;
13595   tmp_tmps = ({   SI tmp_addr;
13596   QI tmp_tmp_mem;
13597   BI tmp_postinc;
13598   tmp_postinc = FLD (f_memmode);
13599 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13600 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
13601 ; if (NEBI (tmp_postinc, 0)) {
13602 {
13603 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13604   tmp_addr = ADDSI (tmp_addr, 1);
13605 }
13606   {
13607     SI opval = tmp_addr;
13608     SET_H_GR (FLD (f_operand1), opval);
13609     written |= (1 << 6);
13610     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13611   }
13612 }
13613 }
13614 ; tmp_tmp_mem; });
13615   {
13616     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (tmp_tmps));
13617     CPU (h_prefixreg_pre_v32) = opval;
13618     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13619   }
13620   {
13621     BI opval = 1;
13622     SET_H_INSN_PREFIXED_P (opval);
13623     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13624   }
13625 }
13626
13627   abuf->written = written;
13628 #undef FLD
13629 }
13630   NEXT (vpc);
13631
13632   CASE (sem, INSN_ADDO_M_W_M) : /* addo-m.w [${Rs}${inc}],$Rd,ACR */
13633 {
13634   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13635   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13636 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
13637   int UNUSED written = 0;
13638   IADDR UNUSED pc = abuf->addr;
13639   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13640
13641 {
13642   HI tmp_tmps;
13643   tmp_tmps = ({   SI tmp_addr;
13644   HI tmp_tmp_mem;
13645   BI tmp_postinc;
13646   tmp_postinc = FLD (f_memmode);
13647 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13648 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
13649 ; if (NEBI (tmp_postinc, 0)) {
13650 {
13651 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13652   tmp_addr = ADDSI (tmp_addr, 2);
13653 }
13654   {
13655     SI opval = tmp_addr;
13656     SET_H_GR (FLD (f_operand1), opval);
13657     written |= (1 << 6);
13658     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13659   }
13660 }
13661 }
13662 ; tmp_tmp_mem; });
13663   {
13664     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (tmp_tmps));
13665     CPU (h_prefixreg_pre_v32) = opval;
13666     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13667   }
13668   {
13669     BI opval = 1;
13670     SET_H_INSN_PREFIXED_P (opval);
13671     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13672   }
13673 }
13674
13675   abuf->written = written;
13676 #undef FLD
13677 }
13678   NEXT (vpc);
13679
13680   CASE (sem, INSN_ADDO_M_D_M) : /* addo-m.d [${Rs}${inc}],$Rd,ACR */
13681 {
13682   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13683   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13684 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
13685   int UNUSED written = 0;
13686   IADDR UNUSED pc = abuf->addr;
13687   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13688
13689 {
13690   SI tmp_tmps;
13691   tmp_tmps = ({   SI tmp_addr;
13692   SI tmp_tmp_mem;
13693   BI tmp_postinc;
13694   tmp_postinc = FLD (f_memmode);
13695 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13696 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13697 ; if (NEBI (tmp_postinc, 0)) {
13698 {
13699 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13700   tmp_addr = ADDSI (tmp_addr, 4);
13701 }
13702   {
13703     SI opval = tmp_addr;
13704     SET_H_GR (FLD (f_operand1), opval);
13705     written |= (1 << 6);
13706     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13707   }
13708 }
13709 }
13710 ; tmp_tmp_mem; });
13711   {
13712     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), tmp_tmps);
13713     CPU (h_prefixreg_pre_v32) = opval;
13714     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13715   }
13716   {
13717     BI opval = 1;
13718     SET_H_INSN_PREFIXED_P (opval);
13719     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13720   }
13721 }
13722
13723   abuf->written = written;
13724 #undef FLD
13725 }
13726   NEXT (vpc);
13727
13728   CASE (sem, INSN_ADDO_CB) : /* addo.b [PC+],$Rd,ACR */
13729 {
13730   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13731   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13732 #define FLD(f) abuf->fields.sfmt_bound_cb.f
13733   int UNUSED written = 0;
13734   IADDR UNUSED pc = abuf->addr;
13735   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13736
13737 {
13738   {
13739     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))));
13740     CPU (h_prefixreg_pre_v32) = opval;
13741     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13742   }
13743   {
13744     BI opval = 1;
13745     SET_H_INSN_PREFIXED_P (opval);
13746     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13747   }
13748 }
13749
13750 #undef FLD
13751 }
13752   NEXT (vpc);
13753
13754   CASE (sem, INSN_ADDO_CW) : /* addo.w [PC+],$Rd,ACR */
13755 {
13756   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13757   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13758 #define FLD(f) abuf->fields.sfmt_bound_cw.f
13759   int UNUSED written = 0;
13760   IADDR UNUSED pc = abuf->addr;
13761   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13762
13763 {
13764   {
13765     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))));
13766     CPU (h_prefixreg_pre_v32) = opval;
13767     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13768   }
13769   {
13770     BI opval = 1;
13771     SET_H_INSN_PREFIXED_P (opval);
13772     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13773   }
13774 }
13775
13776 #undef FLD
13777 }
13778   NEXT (vpc);
13779
13780   CASE (sem, INSN_ADDO_CD) : /* addo.d [PC+],$Rd,ACR */
13781 {
13782   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13783   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13784 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13785   int UNUSED written = 0;
13786   IADDR UNUSED pc = abuf->addr;
13787   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13788
13789 {
13790   {
13791     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
13792     CPU (h_prefixreg_pre_v32) = opval;
13793     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13794   }
13795   {
13796     BI opval = 1;
13797     SET_H_INSN_PREFIXED_P (opval);
13798     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13799   }
13800 }
13801
13802 #undef FLD
13803 }
13804   NEXT (vpc);
13805
13806   CASE (sem, INSN_DIP_M) : /* dip [${Rs}${inc}] */
13807 {
13808   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13809   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13810 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
13811   int UNUSED written = 0;
13812   IADDR UNUSED pc = abuf->addr;
13813   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13814
13815 {
13816   SI tmp_tmps;
13817   tmp_tmps = ({   SI tmp_addr;
13818   SI tmp_tmp_mem;
13819   BI tmp_postinc;
13820   tmp_postinc = FLD (f_memmode);
13821 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13822 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13823 ; if (NEBI (tmp_postinc, 0)) {
13824 {
13825 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13826   tmp_addr = ADDSI (tmp_addr, 4);
13827 }
13828   {
13829     SI opval = tmp_addr;
13830     SET_H_GR (FLD (f_operand1), opval);
13831     written |= (1 << 5);
13832     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13833   }
13834 }
13835 }
13836 ; tmp_tmp_mem; });
13837   {
13838     SI opval = tmp_tmps;
13839     CPU (h_prefixreg_pre_v32) = opval;
13840     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13841   }
13842   {
13843     BI opval = 1;
13844     SET_H_INSN_PREFIXED_P (opval);
13845     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13846   }
13847 }
13848
13849   abuf->written = written;
13850 #undef FLD
13851 }
13852   NEXT (vpc);
13853
13854   CASE (sem, INSN_DIP_C) : /* dip [PC+] */
13855 {
13856   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13857   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13858 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
13859   int UNUSED written = 0;
13860   IADDR UNUSED pc = abuf->addr;
13861   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13862
13863 {
13864   {
13865     SI opval = FLD (f_indir_pc__dword);
13866     CPU (h_prefixreg_pre_v32) = opval;
13867     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13868   }
13869   {
13870     BI opval = 1;
13871     SET_H_INSN_PREFIXED_P (opval);
13872     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13873   }
13874 }
13875
13876 #undef FLD
13877 }
13878   NEXT (vpc);
13879
13880   CASE (sem, INSN_ADDI_ACR_B_R) : /* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
13881 {
13882   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13883   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13884 #define FLD(f) abuf->fields.sfmt_add_b_r.f
13885   int UNUSED written = 0;
13886   IADDR UNUSED pc = abuf->addr;
13887   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13888
13889 {
13890   {
13891     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
13892     CPU (h_prefixreg_pre_v32) = opval;
13893     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13894   }
13895   {
13896     BI opval = 1;
13897     SET_H_INSN_PREFIXED_P (opval);
13898     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13899   }
13900 }
13901
13902 #undef FLD
13903 }
13904   NEXT (vpc);
13905
13906   CASE (sem, INSN_ADDI_ACR_W_R) : /* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
13907 {
13908   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13909   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13910 #define FLD(f) abuf->fields.sfmt_add_b_r.f
13911   int UNUSED written = 0;
13912   IADDR UNUSED pc = abuf->addr;
13913   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13914
13915 {
13916   {
13917     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
13918     CPU (h_prefixreg_pre_v32) = opval;
13919     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13920   }
13921   {
13922     BI opval = 1;
13923     SET_H_INSN_PREFIXED_P (opval);
13924     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13925   }
13926 }
13927
13928 #undef FLD
13929 }
13930   NEXT (vpc);
13931
13932   CASE (sem, INSN_ADDI_ACR_D_R) : /* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
13933 {
13934   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13935   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13936 #define FLD(f) abuf->fields.sfmt_add_b_r.f
13937   int UNUSED written = 0;
13938   IADDR UNUSED pc = abuf->addr;
13939   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13940
13941 {
13942   {
13943     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
13944     CPU (h_prefixreg_pre_v32) = opval;
13945     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13946   }
13947   {
13948     BI opval = 1;
13949     SET_H_INSN_PREFIXED_P (opval);
13950     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13951   }
13952 }
13953
13954 #undef FLD
13955 }
13956   NEXT (vpc);
13957
13958   CASE (sem, INSN_BIAP_PC_B_R) : /* biap-pc.b ${Rs-dfield}.m,PC */
13959 {
13960   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13961   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13962 #define FLD(f) abuf->fields.sfmt_addoq.f
13963   int UNUSED written = 0;
13964   IADDR UNUSED pc = abuf->addr;
13965   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13966
13967 {
13968   {
13969     SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 1));
13970     CPU (h_prefixreg_pre_v32) = opval;
13971     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13972   }
13973   {
13974     BI opval = 1;
13975     SET_H_INSN_PREFIXED_P (opval);
13976     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13977   }
13978 }
13979
13980 #undef FLD
13981 }
13982   NEXT (vpc);
13983
13984   CASE (sem, INSN_BIAP_PC_W_R) : /* biap-pc.w ${Rs-dfield}.m,PC */
13985 {
13986   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13987   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13988 #define FLD(f) abuf->fields.sfmt_addoq.f
13989   int UNUSED written = 0;
13990   IADDR UNUSED pc = abuf->addr;
13991   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13992
13993 {
13994   {
13995     SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 2));
13996     CPU (h_prefixreg_pre_v32) = opval;
13997     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13998   }
13999   {
14000     BI opval = 1;
14001     SET_H_INSN_PREFIXED_P (opval);
14002     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14003   }
14004 }
14005
14006 #undef FLD
14007 }
14008   NEXT (vpc);
14009
14010   CASE (sem, INSN_BIAP_PC_D_R) : /* biap-pc.d ${Rs-dfield}.m,PC */
14011 {
14012   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14013   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14014 #define FLD(f) abuf->fields.sfmt_addoq.f
14015   int UNUSED written = 0;
14016   IADDR UNUSED pc = abuf->addr;
14017   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14018
14019 {
14020   {
14021     SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 4));
14022     CPU (h_prefixreg_pre_v32) = opval;
14023     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14024   }
14025   {
14026     BI opval = 1;
14027     SET_H_INSN_PREFIXED_P (opval);
14028     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14029   }
14030 }
14031
14032 #undef FLD
14033 }
14034   NEXT (vpc);
14035
14036
14037     }
14038   ENDSWITCH (sem) /* End of semantic switch.  */
14039
14040   /* At this point `vpc' contains the next insn to execute.  */
14041 }
14042
14043 #undef DEFINE_SWITCH
14044 #endif /* DEFINE_SWITCH */