6 #include "opcode/d10v.h"
9 #define DEBUG_TRACE 0x00000001
10 #define DEBUG_VALUES 0x00000002
11 #define DEBUG_LINE_NUMBER 0x00000004
12 #define DEBUG_MEMSIZE 0x00000008
13 #define DEBUG_INSTRUCTION 0x00000010
16 #define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
19 extern int d10v_debug
;
22 typedef unsigned char uint8
;
23 typedef signed char int8
;
25 #error "Char is not an 8-bit type"
29 typedef unsigned short uint16
;
30 typedef signed short int16
;
32 #error "Short is not a 16-bit type"
35 #if INT_MAX == 2147483647
36 typedef unsigned int uint32
;
37 typedef signed int int32
;
39 #elif LONG_MAX == 2147483647
40 typedef unsigned long uint32
;
41 typedef signed long int32
;
44 #error "Neither int nor long is a 32-bit type"
47 #if LONG_MAX > 2147483647
48 typedef unsigned long uint64
;
49 typedef signed long int64
;
52 typedef unsigned long long uint64
;
53 typedef signed long long int64
;
56 #error "Can't find an appropriate 64-bit type"
59 /* FIXME: D10V defines */
77 INS_UNKNOWN
, /* unknown instruction */
78 INS_COND_TRUE
, /* # times EXExxx executed other instruction */
79 INS_COND_FALSE
, /* # times EXExxx did not execute other instruction */
80 INS_COND_JUMP
, /* # times JUMP skipped other instruction */
81 INS_CYCLES
, /* # cycles */
82 INS_LONG
, /* long instruction (both containers, ie FM == 11) */
83 INS_LEFTRIGHT
, /* # times instruction encoded as L -> R (ie, FM == 01) */
84 INS_RIGHTLEFT
, /* # times instruction encoded as L <- R (ie, FM == 10) */
85 INS_PARALLEL
, /* # times instruction encoded as L || R (ie, RM == 00) */
87 INS_LEFT
, /* normal left instructions */
88 INS_LEFT_PARALLEL
, /* left side of || */
89 INS_LEFT_COND_TEST
, /* EXExx test on left side */
90 INS_LEFT_COND_EXE
, /* execution after EXExxx test on right side succeeded */
91 INS_LEFT_NOPS
, /* NOP on left side */
93 INS_RIGHT
, /* normal right instructions */
94 INS_RIGHT_PARALLEL
, /* right side of || */
95 INS_RIGHT_COND_TEST
, /* EXExx test on right side */
96 INS_RIGHT_COND_EXE
, /* execution after EXExxx test on left side succeeded */
97 INS_RIGHT_NOPS
, /* NOP on right side */
102 extern unsigned long ins_type_counters
[ (int)INS_MAX
];
106 reg_t regs
[16]; /* general-purpose registers */
107 reg_t cregs
[16]; /* control registers */
108 int64 a
[2]; /* accumulators */
122 /* everything below this line is not reset by sim_create_inferior() */
126 enum _ins_type ins_type
;
129 extern host_callback
*d10v_callback
;
131 extern struct simops Simops
[];
132 extern asection
*text
;
133 extern bfd_vma text_start
;
134 extern bfd_vma text_end
;
135 extern bfd
*exec_bfd
;
137 #define PC (State.cregs[2])
138 #define PSW (State.cregs[0])
139 #define BPSW (State.cregs[1])
140 #define BPC (State.cregs[3])
141 #define RPT_C (State.cregs[7])
142 #define RPT_S (State.cregs[8])
143 #define RPT_E (State.cregs[9])
144 #define MOD_S (State.cregs[10])
145 #define MOD_E (State.cregs[11])
146 #define IBA (State.cregs[14])
148 #define SIG_D10V_STOP -1
149 #define SIG_D10V_EXIT -2
151 #define SEXT3(x) ((((x)&0x7)^(~3))+4)
153 /* sign-extend a 4-bit number */
154 #define SEXT4(x) ((((x)&0xf)^(~7))+8)
156 /* sign-extend an 8-bit number */
157 #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
159 /* sign-extend a 16-bit number */
160 #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
162 /* sign-extend a 32-bit number */
163 #define SEXT32(x) ((((x)&0xffffffffLL)^(~0x7fffffffLL))+0x80000000LL)
165 /* sign extend a 40 bit number */
166 #define SEXT40(x) ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL)
168 /* sign extend a 44 bit number */
169 #define SEXT44(x) ((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL)
171 /* sign extend a 60 bit number */
172 #define SEXT60(x) ((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL)
174 #define MAX32 0x7fffffffLL
175 #define MIN32 0xff80000000LL
176 #define MASK32 0xffffffffLL
177 #define MASK40 0xffffffffffLL
179 #define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
181 extern uint8
*dmem_addr
PARAMS ((uint32
));
182 extern bfd_vma decode_pc
PARAMS ((void));
184 #define RB(x) (*(dmem_addr(x)))
185 #define SB(addr,data) ( RB(addr) = (data & 0xff))
187 #if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
188 #define ENDIAN_INLINE static __inline__
193 extern uint32 get_longword
PARAMS ((uint8
*));
194 extern uint16 get_word
PARAMS ((uint8
*));
195 extern int64 get_longlong
PARAMS ((uint8
*));
196 extern void write_word
PARAMS ((uint8
*addr
, uint16 data
));
197 extern void write_longword
PARAMS ((uint8
*addr
, uint32 data
));
198 extern void write_longlong
PARAMS ((uint8
*addr
, int64 data
));
201 #define SW(addr,data) write_word(dmem_addr(addr),data)
202 #define RW(x) get_word(dmem_addr(x))
203 #define SLW(addr,data) write_longword(dmem_addr(addr),data)
204 #define RLW(x) get_longword(dmem_addr(x))
205 #define READ_16(x) get_word(x)
206 #define WRITE_16(addr,data) write_word(addr,data)
207 #define READ_64(x) get_longlong(x)
208 #define WRITE_64(addr,data) write_longlong(addr,data)
210 #define IMAP0 RW(0xff00)
211 #define IMAP1 RW(0xff02)
212 #define DMAP RW(0xff04)
213 #define SET_IMAP0(x) SW(0xff00,x)
214 #define SET_IMAP1(x) SW(0xff02,x)
215 #define SET_DMAP(x) SW(0xff04,x)
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