59787f15e63e23b726d1d696206bfa0b6b22810f
7 #include "opcode/d10v.h"
10 #define DEBUG_TRACE 0x00000001
11 #define DEBUG_VALUES 0x00000002
12 #define DEBUG_LINE_NUMBER 0x00000004
13 #define DEBUG_MEMSIZE 0x00000008
14 #define DEBUG_INSTRUCTION 0x00000010
17 #define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
20 extern int d10v_debug
;
22 #include "sim-types.h"
23 typedef unsigned8 uint8
;
24 typedef unsigned16 uint16
;
25 typedef signed16 int16
;
26 typedef unsigned32 uint32
;
27 typedef signed32 int32
;
28 typedef unsigned64 uint64
;
29 typedef signed64 int64
;
31 /* FIXME: D10V defines */
50 INS_UNKNOWN
, /* unknown instruction */
51 INS_COND_TRUE
, /* # times EXExxx executed other instruction */
52 INS_COND_FALSE
, /* # times EXExxx did not execute other instruction */
53 INS_COND_JUMP
, /* # times JUMP skipped other instruction */
54 INS_CYCLES
, /* # cycles */
55 INS_LONG
, /* long instruction (both containers, ie FM == 11) */
56 INS_LEFTRIGHT
, /* # times instruction encoded as L -> R (ie, FM == 01) */
57 INS_RIGHTLEFT
, /* # times instruction encoded as L <- R (ie, FM == 10) */
58 INS_PARALLEL
, /* # times instruction encoded as L || R (ie, RM == 00) */
60 INS_LEFT
, /* normal left instructions */
61 INS_LEFT_PARALLEL
, /* left side of || */
62 INS_LEFT_COND_TEST
, /* EXExx test on left side */
63 INS_LEFT_COND_EXE
, /* execution after EXExxx test on right side succeeded */
64 INS_LEFT_NOPS
, /* NOP on left side */
66 INS_RIGHT
, /* normal right instructions */
67 INS_RIGHT_PARALLEL
, /* right side of || */
68 INS_RIGHT_COND_TEST
, /* EXExx test on right side */
69 INS_RIGHT_COND_EXE
, /* execution after EXExxx test on left side succeeded */
70 INS_RIGHT_NOPS
, /* NOP on right side */
75 extern unsigned long ins_type_counters
[ (int)INS_MAX
];
79 reg_t regs
[16]; /* general-purpose registers */
80 reg_t cregs
[16]; /* control registers */
81 int64 a
[2]; /* accumulators */
97 /* everything below this line is not reset by sim_create_inferior() */
101 enum _ins_type ins_type
;
104 extern host_callback
*d10v_callback
;
106 extern struct simops Simops
[];
107 extern asection
*text
;
108 extern bfd_vma text_start
;
109 extern bfd_vma text_end
;
110 extern bfd
*prog_bfd
;
142 /* See simopsc.:move_to_cr() for registers that can not be read-from
143 or assigned-to directly */
144 #define PC (State.cregs[PC_CR])
145 #define PSW (move_from_cr (PSW_CR))
146 #define BPSW (0 + State.cregs[PSW_CR])
147 #define BPC (State.cregs[BPC_CR])
148 #define RPT_C (State.cregs[RPT_C_CR])
149 #define RPT_S (State.cregs[RPT_S_CR])
150 #define RPT_E (State.cregs[RPT_E_CR])
151 #define MOD_S (0 + State.cregs[MOD_S_CR])
152 #define MOD_E (0 + State.cregs[MOD_E_CR])
153 #define IBA (State.cregs[IBA_CR])
155 #define SIG_D10V_STOP -1
156 #define SIG_D10V_EXIT -2
158 #define SEXT3(x) ((((x)&0x7)^(~3))+4)
160 /* sign-extend a 4-bit number */
161 #define SEXT4(x) ((((x)&0xf)^(~7))+8)
163 /* sign-extend an 8-bit number */
164 #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
166 /* sign-extend a 16-bit number */
167 #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
169 /* sign-extend a 32-bit number */
170 #define SEXT32(x) ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000))
172 /* sign extend a 40 bit number */
173 #define SEXT40(x) ((((x)&SIGNED64(0xffffffffff))^(~SIGNED64(0x7fffffffff)))+SIGNED64(0x8000000000))
175 /* sign extend a 44 bit number */
176 #define SEXT44(x) ((((x)&SIGNED64(0xfffffffffff))^(~SIGNED64(0x7ffffffffff)))+SIGNED64(0x80000000000))
178 /* sign extend a 56 bit number */
179 #define SEXT56(x) ((((x)&SIGNED64(0xffffffffffffff))^(~SIGNED64(0x7fffffffffffff)))+SIGNED64(0x80000000000000))
181 /* sign extend a 60 bit number */
182 #define SEXT60(x) ((((x)&SIGNED64(0xfffffffffffffff))^(~SIGNED64(0x7ffffffffffffff)))+SIGNED64(0x800000000000000))
184 #define MAX32 SIGNED64(0x7fffffff)
185 #define MIN32 SIGNED64(0xff80000000)
186 #define MASK32 SIGNED64(0xffffffff)
187 #define MASK40 SIGNED64(0xffffffffff)
189 /* The alignment of MOD_E in the following macro depends upon "i" always being a power of 2. */
190 #define INC_ADDR(x,i) x = ((State.MD && x == (MOD_E & ~((i)-1))) ? MOD_S : (x)+(i))
192 extern uint8
*dmem_addr
PARAMS ((uint32
));
193 extern bfd_vma decode_pc
PARAMS ((void));
195 #define RB(x) (*(dmem_addr(x)))
196 #define SB(addr,data) ( RB(addr) = (data & 0xff))
198 #if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
199 #define ENDIAN_INLINE static __inline__
204 extern uint32 get_longword
PARAMS ((uint8
*));
205 extern uint16 get_word
PARAMS ((uint8
*));
206 extern int64 get_longlong
PARAMS ((uint8
*));
207 extern void write_word
PARAMS ((uint8
*addr
, uint16 data
));
208 extern void write_longword
PARAMS ((uint8
*addr
, uint32 data
));
209 extern void write_longlong
PARAMS ((uint8
*addr
, int64 data
));
212 #define SW(addr,data) write_word(dmem_addr(addr),data)
213 #define RW(x) get_word(dmem_addr(x))
214 #define SLW(addr,data) write_longword(dmem_addr(addr),data)
215 #define RLW(x) get_longword(dmem_addr(x))
216 #define READ_16(x) get_word(x)
217 #define WRITE_16(addr,data) write_word(addr,data)
218 #define READ_64(x) get_longlong(x)
219 #define WRITE_64(addr,data) write_longlong(addr,data)
221 #define IMAP0 RW(0xff00)
222 #define IMAP1 RW(0xff02)
223 #define DMAP RW(0xff04)
224 #define SET_IMAP0(x) SW(0xff00,x)
225 #define SET_IMAP1(x) SW(0xff02,x)
226 #define SET_DMAP(x) SW(0xff04,x)
228 #define JMP(x) { PC = (x); State.pc_changed = 1; }
230 #define AE_VECTOR_START 0xffc3
231 #define RIE_VECTOR_START 0xffc2
232 #define SDBT_VECTOR_START 0xffd5
233 #define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */
235 extern void move_to_cr
PARAMS ((int cr
, reg_t val
));
236 extern reg_t move_from_cr
PARAMS ((int cr
));
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