4 #include "opcode/d10v.h"
6 /* FIXME: host defines */
7 typedef unsigned char uint8
;
8 typedef unsigned short uint16
;
9 typedef unsigned int uint32
;
10 typedef signed char int8
;
11 typedef signed short int16
;
12 typedef signed int int32
;
13 typedef signed long long int64
;
15 /* FIXME: D10V defines */
33 reg_t regs
[16]; /* general-purpose registers */
34 reg_t cregs
[15]; /* control registers */
35 int64 a
[2]; /* accumulators */
53 extern struct simops Simops
[];
55 #define PC (State.cregs[2])
56 #define PSW (State.cregs[0])
57 #define BPSW (State.cregs[1])
58 #define BPC (State.cregs[3])
59 #define RPT_C (State.cregs[7])
60 #define RPT_S (State.cregs[8])
61 #define RPT_E (State.cregs[9])
62 #define MOD_S (State.cregs[10])
63 #define MOD_E (State.cregs[11])
64 #define IBA (State.cregs[14])
66 #define SEXT3(x) ((((x)&0x7)^(~3))+4)
68 /* sign-extend a 4-bit number */
69 #define SEXT4(x) ((((x)&0xf)^(~7))+8)
71 /* sign-extend an 8-bit number */
72 #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
74 /* sign-extend a 16-bit number */
75 #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
77 /* sign extend a 40 bit number */
78 #define SEXT40(x) ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL)
80 #define MAX32 0x7fffffffLL
81 #define MIN32 0xff80000000LL
82 #define MASK32 0xffffffffLL
83 #define MASK40 0xffffffffffLL
85 #define RB(x) (*((uint8 *)((x)+State.imem)))
86 #define SB(addr,data) ( RB(addr) = (data & 0xff))
88 #ifdef WORDS_BIGENDIAN
90 #define RW(x) (*((uint16 *)((x)+State.imem)))
91 #define RLW(x) (*((uint32 *)((x)+State.imem)))
92 #define SW(addr,data) RW(addr)=data
96 uint32 get_longword_swap
PARAMS ((uint16 x
));
97 uint16 get_word_swap
PARAMS ((uint16 x
));
98 void write_word_swap
PARAMS ((uint16 addr
, uint16 data
));
100 #define SW(addr,data) write_word_swap(addr,data)
101 #define RW(x) get_word_swap(x)
102 #define RLW(x) get_longword_swap(x)
104 #endif /* not WORDS_BIGENDIAN */
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