1a1ede976b99c9360ddeaf54e52aa3db944c9043
4 #include "remote-sim.h"
8 #define IMEM_SIZE 18 /* D10V instruction memory size is 18 bits */
9 #define DMEM_SIZE 16 /* Data memory */
11 enum _leftright
{ LEFT_FIRST
, RIGHT_FIRST
};
14 host_callback
*d10v_callback
;
15 long ins_type_counters
[ (int)INS_MAX
];
16 long left_nops
, right_nops
;
20 static struct hash_entry
*lookup_hash
PARAMS ((uint32 ins
, int size
));
25 struct hash_entry
*next
;
31 struct hash_entry hash_table
[MAX_HASH
+1];
38 if (format
& LONG_OPCODE
)
39 return ((insn
& 0x3F000000) >> 24);
41 return((insn
& 0x7E00) >> 9);
44 static struct hash_entry
*
45 lookup_hash (ins
, size
)
52 h
= &hash_table
[(ins
& 0x3F000000) >> 24];
54 h
= &hash_table
[(ins
& 0x7E00) >> 9];
56 while ( (ins
& h
->mask
) != h
->opcode
)
60 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR looking up hash for %x at PC %x\n",ins
, PC
);
73 return (a
[0]<<24) + (a
[1]<<16) + (a
[2]<<8) + (a
[3]);
81 return ((int64
)a
[0]<<56) + ((int64
)a
[1]<<48) + ((int64
)a
[2]<<40) + ((int64
)a
[3]<<32) +
82 ((int64
)a
[4]<< 24) + ((int64
)a
[5]<<16) + ((int64
)a
[6]<<8) + (int64
)a
[7];
90 return ((uint16
)a
[0]<<8) + a
[1];
95 write_word (addr
, data
)
105 write_longword (addr
, data
)
109 addr
[0] = (data
>> 24) & 0xff;
110 addr
[1] = (data
>> 16) & 0xff;
111 addr
[2] = (data
>> 8) & 0xff;
112 addr
[3] = data
& 0xff;
116 write_longlong (addr
, data
)
122 a
[1] = (data
>> 48) & 0xff;
123 a
[2] = (data
>> 40) & 0xff;
124 a
[3] = (data
>> 32) & 0xff;
125 a
[4] = (data
>> 24) & 0xff;
126 a
[5] = (data
>> 16) & 0xff;
127 a
[6] = (data
>> 8) & 0xff;
132 get_operands (struct simops
*s
, uint32 ins
)
134 int i
, shift
, bits
, flags
;
136 for (i
=0; i
< s
->numops
; i
++)
138 shift
= s
->operands
[3*i
];
139 bits
= s
->operands
[3*i
+1];
140 flags
= s
->operands
[3*i
+2];
141 mask
= 0x7FFFFFFF >> (31 - bits
);
142 OP
[i
] = (ins
>> shift
) & mask
;
150 struct hash_entry
*h
;
152 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
153 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_long 0x%x\n", ins
);
155 h
= lookup_hash (ins
, 1);
156 get_operands (h
->ops
, ins
);
157 State
.ins_type
= INS_LONG
;
158 ins_type_counters
[ (int)State
.ins_type
]++;
162 do_2_short (ins1
, ins2
, leftright
)
164 enum _leftright leftright
;
166 struct hash_entry
*h
;
168 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
169 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_2_short 0x%x (%s) -> 0x%x\n",
170 ins1
, (leftright
) ? "left" : "right", ins2
);
172 /* printf ("do_2_short %x -> %x\n",ins1,ins2); */
173 h
= lookup_hash (ins1
, 0);
174 get_operands (h
->ops
, ins1
);
175 State
.ins_type
= (leftright
== LEFT_FIRST
) ? INS_LEFT
: INS_RIGHT
;
176 ins_type_counters
[ (int)State
.ins_type
]++;
178 h
= lookup_hash (ins2
, 0);
179 get_operands (h
->ops
, ins2
);
180 State
.ins_type
= (leftright
== LEFT_FIRST
) ? INS_RIGHT
: INS_LEFT
;
181 ins_type_counters
[ (int)State
.ins_type
]++;
185 do_parallel (ins1
, ins2
)
188 struct hash_entry
*h1
, *h2
;
190 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
191 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_parallel 0x%x || 0x%x\n", ins1
, ins2
);
193 h1
= lookup_hash (ins1
, 0);
194 h2
= lookup_hash (ins2
, 0);
196 if (h1
->ops
->exec_type
== PARONLY
)
198 get_operands (h1
->ops
, ins1
);
199 State
.ins_type
= INS_LEFT
;
200 ins_type_counters
[ (int)State
.ins_type
]++;
204 get_operands (h2
->ops
, ins2
);
205 State
.ins_type
= INS_RIGHT
;
209 else if (h2
->ops
->exec_type
== PARONLY
)
211 get_operands (h2
->ops
, ins2
);
212 State
.ins_type
= INS_RIGHT
;
213 ins_type_counters
[ (int)State
.ins_type
]++;
217 get_operands (h1
->ops
, ins1
);
218 State
.ins_type
= INS_LEFT
;
224 get_operands (h1
->ops
, ins1
);
225 State
.ins_type
= INS_LEFT_PARALLEL
;
226 ins_type_counters
[ (int)State
.ins_type
]++;
228 get_operands (h2
->ops
, ins2
);
229 State
.ins_type
= INS_RIGHT_PARALLEL
;
230 ins_type_counters
[ (int)State
.ins_type
]++;
247 State
.imem
= (uint8
*)calloc(1,1<<IMEM_SIZE
);
248 State
.dmem
= (uint8
*)calloc(1,1<<DMEM_SIZE
);
249 if (!State
.imem
|| !State
.dmem
)
251 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Memory allocation failed.\n");
256 if ((d10v_debug
& DEBUG_MEMSIZE
) != 0)
258 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Allocated %d bytes instruction memory and\n",1<<IMEM_SIZE
);
259 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %d bytes data memory.\n", 1<<DMEM_SIZE
);
272 sim_write (addr
, buffer
, size
)
274 unsigned char *buffer
;
280 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%x\n",size,addr); */
281 for (i
= 0; i
< size
; i
++)
283 State
.imem
[i
+addr
] = buffer
[i
];
293 struct hash_entry
*h
, *prev
;
295 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_open %s\n",args
);
297 /* put all the opcodes in the hash table */
298 for (s
= Simops
; s
->func
; s
++)
300 h
= &hash_table
[hash(s
->opcode
,s
->format
)];
302 /* go to the last entry in the chain */
308 h
->next
= calloc(1,sizeof(struct hash_entry
));
313 h
->opcode
= s
->opcode
;
329 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_set_profile %d\n",n
);
333 sim_set_profile_size (n
)
336 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_set_profile_size %d\n",n
);
340 sim_resume (step
, siggnal
)
347 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
350 State
.exception
= SIGTRAP
;
356 inst
= RLW (PC
<< 2);
358 switch (inst
& 0xC0000000)
361 /* long instruction */
362 do_long (inst
& 0x3FFFFFFF);
366 do_2_short ( inst
& 0x7FFF, (inst
& 0x3FFF8000) >> 15, 0);
370 do_2_short ((inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF, 1);
373 do_parallel ((inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF);
377 if (State
.RP
&& PC
== RPT_E
)
390 while (!State
.exception
);
409 long total
= (ins_type_counters
[ (int)INS_LONG
]
410 + ins_type_counters
[ (int)INS_LEFT
]
411 + ins_type_counters
[ (int)INS_LEFT_PARALLEL
]
412 + ins_type_counters
[ (int)INS_RIGHT
]
413 + ins_type_counters
[ (int)INS_RIGHT_PARALLEL
]);
415 sprintf (buf
, "%ld", total
);
418 (*d10v_callback
->printf_filtered
) (d10v_callback
,
419 "executed %*ld instructions in the left container, %*ld parallel, %*ld nops\n",
420 size
, ins_type_counters
[ (int)INS_LEFT
] + ins_type_counters
[ (int)INS_LEFT_PARALLEL
],
421 size
, ins_type_counters
[ (int)INS_LEFT_PARALLEL
],
424 (*d10v_callback
->printf_filtered
) (d10v_callback
,
425 "executed %*ld instructions in the right container, %*ld parallel, %*ld nops\n",
426 size
, ins_type_counters
[ (int)INS_RIGHT
] + ins_type_counters
[ (int)INS_RIGHT_PARALLEL
],
427 size
, ins_type_counters
[ (int)INS_RIGHT_PARALLEL
],
430 (*d10v_callback
->printf_filtered
) (d10v_callback
,
431 "executed %*ld long instructions\n",
432 size
, ins_type_counters
[ (int)INS_LONG
]);
434 (*d10v_callback
->printf_filtered
) (d10v_callback
,
435 "executed %*ld total instructions\n",
440 sim_create_inferior (start_address
, argv
, env
)
441 SIM_ADDR start_address
;
447 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_create_inferior: PC=0x%x\n", start_address
);
449 PC
= start_address
>> 2;
463 /* printf ("sim_set_callbacks\n"); */
468 sim_stop_reason (reason
, sigrc
)
469 enum sim_stop
*reason
;
472 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
474 if (State
.exception
== SIGQUIT
)
476 *reason
= sim_exited
;
477 *sigrc
= State
.exception
;
481 *reason
= sim_stopped
;
482 *sigrc
= State
.exception
;
487 sim_fetch_register (rn
, memory
)
489 unsigned char *memory
;
493 WRITE_64 (memory
, State
.a
[rn
-32]);
494 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_fetch_register %d 0x%llx\n",rn,State.a[rn-32]); */
498 WRITE_16 (memory
, State
.regs
[rn
]);
499 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_fetch_register %d 0x%x\n",rn,State.regs[rn]); */
504 sim_store_register (rn
, memory
)
506 unsigned char *memory
;
510 State
.a
[rn
-32] = READ_64 (memory
) & MASK40
;
511 /* (*d10v_callback->printf_filtered) (d10v_callback, "store: a%d=0x%llx\n",rn-32,State.a[rn-32]); */
515 State
.regs
[rn
]= READ_16 (memory
);
516 /* (*d10v_callback->printf_filtered) (d10v_callback, "store: r%d=0x%x\n",rn,State.regs[rn]); */
520 sim_read (addr
, buffer
, size
)
522 unsigned char *buffer
;
526 for (i
= 0; i
< size
; i
++)
528 buffer
[i
] = State
.imem
[addr
+ i
];
537 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_do_command: %s\n",cmd
);
541 sim_load (prog
, from_tty
)
545 /* Return nonzero so GDB will handle it. */
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