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[deliverable/binutils-gdb.git] / sim / d10v / interp.c
1 #include <signal.h>
2 #include "sysdep.h"
3 #include "bfd.h"
4 #include "remote-sim.h"
5
6 #include "d10v_sim.h"
7
8 #define IMEM_SIZE 18 /* D10V instruction memory size is 18 bits */
9 #define DMEM_SIZE 16 /* Data memory is 64K (but only 32K internal RAM) */
10 #define UMEM_SIZE 17 /* each unified memory region is 17 bits */
11
12 enum _leftright { LEFT_FIRST, RIGHT_FIRST };
13
14 int d10v_debug;
15 host_callback *d10v_callback;
16 unsigned long ins_type_counters[ (int)INS_MAX ];
17
18 uint16 OP[4];
19
20 static long hash PARAMS ((long insn, int format));
21 static struct hash_entry *lookup_hash PARAMS ((uint32 ins, int size));
22 static void get_operands PARAMS ((struct simops *s, uint32 ins));
23 static void do_long PARAMS ((uint32 ins));
24 static void do_2_short PARAMS ((uint16 ins1, uint16 ins2, enum _leftright leftright));
25 static void do_parallel PARAMS ((uint16 ins1, uint16 ins2));
26 static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value));
27 extern void sim_size PARAMS ((int power));
28 static void init_system PARAMS ((void));
29 extern int sim_write PARAMS ((SIM_ADDR addr, unsigned char *buffer, int size));
30 extern void sim_open PARAMS ((char *args));
31 extern void sim_close PARAMS ((int quitting));
32 extern void sim_set_profile PARAMS ((int n));
33 extern void sim_set_profile_size PARAMS ((int n));
34 extern void sim_resume PARAMS ((int step, int siggnal));
35 extern void sim_info PARAMS ((int verbose));
36 extern void sim_create_inferior PARAMS ((SIM_ADDR start_address, char **argv, char **env));
37 extern void sim_kill PARAMS ((void));
38 extern void sim_set_callbacks PARAMS ((host_callback *p));
39 extern void sim_stop_reason PARAMS ((enum sim_stop *reason, int *sigrc));
40 extern void sim_fetch_register PARAMS ((int rn, unsigned char *memory));
41 extern void sim_store_register PARAMS ((int rn, unsigned char *memory));
42 extern int sim_read PARAMS ((SIM_ADDR addr, unsigned char *buffer, int size));
43 extern void sim_do_command PARAMS ((char *cmd));
44
45 #ifndef INLINE
46 #if defined(__GNUC__) && defined(__OPTIMIZE__)
47 #define INLINE __inline__
48 #else
49 #define INLINE
50 #endif
51 #endif
52
53 #define MAX_HASH 63
54 struct hash_entry
55 {
56 struct hash_entry *next;
57 long opcode;
58 long mask;
59 struct simops *ops;
60 };
61
62 struct hash_entry hash_table[MAX_HASH+1];
63
64 INLINE static long
65 hash(insn, format)
66 long insn;
67 int format;
68 {
69 if (format & LONG_OPCODE)
70 return ((insn & 0x3F000000) >> 24);
71 else
72 return((insn & 0x7E00) >> 9);
73 }
74
75 INLINE static struct hash_entry *
76 lookup_hash (ins, size)
77 uint32 ins;
78 int size;
79 {
80 struct hash_entry *h;
81
82 if (size)
83 h = &hash_table[(ins & 0x3F000000) >> 24];
84 else
85 h = &hash_table[(ins & 0x7E00) >> 9];
86
87 while ((ins & h->mask) != h->opcode)
88 {
89 if (h->next == NULL)
90 {
91 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR looking up hash for %x at PC %x\n",ins, PC);
92 exit (1);
93 }
94 h = h->next;
95 }
96 return (h);
97 }
98
99 INLINE static void
100 get_operands (struct simops *s, uint32 ins)
101 {
102 int i, shift, bits, flags;
103 uint32 mask;
104 for (i=0; i < s->numops; i++)
105 {
106 shift = s->operands[3*i];
107 bits = s->operands[3*i+1];
108 flags = s->operands[3*i+2];
109 mask = 0x7FFFFFFF >> (31 - bits);
110 OP[i] = (ins >> shift) & mask;
111 }
112 }
113
114 static void
115 do_long (ins)
116 uint32 ins;
117 {
118 struct hash_entry *h;
119 #ifdef DEBUG
120 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
121 (*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins);
122 #endif
123 h = lookup_hash (ins, 1);
124 get_operands (h->ops, ins);
125 State.ins_type = INS_LONG;
126 ins_type_counters[ (int)State.ins_type ]++;
127 (h->ops->func)();
128 }
129
130 static void
131 do_2_short (ins1, ins2, leftright)
132 uint16 ins1, ins2;
133 enum _leftright leftright;
134 {
135 struct hash_entry *h;
136 reg_t orig_pc = PC;
137 enum _ins_type first, second;
138
139 #ifdef DEBUG
140 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
141 (*d10v_callback->printf_filtered) (d10v_callback, "do_2_short 0x%x (%s) -> 0x%x\n",
142 ins1, (leftright) ? "left" : "right", ins2);
143 #endif
144
145 if (leftright == LEFT_FIRST)
146 {
147 first = INS_LEFT;
148 second = INS_RIGHT;
149 ins_type_counters[ (int)INS_LEFTRIGHT ]++;
150 }
151 else
152 {
153 first = INS_RIGHT;
154 second = INS_LEFT;
155 ins_type_counters[ (int)INS_RIGHTLEFT ]++;
156 }
157
158 h = lookup_hash (ins1, 0);
159 get_operands (h->ops, ins1);
160 State.ins_type = first;
161 ins_type_counters[ (int)State.ins_type ]++;
162 (h->ops->func)();
163
164 /* If the PC has changed (ie, a jump), don't do the second instruction */
165 if (orig_pc == PC && !State.exception)
166 {
167 h = lookup_hash (ins2, 0);
168 get_operands (h->ops, ins2);
169 State.ins_type = second;
170 ins_type_counters[ (int)State.ins_type ]++;
171 ins_type_counters[ (int)INS_CYCLES ]++;
172 (h->ops->func)();
173 }
174 else if (orig_pc != PC && !State.exception)
175 ins_type_counters[ (int)INS_COND_JUMP ]++;
176 }
177
178 static void
179 do_parallel (ins1, ins2)
180 uint16 ins1, ins2;
181 {
182 struct hash_entry *h1, *h2;
183 #ifdef DEBUG
184 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
185 (*d10v_callback->printf_filtered) (d10v_callback, "do_parallel 0x%x || 0x%x\n", ins1, ins2);
186 #endif
187 ins_type_counters[ (int)INS_PARALLEL ]++;
188 h1 = lookup_hash (ins1, 0);
189 h2 = lookup_hash (ins2, 0);
190
191 if (h1->ops->exec_type == PARONLY)
192 {
193 get_operands (h1->ops, ins1);
194 State.ins_type = INS_LEFT_COND_TEST;
195 ins_type_counters[ (int)State.ins_type ]++;
196 (h1->ops->func)();
197 if (State.exe)
198 {
199 ins_type_counters[ (int)INS_COND_TRUE ]++;
200 get_operands (h2->ops, ins2);
201 State.ins_type = INS_RIGHT_COND_EXE;
202 ins_type_counters[ (int)State.ins_type ]++;
203 (h2->ops->func)();
204 }
205 else
206 ins_type_counters[ (int)INS_COND_FALSE ]++;
207 }
208 else if (h2->ops->exec_type == PARONLY)
209 {
210 get_operands (h2->ops, ins2);
211 State.ins_type = INS_RIGHT_COND_TEST;
212 ins_type_counters[ (int)State.ins_type ]++;
213 (h2->ops->func)();
214 if (State.exe)
215 {
216 ins_type_counters[ (int)INS_COND_TRUE ]++;
217 get_operands (h1->ops, ins1);
218 State.ins_type = INS_LEFT_COND_EXE;
219 ins_type_counters[ (int)State.ins_type ]++;
220 (h1->ops->func)();
221 }
222 else
223 ins_type_counters[ (int)INS_COND_FALSE ]++;
224 }
225 else
226 {
227 get_operands (h1->ops, ins1);
228 State.ins_type = INS_LEFT_PARALLEL;
229 ins_type_counters[ (int)State.ins_type ]++;
230 (h1->ops->func)();
231 if (!State.exception)
232 {
233 get_operands (h2->ops, ins2);
234 State.ins_type = INS_RIGHT_PARALLEL;
235 ins_type_counters[ (int)State.ins_type ]++;
236 (h2->ops->func)();
237 }
238 }
239 }
240
241 static char *
242 add_commas(buf, sizeof_buf, value)
243 char *buf;
244 int sizeof_buf;
245 unsigned long value;
246 {
247 int comma = 3;
248 char *endbuf = buf + sizeof_buf - 1;
249
250 *--endbuf = '\0';
251 do {
252 if (comma-- == 0)
253 {
254 *--endbuf = ',';
255 comma = 2;
256 }
257
258 *--endbuf = (value % 10) + '0';
259 } while ((value /= 10) != 0);
260
261 return endbuf;
262 }
263
264 void
265 sim_size (power)
266 int power;
267
268 {
269 int i;
270
271 if (State.imem)
272 {
273 for (i=0;i<128;i++)
274 {
275 if (State.umem[i])
276 {
277 free (State.umem[i]);
278 State.umem[i] = NULL;
279 }
280 }
281 free (State.imem);
282 free (State.dmem);
283 }
284
285 State.imem = (uint8 *)calloc(1,1<<IMEM_SIZE);
286 State.dmem = (uint8 *)calloc(1,1<<DMEM_SIZE);
287 for (i=1;i<127;i++)
288 State.umem[i] = NULL;
289 State.umem[0] = (uint8 *)calloc(1,1<<UMEM_SIZE);
290 State.umem[1] = (uint8 *)calloc(1,1<<UMEM_SIZE);
291 State.umem[2] = (uint8 *)calloc(1,1<<UMEM_SIZE);
292 State.umem[127] = (uint8 *)calloc(1,1<<UMEM_SIZE);
293 if (!State.imem || !State.dmem || !State.umem[0] || !State.umem[1] || !State.umem[2] || !State.umem[127] )
294 {
295 (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n");
296 exit(1);
297 }
298
299 SET_IMAP0(0x1000);
300 SET_IMAP1(0x1000);
301 SET_DMAP(0);
302
303 #ifdef DEBUG
304 if ((d10v_debug & DEBUG_MEMSIZE) != 0)
305 {
306 char buffer[20];
307 (*d10v_callback->printf_filtered) (d10v_callback,
308 "Allocated %s bytes instruction memory and\n",
309 add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
310
311 (*d10v_callback->printf_filtered) (d10v_callback, " %s bytes data memory.\n",
312 add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
313 }
314 #endif
315 }
316
317 static void
318 init_system ()
319 {
320 if (!State.imem)
321 sim_size(1);
322 }
323
324 static int
325 xfer_mem (addr, buffer, size, write)
326 SIM_ADDR addr;
327 unsigned char *buffer;
328 int size;
329 int write;
330 {
331 if (!State.imem)
332 init_system ();
333
334 #ifdef DEBUG
335 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
336 {
337 if (write)
338 (*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%x\n", size, addr);
339 else
340 (*d10v_callback->printf_filtered) (d10v_callback, "sim_read %d bytes from 0x%x\n", size, addr);
341 }
342 #endif
343
344 /* to access data, we use the following mapping */
345 /* 0x01000000 - 0x0103ffff : instruction memory */
346 /* 0x02000000 - 0x0200ffff : data memory */
347 /* 0x03000000 - 0x03ffffff : unified memory */
348
349 if ( (addr & 0x03000000) == 0x03000000)
350 {
351 /* UNIFIED MEMORY */
352 int segment;
353 addr &= ~0x03000000;
354 segment = addr >> UMEM_SIZE;
355 addr &= 0x1ffff;
356 if (!State.umem[segment])
357 State.umem[segment] = (uint8 *)calloc(1,1<<UMEM_SIZE);
358 if (!State.umem[segment])
359 {
360 (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n");
361 exit(1);
362 }
363 #ifdef DEBUG
364 (*d10v_callback->printf_filtered) (d10v_callback,"Allocated %s bytes unified memory to region %d\n",
365 add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)), segment);
366 #endif
367 /* FIXME: need to check size and read/write multiple segments if necessary */
368 if (write)
369 memcpy (State.umem[segment]+addr, buffer, size);
370 else
371 memcpy (buffer, State.umem[segment]+addr, size);
372 }
373 else if ( (addr & 0x03000000) == 0x02000000)
374 {
375 /* DATA MEMORY */
376 addr &= ~0x02000000;
377 if (size > (1<<(DMEM_SIZE-1)))
378 {
379 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: data section is only %d bytes.\n",1<<(DMEM_SIZE-1));
380 exit(1);
381 }
382 if (write)
383 memcpy (State.dmem+addr, buffer, size);
384 else
385 memcpy (buffer, State.dmem+addr, size);
386 }
387 else if ( (addr & 0x03000000) == 0x01000000)
388 {
389 /* INSTRUCTION MEMORY */
390 addr &= ~0x01000000;
391 if (size > (1<<IMEM_SIZE))
392 {
393 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: inst section is only %d bytes.\n",1<<IMEM_SIZE);
394 exit(1);
395 }
396 if (write)
397 memcpy (State.imem+addr, buffer, size);
398 else
399 memcpy (buffer, State.imem+addr, size);
400 }
401 else if (write)
402 {
403 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: address 0x%x is not in valid range\n",addr);
404 (*d10v_callback->printf_filtered) (d10v_callback, "Instruction addresses start at 0x01000000\n");
405 (*d10v_callback->printf_filtered) (d10v_callback, "Data addresses start at 0x02000000\n");
406 (*d10v_callback->printf_filtered) (d10v_callback, "Unified addresses start at 0x03000000\n");
407 exit(1);
408 }
409 else
410 return 0;
411
412 return size;
413 }
414
415
416 int
417 sim_write (addr, buffer, size)
418 SIM_ADDR addr;
419 unsigned char *buffer;
420 int size;
421 {
422 return xfer_mem( addr, buffer, size, 1);
423 }
424
425 int
426 sim_read (addr, buffer, size)
427 SIM_ADDR addr;
428 unsigned char *buffer;
429 int size;
430 {
431 return xfer_mem( addr, buffer, size, 0);
432 }
433
434
435 void
436 sim_open (args)
437 char *args;
438 {
439 struct simops *s;
440 struct hash_entry *h;
441 static int init_p = 0;
442
443 if (args != NULL)
444 {
445 #ifdef DEBUG
446 if (strcmp (args, "-t") == 0)
447 d10v_debug = DEBUG;
448 else
449 #endif
450 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",args);
451 }
452
453 /* put all the opcodes in the hash table */
454 if (!init_p++)
455 {
456 for (s = Simops; s->func; s++)
457 {
458 h = &hash_table[hash(s->opcode,s->format)];
459
460 /* go to the last entry in the chain */
461 while (h->next)
462 h = h->next;
463
464 if (h->ops)
465 {
466 h->next = calloc(1,sizeof(struct hash_entry));
467 h = h->next;
468 }
469 h->ops = s;
470 h->mask = s->mask;
471 h->opcode = s->opcode;
472 }
473 }
474 }
475
476
477 void
478 sim_close (quitting)
479 int quitting;
480 {
481 /* nothing to do */
482 }
483
484 void
485 sim_set_profile (n)
486 int n;
487 {
488 (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile %d\n",n);
489 }
490
491 void
492 sim_set_profile_size (n)
493 int n;
494 {
495 (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile_size %d\n",n);
496 }
497
498
499 uint8 *
500 dmem_addr( addr )
501 uint32 addr;
502 {
503 int seg;
504
505 addr &= 0xffff;
506
507 if (addr > 0xbfff)
508 {
509 if ( (addr & 0xfff0) != 0xff00)
510 (*d10v_callback->printf_filtered) (d10v_callback, "Data address %x is in I/O space.\n",addr);
511 return State.dmem + addr;
512 }
513
514 if (addr > 0x7fff)
515 {
516 if (DMAP & 0x1000)
517 {
518 /* instruction memory */
519 return (DMAP & 0xf) * 0x4000 + State.imem;
520 }
521 /* unified memory */
522 /* this is ugly because we allocate unified memory in 128K segments and */
523 /* dmap addresses 16k segments */
524 seg = (DMAP & 0x3ff) >> 2;
525 if (State.umem[seg] == NULL)
526 {
527 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped\n", seg);
528 exit(1);
529 }
530 return State.umem[seg] + (DMAP & 3) * 0x4000;
531 }
532
533 return State.dmem + addr;
534 }
535
536
537 static uint8 *
538 pc_addr()
539 {
540 uint32 pc = ((uint32)PC) << 2;
541 uint16 imap;
542
543 if (pc & 0x20000)
544 imap = IMAP1;
545 else
546 imap = IMAP0;
547
548 if (imap & 0x1000)
549 return State.imem + pc;
550
551 if (State.umem[imap & 0xff] == NULL)
552 {
553 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped\n", imap & 0xff);
554 State.exception = SIGILL;
555 return 0;
556 }
557
558 return State.umem[imap & 0xff] + pc;
559 }
560
561
562 void
563 sim_resume (step, siggnal)
564 int step, siggnal;
565 {
566 uint32 inst;
567 reg_t oldpc = 0;
568
569 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
570
571 State.exception = 0;
572 do
573 {
574 inst = get_longword( pc_addr() );
575 oldpc = PC;
576 ins_type_counters[ (int)INS_CYCLES ]++;
577 switch (inst & 0xC0000000)
578 {
579 case 0xC0000000:
580 /* long instruction */
581 do_long (inst & 0x3FFFFFFF);
582 break;
583 case 0x80000000:
584 /* R -> L */
585 do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, 0);
586 break;
587 case 0x40000000:
588 /* L -> R */
589 do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF, 1);
590 break;
591 case 0:
592 do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
593 break;
594 }
595
596 if (State.RP && PC == RPT_E)
597 {
598 RPT_C -= 1;
599 if (RPT_C == 0)
600 State.RP = 0;
601 else
602 PC = RPT_S;
603 }
604
605 /* FIXME */
606 if (PC == oldpc)
607 PC++;
608
609 }
610 while ( !State.exception && !step);
611
612 if (step && !State.exception)
613 State.exception = SIGTRAP;
614 }
615
616 int
617 sim_trace ()
618 {
619 #ifdef DEBUG
620 d10v_debug = DEBUG;
621 #endif
622 sim_resume (0, 0);
623 return 1;
624 }
625
626 void
627 sim_info (verbose)
628 int verbose;
629 {
630 char buf1[40];
631 char buf2[40];
632 char buf3[40];
633 char buf4[40];
634 char buf5[40];
635 unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ];
636 unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ];
637 unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ];
638 unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ];
639 unsigned long left_total = left + left_parallel + left_cond + left_nops;
640
641 unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ];
642 unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ];
643 unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ];
644 unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ];
645 unsigned long right_total = right + right_parallel + right_cond + right_nops;
646
647 unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ];
648 unsigned long ins_long = ins_type_counters[ (int)INS_LONG ];
649 unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ];
650 unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ];
651 unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ];
652 unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ];
653 unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ];
654 unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ];
655 unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ];
656 unsigned long total = (unknown + left_total + right_total + ins_long);
657
658 int size = strlen (add_commas (buf1, sizeof (buf1), total));
659 int parallel_size = strlen (add_commas (buf1, sizeof (buf1),
660 (left_parallel > right_parallel) ? left_parallel : right_parallel));
661 int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond));
662 int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops));
663 int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right));
664
665 (*d10v_callback->printf_filtered) (d10v_callback,
666 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
667 size, add_commas (buf1, sizeof (buf1), left_total),
668 normal_size, add_commas (buf2, sizeof (buf2), left),
669 parallel_size, add_commas (buf3, sizeof (buf3), left_parallel),
670 cond_size, add_commas (buf4, sizeof (buf4), left_cond),
671 nop_size, add_commas (buf5, sizeof (buf5), left_nops));
672
673 (*d10v_callback->printf_filtered) (d10v_callback,
674 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
675 size, add_commas (buf1, sizeof (buf1), right_total),
676 normal_size, add_commas (buf2, sizeof (buf2), right),
677 parallel_size, add_commas (buf3, sizeof (buf3), right_parallel),
678 cond_size, add_commas (buf4, sizeof (buf4), right_cond),
679 nop_size, add_commas (buf5, sizeof (buf5), right_nops));
680
681 if (ins_long)
682 (*d10v_callback->printf_filtered) (d10v_callback,
683 "executed %*s long instruction(s)\n",
684 size, add_commas (buf1, sizeof (buf1), ins_long));
685
686 if (parallel)
687 (*d10v_callback->printf_filtered) (d10v_callback,
688 "executed %*s parallel instruction(s)\n",
689 size, add_commas (buf1, sizeof (buf1), parallel));
690
691 if (leftright)
692 (*d10v_callback->printf_filtered) (d10v_callback,
693 "executed %*s instruction(s) encoded L->R\n",
694 size, add_commas (buf1, sizeof (buf1), leftright));
695
696 if (rightleft)
697 (*d10v_callback->printf_filtered) (d10v_callback,
698 "executed %*s instruction(s) encoded R->L\n",
699 size, add_commas (buf1, sizeof (buf1), rightleft));
700
701 if (unknown)
702 (*d10v_callback->printf_filtered) (d10v_callback,
703 "executed %*s unknown instruction(s)\n",
704 size, add_commas (buf1, sizeof (buf1), unknown));
705
706 if (cond_true)
707 (*d10v_callback->printf_filtered) (d10v_callback,
708 "executed %*s instruction(s) due to EXExxx condition being true\n",
709 size, add_commas (buf1, sizeof (buf1), cond_true));
710
711 if (cond_false)
712 (*d10v_callback->printf_filtered) (d10v_callback,
713 "skipped %*s instruction(s) due to EXExxx condition being false\n",
714 size, add_commas (buf1, sizeof (buf1), cond_false));
715
716 if (cond_jump)
717 (*d10v_callback->printf_filtered) (d10v_callback,
718 "skipped %*s instruction(s) due to conditional branch succeeding\n",
719 size, add_commas (buf1, sizeof (buf1), cond_jump));
720
721 (*d10v_callback->printf_filtered) (d10v_callback,
722 "executed %*s cycle(s)\n",
723 size, add_commas (buf1, sizeof (buf1), cycles));
724
725 (*d10v_callback->printf_filtered) (d10v_callback,
726 "executed %*s total instructions\n",
727 size, add_commas (buf1, sizeof (buf1), total));
728 }
729
730 void
731 sim_create_inferior (start_address, argv, env)
732 SIM_ADDR start_address;
733 char **argv;
734 char **env;
735 {
736 #ifdef DEBUG
737 if (d10v_debug)
738 (*d10v_callback->printf_filtered) (d10v_callback, "sim_create_inferior: PC=0x%x\n", start_address);
739 #endif
740
741 /* reset all state information */
742 memset (&State.regs, 0, (int)&State.imem - (int)&State.regs[0]);
743
744 /* set PC */
745 PC = start_address >> 2;
746
747 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board */
748 /* resets imap0 and imap1 to 0x1000. */
749
750 SET_IMAP0(0x1000);
751 SET_IMAP1(0x1000);
752 SET_DMAP(0);
753 }
754
755
756 void
757 sim_kill ()
758 {
759 /* nothing to do */
760 }
761
762 void
763 sim_set_callbacks(p)
764 host_callback *p;
765 {
766 /* printf ("sim_set_callbacks\n"); */
767 d10v_callback = p;
768 }
769
770 void
771 sim_stop_reason (reason, sigrc)
772 enum sim_stop *reason;
773 int *sigrc;
774 {
775 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
776
777 switch (State.exception)
778 {
779 case SIG_D10V_STOP: /* stop instruction */
780 *reason = sim_exited;
781 *sigrc = 0;
782 break;
783
784 case SIG_D10V_EXIT: /* exit trap */
785 *reason = sim_exited;
786 *sigrc = State.regs[2];
787 break;
788
789 default: /* some signal */
790 *reason = sim_stopped;
791 *sigrc = State.exception;
792 break;
793 }
794 }
795
796 void
797 sim_fetch_register (rn, memory)
798 int rn;
799 unsigned char *memory;
800 {
801 if (!State.imem)
802 init_system();
803
804 if (rn > 34)
805 WRITE_64 (memory, State.a[rn-32]);
806 else if (rn == 32)
807 WRITE_16 (memory, IMAP0);
808 else if (rn == 33)
809 WRITE_16 (memory, IMAP1);
810 else if (rn == 34)
811 WRITE_16 (memory, DMAP);
812 else
813 WRITE_16 (memory, State.regs[rn]);
814 }
815
816 void
817 sim_store_register (rn, memory)
818 int rn;
819 unsigned char *memory;
820 {
821 if (!State.imem)
822 init_system();
823
824 if (rn > 34)
825 State.a[rn-32] = READ_64 (memory) & MASK40;
826 else if (rn == 34)
827 SET_DMAP( READ_16(memory) );
828 else if (rn == 33)
829 SET_IMAP1( READ_16(memory) );
830 else if (rn == 32)
831 SET_IMAP0( READ_16(memory) );
832 else
833 State.regs[rn]= READ_16 (memory);
834 }
835
836
837 void
838 sim_do_command (cmd)
839 char *cmd;
840 {
841 (*d10v_callback->printf_filtered) (d10v_callback, "sim_do_command: %s\n",cmd);
842 }
843
844 int
845 sim_load (prog, from_tty)
846 char *prog;
847 int from_tty;
848 {
849 /* Return nonzero so GDB will handle it. */
850 return 1;
851 }
GDB Binutils - Deliverables
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