071a7ce49c9ef9dcb0fb045ca1e7a5150e25ad7b
11 printf(" abs\tr%d\n",OP
[0]);
14 if ((int16
)(State
.regs
[OP
[0]]) < 0)
16 State
.regs
[OP
[0]] = -(int16
)(State
.regs
[OP
[0]]);
30 printf(" abs\ta%d\n",OP
[0]);
33 if (State
.a
[OP
[0]] < 0 )
35 tmp
= -State
.a
[OP
[0]];
39 State
.a
[OP
[0]] = MAX32
;
41 State
.a
[OP
[0]] = MIN32
;
57 uint16 tmp
= State
.regs
[OP
[0]];
59 printf(" add\tr%d,r%d\n",OP
[0],OP
[1]);
61 State
.regs
[OP
[0]] += State
.regs
[OP
[1]];
62 if ( tmp
> State
.regs
[OP
[0]])
74 printf(" add\ta%d,r%d\n",OP
[0],OP
[1]);
76 tmp
= State
.a
[OP
[0]] + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
80 State
.a
[OP
[0]] = MAX32
;
81 else if ( tmp
< MIN32
)
82 State
.a
[OP
[0]] = MIN32
;
96 printf(" add\ta%d,a%d\n",OP
[0],OP
[1]);
98 tmp
= State
.a
[OP
[0]] + State
.a
[OP
[1]];
102 State
.a
[OP
[0]] = MAX32
;
103 else if ( tmp
< MIN32
)
104 State
.a
[OP
[0]] = MIN32
;
106 State
.a
[OP
[0]] = tmp
;
109 State
.a
[OP
[0]] = tmp
;
117 uint32 tmp1
= (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1];
118 uint32 tmp2
= (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
120 printf(" add2w\tr%d,r%d\n",OP
[0],OP
[1]);
123 if ( (tmp
< tmp1
) || (tmp
< tmp2
) )
127 State
.regs
[OP
[0]] = tmp
>> 16;
128 State
.regs
[OP
[0]+1] = tmp
& 0xFFFF;
135 uint16 tmp
= State
.regs
[OP
[0]];
137 printf(" add3\tr%d,r%d,0x%x\n",OP
[0],OP
[1],OP
[2]);
139 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] + OP
[2];
140 if ( tmp
> State
.regs
[OP
[0]])
152 printf(" addac3\tr%d,r%d,a%d\n",OP
[0],OP
[1],OP
[2]);
154 tmp
= State
.a
[OP
[2]] + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
155 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
156 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
165 printf(" addac3\tr%d,a%d,a%d\n",OP
[0],OP
[1],OP
[2]);
167 tmp
= State
.a
[OP
[1]] + State
.a
[OP
[2]];
168 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
169 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
178 printf(" addac3s\tr%d,r%d,a%d\n",OP
[0],OP
[1],OP
[2]);
181 tmp
= State
.a
[OP
[2]] + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
184 State
.regs
[OP
[0]] = 0x7fff;
185 State
.regs
[OP
[0]+1] = 0xffff;
188 else if (tmp
< MIN32
)
190 State
.regs
[OP
[0]] = 0x8000;
191 State
.regs
[OP
[0]+1] = 0;
196 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
197 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
208 printf(" addac3s\tr%d,a%d,a%d\n",OP
[0],OP
[1],OP
[2]);
211 tmp
= State
.a
[OP
[1]] + State
.a
[OP
[2]];
214 State
.regs
[OP
[0]] = 0x7fff;
215 State
.regs
[OP
[0]+1] = 0xffff;
218 else if (tmp
< MIN32
)
220 State
.regs
[OP
[0]] = 0x8000;
221 State
.regs
[OP
[0]+1] = 0;
226 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
227 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
237 printf(" addi\tr%d,0x%x\n",OP
[0],OP
[1]);
239 State
.regs
[OP
[0]] += OP
[1];
247 printf(" and\tr%d,r%d\n",OP
[0],OP
[1]);
249 State
.regs
[OP
[0]] &= State
.regs
[OP
[1]];
257 printf(" and3\tr%d,r%d,0x%x\n",OP
[0],OP
[1],OP
[2]);
259 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & OP
[2];
267 printf(" bclri\tr%d,%d\n",OP
[0],OP
[1]);
269 State
.regs
[OP
[0]] &= ~(0x8000 >> OP
[1]);
277 printf(" bl.s\t0x%x\n",OP
[0]);
279 State
.regs
[13] = PC
+1;
288 printf(" bl.l\t0x%x\n",OP
[0]);
290 State
.regs
[13] = PC
+1;
299 printf(" bnoti\tr%d,%d\n",OP
[0],OP
[1]);
301 State
.regs
[OP
[0]] ^= 0x8000 >> OP
[1];
309 printf(" bra.s\t0x%x\n",OP
[0]);
319 printf(" bra.l\t0x%x\n",OP
[0]);
329 printf(" brf0f.s\t0x%x\n",OP
[0]);
340 printf(" brf0f.l\t0x%x\n",OP
[0]);
351 printf(" brf0t.s\t0x%x\n",OP
[0]);
362 printf(" brf0t.l\t0x%x\n",OP
[0]);
373 printf(" bseti\tr%d,%d\n",OP
[0],OP
[1]);
375 State
.regs
[OP
[0]] |= 0x8000 >> OP
[1];
383 printf(" btsti\tr%d,%d\n",OP
[0],OP
[1]);
386 State
.F0
= (State
.regs
[OP
[0]] & (0x8000 >> OP
[1])) ? 1 : 0;
394 printf(" clrac\ta%d\n",OP
[0]);
404 printf(" cmp\tr%d,r%d\n",OP
[0],OP
[1]);
407 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(State
.regs
[OP
[1]])) ? 1 : 0;
415 printf(" cmp\ta%d,a%d\n",OP
[0],OP
[1]);
418 State
.F0
= (State
.a
[OP
[0]] < State
.a
[OP
[1]]) ? 1 : 0;
426 printf(" cmpeq\tr%d,r%d\n",OP
[0],OP
[1]);
429 State
.F0
= (State
.regs
[OP
[0]] == State
.regs
[OP
[1]]) ? 1 : 0;
437 printf(" cmpeq\ta%d,a%d\n",OP
[0],OP
[1]);
440 State
.F0
= (State
.a
[OP
[0]] == State
.a
[OP
[1]]) ? 1 : 0;
448 printf(" cmpeqi.s\tr%d,0x%x\n",OP
[0],OP
[1]);
451 State
.F0
= (State
.regs
[OP
[0]] == SEXT4(OP
[1])) ? 1 : 0;
459 printf(" cmpeqi.l\tr%d,0x%x\n",OP
[0],OP
[1]);
462 State
.F0
= (State
.regs
[OP
[0]] == OP
[1]) ? 1 : 0;
470 printf(" cmpi.s\tr%d,0x%x\n",OP
[0],OP
[1]);
473 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < SEXT4(OP
[1])) ? 1 : 0;
481 printf(" cmpi.l\tr%d,0x%x\n",OP
[0],OP
[1]);
484 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(OP
[1])) ? 1 : 0;
492 printf(" cmpu\tr%d,r%d\n",OP
[0],OP
[1]);
495 State
.F0
= (State
.regs
[OP
[0]] < State
.regs
[OP
[1]]) ? 1 : 0;
503 printf(" cmpui\tr%d,0x%x\n",OP
[0],OP
[1]);
506 State
.F0
= (State
.regs
[OP
[0]] < OP
[1]) ? 1 : 0;
515 printf(" cpfg\t%x,%x\n",OP
[0],OP
[1]);
537 printf(" dbt - NOT IMPLEMENTED\n");
544 uint16 foo
, tmp
, tmpf
;
546 printf(" divs\tr%d,r%d\n",OP
[0],OP
[1]);
548 foo
= (State
.regs
[OP
[0]] << 1) | (State
.regs
[OP
[0]+1] >> 15);
549 tmp
= (int16
)foo
- (int16
)(State
.regs
[OP
[1]]);
550 tmpf
= (foo
>= State
.regs
[OP
[1]]) ? 1 : 0;
551 State
.regs
[OP
[0]] = (tmpf
== 1) ? tmp
: foo
;
552 State
.regs
[OP
[0]+1] = (State
.regs
[OP
[0]+1] << 1) | tmpf
;
562 State
.exe
= (State
.F0
) ? 0 : 1;
572 State
.exe
= State
.F0
;
582 State
.exe
= (State
.F1
) ? 0 : 1;
592 State
.exe
= State
.F1
;
602 State
.exe
= (State
.F0
| State
.F1
) ? 0 : 1;
612 State
.exe
= (State
.F0
) ? 0 : (State
.F1
);
622 State
.exe
= (State
.F1
) ? 0 : (State
.F0
);
632 State
.exe
= (State
.F0
) ? (State
.F1
) : 0;
643 printf(" exp\tr%d,r%d\n",OP
[0],OP
[1]);
645 if (((int16
)State
.regs
[OP
[1]]) >= 0)
646 tmp
= (State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1];
648 tmp
= ~((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
655 State
.regs
[OP
[0]] = i
-1;
660 State
.regs
[OP
[0]] = 16;
670 printf(" exp\tr%d,a%d\n",OP
[0],OP
[1]);
672 if (State
.a
[OP
[1]] >= 0)
673 tmp
= State
.a
[OP
[1]];
675 tmp
= ~(State
.a
[OP
[1]]);
677 foo
= 0x4000000000LL
;
682 State
.regs
[OP
[0]] = i
-9;
687 State
.regs
[OP
[0]] = 16;
695 printf(" jl\t%x\n",OP
[0]);
697 State
.regs
[13] = PC
+1;
698 PC
= State
.regs
[OP
[0]];
706 printf(" jmp\tr%d\n",OP
[0]);
708 PC
= State
.regs
[OP
[0]];
716 printf(" ld\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
718 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
726 printf(" ld\tr%d,@r%d-\n",OP
[0],OP
[1]);
728 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
729 State
.regs
[OP
[1]] -= 2;
737 printf(" ld\tr%d,@r%d+\n",OP
[0],OP
[1]);
739 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
740 State
.regs
[OP
[1]] += 2;
748 printf(" ld\tr%d,@r%d\n",OP
[0],OP
[1]);
750 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
758 printf(" ld2w\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
760 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
761 State
.regs
[OP
[0]+1] = RW (OP
[1] + State
.regs
[OP
[2]] + 2);
769 printf(" ld2w\tr%d,@r%d-\n",OP
[0],OP
[1]);
771 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
772 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
773 State
.regs
[OP
[1]] -= 4;
781 printf(" ld2w\tr%d,@r%d+\n",OP
[0],OP
[1]);
783 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
784 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
785 State
.regs
[OP
[1]] += 4;
793 printf(" ld2w\tr%d,@r%d\n",OP
[0],OP
[1]);
795 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
796 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
804 printf(" ldb\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
806 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
807 SEXT8 (State
.regs
[OP
[0]]);
815 printf(" ldb\tr%d,@r%d\n",OP
[0],OP
[1]);
817 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
818 SEXT8 (State
.regs
[OP
[0]]);
826 printf(" ldi.s\tr%d,%x\n",OP
[0],SEXT4(OP
[1]));
828 State
.regs
[OP
[0]] = SEXT4(OP
[1]);
836 printf(" ldi.l\tr%d,%d\t;0x%x\n",OP
[0],OP
[1],OP
[1]);
838 State
.regs
[OP
[0]] = OP
[1];
846 printf(" ldub\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
848 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
856 printf(" ldub\tr%d,@r%d\n",OP
[0],OP
[1]);
858 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
867 printf(" mac\ta%d,r%d,r%d\n",OP
[0],OP
[1],OP
[2]);
869 tmp
= (int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]);
874 if (State
.ST
&& tmp
> MAX32
)
877 tmp
+= State
.a
[OP
[0]];
881 State
.a
[OP
[0]] = MAX32
;
882 else if (tmp
< MIN32
)
883 State
.a
[OP
[0]] = MIN32
;
885 State
.a
[OP
[0]] = tmp
;
888 State
.a
[OP
[0]] = tmp
;
896 printf(" macsu\t%x,%x,%x\n",OP
[0],OP
[1],OP
[2]);
905 printf(" macu\t%x,%x,%x\n",OP
[0],OP
[1],OP
[2]);
914 printf(" max\tr%d,r%d\n",OP
[0],OP
[1]);
917 if (State
.regs
[OP
[1]] > State
.regs
[OP
[0]])
919 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
931 printf(" max\t%x,%x\n",OP
[0],OP
[1]);
940 printf(" max\t%x,%x\n",OP
[0],OP
[1]);
949 printf(" min\tr%d,r%d\n",OP
[0],OP
[1]);
952 if (State
.regs
[OP
[1]] < State
.regs
[OP
[0]])
954 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
966 printf(" min\t%x,%x\n",OP
[0],OP
[1]);
975 printf(" min\t%x,%x\n",OP
[0],OP
[1]);
984 printf(" msb\t%x,%x,%x\n",OP
[0],OP
[1],OP
[2]);
993 printf(" msbsu\t%x,%x,%x\n",OP
[0],OP
[1],OP
[2]);
1002 printf(" msbu\t%x,%x,%x\n",OP
[0],OP
[1],OP
[2]);
1011 printf(" mul\tr%d,r%d\n",OP
[0],OP
[1]);
1013 State
.regs
[OP
[0]] *= State
.regs
[OP
[1]];
1021 printf(" mulx\t%x,%x,%x\n",OP
[0],OP
[1],OP
[2]);
1030 printf(" mulxsu\t%x,%x,%x\n",OP
[0],OP
[1],OP
[2]);
1039 printf(" mulxu\t%x,%x,%x\n",OP
[0],OP
[1],OP
[2]);
1048 printf(" mv\tr%d,r%d\n",OP
[0],OP
[1]);
1050 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1058 printf(" mv2w\tr%d,r%d\n",OP
[0],OP
[1]);
1060 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1061 State
.regs
[OP
[0]+1] = State
.regs
[OP
[1]+1];
1069 printf(" mv2wfac\tr%d,a%d\n",OP
[0],OP
[1]);
1071 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1072 State
.regs
[OP
[0]+1] = State
.a
[OP
[1]] & 0xffff;
1080 printf(" mv2wtac\tr%d,a%d\n",OP
[0],OP
[1]);
1082 State
.a
[OP
[1]] = SEXT16 (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1];
1090 printf(" mvac\ta%d,a%d\n",OP
[0],OP
[1]);
1092 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1100 printf(" mvb\tr%d,r%d\n",OP
[0],OP
[1]);
1102 State
.regs
[OP
[0]] = SEXT8 (State
.regs
[OP
[1]] & 0xff);
1110 printf(" mvf0f\tr%d,r%d\n",OP
[0],OP
[1]);
1113 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1121 printf(" mvf0t\tr%d,r%d\n",OP
[0],OP
[1]);
1124 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1132 printf(" mvfacg\tr%d,a%d\n",OP
[0],OP
[1]);
1134 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 32) & 0xff;
1142 printf(" mvfachi\tr%d,a%d\n",OP
[0],OP
[1]);
1144 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1152 printf(" mvfaclo\tr%d,a%d\n",OP
[0],OP
[1]);
1154 State
.regs
[OP
[0]] = State
.a
[OP
[1]] & 0xffff;
1162 printf(" mvfc\tr%d,cr%d\n",OP
[0],OP
[1]);
1166 /* PSW is treated specially */
1168 if (State
.SM
) PSW
|= 0x8000;
1169 if (State
.EA
) PSW
|= 0x2000;
1170 if (State
.DB
) PSW
|= 0x1000;
1171 if (State
.IE
) PSW
|= 0x400;
1172 if (State
.RP
) PSW
|= 0x200;
1173 if (State
.MD
) PSW
|= 0x100;
1174 if (State
.FX
) PSW
|= 0x80;
1175 if (State
.ST
) PSW
|= 0x40;
1176 if (State
.F0
) PSW
|= 8;
1177 if (State
.F1
) PSW
|= 4;
1178 if (State
.C
) PSW
|= 1;
1180 State
.regs
[OP
[0]] = State
.cregs
[OP
[1]];
1188 printf(" mvtacg\tr%d,a%d\n",OP
[0],OP
[1]);
1190 State
.a
[OP
[1]] &= MASK32
;
1191 State
.a
[OP
[1]] |= (int64
)(State
.regs
[OP
[0]] & 0xff) << 32;
1200 printf(" mvtachi\tr%d,a%d\n",OP
[0],OP
[1]);
1202 tmp
= State
.a
[OP
[1]] & 0xffff;
1203 State
.a
[OP
[1]] = SEXT16 (State
.regs
[OP
[0]]) << 16 | tmp
;
1204 printf("put 0x%llx\n",State
.a
[OP
[1]]);
1212 printf(" mvtaclo\tr%d,a%d\n",OP
[0],OP
[1]);
1214 State
.a
[OP
[1]] = SEXT16 (State
.regs
[OP
[0]]);
1222 printf(" mvtc\tr%d,cr%d\n",OP
[0],OP
[1]);
1224 State
.cregs
[OP
[1]] = State
.regs
[OP
[0]];
1227 /* PSW is treated specially */
1228 State
.SM
= (PSW
& 0x8000) ? 1 : 0;
1229 State
.EA
= (PSW
& 0x2000) ? 1 : 0;
1230 State
.DB
= (PSW
& 0x1000) ? 1 : 0;
1231 State
.IE
= (PSW
& 0x400) ? 1 : 0;
1232 State
.RP
= (PSW
& 0x200) ? 1 : 0;
1233 State
.MD
= (PSW
& 0x100) ? 1 : 0;
1234 State
.FX
= (PSW
& 0x80) ? 1 : 0;
1235 State
.ST
= (PSW
& 0x40) ? 1 : 0;
1236 State
.F0
= (PSW
& 8) ? 1 : 0;
1237 State
.F1
= (PSW
& 4) ? 1 : 0;
1239 if (State
.ST
&& !State
.FX
)
1241 fprintf (stderr
,"ERROR at PC 0x%x: ST can only be set when FX is set.\n",PC
<<2);
1252 printf(" mvub\tr%d,r%d\n",OP
[0],OP
[1]);
1254 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & 0xff;
1262 printf(" neg\tr%d\n",OP
[0]);
1264 State
.regs
[OP
[0]] = 0 - State
.regs
[OP
[0]];
1273 printf(" neg\ta%d\n",OP
[0]);
1275 tmp
= -State
.a
[OP
[0]];
1279 State
.a
[OP
[0]] = MAX32
;
1280 else if (tmp
< MIN32
)
1281 State
.a
[OP
[0]] = MIN32
;
1283 State
.a
[OP
[0]] = tmp
;
1286 State
.a
[OP
[0]] = tmp
;
1301 printf(" not\tr%d\n",OP
[0]);
1303 State
.regs
[OP
[0]] = ~(State
.regs
[OP
[0]]);
1311 printf(" or\tr%d,r%d\n",OP
[0],OP
[1]);
1313 State
.regs
[OP
[0]] |= State
.regs
[OP
[1]];
1321 printf(" or3\tr%d,r%d,0x%x\n",OP
[0],OP
[1],OP
[2]);
1323 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] | OP
[2];
1331 int shift
= SEXT3 (OP
[2]);
1333 printf(" rac\tr%d,a%d,%d\n",OP
[0],OP
[1],shift
);
1335 State
.F1
= State
.F0
;
1337 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) << shift
;
1339 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) >> -shift
;
1340 tmp
= (tmp
+ 0x8000) >> 16;
1344 State
.regs
[OP
[0]] = 0x7fff;
1345 State
.regs
[OP
[0]+1] = 0xffff;
1348 else if (tmp
< MIN32
)
1350 State
.regs
[OP
[0]] = 0x8000;
1351 State
.regs
[OP
[0]+1] = 0;
1356 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1357 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
1367 int shift
= SEXT3 (OP
[2]);
1369 printf(" rachi\tr%d,a%d,%d\n",OP
[0],OP
[1],shift
);
1371 State
.F1
= State
.F0
;
1373 tmp
= SEXT40 (State
.a
[1]) << shift
;
1375 tmp
= SEXT40 (State
.a
[1]) >> -shift
;
1379 State
.regs
[OP
[0]] = 0x7fff;
1382 else if (tmp
< 0xfff80000000LL
)
1384 State
.regs
[OP
[0]] = 0x8000;
1389 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1399 printf(" rep\tr%d,0x%x\n",OP
[0],OP
[1]);
1403 RPT_C
= State
.regs
[OP
[0]];
1407 fprintf (stderr
, "ERROR: rep with count=0 is illegal.\n");
1412 fprintf (stderr
, "ERROR: rep must include at least 4 instructions.\n");
1422 printf(" repi\t%d,0x%x\n",OP
[0],OP
[1]);
1430 fprintf (stderr
, "ERROR: repi with count=0 is illegal.\n");
1435 fprintf (stderr
, "ERROR: repi must include at least 4 instructions.\n");
1444 printf(" rtd - NOT IMPLEMENTED\n");
1464 printf(" sadd\ta%d,a%d\n",OP
[0],OP
[1]);
1466 tmp
= State
.a
[OP
[0]] + (State
.a
[OP
[1]] >> 16);
1470 State
.a
[OP
[0]] = MAX32
;
1471 else if (tmp
< MIN32
)
1472 State
.a
[OP
[0]] = MIN32
;
1474 State
.a
[OP
[0]] = tmp
;
1477 State
.a
[OP
[0]] = tmp
;
1485 printf(" setf0f\tr%d\n",OP
[0]);
1487 State
.regs
[OP
[0]] = (State
.F0
== 0) ? 1 : 0;
1495 printf(" setf0t\tr%d\n",OP
[0]);
1497 State
.regs
[OP
[0]] = (State
.F0
== 1) ? 1 : 0;
1515 printf(" sll\tr%d,r%d\n",OP
[0],OP
[1]);
1517 State
.regs
[OP
[0]] <<= (State
.regs
[OP
[1]] & 0xf);
1526 printf(" sll\ta%d,r%d\n",OP
[0],OP
[1]);
1528 if (State
.regs
[OP
[1]] & 31 <= 16)
1529 tmp
= SEXT40 (State
.a
[OP
[0]]) << (State
.regs
[OP
[1]] & 31);
1534 State
.a
[OP
[0]] = MAX32
;
1535 else if (tmp
< 0xffffff80000000LL
)
1536 State
.a
[OP
[0]] = MIN32
;
1538 State
.a
[OP
[0]] = tmp
& MASK40
;
1541 State
.a
[OP
[0]] = tmp
& MASK40
;
1549 printf(" slli\tr%d,%d\n",OP
[0],OP
[1]);
1551 State
.regs
[OP
[0]] <<= OP
[1];
1560 printf(" slli\ta%d,%d\n",OP
[0],OP
[1]);
1563 tmp
= SEXT40(State
.a
[OP
[0]]) << 16;
1565 tmp
= SEXT40(State
.a
[OP
[0]]) << OP
[2];
1570 State
.a
[OP
[0]] = MAX32
;
1571 else if (tmp
< 0xffffff80000000LL
)
1572 State
.a
[OP
[0]] = MIN32
;
1574 State
.a
[OP
[0]] = tmp
& MASK40
;
1577 State
.a
[OP
[0]] = tmp
& MASK40
;
1586 printf(" slx\tr%d\n",OP
[0]);
1588 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] << 1) | State
.F0
;
1596 printf(" sra\tr%d,r%d\n",OP
[0],OP
[1]);
1598 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> (State
.regs
[OP
[1]] & 0xf);
1606 printf(" sra\ta%d,r%d\n",OP
[0],OP
[1]);
1608 if (State
.regs
[OP
[1]] & 31 <= 16)
1609 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
1617 printf(" srai\tr%d,%d\n",OP
[0],OP
[1]);
1619 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> OP
[1];
1627 printf(" srai\ta%d,%d\n",OP
[0],OP
[1]);
1630 State
.a
[OP
[0]] >>= 16;
1632 State
.a
[OP
[0]] >>= OP
[1];
1640 printf(" srl\tr%d,r%d\n",OP
[0],OP
[1]);
1642 State
.regs
[OP
[0]] >>= (State
.regs
[OP
[1]] & 0xf);
1650 printf(" srl\ta%d,r%d\n",OP
[0],OP
[1]);
1652 if (State
.regs
[OP
[1]] & 31 <= 16)
1653 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
1661 printf(" srli\tr%d,%d\n",OP
[0],OP
[1]);
1663 State
.regs
[OP
[0]] >>= OP
[1];
1671 printf(" srli\ta%d,%d\n",OP
[0],OP
[1]);
1674 State
.a
[OP
[0]] >>= 16;
1676 State
.a
[OP
[0]] >>= OP
[1];
1685 printf(" srx\tr%d\n",OP
[0]);
1687 tmp
= State
.F0
<< 15;
1688 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] >> 1) | tmp
;
1696 printf(" st\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
1698 SW (OP
[1] + State
.regs
[OP
[2]], State
.regs
[OP
[0]]);
1706 printf(" st\tr%d,@r%d\n",OP
[0],OP
[1]);
1708 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1716 printf(" st\tr%d,@-r%d\n",OP
[0],OP
[1]);
1720 fprintf (stderr
,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
1723 State
.regs
[OP
[1]] -= 2;
1724 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1732 printf(" st\tr%d,@r%d+\n",OP
[0],OP
[1]);
1734 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1735 State
.regs
[OP
[1]] += 2;
1743 printf(" st\tr%d,@r%d-\n",OP
[0],OP
[1]);
1745 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1746 State
.regs
[OP
[1]] -= 2;
1754 printf(" st2w\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
1756 SW (State
.regs
[OP
[1]]+OP
[2], State
.regs
[OP
[0]]);
1757 SW (State
.regs
[OP
[1]]+OP
[2]+2, State
.regs
[OP
[0]+1]);
1765 printf(" st2w\tr%d,@r%d\n",OP
[0],OP
[1]);
1767 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1768 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
1776 printf(" st2w\tr%d,@-r%d\n",OP
[0],OP
[1]);
1780 fprintf (stderr
,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
1783 State
.regs
[OP
[1]] -= 4;
1784 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1785 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
1793 printf(" st2w\tr%d,r%d+\n",OP
[0],OP
[1]);
1795 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1796 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
1797 State
.regs
[OP
[1]] += 4;
1805 printf(" st2w\tr%d,r%d-\n",OP
[0],OP
[1]);
1807 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1808 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
1809 State
.regs
[OP
[1]] -= 4;
1817 printf(" stb\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
1819 SB (State
.regs
[OP
[1]]+OP
[2], State
.regs
[OP
[0]]);
1827 printf(" stb\tr%d,@r%d\n",OP
[0],OP
[1]);
1829 SB (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1848 printf(" sub\tr%d,r%d\n",OP
[0],OP
[1]);
1850 tmp
= (int16
)State
.regs
[OP
[0]]- (int16
)State
.regs
[OP
[1]];
1851 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
1852 State
.regs
[OP
[0]] = tmp
& 0xffff;
1860 printf(" sub\ta%d,r%d\n",OP
[0],OP
[1]);
1870 printf(" sub\ta%d,a%d\n",OP
[0],OP
[1]);
1882 printf(" sub2w\tr%d,r%d\n",OP
[0],OP
[1]);
1885 a
= (int32
)((State
.regs
[OP
[0]] << 16) | State
.regs
[OP
[0]+1]);
1886 b
= (int32
)((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
1888 State
.C
= (tmp
& 0xffffffff00000000LL
) ? 1 : 0;
1889 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1890 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
1898 printf(" subac3\t%x,%x,%x\n",OP
[0],OP
[1],OP
[2]);
1907 printf(" subac3\t%x,%x,%x\n",OP
[0],OP
[1],OP
[2]);
1916 printf(" subac3s\t%x,%x,%x\n",OP
[0],OP
[1],OP
[2]);
1925 printf(" subac3s\t%x,%x,%x\n",OP
[0],OP
[1],OP
[2]);
1935 printf(" subi\tr%d,%d\n",OP
[0],OP
[1]);
1939 tmp
= (int16
)State
.regs
[OP
[0]] - OP
[1];
1940 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
1941 State
.regs
[OP
[0]] = tmp
& 0xffff;
1949 printf(" trap\t%d\n",OP
[0]);
1952 /* for now, trap 0 is used for simulating IO */
1956 char *fstr
= State
.regs
[2] + State
.imem
;
1957 printf (fstr
,State
.regs
[3],State
.regs
[4],State
.regs
[5]);
1959 else if (OP
[0] == 1 )
1961 char *fstr
= State
.regs
[2] + State
.imem
;
1971 printf(" tst0i\tr%d,0x%x\n",OP
[0],OP
[1]);
1973 State
.F1
= State
.F0
;
1974 State
.F0
= (State
.regs
[OP
[0]] & OP
[2]) ? 1 : 0;
1982 printf(" tst1i\tr%d,0x%x\n",OP
[0],OP
[1]);
1984 State
.F1
= State
.F0
;
1985 State
.F0
= (~(State
.regs
[OP
[0]]) & OP
[2]) ? 1 : 0;
2003 printf(" xor\tr%d,r%d\n",OP
[0],OP
[1]);
2005 State
.regs
[OP
[0]] ^= State
.regs
[OP
[1]];
2013 printf(" xor3\tr%d,r%d,0x%x\n",OP
[0],OP
[1],OP
[2]);
2015 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] ^ OP
[2];
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