1081639f3db40083b36ae5ac1e0ce24f3c86ae1f
12 printf(" abs\tr%d\n",OP
[0]);
15 if ((int16
)(State
.regs
[OP
[0]]) < 0)
17 State
.regs
[OP
[0]] = -(int16
)(State
.regs
[OP
[0]]);
31 printf(" abs\ta%d\n",OP
[0]);
34 State
.a
[OP
[0]] = SEXT40(State
.a
[OP
[0]]);
36 if (State
.a
[OP
[0]] < 0 )
38 tmp
= -State
.a
[OP
[0]];
42 State
.a
[OP
[0]] = MAX32
;
44 State
.a
[OP
[0]] = MIN32
;
46 State
.a
[OP
[0]] = tmp
& MASK40
;
49 State
.a
[OP
[0]] = tmp
& MASK40
;
60 uint16 tmp
= State
.regs
[OP
[0]];
62 printf(" add\tr%d,r%d\n",OP
[0],OP
[1]);
64 State
.regs
[OP
[0]] += State
.regs
[OP
[1]];
65 if ( tmp
> State
.regs
[OP
[0]])
77 printf(" add\ta%d,r%d\n",OP
[0],OP
[1]);
79 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
83 State
.a
[OP
[0]] = MAX32
;
84 else if ( tmp
< MIN32
)
85 State
.a
[OP
[0]] = MIN32
;
87 State
.a
[OP
[0]] = tmp
& MASK40
;
90 State
.a
[OP
[0]] = tmp
& MASK40
;
99 printf(" add\ta%d,a%d\n",OP
[0],OP
[1]);
101 tmp
= SEXT40(State
.a
[OP
[0]]) + SEXT40(State
.a
[OP
[1]]);
105 State
.a
[OP
[0]] = MAX32
;
106 else if ( tmp
< MIN32
)
107 State
.a
[OP
[0]] = MIN32
;
109 State
.a
[OP
[0]] = tmp
& MASK40
;
112 State
.a
[OP
[0]] = tmp
& MASK40
;
120 uint32 tmp1
= (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1];
121 uint32 tmp2
= (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
123 printf(" add2w\tr%d,r%d\n",OP
[0],OP
[1]);
126 if ( (tmp
< tmp1
) || (tmp
< tmp2
) )
130 State
.regs
[OP
[0]] = tmp
>> 16;
131 State
.regs
[OP
[0]+1] = tmp
& 0xFFFF;
138 uint16 tmp
= State
.regs
[OP
[0]];
140 printf(" add3\tr%d,r%d,0x%x\n",OP
[0],OP
[1],OP
[2]);
142 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] + OP
[2];
143 if ( tmp
> State
.regs
[OP
[0]])
155 printf(" addac3\tr%d,r%d,a%d\n",OP
[0],OP
[1],OP
[2]);
157 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
158 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
159 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
168 printf(" addac3\tr%d,a%d,a%d\n",OP
[0],OP
[1],OP
[2]);
170 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
171 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
172 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
181 printf(" addac3s\tr%d,r%d,a%d\n",OP
[0],OP
[1],OP
[2]);
184 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
187 State
.regs
[OP
[0]] = 0x7fff;
188 State
.regs
[OP
[0]+1] = 0xffff;
191 else if (tmp
< MIN32
)
193 State
.regs
[OP
[0]] = 0x8000;
194 State
.regs
[OP
[0]+1] = 0;
199 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
200 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
211 printf(" addac3s\tr%d,a%d,a%d\n",OP
[0],OP
[1],OP
[2]);
214 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
217 State
.regs
[OP
[0]] = 0x7fff;
218 State
.regs
[OP
[0]+1] = 0xffff;
221 else if (tmp
< MIN32
)
223 State
.regs
[OP
[0]] = 0x8000;
224 State
.regs
[OP
[0]+1] = 0;
229 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
230 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
242 printf(" addi\tr%d,0x%x\n",OP
[0],OP
[1]);
244 State
.regs
[OP
[0]] += OP
[1];
252 printf(" and\tr%d,r%d\n",OP
[0],OP
[1]);
254 State
.regs
[OP
[0]] &= State
.regs
[OP
[1]];
262 printf(" and3\tr%d,r%d,0x%x\n",OP
[0],OP
[1],OP
[2]);
264 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & OP
[2];
272 printf(" bclri\tr%d,%d\n",OP
[0],OP
[1]);
274 State
.regs
[OP
[0]] &= ~(0x8000 >> OP
[1]);
282 printf(" bl.s\t0x%x\n",OP
[0]);
284 State
.regs
[13] = PC
+1;
293 printf(" bl.l\t0x%x\n",OP
[0]);
295 State
.regs
[13] = PC
+1;
304 printf(" bnoti\tr%d,%d\n",OP
[0],OP
[1]);
306 State
.regs
[OP
[0]] ^= 0x8000 >> OP
[1];
314 printf(" bra.s\t0x%x\n",OP
[0]);
324 printf(" bra.l\t0x%x\n",OP
[0]);
334 printf(" brf0f.s\t0x%x\n",OP
[0]);
345 printf(" brf0f.l\t0x%x\n",OP
[0]);
356 printf(" brf0t.s\t0x%x\n",OP
[0]);
367 printf(" brf0t.l\t0x%x\n",OP
[0]);
378 printf(" bseti\tr%d,%d\n",OP
[0],OP
[1]);
380 State
.regs
[OP
[0]] |= 0x8000 >> OP
[1];
388 printf(" btsti\tr%d,%d\n",OP
[0],OP
[1]);
391 State
.F0
= (State
.regs
[OP
[0]] & (0x8000 >> OP
[1])) ? 1 : 0;
399 printf(" clrac\ta%d\n",OP
[0]);
409 printf(" cmp\tr%d,r%d\n",OP
[0],OP
[1]);
412 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(State
.regs
[OP
[1]])) ? 1 : 0;
420 printf(" cmp\ta%d,a%d\n",OP
[0],OP
[1]);
423 State
.F0
= (SEXT40(State
.a
[OP
[0]]) < SEXT40(State
.a
[OP
[1]])) ? 1 : 0;
431 printf(" cmpeq\tr%d,r%d\n",OP
[0],OP
[1]);
434 State
.F0
= (State
.regs
[OP
[0]] == State
.regs
[OP
[1]]) ? 1 : 0;
442 printf(" cmpeq\ta%d,a%d\n",OP
[0],OP
[1]);
445 State
.F0
= (State
.a
[OP
[0]] == State
.a
[OP
[1]]) ? 1 : 0;
453 printf(" cmpeqi.s\tr%d,0x%x\n",OP
[0],OP
[1]);
456 State
.F0
= (State
.regs
[OP
[0]] == SEXT4(OP
[1])) ? 1 : 0;
464 printf(" cmpeqi.l\tr%d,0x%x\n",OP
[0],OP
[1]);
467 State
.F0
= (State
.regs
[OP
[0]] == OP
[1]) ? 1 : 0;
475 printf(" cmpi.s\tr%d,0x%x\n",OP
[0],OP
[1]);
478 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < SEXT4(OP
[1])) ? 1 : 0;
486 printf(" cmpi.l\tr%d,0x%x\n",OP
[0],OP
[1]);
489 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(OP
[1])) ? 1 : 0;
497 printf(" cmpu\tr%d,r%d\n",OP
[0],OP
[1]);
500 State
.F0
= (State
.regs
[OP
[0]] < State
.regs
[OP
[1]]) ? 1 : 0;
508 printf(" cmpui\tr%d,0x%x\n",OP
[0],OP
[1]);
511 State
.F0
= (State
.regs
[OP
[0]] < OP
[1]) ? 1 : 0;
520 printf(" cpfg\t%x,%x\n",OP
[0],OP
[1]);
542 printf("***** DBT ***** PC=%x\n",PC
);
543 State
.exception
= SIGTRAP
;
550 uint16 foo
, tmp
, tmpf
;
552 printf(" divs\tr%d,r%d\n",OP
[0],OP
[1]);
554 foo
= (State
.regs
[OP
[0]] << 1) | (State
.regs
[OP
[0]+1] >> 15);
555 tmp
= (int16
)foo
- (int16
)(State
.regs
[OP
[1]]);
556 tmpf
= (foo
>= State
.regs
[OP
[1]]) ? 1 : 0;
557 State
.regs
[OP
[0]] = (tmpf
== 1) ? tmp
: foo
;
558 State
.regs
[OP
[0]+1] = (State
.regs
[OP
[0]+1] << 1) | tmpf
;
568 State
.exe
= (State
.F0
) ? 0 : 1;
578 State
.exe
= State
.F0
;
588 State
.exe
= (State
.F1
) ? 0 : 1;
598 State
.exe
= State
.F1
;
608 State
.exe
= (State
.F0
| State
.F1
) ? 0 : 1;
618 State
.exe
= (State
.F0
) ? 0 : (State
.F1
);
628 State
.exe
= (State
.F1
) ? 0 : (State
.F0
);
638 State
.exe
= (State
.F0
) ? (State
.F1
) : 0;
649 printf(" exp\tr%d,r%d\n",OP
[0],OP
[1]);
651 if (((int16
)State
.regs
[OP
[1]]) >= 0)
652 tmp
= (State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1];
654 tmp
= ~((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
661 State
.regs
[OP
[0]] = i
-1;
666 State
.regs
[OP
[0]] = 16;
676 printf(" exp\tr%d,a%d\n",OP
[0],OP
[1]);
678 if (SEXT40(State
.a
[OP
[1]]) >= 0)
679 tmp
= State
.a
[OP
[1]];
681 tmp
= ~(State
.a
[OP
[1]]);
683 foo
= 0x4000000000LL
;
688 State
.regs
[OP
[0]] = i
-9;
693 State
.regs
[OP
[0]] = 16;
701 printf(" jl\t%x\n",OP
[0]);
703 State
.regs
[13] = PC
+1;
704 PC
= State
.regs
[OP
[0]];
712 printf(" jmp\tr%d\n",OP
[0]);
714 PC
= State
.regs
[OP
[0]];
722 printf(" ld\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
724 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
732 printf(" ld\tr%d,@r%d-\n",OP
[0],OP
[1]);
734 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
735 INC_ADDR(State
.regs
[OP
[1]],-2);
743 printf(" ld\tr%d,@r%d+\n",OP
[0],OP
[1]);
745 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
746 INC_ADDR(State
.regs
[OP
[1]],2);
754 printf(" ld\tr%d,@r%d\n",OP
[0],OP
[1]);
756 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
764 printf(" ld2w\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
766 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
767 State
.regs
[OP
[0]+1] = RW (OP
[1] + State
.regs
[OP
[2]] + 2);
775 printf(" ld2w\tr%d,@r%d-\n",OP
[0],OP
[1]);
777 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
778 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
779 INC_ADDR(State
.regs
[OP
[1]],-4);
787 printf(" ld2w\tr%d,@r%d+\n",OP
[0],OP
[1]);
789 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
790 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
791 INC_ADDR(State
.regs
[OP
[1]],4);
799 printf(" ld2w\tr%d,@r%d\n",OP
[0],OP
[1]);
801 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
802 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
810 printf(" ldb\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
812 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
813 SEXT8 (State
.regs
[OP
[0]]);
821 printf(" ldb\tr%d,@r%d\n",OP
[0],OP
[1]);
823 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
824 SEXT8 (State
.regs
[OP
[0]]);
832 printf(" ldi.s\tr%d,%x\n",OP
[0],SEXT4(OP
[1]));
834 State
.regs
[OP
[0]] = SEXT4(OP
[1]);
842 printf(" ldi.l\tr%d,%d\t;0x%x\n",OP
[0],OP
[1],OP
[1]);
844 State
.regs
[OP
[0]] = OP
[1];
852 printf(" ldub\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
854 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
862 printf(" ldub\tr%d,@r%d\n",OP
[0],OP
[1]);
864 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
873 printf(" mac\ta%d,r%d,r%d\n",OP
[0],OP
[1],OP
[2]);
875 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
878 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
880 if (State
.ST
&& tmp
> MAX32
)
883 tmp
+= SEXT40(State
.a
[OP
[0]]);
887 State
.a
[OP
[0]] = MAX32
;
888 else if (tmp
< MIN32
)
889 State
.a
[OP
[0]] = MIN32
;
891 State
.a
[OP
[0]] = tmp
& MASK40
;
894 State
.a
[OP
[0]] = tmp
& MASK40
;
903 printf(" macsu\ta%d,r%d,r%d\n",OP
[0],OP
[1],OP
[2]);
905 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
907 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
909 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
918 printf(" macu\ta%d,r%d,r%d\n",OP
[0],OP
[1],OP
[2]);
920 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
922 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
923 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
931 printf(" max\tr%d,r%d\n",OP
[0],OP
[1]);
934 if (State
.regs
[OP
[1]] > State
.regs
[OP
[0]])
936 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
949 printf(" max\ta%d,r%d\n",OP
[0],OP
[1]);
952 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
953 if (tmp
> SEXT40(State
.a
[OP
[0]]))
955 State
.a
[OP
[0]] = tmp
& MASK40
;
967 printf(" max\ta%d,a%d\n",OP
[0],OP
[1]);
970 if (SEXT40(State
.a
[OP
[1]]) > SEXT40(State
.a
[OP
[0]]))
972 State
.a
[OP
[0]] = State
.a
[OP
[1]];
985 printf(" min\tr%d,r%d\n",OP
[0],OP
[1]);
988 if (State
.regs
[OP
[1]] < State
.regs
[OP
[0]])
990 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1003 printf(" min\ta%d,r%d\n",OP
[0],OP
[1]);
1005 State
.F1
= State
.F0
;
1006 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1007 if (tmp
< SEXT40(State
.a
[OP
[0]]))
1009 State
.a
[OP
[0]] = tmp
& MASK40
;
1021 printf(" min\ta%d,a%d\n",OP
[0],OP
[1]);
1023 State
.F1
= State
.F0
;
1024 if (SEXT40(State
.a
[OP
[1]]) < SEXT40(State
.a
[OP
[0]]))
1026 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1039 printf(" msb\ta%d,r%d,r%d\n",OP
[0],OP
[1],OP
[2]);
1041 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1044 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1046 if (State
.ST
&& tmp
> MAX32
)
1049 tmp
= SEXT40(State
.a
[OP
[0]]) - tmp
;
1053 State
.a
[OP
[0]] = MAX32
;
1054 else if (tmp
< MIN32
)
1055 State
.a
[OP
[0]] = MIN32
;
1057 State
.a
[OP
[0]] = tmp
& MASK40
;
1060 State
.a
[OP
[0]] = tmp
& MASK40
;
1069 printf(" msbsu\ta%d,r%d,r%d\n",OP
[0],OP
[1],OP
[2]);
1071 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1073 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1075 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1084 printf(" msbu\ta%d,r%d,r%d\n",OP
[0],OP
[1],OP
[2]);
1086 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1088 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1090 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1098 printf(" mul\tr%d,r%d\n",OP
[0],OP
[1]);
1100 State
.regs
[OP
[0]] *= State
.regs
[OP
[1]];
1109 printf(" mulx\ta%d,r%d,r%d\n",OP
[0],OP
[1],OP
[2]);
1111 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1114 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1116 if (State
.ST
&& tmp
> MAX32
)
1117 State
.a
[OP
[0]] = MAX32
;
1119 State
.a
[OP
[0]] = tmp
& MASK40
;
1128 printf(" mulxsu\ta%d,r%d,r%d\n",OP
[0],OP
[1],OP
[2]);
1130 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * State
.regs
[OP
[2]]);
1135 State
.a
[OP
[0]] = tmp
& MASK40
;
1144 printf(" mulxu\ta%d,r%d,r%d\n",OP
[0],OP
[1],OP
[2]);
1146 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1151 State
.a
[OP
[0]] = tmp
& MASK40
;
1159 printf(" mv\tr%d,r%d\n",OP
[0],OP
[1]);
1161 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1169 printf(" mv2w\tr%d,r%d\n",OP
[0],OP
[1]);
1171 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1172 State
.regs
[OP
[0]+1] = State
.regs
[OP
[1]+1];
1180 printf(" mv2wfac\tr%d,a%d\n",OP
[0],OP
[1]);
1182 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1183 State
.regs
[OP
[0]+1] = State
.a
[OP
[1]] & 0xffff;
1191 printf(" mv2wtac\tr%d,a%d\n",OP
[0],OP
[1]);
1193 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1]) & MASK40
;
1201 printf(" mvac\ta%d,a%d\n",OP
[0],OP
[1]);
1203 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1211 printf(" mvb\tr%d,r%d\n",OP
[0],OP
[1]);
1213 State
.regs
[OP
[0]] = SEXT8 (State
.regs
[OP
[1]] & 0xff);
1221 printf(" mvf0f\tr%d,r%d\n",OP
[0],OP
[1]);
1224 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1232 printf(" mvf0t\tr%d,r%d\n",OP
[0],OP
[1]);
1235 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1243 printf(" mvfacg\tr%d,a%d\n",OP
[0],OP
[1]);
1245 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 32) & 0xff;
1253 printf(" mvfachi\tr%d,a%d\n",OP
[0],OP
[1]);
1255 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1263 printf(" mvfaclo\tr%d,a%d\n",OP
[0],OP
[1]);
1265 State
.regs
[OP
[0]] = State
.a
[OP
[1]] & 0xffff;
1273 printf(" mvfc\tr%d,cr%d\n",OP
[0],OP
[1]);
1277 /* PSW is treated specially */
1279 if (State
.SM
) PSW
|= 0x8000;
1280 if (State
.EA
) PSW
|= 0x2000;
1281 if (State
.DB
) PSW
|= 0x1000;
1282 if (State
.IE
) PSW
|= 0x400;
1283 if (State
.RP
) PSW
|= 0x200;
1284 if (State
.MD
) PSW
|= 0x100;
1285 if (State
.FX
) PSW
|= 0x80;
1286 if (State
.ST
) PSW
|= 0x40;
1287 if (State
.F0
) PSW
|= 8;
1288 if (State
.F1
) PSW
|= 4;
1289 if (State
.C
) PSW
|= 1;
1291 State
.regs
[OP
[0]] = State
.cregs
[OP
[1]];
1299 printf(" mvtacg\tr%d,a%d\n",OP
[0],OP
[1]);
1301 State
.a
[OP
[1]] &= MASK32
;
1302 State
.a
[OP
[1]] |= (int64
)(State
.regs
[OP
[0]] & 0xff) << 32;
1311 printf(" mvtachi\tr%d,a%d\n",OP
[0],OP
[1]);
1313 tmp
= State
.a
[OP
[1]] & 0xffff;
1314 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | tmp
) & MASK40
;
1322 printf(" mvtaclo\tr%d,a%d\n",OP
[0],OP
[1]);
1324 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]])) & MASK40
;
1332 printf(" mvtc\tr%d,cr%d\n",OP
[0],OP
[1]);
1334 State
.cregs
[OP
[1]] = State
.regs
[OP
[0]];
1337 /* PSW is treated specially */
1338 State
.SM
= (PSW
& 0x8000) ? 1 : 0;
1339 State
.EA
= (PSW
& 0x2000) ? 1 : 0;
1340 State
.DB
= (PSW
& 0x1000) ? 1 : 0;
1341 State
.IE
= (PSW
& 0x400) ? 1 : 0;
1342 State
.RP
= (PSW
& 0x200) ? 1 : 0;
1343 State
.MD
= (PSW
& 0x100) ? 1 : 0;
1344 State
.FX
= (PSW
& 0x80) ? 1 : 0;
1345 State
.ST
= (PSW
& 0x40) ? 1 : 0;
1346 State
.F0
= (PSW
& 8) ? 1 : 0;
1347 State
.F1
= (PSW
& 4) ? 1 : 0;
1349 if (State
.ST
&& !State
.FX
)
1351 fprintf (stderr
,"ERROR at PC 0x%x: ST can only be set when FX is set.\n",PC
<<2);
1352 State
.exception
= SIGILL
;
1362 printf(" mvub\tr%d,r%d\n",OP
[0],OP
[1]);
1364 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & 0xff;
1372 printf(" neg\tr%d\n",OP
[0]);
1374 State
.regs
[OP
[0]] = 0 - State
.regs
[OP
[0]];
1383 printf(" neg\ta%d\n",OP
[0]);
1385 tmp
= -SEXT40(State
.a
[OP
[0]]);
1389 State
.a
[OP
[0]] = MAX32
;
1390 else if (tmp
< MIN32
)
1391 State
.a
[OP
[0]] = MIN32
;
1393 State
.a
[OP
[0]] = tmp
& MASK40
;
1396 State
.a
[OP
[0]] = tmp
& MASK40
;
1411 printf(" not\tr%d\n",OP
[0]);
1413 State
.regs
[OP
[0]] = ~(State
.regs
[OP
[0]]);
1421 printf(" or\tr%d,r%d\n",OP
[0],OP
[1]);
1423 State
.regs
[OP
[0]] |= State
.regs
[OP
[1]];
1431 printf(" or3\tr%d,r%d,0x%x\n",OP
[0],OP
[1],OP
[2]);
1433 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] | OP
[2];
1441 int shift
= SEXT3 (OP
[2]);
1443 printf(" rac\tr%d,a%d,%d\n",OP
[0],OP
[1],shift
);
1445 State
.F1
= State
.F0
;
1447 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) << shift
;
1449 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) >> -shift
;
1450 tmp
= (tmp
+ 0x8000) >> 16;
1454 State
.regs
[OP
[0]] = 0x7fff;
1455 State
.regs
[OP
[0]+1] = 0xffff;
1458 else if (tmp
< MIN32
)
1460 State
.regs
[OP
[0]] = 0x8000;
1461 State
.regs
[OP
[0]+1] = 0;
1466 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1467 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
1477 int shift
= SEXT3 (OP
[2]);
1479 printf(" rachi\tr%d,a%d,%d\n",OP
[0],OP
[1],shift
);
1481 State
.F1
= State
.F0
;
1483 tmp
= SEXT40 (State
.a
[1]) << shift
;
1485 tmp
= SEXT40 (State
.a
[1]) >> -shift
;
1489 State
.regs
[OP
[0]] = 0x7fff;
1492 else if (tmp
< 0xfff80000000LL
)
1494 State
.regs
[OP
[0]] = 0x8000;
1499 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1509 printf(" rep\tr%d,0x%x\n",OP
[0],OP
[1]);
1513 RPT_C
= State
.regs
[OP
[0]];
1517 fprintf (stderr
, "ERROR: rep with count=0 is illegal.\n");
1518 State
.exception
= SIGILL
;
1522 fprintf (stderr
, "ERROR: rep must include at least 4 instructions.\n");
1523 State
.exception
= SIGILL
;
1532 printf(" repi\t%d,0x%x\n",OP
[0],OP
[1]);
1540 fprintf (stderr
, "ERROR: repi with count=0 is illegal.\n");
1541 State
.exception
= SIGILL
;
1545 fprintf (stderr
, "ERROR: repi must include at least 4 instructions.\n");
1546 State
.exception
= SIGILL
;
1554 printf(" rtd - NOT IMPLEMENTED\n");
1574 printf(" sadd\ta%d,a%d\n",OP
[0],OP
[1]);
1576 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT40(State
.a
[OP
[1]]) >> 16);
1580 State
.a
[OP
[0]] = MAX32
;
1581 else if (tmp
< MIN32
)
1582 State
.a
[OP
[0]] = MIN32
;
1584 State
.a
[OP
[0]] = tmp
& MASK40
;
1587 State
.a
[OP
[0]] = tmp
& MASK40
;
1595 printf(" setf0f\tr%d\n",OP
[0]);
1597 State
.regs
[OP
[0]] = (State
.F0
== 0) ? 1 : 0;
1605 printf(" setf0t\tr%d\n",OP
[0]);
1607 State
.regs
[OP
[0]] = (State
.F0
== 1) ? 1 : 0;
1625 printf(" sll\tr%d,r%d\n",OP
[0],OP
[1]);
1627 State
.regs
[OP
[0]] <<= (State
.regs
[OP
[1]] & 0xf);
1636 printf(" sll\ta%d,r%d\n",OP
[0],OP
[1]);
1638 if (State
.regs
[OP
[1]] & 31 <= 16)
1639 tmp
= SEXT40 (State
.a
[OP
[0]]) << (State
.regs
[OP
[1]] & 31);
1644 State
.a
[OP
[0]] = MAX32
;
1645 else if (tmp
< 0xffffff80000000LL
)
1646 State
.a
[OP
[0]] = MIN32
;
1648 State
.a
[OP
[0]] = tmp
& MASK40
;
1651 State
.a
[OP
[0]] = tmp
& MASK40
;
1659 printf(" slli\tr%d,%d\n",OP
[0],OP
[1]);
1661 State
.regs
[OP
[0]] <<= OP
[1];
1673 printf(" slli\ta%d,%d\n",OP
[0],OP
[1]);
1676 tmp
= SEXT40(State
.a
[OP
[0]]) << OP
[1];
1681 State
.a
[OP
[0]] = MAX32
;
1682 else if (tmp
< 0xffffff80000000LL
)
1683 State
.a
[OP
[0]] = MIN32
;
1685 State
.a
[OP
[0]] = tmp
& MASK40
;
1688 State
.a
[OP
[0]] = tmp
& MASK40
;
1697 printf(" slx\tr%d\n",OP
[0]);
1699 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] << 1) | State
.F0
;
1707 printf(" sra\tr%d,r%d\n",OP
[0],OP
[1]);
1709 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> (State
.regs
[OP
[1]] & 0xf);
1717 printf(" sra\ta%d,r%d\n",OP
[0],OP
[1]);
1719 if (State
.regs
[OP
[1]] & 31 <= 16)
1720 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
1728 printf(" srai\tr%d,%d\n",OP
[0],OP
[1]);
1730 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> OP
[1];
1740 printf(" srai\ta%d,%d\n",OP
[0],OP
[1]);
1742 State
.a
[OP
[0]] >>= OP
[1];
1750 printf(" srl\tr%d,r%d\n",OP
[0],OP
[1]);
1752 State
.regs
[OP
[0]] >>= (State
.regs
[OP
[1]] & 0xf);
1760 printf(" srl\ta%d,r%d\n",OP
[0],OP
[1]);
1762 if (State
.regs
[OP
[1]] & 31 <= 16)
1763 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
1771 printf(" srli\tr%d,%d\n",OP
[0],OP
[1]);
1773 State
.regs
[OP
[0]] >>= OP
[1];
1783 printf(" srli\ta%d,%d\n",OP
[0],OP
[1]);
1785 State
.a
[OP
[0]] >>= OP
[1];
1794 printf(" srx\tr%d\n",OP
[0]);
1796 tmp
= State
.F0
<< 15;
1797 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] >> 1) | tmp
;
1805 printf(" st\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
1807 SW (OP
[1] + State
.regs
[OP
[2]], State
.regs
[OP
[0]]);
1815 printf(" st\tr%d,@r%d\n",OP
[0],OP
[1]);
1817 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1825 printf(" st\tr%d,@-r%d\n",OP
[0],OP
[1]);
1829 fprintf (stderr
,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
1830 State
.exception
= SIGILL
;
1833 State
.regs
[OP
[1]] -= 2;
1834 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1842 printf(" st\tr%d,@r%d+\n",OP
[0],OP
[1]);
1844 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1845 INC_ADDR (State
.regs
[OP
[1]],2);
1853 printf(" st\tr%d,@r%d-\n",OP
[0],OP
[1]);
1855 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1856 INC_ADDR (State
.regs
[OP
[1]],-2);
1864 printf(" st2w\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
1866 SW (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
1867 SW (State
.regs
[OP
[2]]+OP
[1]+2, State
.regs
[OP
[0]+1]);
1875 printf(" st2w\tr%d,@r%d\n",OP
[0],OP
[1]);
1877 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1878 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
1886 printf(" st2w\tr%d,@-r%d\n",OP
[0],OP
[1]);
1890 fprintf (stderr
,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
1891 State
.exception
= SIGILL
;
1894 State
.regs
[OP
[1]] -= 4;
1895 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1896 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
1904 printf(" st2w\tr%d,r%d+\n",OP
[0],OP
[1]);
1906 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1907 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
1908 INC_ADDR (State
.regs
[OP
[1]],4);
1916 printf(" st2w\tr%d,r%d-\n",OP
[0],OP
[1]);
1918 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1919 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
1920 INC_ADDR (State
.regs
[OP
[1]],-4);
1928 printf(" stb\tr%d,@(0x%x,r%d)\n",OP
[0],OP
[1],OP
[2]);
1930 SB (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
1938 printf(" stb\tr%d,@r%d\n",OP
[0],OP
[1]);
1940 SB (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
1950 State
.exception
= SIGQUIT
;
1959 printf(" sub\tr%d,r%d\n",OP
[0],OP
[1]);
1961 tmp
= (int16
)State
.regs
[OP
[0]]- (int16
)State
.regs
[OP
[1]];
1962 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
1963 State
.regs
[OP
[0]] = tmp
& 0xffff;
1972 printf(" sub\ta%d,r%d\n",OP
[0],OP
[1]);
1974 tmp
= SEXT40(State
.a
[OP
[0]]) - (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
1978 State
.a
[OP
[0]] = MAX32
;
1979 else if ( tmp
< MIN32
)
1980 State
.a
[OP
[0]] = MIN32
;
1982 State
.a
[OP
[0]] = tmp
& MASK40
;
1985 State
.a
[OP
[0]] = tmp
& MASK40
;
1995 printf(" sub\ta%d,a%d\n",OP
[0],OP
[1]);
1997 tmp
= SEXT40(State
.a
[OP
[0]]) - SEXT40(State
.a
[OP
[1]]);
2001 State
.a
[OP
[0]] = MAX32
;
2002 else if ( tmp
< MIN32
)
2003 State
.a
[OP
[0]] = MIN32
;
2005 State
.a
[OP
[0]] = tmp
& MASK40
;
2008 State
.a
[OP
[0]] = tmp
& MASK40
;
2018 printf(" sub2w\tr%d,r%d\n",OP
[0],OP
[1]);
2021 a
= (int32
)((State
.regs
[OP
[0]] << 16) | State
.regs
[OP
[0]+1]);
2022 b
= (int32
)((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
2024 State
.C
= (tmp
& 0xffffffff00000000LL
) ? 1 : 0;
2025 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2026 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2035 printf(" subac3\tr%d,r%d,a%d\n",OP
[0],OP
[1],OP
[2]);
2037 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40 (State
.a
[OP
[2]]);
2038 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2039 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2048 printf(" subac3\tr%d,a%d,a%d\n",OP
[0],OP
[1],OP
[2]);
2050 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2051 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2052 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2061 printf(" subac3s\tr%d,r%d,a%d\n",OP
[0],OP
[1],OP
[2]);
2063 State
.F1
= State
.F0
;
2064 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40(State
.a
[OP
[2]]);
2067 State
.regs
[OP
[0]] = 0x7fff;
2068 State
.regs
[OP
[0]+1] = 0xffff;
2071 else if (tmp
< MIN32
)
2073 State
.regs
[OP
[0]] = 0x8000;
2074 State
.regs
[OP
[0]+1] = 0;
2079 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2080 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2091 printf(" subac3s\tr%d,a%d,a%d\n",OP
[0],OP
[1],OP
[2]);
2093 State
.F1
= State
.F0
;
2094 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2097 State
.regs
[OP
[0]] = 0x7fff;
2098 State
.regs
[OP
[0]+1] = 0xffff;
2101 else if (tmp
< MIN32
)
2103 State
.regs
[OP
[0]] = 0x8000;
2104 State
.regs
[OP
[0]+1] = 0;
2109 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2110 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2123 printf(" subi\tr%d,%d\n",OP
[0],OP
[1]);
2125 tmp
= (int16
)State
.regs
[OP
[0]] - OP
[1];
2126 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2127 State
.regs
[OP
[0]] = tmp
& 0xffff;
2135 printf(" trap\t%d\n",OP
[0]);
2138 /* for now, trap is used for simulating IO */
2142 char *fstr
= State
.regs
[2] + State
.imem
;
2143 printf (fstr
,State
.regs
[3],State
.regs
[4],State
.regs
[5]);
2145 else if (OP
[0] == 1 )
2147 char *fstr
= State
.regs
[2] + State
.imem
;
2157 printf(" tst0i\tr%d,0x%x\n",OP
[0],OP
[1]);
2159 State
.F1
= State
.F0
;
2160 State
.F0
= (State
.regs
[OP
[0]] & OP
[1]) ? 1 : 0;
2168 printf(" tst1i\tr%d,0x%x\n",OP
[0],OP
[1]);
2170 State
.F1
= State
.F0
;
2171 State
.F0
= (~(State
.regs
[OP
[0]]) & OP
[1]) ? 1 : 0;
2189 printf(" xor\tr%d,r%d\n",OP
[0],OP
[1]);
2191 State
.regs
[OP
[0]] ^= State
.regs
[OP
[1]];
2199 printf(" xor3\tr%d,r%d,0x%x\n",OP
[0],OP
[1],OP
[2]);
2201 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] ^ OP
[2];
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