1af4e09a70672a5b71690e06e85de0eed0d450d8
9 #include "sys/syscall.h"
36 static void trace_input
PARAMS ((char *name
,
41 static void trace_output
PARAMS ((enum op_types result
));
43 #ifndef SIZE_INSTRUCTION
44 #define SIZE_INSTRUCTION 10
48 #define SIZE_OPERANDS 24
52 #define SIZE_VALUES 13
56 trace_input (name
, in1
, in2
, in3
)
70 if ((d10v_debug
& DEBUG_TRACE
) == 0)
73 switch (State
.ins_type
)
76 case INS_UNKNOWN
: type
= " ?"; break;
77 case INS_LEFT
: type
= " L"; break;
78 case INS_RIGHT
: type
= " R"; break;
79 case INS_LEFT_PARALLEL
: type
= "*L"; break;
80 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
81 case INS_LONG
: type
= " B"; break;
84 (*d10v_callback
->printf_filtered
) (d10v_callback
,
87 SIZE_INSTRUCTION
, name
);
94 for (i
= 0; i
< 3; i
++)
105 sprintf (p
, "%sr%d", comma
, OP
[i
]);
113 sprintf (p
, "%scr%d", comma
, OP
[i
]);
119 case OP_ACCUM_OUTPUT
:
120 case OP_ACCUM_REVERSE
:
121 sprintf (p
, "%sa%d", comma
, OP
[i
]);
127 sprintf (p
, "%s%d", comma
, OP
[i
]);
133 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
139 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
145 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
151 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
157 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
163 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
169 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
177 sprintf (p
, "%sf0", comma
);
180 sprintf (p
, "%sf1", comma
);
183 sprintf (p
, "%sc", comma
);
191 if ((d10v_debug
& DEBUG_VALUES
) == 0)
195 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%s", buf
);
200 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%-*s", SIZE_OPERANDS
, buf
);
203 for (i
= 0; i
< 3; i
++)
209 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "");
215 case OP_ACCUM_OUTPUT
:
217 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "---");
225 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
226 (uint16
)State
.regs
[OP
[i
]]);
230 tmp
= (long)((((uint32
) State
.regs
[OP
[i
]]) << 16) | ((uint32
) State
.regs
[OP
[i
]+1]));
231 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
236 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
237 (uint16
)State
.cregs
[OP
[i
]]);
241 case OP_ACCUM_REVERSE
:
242 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
243 ((int)(State
.a
[OP
[i
]] >> 32) & 0xff),
244 ((unsigned long)State
.a
[OP
[i
]]) & 0xffffffff);
248 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
253 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
254 (uint16
)SEXT4(OP
[i
]));
258 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
259 (uint16
)SEXT3(OP
[i
]));
264 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF0 = %d", SIZE_VALUES
-6, "",
268 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF1 = %d", SIZE_VALUES
-6, "",
272 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sC = %d", SIZE_VALUES
-5, "",
278 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
280 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
281 (uint16
)State
.regs
[OP
[++i
]]);
289 trace_output (result
)
290 enum op_types result
;
292 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
304 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
305 (uint16
)State
.regs
[OP
[0]],
306 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
311 tmp
= (long)((((uint32
) State
.regs
[OP
[0]]) << 16) | ((uint32
) State
.regs
[OP
[0]+1]));
312 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "", tmp
,
313 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
318 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
319 (uint16
)State
.cregs
[OP
[0]],
320 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
324 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
325 (uint16
)State
.cregs
[OP
[1]],
326 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
330 case OP_ACCUM_OUTPUT
:
331 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
332 ((int)(State
.a
[OP
[0]] >> 32) & 0xff),
333 ((unsigned long)State
.a
[OP
[0]]) & 0xffffffff,
334 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
337 case OP_ACCUM_REVERSE
:
338 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
339 ((int)(State
.a
[OP
[1]] >> 32) & 0xff),
340 ((unsigned long)State
.a
[OP
[1]]) & 0xffffffff,
341 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
346 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES
, "",
347 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
354 #define trace_input(NAME, IN1, IN2, IN3)
355 #define trace_output(RESULT)
362 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
364 if ((int16
)(State
.regs
[OP
[0]]) < 0)
366 State
.regs
[OP
[0]] = -(int16
)(State
.regs
[OP
[0]]);
371 trace_output (OP_REG
);
380 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
382 State
.a
[OP
[0]] = SEXT40(State
.a
[OP
[0]]);
384 if (State
.a
[OP
[0]] < 0 )
386 tmp
= -State
.a
[OP
[0]];
390 State
.a
[OP
[0]] = MAX32
;
391 else if (tmp
< MIN32
)
392 State
.a
[OP
[0]] = MIN32
;
394 State
.a
[OP
[0]] = tmp
& MASK40
;
397 State
.a
[OP
[0]] = tmp
& MASK40
;
402 trace_output (OP_ACCUM
);
409 uint16 tmp
= State
.regs
[OP
[0]];
410 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
411 State
.regs
[OP
[0]] += State
.regs
[OP
[1]];
412 if ( tmp
> State
.regs
[OP
[0]])
416 trace_output (OP_REG
);
424 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
426 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
430 State
.a
[OP
[0]] = MAX32
;
431 else if ( tmp
< MIN32
)
432 State
.a
[OP
[0]] = MIN32
;
434 State
.a
[OP
[0]] = tmp
& MASK40
;
437 State
.a
[OP
[0]] = tmp
& MASK40
;
438 trace_output (OP_ACCUM
);
446 tmp
= SEXT40(State
.a
[OP
[0]]) + SEXT40(State
.a
[OP
[1]]);
448 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
452 State
.a
[OP
[0]] = MAX32
;
453 else if ( tmp
< MIN32
)
454 State
.a
[OP
[0]] = MIN32
;
456 State
.a
[OP
[0]] = tmp
& MASK40
;
459 State
.a
[OP
[0]] = tmp
& MASK40
;
460 trace_output (OP_ACCUM
);
468 uint32 tmp1
= (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1];
469 uint32 tmp2
= (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
471 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
473 if ( (tmp
< tmp1
) || (tmp
< tmp2
) )
477 State
.regs
[OP
[0]] = tmp
>> 16;
478 State
.regs
[OP
[0]+1] = tmp
& 0xFFFF;
479 trace_output (OP_DREG
);
486 uint16 tmp
= State
.regs
[OP
[0]];
487 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] + OP
[2];
489 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
490 if ( tmp
> State
.regs
[OP
[0]])
494 trace_output (OP_REG
);
502 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
504 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
505 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
506 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
507 trace_output (OP_DREG
);
515 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
517 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
518 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
519 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
520 trace_output (OP_DREG
);
530 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
531 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
534 State
.regs
[OP
[0]] = 0x7fff;
535 State
.regs
[OP
[0]+1] = 0xffff;
538 else if (tmp
< MIN32
)
540 State
.regs
[OP
[0]] = 0x8000;
541 State
.regs
[OP
[0]+1] = 0;
546 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
547 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
550 trace_output (OP_DREG
);
560 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
561 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
564 State
.regs
[OP
[0]] = 0x7fff;
565 State
.regs
[OP
[0]+1] = 0xffff;
568 else if (tmp
< MIN32
)
570 State
.regs
[OP
[0]] = 0x8000;
571 State
.regs
[OP
[0]+1] = 0;
576 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
577 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
580 trace_output (OP_DREG
);
589 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
590 State
.regs
[OP
[0]] += OP
[1];
591 trace_output (OP_REG
);
598 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
599 State
.regs
[OP
[0]] &= State
.regs
[OP
[1]];
600 trace_output (OP_REG
);
607 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
608 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & OP
[2];
609 trace_output (OP_REG
);
616 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
617 State
.regs
[OP
[0]] &= ~(0x8000 >> OP
[1]);
618 trace_output (OP_REG
);
625 trace_input ("bl.s", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
626 State
.regs
[13] = PC
+1;
628 trace_output (OP_VOID
);
635 trace_input ("bl.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
636 State
.regs
[13] = PC
+1;
638 trace_output (OP_VOID
);
645 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
646 State
.regs
[OP
[0]] ^= 0x8000 >> OP
[1];
647 trace_output (OP_REG
);
654 trace_input ("bra.s", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
656 trace_output (OP_VOID
);
663 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
665 trace_output (OP_VOID
);
672 trace_input ("brf0f.s", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
675 trace_output (OP_FLAG
);
682 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
685 trace_output (OP_FLAG
);
692 trace_input ("brf0t.s", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
695 trace_output (OP_FLAG
);
702 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
705 trace_output (OP_FLAG
);
712 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
713 State
.regs
[OP
[0]] |= 0x8000 >> OP
[1];
714 trace_output (OP_REG
);
721 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
723 State
.F0
= (State
.regs
[OP
[0]] & (0x8000 >> OP
[1])) ? 1 : 0;
724 trace_output (OP_FLAG
);
731 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
733 trace_output (OP_ACCUM
);
740 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
742 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(State
.regs
[OP
[1]])) ? 1 : 0;
743 trace_output (OP_FLAG
);
750 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
752 State
.F0
= (SEXT40(State
.a
[OP
[0]]) < SEXT40(State
.a
[OP
[1]])) ? 1 : 0;
753 trace_output (OP_FLAG
);
760 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
762 State
.F0
= (State
.regs
[OP
[0]] == State
.regs
[OP
[1]]) ? 1 : 0;
763 trace_output (OP_FLAG
);
770 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
772 State
.F0
= (State
.a
[OP
[0]] == State
.a
[OP
[1]]) ? 1 : 0;
773 trace_output (OP_FLAG
);
780 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT16
, OP_VOID
);
782 State
.F0
= (State
.regs
[OP
[0]] == SEXT4(OP
[1])) ? 1 : 0;
783 trace_output (OP_FLAG
);
790 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
792 State
.F0
= (State
.regs
[OP
[0]] == OP
[1]) ? 1 : 0;
793 trace_output (OP_FLAG
);
800 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
802 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < SEXT4(OP
[1])) ? 1 : 0;
803 trace_output (OP_FLAG
);
810 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
812 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(OP
[1])) ? 1 : 0;
813 trace_output (OP_FLAG
);
820 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
822 State
.F0
= (State
.regs
[OP
[0]] < State
.regs
[OP
[1]]) ? 1 : 0;
823 trace_output (OP_FLAG
);
830 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
832 State
.F0
= (State
.regs
[OP
[0]] < OP
[1]) ? 1 : 0;
833 trace_output (OP_FLAG
);
842 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
856 trace_output (OP_FLAG
);
863 d10v_callback
->printf_filtered(d10v_callback
, "***** DBT ***** PC=%x\n",PC
);
864 State
.exception
= SIGTRAP
;
871 uint16 foo
, tmp
, tmpf
;
873 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
874 foo
= (State
.regs
[OP
[0]] << 1) | (State
.regs
[OP
[0]+1] >> 15);
875 tmp
= (int16
)foo
- (int16
)(State
.regs
[OP
[1]]);
876 tmpf
= (foo
>= State
.regs
[OP
[1]]) ? 1 : 0;
877 State
.regs
[OP
[0]] = (tmpf
== 1) ? tmp
: foo
;
878 State
.regs
[OP
[0]+1] = (State
.regs
[OP
[0]+1] << 1) | tmpf
;
879 trace_output (OP_DREG
);
886 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
887 State
.exe
= (State
.F0
== 0);
888 trace_output (OP_FLAG
);
895 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
896 State
.exe
= (State
.F0
!= 0);
897 trace_output (OP_FLAG
);
904 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
905 State
.exe
= (State
.F1
== 0);
906 trace_output (OP_FLAG
);
913 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
914 State
.exe
= (State
.F1
!= 0);
915 trace_output (OP_FLAG
);
922 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
923 State
.exe
= (State
.F0
== 0) & (State
.F1
== 0);
924 trace_output (OP_FLAG
);
931 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
932 State
.exe
= (State
.F0
== 0) & (State
.F1
!= 0);
933 trace_output (OP_FLAG
);
940 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
941 State
.exe
= (State
.F0
!= 0) & (State
.F1
== 0);
942 trace_output (OP_FLAG
);
949 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
950 State
.exe
= (State
.F0
!= 0) & (State
.F1
!= 0);
951 trace_output (OP_FLAG
);
961 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
962 if (((int16
)State
.regs
[OP
[1]]) >= 0)
963 tmp
= (State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1];
965 tmp
= ~((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
972 State
.regs
[OP
[0]] = i
-1;
973 trace_output (OP_REG
);
978 State
.regs
[OP
[0]] = 16;
979 trace_output (OP_REG
);
989 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
990 if (SEXT40(State
.a
[OP
[1]]) >= 0)
991 tmp
= State
.a
[OP
[1]];
993 tmp
= ~(State
.a
[OP
[1]]);
995 foo
= 0x4000000000LL
;
1000 State
.regs
[OP
[0]] = i
-9;
1001 trace_output (OP_REG
);
1006 State
.regs
[OP
[0]] = 16;
1007 trace_output (OP_REG
);
1014 trace_input ("jl", OP_REG
, OP_VOID
, OP_VOID
);
1015 State
.regs
[13] = PC
+1;
1016 PC
= State
.regs
[OP
[0]];
1017 trace_output (OP_VOID
);
1024 trace_input ("jmp", OP_REG
, OP_VOID
, OP_VOID
);
1025 PC
= State
.regs
[OP
[0]];
1026 trace_output (OP_VOID
);
1033 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1034 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1035 trace_output (OP_REG
);
1042 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1043 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1044 INC_ADDR(State
.regs
[OP
[1]],-2);
1045 trace_output (OP_REG
);
1052 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1053 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1054 INC_ADDR(State
.regs
[OP
[1]],2);
1055 trace_output (OP_REG
);
1062 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1063 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1064 trace_output (OP_REG
);
1071 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1072 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1073 State
.regs
[OP
[0]+1] = RW (OP
[1] + State
.regs
[OP
[2]] + 2);
1074 trace_output (OP_DREG
);
1081 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1082 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1083 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
1084 INC_ADDR(State
.regs
[OP
[1]],-4);
1085 trace_output (OP_DREG
);
1092 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1093 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1094 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
1095 INC_ADDR(State
.regs
[OP
[1]],4);
1096 trace_output (OP_REG
);
1103 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1104 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1105 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
1106 trace_output (OP_REG
);
1113 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1114 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1115 SEXT8 (State
.regs
[OP
[0]]);
1116 trace_output (OP_REG
);
1123 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1124 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1125 SEXT8 (State
.regs
[OP
[0]]);
1126 trace_output (OP_REG
);
1133 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1134 State
.regs
[OP
[0]] = SEXT4(OP
[1]);
1135 trace_output (OP_REG
);
1142 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1143 State
.regs
[OP
[0]] = OP
[1];
1144 trace_output (OP_REG
);
1151 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1152 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1153 trace_output (OP_REG
);
1160 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1161 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1162 trace_output (OP_REG
);
1171 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1172 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1175 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1177 if (State
.ST
&& tmp
> MAX32
)
1180 tmp
+= SEXT40(State
.a
[OP
[0]]);
1184 State
.a
[OP
[0]] = MAX32
;
1185 else if (tmp
< MIN32
)
1186 State
.a
[OP
[0]] = MIN32
;
1188 State
.a
[OP
[0]] = tmp
& MASK40
;
1191 State
.a
[OP
[0]] = tmp
& MASK40
;
1192 trace_output (OP_ACCUM
);
1201 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1202 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1204 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1206 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1207 trace_output (OP_ACCUM
);
1216 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1217 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1219 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1220 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1221 trace_output (OP_ACCUM
);
1228 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1229 State
.F1
= State
.F0
;
1230 if ((int16
)State
.regs
[OP
[1]] > (int16
)State
.regs
[OP
[0]])
1232 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1237 trace_output (OP_REG
);
1246 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1247 State
.F1
= State
.F0
;
1248 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1249 if (tmp
> SEXT40(State
.a
[OP
[0]]))
1251 State
.a
[OP
[0]] = tmp
& MASK40
;
1256 trace_output (OP_ACCUM
);
1263 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1264 State
.F1
= State
.F0
;
1265 if (SEXT40(State
.a
[OP
[1]]) > SEXT40(State
.a
[OP
[0]]))
1267 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1272 trace_output (OP_ACCUM
);
1280 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1281 State
.F1
= State
.F0
;
1282 if ((int16
)State
.regs
[OP
[1]] < (int16
)State
.regs
[OP
[0]])
1284 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1289 trace_output (OP_REG
);
1298 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1299 State
.F1
= State
.F0
;
1300 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1301 if (tmp
< SEXT40(State
.a
[OP
[0]]))
1303 State
.a
[OP
[0]] = tmp
& MASK40
;
1308 trace_output (OP_ACCUM
);
1315 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1316 State
.F1
= State
.F0
;
1317 if (SEXT40(State
.a
[OP
[1]]) < SEXT40(State
.a
[OP
[0]]))
1319 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1324 trace_output (OP_ACCUM
);
1333 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1334 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1337 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1339 if (State
.ST
&& tmp
> MAX32
)
1342 tmp
= SEXT40(State
.a
[OP
[0]]) - tmp
;
1346 State
.a
[OP
[0]] = MAX32
;
1347 else if (tmp
< MIN32
)
1348 State
.a
[OP
[0]] = MIN32
;
1350 State
.a
[OP
[0]] = tmp
& MASK40
;
1353 State
.a
[OP
[0]] = tmp
& MASK40
;
1354 trace_output (OP_ACCUM
);
1363 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1364 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1366 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1368 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1369 trace_output (OP_ACCUM
);
1378 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1379 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1381 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1383 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1384 trace_output (OP_ACCUM
);
1391 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1392 State
.regs
[OP
[0]] *= State
.regs
[OP
[1]];
1393 trace_output (OP_REG
);
1402 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1403 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1406 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1408 if (State
.ST
&& tmp
> MAX32
)
1409 State
.a
[OP
[0]] = MAX32
;
1411 State
.a
[OP
[0]] = tmp
& MASK40
;
1412 trace_output (OP_ACCUM
);
1421 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1422 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * State
.regs
[OP
[2]]);
1427 State
.a
[OP
[0]] = tmp
& MASK40
;
1428 trace_output (OP_ACCUM
);
1437 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1438 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1443 State
.a
[OP
[0]] = tmp
& MASK40
;
1444 trace_output (OP_ACCUM
);
1451 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1452 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1453 trace_output (OP_REG
);
1460 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1461 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1462 State
.regs
[OP
[0]+1] = State
.regs
[OP
[1]+1];
1463 trace_output (OP_DREG
);
1470 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1471 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1472 State
.regs
[OP
[0]+1] = State
.a
[OP
[1]] & 0xffff;
1473 trace_output (OP_DREG
);
1480 trace_input ("mv2wtac", OP_ACCUM_OUTPUT
, OP_DREG
, OP_VOID
);
1481 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1]) & MASK40
;
1482 trace_output (OP_ACCUM
);
1489 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1490 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1491 trace_output (OP_ACCUM
);
1498 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1499 State
.regs
[OP
[0]] = SEXT8 (State
.regs
[OP
[1]] & 0xff);
1500 trace_output (OP_REG
);
1507 trace_input ("mf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1509 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1510 trace_output (OP_REG
);
1517 trace_input ("mf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1519 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1520 trace_output (OP_REG
);
1527 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1528 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 32) & 0xff;
1529 trace_output (OP_ACCUM
);
1536 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1537 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1538 trace_output (OP_REG
);
1545 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1546 State
.regs
[OP
[0]] = State
.a
[OP
[1]] & 0xffff;
1547 trace_output (OP_REG
);
1554 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
1557 /* PSW is treated specially */
1559 if (State
.SM
) PSW
|= 0x8000;
1560 if (State
.EA
) PSW
|= 0x2000;
1561 if (State
.DB
) PSW
|= 0x1000;
1562 if (State
.IE
) PSW
|= 0x400;
1563 if (State
.RP
) PSW
|= 0x200;
1564 if (State
.MD
) PSW
|= 0x100;
1565 if (State
.FX
) PSW
|= 0x80;
1566 if (State
.ST
) PSW
|= 0x40;
1567 if (State
.F0
) PSW
|= 8;
1568 if (State
.F1
) PSW
|= 4;
1569 if (State
.C
) PSW
|= 1;
1571 State
.regs
[OP
[0]] = State
.cregs
[OP
[1]];
1572 trace_output (OP_REG
);
1579 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
1580 State
.a
[OP
[1]] &= MASK32
;
1581 State
.a
[OP
[1]] |= (int64
)(State
.regs
[OP
[0]] & 0xff) << 32;
1582 trace_output (OP_ACCUM_REVERSE
);
1591 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
1592 tmp
= State
.a
[OP
[1]] & 0xffff;
1593 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | tmp
) & MASK40
;
1594 trace_output (OP_ACCUM_REVERSE
);
1601 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
1602 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]])) & MASK40
;
1603 trace_output (OP_ACCUM_REVERSE
);
1610 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
1611 State
.cregs
[OP
[1]] = State
.regs
[OP
[0]];
1614 /* PSW is treated specially */
1615 State
.SM
= (PSW
& 0x8000) ? 1 : 0;
1616 State
.EA
= (PSW
& 0x2000) ? 1 : 0;
1617 State
.DB
= (PSW
& 0x1000) ? 1 : 0;
1618 State
.IE
= (PSW
& 0x400) ? 1 : 0;
1619 State
.RP
= (PSW
& 0x200) ? 1 : 0;
1620 State
.MD
= (PSW
& 0x100) ? 1 : 0;
1621 State
.FX
= (PSW
& 0x80) ? 1 : 0;
1622 State
.ST
= (PSW
& 0x40) ? 1 : 0;
1623 State
.F0
= (PSW
& 8) ? 1 : 0;
1624 State
.F1
= (PSW
& 4) ? 1 : 0;
1626 if (State
.ST
&& !State
.FX
)
1628 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1629 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1631 State
.exception
= SIGILL
;
1634 trace_output (OP_CR_REVERSE
);
1641 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1642 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & 0xff;
1643 trace_output (OP_REG
);
1650 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
1651 State
.regs
[OP
[0]] = 0 - State
.regs
[OP
[0]];
1652 trace_output (OP_REG
);
1661 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
1662 tmp
= -SEXT40(State
.a
[OP
[0]]);
1666 State
.a
[OP
[0]] = MAX32
;
1667 else if (tmp
< MIN32
)
1668 State
.a
[OP
[0]] = MIN32
;
1670 State
.a
[OP
[0]] = tmp
& MASK40
;
1673 State
.a
[OP
[0]] = tmp
& MASK40
;
1674 trace_output (OP_ACCUM
);
1682 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
1683 trace_output (OP_VOID
);
1685 if (State
.ins_type
== INS_LEFT
|| State
.ins_type
== INS_LEFT_PARALLEL
)
1695 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
1696 State
.regs
[OP
[0]] = ~(State
.regs
[OP
[0]]);
1697 trace_output (OP_REG
);
1704 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
1705 State
.regs
[OP
[0]] |= State
.regs
[OP
[1]];
1706 trace_output (OP_REG
);
1713 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
1714 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] | OP
[2];
1715 trace_output (OP_REG
);
1723 int shift
= SEXT3 (OP
[2]);
1725 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1728 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1729 "ERROR at PC 0x%x: instruction only valid for A0\n",
1731 State
.exception
= SIGILL
;
1734 State
.F1
= State
.F0
;
1736 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) << shift
;
1738 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) >> -shift
;
1739 tmp
= ( SEXT60(tmp
) + 0x8000 ) >> 16;
1742 State
.regs
[OP
[0]] = 0x7fff;
1743 State
.regs
[OP
[0]+1] = 0xffff;
1746 else if (tmp
< MIN32
)
1748 State
.regs
[OP
[0]] = 0x8000;
1749 State
.regs
[OP
[0]+1] = 0;
1754 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1755 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
1758 trace_output (OP_DREG
);
1766 int shift
= SEXT3 (OP
[2]);
1768 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1769 State
.F1
= State
.F0
;
1771 tmp
= SEXT44 (State
.a
[1]) << shift
;
1773 tmp
= SEXT44 (State
.a
[1]) >> -shift
;
1778 State
.regs
[OP
[0]] = 0x7fff;
1781 else if (tmp
< 0xfff80000000LL
)
1783 State
.regs
[OP
[0]] = 0x8000;
1788 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1791 trace_output (OP_REG
);
1798 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1801 RPT_C
= State
.regs
[OP
[0]];
1805 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep with count=0 is illegal.\n");
1806 State
.exception
= SIGILL
;
1810 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep must include at least 4 instructions.\n");
1811 State
.exception
= SIGILL
;
1813 trace_output (OP_VOID
);
1820 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
1827 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi with count=0 is illegal.\n");
1828 State
.exception
= SIGILL
;
1832 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi must include at least 4 instructions.\n");
1833 State
.exception
= SIGILL
;
1835 trace_output (OP_VOID
);
1842 d10v_callback
->printf_filtered(d10v_callback
, "ERROR: rtd - NOT IMPLEMENTED\n");
1843 State
.exception
= SIGILL
;
1850 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
1853 trace_output (OP_VOID
);
1862 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1863 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT40(State
.a
[OP
[1]]) >> 16);
1867 State
.a
[OP
[0]] = MAX32
;
1868 else if (tmp
< MIN32
)
1869 State
.a
[OP
[0]] = MIN32
;
1871 State
.a
[OP
[0]] = tmp
& MASK40
;
1874 State
.a
[OP
[0]] = tmp
& MASK40
;
1875 trace_output (OP_ACCUM
);
1882 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
1883 State
.regs
[OP
[0]] = (State
.F0
== 0) ? 1 : 0;
1884 trace_output (OP_REG
);
1891 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
1892 State
.regs
[OP
[0]] = (State
.F0
== 1) ? 1 : 0;
1893 trace_output (OP_REG
);
1900 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
1902 trace_output (OP_VOID
);
1909 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
1910 State
.regs
[OP
[0]] <<= (State
.regs
[OP
[1]] & 0xf);
1911 trace_output (OP_REG
);
1919 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
1920 if ((State
.regs
[OP
[1]] & 31) <= 16)
1921 tmp
= SEXT40 (State
.a
[OP
[0]]) << (State
.regs
[OP
[1]] & 31);
1924 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
1925 State
.exception
= SIGILL
;
1932 State
.a
[OP
[0]] = MAX32
;
1933 else if (tmp
< 0xffffff80000000LL
)
1934 State
.a
[OP
[0]] = MIN32
;
1936 State
.a
[OP
[0]] = tmp
& MASK40
;
1939 State
.a
[OP
[0]] = tmp
& MASK40
;
1940 trace_output (OP_ACCUM
);
1947 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1948 State
.regs
[OP
[0]] <<= OP
[1];
1949 trace_output (OP_REG
);
1961 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
1962 tmp
= SEXT40(State
.a
[OP
[0]]) << OP
[1];
1967 State
.a
[OP
[0]] = MAX32
;
1968 else if (tmp
< 0xffffff80000000LL
)
1969 State
.a
[OP
[0]] = MIN32
;
1971 State
.a
[OP
[0]] = tmp
& MASK40
;
1974 State
.a
[OP
[0]] = tmp
& MASK40
;
1975 trace_output (OP_ACCUM
);
1984 trace_input ("slx", OP_REG
, OP_FLAG
, OP_VOID
);
1985 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] << 1) | State
.F0
;
1986 trace_output (OP_REG
);
1993 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
1994 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> (State
.regs
[OP
[1]] & 0xf);
1995 trace_output (OP_REG
);
2002 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2003 if ((State
.regs
[OP
[1]] & 31) <= 16)
2004 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
2007 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2008 State
.exception
= SIGILL
;
2012 trace_output (OP_ACCUM
);
2019 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2020 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> OP
[1];
2021 trace_output (OP_REG
);
2031 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2032 State
.a
[OP
[0]] >>= OP
[1];
2033 trace_output (OP_ACCUM
);
2040 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2041 State
.regs
[OP
[0]] >>= (State
.regs
[OP
[1]] & 0xf);
2042 trace_output (OP_REG
);
2049 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2050 if ((State
.regs
[OP
[1]] & 31) <= 16)
2051 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
2054 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2055 State
.exception
= SIGILL
;
2059 trace_output (OP_ACCUM
);
2066 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2067 State
.regs
[OP
[0]] >>= OP
[1];
2068 trace_output (OP_REG
);
2078 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2079 State
.a
[OP
[0]] >>= OP
[1];
2080 trace_output (OP_ACCUM
);
2089 trace_input ("srx", OP_REG
, OP_FLAG
, OP_VOID
);
2090 tmp
= State
.F0
<< 15;
2091 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] >> 1) | tmp
;
2092 trace_output (OP_REG
);
2099 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2100 SW (OP
[1] + State
.regs
[OP
[2]], State
.regs
[OP
[0]]);
2101 trace_output (OP_VOID
);
2108 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2109 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2110 trace_output (OP_VOID
);
2117 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2120 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2121 State
.exception
= SIGILL
;
2124 State
.regs
[OP
[1]] -= 2;
2125 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2126 trace_output (OP_VOID
);
2133 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2134 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2135 INC_ADDR (State
.regs
[OP
[1]],2);
2136 trace_output (OP_VOID
);
2143 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2144 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2145 INC_ADDR (State
.regs
[OP
[1]],-2);
2146 trace_output (OP_VOID
);
2153 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2154 SW (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2155 SW (State
.regs
[OP
[2]]+OP
[1]+2, State
.regs
[OP
[0]+1]);
2156 trace_output (OP_VOID
);
2163 trace_input ("st2w", OP_REG
, OP_MEMREF
, OP_VOID
);
2164 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2165 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2166 trace_output (OP_VOID
);
2173 trace_input ("st2w", OP_REG
, OP_PREDEC
, OP_VOID
);
2176 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2177 State
.exception
= SIGILL
;
2180 State
.regs
[OP
[1]] -= 4;
2181 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2182 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2183 trace_output (OP_VOID
);
2190 trace_input ("st2w", OP_REG
, OP_POSTDEC
, OP_VOID
);
2191 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2192 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2193 INC_ADDR (State
.regs
[OP
[1]],4);
2194 trace_output (OP_VOID
);
2201 trace_input ("st2w", OP_REG
, OP_POSTINC
, OP_VOID
);
2202 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2203 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2204 INC_ADDR (State
.regs
[OP
[1]],-4);
2205 trace_output (OP_VOID
);
2212 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2213 SB (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2214 trace_output (OP_VOID
);
2221 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2222 SB (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2223 trace_output (OP_VOID
);
2230 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2231 State
.exception
= SIGQUIT
;
2232 trace_output (OP_VOID
);
2241 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
2242 tmp
= (int16
)State
.regs
[OP
[0]]- (int16
)State
.regs
[OP
[1]];
2243 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2244 State
.regs
[OP
[0]] = tmp
& 0xffff;
2245 trace_output (OP_REG
);
2254 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
2255 tmp
= SEXT40(State
.a
[OP
[0]]) - (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
2259 State
.a
[OP
[0]] = MAX32
;
2260 else if ( tmp
< MIN32
)
2261 State
.a
[OP
[0]] = MIN32
;
2263 State
.a
[OP
[0]] = tmp
& MASK40
;
2266 State
.a
[OP
[0]] = tmp
& MASK40
;
2268 trace_output (OP_ACCUM
);
2278 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2279 tmp
= SEXT40(State
.a
[OP
[0]]) - SEXT40(State
.a
[OP
[1]]);
2283 State
.a
[OP
[0]] = MAX32
;
2284 else if ( tmp
< MIN32
)
2285 State
.a
[OP
[0]] = MIN32
;
2287 State
.a
[OP
[0]] = tmp
& MASK40
;
2290 State
.a
[OP
[0]] = tmp
& MASK40
;
2292 trace_output (OP_ACCUM
);
2302 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
2303 a
= (int32
)((State
.regs
[OP
[0]] << 16) | State
.regs
[OP
[0]+1]);
2304 b
= (int32
)((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
2306 State
.C
= (tmp
& 0xffffffff00000000LL
) ? 1 : 0;
2307 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2308 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2309 trace_output (OP_DREG
);
2318 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2319 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40 (State
.a
[OP
[2]]);
2320 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2321 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2322 trace_output (OP_DREG
);
2331 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2332 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2333 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2334 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2335 trace_output (OP_DREG
);
2344 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2345 State
.F1
= State
.F0
;
2346 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40(State
.a
[OP
[2]]);
2349 State
.regs
[OP
[0]] = 0x7fff;
2350 State
.regs
[OP
[0]+1] = 0xffff;
2353 else if (tmp
< MIN32
)
2355 State
.regs
[OP
[0]] = 0x8000;
2356 State
.regs
[OP
[0]+1] = 0;
2361 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2362 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2365 trace_output (OP_DREG
);
2374 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2375 State
.F1
= State
.F0
;
2376 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2379 State
.regs
[OP
[0]] = 0x7fff;
2380 State
.regs
[OP
[0]+1] = 0xffff;
2383 else if (tmp
< MIN32
)
2385 State
.regs
[OP
[0]] = 0x8000;
2386 State
.regs
[OP
[0]+1] = 0;
2391 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2392 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2395 trace_output (OP_DREG
);
2406 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2407 tmp
= (int16
)State
.regs
[OP
[0]] - OP
[1];
2408 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2409 State
.regs
[OP
[0]] = tmp
& 0xffff;
2410 trace_output (OP_REG
);
2417 trace_input ("trap", OP_CONSTANT16
, OP_REG
, OP_VOID
);
2418 trace_output (OP_VOID
);
2423 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown trap code %d\n", OP
[0]);
2424 State
.exception
= SIGILL
;
2427 /* Trap 0 is used for simulating low-level I/O */
2429 int save_errno
= errno
;
2432 /* Registers passed to trap 0 */
2434 #define FUNC State.regs[2] /* function number, return value */
2435 #define PARM1 State.regs[3] /* optional parm 1 */
2436 #define PARM2 State.regs[4] /* optional parm 2 */
2437 #define PARM3 State.regs[5] /* optional parm 3 */
2439 /* Registers set by trap 0 */
2441 #define RETVAL State.regs[2] /* return value */
2442 #define RETERR State.regs[3] /* return error code */
2444 /* Turn a pointer in a register into a pointer into real memory. */
2446 #define MEMPTR(x) ((char *)((x) + State.imem))
2450 #if !defined(__GO32__) && !defined(_WIN32)
2458 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2459 (char **)MEMPTR (PARM3
));
2464 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2474 RETVAL
= pipe (host_fd
);
2475 SW (buf
, host_fd
[0]);
2476 buf
+= sizeof(uint16
);
2477 SW (buf
, host_fd
[1]);
2486 RETVAL
= wait (&status
);
2495 RETVAL
= d10v_callback
->read (d10v_callback
, PARM1
, MEMPTR (PARM2
),
2502 RETVAL
= (int)d10v_callback
->write_stdout (d10v_callback
,
2503 MEMPTR (PARM2
), PARM3
);
2505 RETVAL
= (int)d10v_callback
->write (d10v_callback
, PARM1
,
2506 MEMPTR (PARM2
), PARM3
);
2511 RETVAL
= d10v_callback
->lseek (d10v_callback
, PARM1
, PARM2
, PARM3
);
2516 RETVAL
= d10v_callback
->close (d10v_callback
, PARM1
);
2521 RETVAL
= d10v_callback
->open (d10v_callback
, MEMPTR (PARM1
), PARM2
);
2526 /* EXIT - caller can look in PARM1 to work out the
2528 State
.exception
= SIGQUIT
;
2534 /* stat system call */
2536 struct stat host_stat
;
2539 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2543 /* The hard-coded offsets and sizes were determined by using
2544 * the D10V compiler on a test program that used struct stat.
2546 SW (buf
, host_stat
.st_dev
);
2547 SW (buf
+2, host_stat
.st_ino
);
2548 SW (buf
+4, host_stat
.st_mode
);
2549 SW (buf
+6, host_stat
.st_nlink
);
2550 SW (buf
+8, host_stat
.st_uid
);
2551 SW (buf
+10, host_stat
.st_gid
);
2552 SW (buf
+12, host_stat
.st_rdev
);
2553 SLW (buf
+16, host_stat
.st_size
);
2554 SLW (buf
+20, host_stat
.st_atime
);
2555 SLW (buf
+28, host_stat
.st_mtime
);
2556 SLW (buf
+36, host_stat
.st_ctime
);
2563 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2568 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2573 /* Cast the second argument to void *, to avoid type mismatch
2574 if a prototype is present. */
2575 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2587 /* Trap 1 prints a string */
2589 char *fstr
= State
.regs
[2] + State
.imem
;
2590 fputs (fstr
, stdout
);
2595 /* Trap 2 calls printf */
2597 char *fstr
= State
.regs
[2] + State
.imem
;
2598 (*d10v_callback
->printf_filtered
) (d10v_callback
, fstr
,
2599 (int16
)State
.regs
[3],
2600 (int16
)State
.regs
[4],
2601 (int16
)State
.regs
[5]);
2606 /* Trap 3 writes a character */
2607 putchar (State
.regs
[2]);
2616 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2617 State
.F1
= State
.F0
;
2618 State
.F0
= (State
.regs
[OP
[0]] & OP
[1]) ? 1 : 0;
2619 trace_output (OP_FLAG
);
2626 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2627 State
.F1
= State
.F0
;
2628 State
.F0
= (~(State
.regs
[OP
[0]]) & OP
[1]) ? 1 : 0;
2629 trace_output (OP_FLAG
);
2636 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
2638 trace_output (OP_VOID
);
2645 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
2646 State
.regs
[OP
[0]] ^= State
.regs
[OP
[1]];
2647 trace_output (OP_REG
);
2654 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
2655 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] ^ OP
[2];
2656 trace_output (OP_REG
);
This page took 0.096305 seconds and 3 git commands to generate.