a1af4f90f8b4b1de8c52fd0c825ac9b8fe39f345
9 #include "sys/syscall.h"
37 static void trace_input_func
PARAMS ((char *name
,
42 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
44 static void trace_output_func
PARAMS ((enum op_types result
));
46 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
48 static int init_text_p
= 0;
49 static asection
*text
;
50 static bfd_vma text_start
;
51 static bfd_vma text_end
;
54 #ifndef SIZE_INSTRUCTION
55 #define SIZE_INSTRUCTION 8
59 #define SIZE_OPERANDS 18
63 #define SIZE_VALUES 13
67 #define SIZE_LOCATION 20
74 #ifndef SIZE_LINE_NUMBER
75 #define SIZE_LINE_NUMBER 4
79 trace_input_func (name
, in1
, in2
, in3
)
94 const char *functionname
;
95 unsigned int linenumber
;
98 if ((d10v_debug
& DEBUG_TRACE
) == 0)
101 switch (State
.ins_type
)
104 case INS_UNKNOWN
: type
= " ?"; break;
105 case INS_LEFT
: type
= " L"; break;
106 case INS_RIGHT
: type
= " R"; break;
107 case INS_LEFT_PARALLEL
: type
= "*L"; break;
108 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
109 case INS_LONG
: type
= " B"; break;
112 if ((d10v_debug
& DEBUG_LINE_NUMBER
) == 0)
113 (*d10v_callback
->printf_filtered
) (d10v_callback
,
115 SIZE_PC
, (unsigned)PC
,
117 SIZE_INSTRUCTION
, name
);
124 for (s
= exec_bfd
->sections
; s
; s
= s
->next
)
125 if (strcmp (bfd_get_section_name (exec_bfd
, s
), ".text") == 0)
128 text_start
= bfd_get_section_vma (exec_bfd
, s
);
129 text_end
= text_start
+ bfd_section_size (exec_bfd
, s
);
135 byte_pc
= (bfd_vma
)PC
<< 2;
136 if (text
&& byte_pc
>= text_start
&& byte_pc
< text_end
)
138 filename
= (const char *)0;
139 functionname
= (const char *)0;
141 if (bfd_find_nearest_line (exec_bfd
, text
, (struct symbol_cache_entry
**)0, byte_pc
- text_start
,
142 &filename
, &functionname
, &linenumber
))
147 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
152 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
153 p
+= SIZE_LINE_NUMBER
+2;
158 sprintf (p
, "%s ", functionname
);
163 char *q
= (char *) strrchr (filename
, '/');
164 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
173 (*d10v_callback
->printf_filtered
) (d10v_callback
,
174 "0x%.*x %s: %-*.*s %-*s ",
175 SIZE_PC
, (unsigned)PC
,
177 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
178 SIZE_INSTRUCTION
, name
);
186 for (i
= 0; i
< 3; i
++)
197 sprintf (p
, "%sr%d", comma
, OP
[i
]);
205 sprintf (p
, "%scr%d", comma
, OP
[i
]);
211 case OP_ACCUM_OUTPUT
:
212 case OP_ACCUM_REVERSE
:
213 sprintf (p
, "%sa%d", comma
, OP
[i
]);
219 sprintf (p
, "%s%d", comma
, OP
[i
]);
225 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
231 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
237 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
243 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
249 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
255 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
261 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
269 sprintf (p
, "%sf0", comma
);
272 sprintf (p
, "%sf1", comma
);
275 sprintf (p
, "%sc", comma
);
283 if ((d10v_debug
& DEBUG_VALUES
) == 0)
287 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%s", buf
);
292 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%-*s", SIZE_OPERANDS
, buf
);
295 for (i
= 0; i
< 3; i
++)
301 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "");
307 case OP_ACCUM_OUTPUT
:
309 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "---");
317 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
318 (uint16
)State
.regs
[OP
[i
]]);
322 tmp
= (long)((((uint32
) State
.regs
[OP
[i
]]) << 16) | ((uint32
) State
.regs
[OP
[i
]+1]));
323 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
328 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
329 (uint16
)State
.cregs
[OP
[i
]]);
333 case OP_ACCUM_REVERSE
:
334 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
335 ((int)(State
.a
[OP
[i
]] >> 32) & 0xff),
336 ((unsigned long)State
.a
[OP
[i
]]) & 0xffffffff);
340 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
345 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
346 (uint16
)SEXT4(OP
[i
]));
350 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
351 (uint16
)SEXT3(OP
[i
]));
356 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF0 = %d", SIZE_VALUES
-6, "",
360 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF1 = %d", SIZE_VALUES
-6, "",
364 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sC = %d", SIZE_VALUES
-5, "",
370 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
372 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
373 (uint16
)State
.regs
[OP
[++i
]]);
381 trace_output_func (result
)
382 enum op_types result
;
384 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
396 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
397 (uint16
)State
.regs
[OP
[0]],
398 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
403 tmp
= (long)((((uint32
) State
.regs
[OP
[0]]) << 16) | ((uint32
) State
.regs
[OP
[0]+1]));
404 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "", tmp
,
405 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
410 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
411 (uint16
)State
.cregs
[OP
[0]],
412 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
416 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
417 (uint16
)State
.cregs
[OP
[1]],
418 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
422 case OP_ACCUM_OUTPUT
:
423 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
424 ((int)(State
.a
[OP
[0]] >> 32) & 0xff),
425 ((unsigned long)State
.a
[OP
[0]]) & 0xffffffff,
426 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
429 case OP_ACCUM_REVERSE
:
430 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
431 ((int)(State
.a
[OP
[1]] >> 32) & 0xff),
432 ((unsigned long)State
.a
[OP
[1]]) & 0xffffffff,
433 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
438 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES
, "",
439 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
446 #define trace_input(NAME, IN1, IN2, IN3)
447 #define trace_output(RESULT)
454 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
456 if ((int16
)(State
.regs
[OP
[0]]) < 0)
458 State
.regs
[OP
[0]] = -(int16
)(State
.regs
[OP
[0]]);
463 trace_output (OP_REG
);
472 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
474 State
.a
[OP
[0]] = SEXT40(State
.a
[OP
[0]]);
476 if (State
.a
[OP
[0]] < 0 )
478 tmp
= -State
.a
[OP
[0]];
482 State
.a
[OP
[0]] = MAX32
;
483 else if (tmp
< MIN32
)
484 State
.a
[OP
[0]] = MIN32
;
486 State
.a
[OP
[0]] = tmp
& MASK40
;
489 State
.a
[OP
[0]] = tmp
& MASK40
;
494 trace_output (OP_ACCUM
);
501 uint16 tmp
= State
.regs
[OP
[0]];
502 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
503 State
.regs
[OP
[0]] += State
.regs
[OP
[1]];
504 if ( tmp
> State
.regs
[OP
[0]])
508 trace_output (OP_REG
);
516 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
518 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
522 State
.a
[OP
[0]] = MAX32
;
523 else if ( tmp
< MIN32
)
524 State
.a
[OP
[0]] = MIN32
;
526 State
.a
[OP
[0]] = tmp
& MASK40
;
529 State
.a
[OP
[0]] = tmp
& MASK40
;
530 trace_output (OP_ACCUM
);
538 tmp
= SEXT40(State
.a
[OP
[0]]) + SEXT40(State
.a
[OP
[1]]);
540 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
544 State
.a
[OP
[0]] = MAX32
;
545 else if ( tmp
< MIN32
)
546 State
.a
[OP
[0]] = MIN32
;
548 State
.a
[OP
[0]] = tmp
& MASK40
;
551 State
.a
[OP
[0]] = tmp
& MASK40
;
552 trace_output (OP_ACCUM
);
560 uint32 tmp1
= (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1];
561 uint32 tmp2
= (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
563 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
565 if ( (tmp
< tmp1
) || (tmp
< tmp2
) )
569 State
.regs
[OP
[0]] = tmp
>> 16;
570 State
.regs
[OP
[0]+1] = tmp
& 0xFFFF;
571 trace_output (OP_DREG
);
578 uint16 tmp
= State
.regs
[OP
[0]];
579 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] + OP
[2];
581 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
582 if ( tmp
> State
.regs
[OP
[0]])
586 trace_output (OP_REG
);
594 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
596 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
597 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
598 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
599 trace_output (OP_DREG
);
607 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
609 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
610 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
611 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
612 trace_output (OP_DREG
);
622 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
623 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
626 State
.regs
[OP
[0]] = 0x7fff;
627 State
.regs
[OP
[0]+1] = 0xffff;
630 else if (tmp
< MIN32
)
632 State
.regs
[OP
[0]] = 0x8000;
633 State
.regs
[OP
[0]+1] = 0;
638 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
639 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
642 trace_output (OP_DREG
);
652 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
653 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
656 State
.regs
[OP
[0]] = 0x7fff;
657 State
.regs
[OP
[0]+1] = 0xffff;
660 else if (tmp
< MIN32
)
662 State
.regs
[OP
[0]] = 0x8000;
663 State
.regs
[OP
[0]+1] = 0;
668 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
669 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
672 trace_output (OP_DREG
);
679 uint tmp
= State
.regs
[OP
[0]];
682 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
683 State
.regs
[OP
[0]] += OP
[1];
684 if (tmp
> State
.regs
[OP
[0]])
688 trace_output (OP_REG
);
695 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
696 State
.regs
[OP
[0]] &= State
.regs
[OP
[1]];
697 trace_output (OP_REG
);
704 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
705 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & OP
[2];
706 trace_output (OP_REG
);
713 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
714 State
.regs
[OP
[0]] &= ~(0x8000 >> OP
[1]);
715 trace_output (OP_REG
);
722 trace_input ("bl.s", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
723 State
.regs
[13] = PC
+1;
725 trace_output (OP_VOID
);
732 trace_input ("bl.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
733 State
.regs
[13] = PC
+1;
735 trace_output (OP_VOID
);
742 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
743 State
.regs
[OP
[0]] ^= 0x8000 >> OP
[1];
744 trace_output (OP_REG
);
751 trace_input ("bra.s", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
753 trace_output (OP_VOID
);
760 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
762 trace_output (OP_VOID
);
769 trace_input ("brf0f.s", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
772 trace_output (OP_FLAG
);
779 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
782 trace_output (OP_FLAG
);
789 trace_input ("brf0t.s", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
792 trace_output (OP_FLAG
);
799 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
802 trace_output (OP_FLAG
);
809 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
810 State
.regs
[OP
[0]] |= 0x8000 >> OP
[1];
811 trace_output (OP_REG
);
818 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
820 State
.F0
= (State
.regs
[OP
[0]] & (0x8000 >> OP
[1])) ? 1 : 0;
821 trace_output (OP_FLAG
);
828 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
830 trace_output (OP_ACCUM
);
837 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
839 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(State
.regs
[OP
[1]])) ? 1 : 0;
840 trace_output (OP_FLAG
);
847 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
849 State
.F0
= (SEXT40(State
.a
[OP
[0]]) < SEXT40(State
.a
[OP
[1]])) ? 1 : 0;
850 trace_output (OP_FLAG
);
857 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
859 State
.F0
= (State
.regs
[OP
[0]] == State
.regs
[OP
[1]]) ? 1 : 0;
860 trace_output (OP_FLAG
);
867 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
869 State
.F0
= (State
.a
[OP
[0]] == State
.a
[OP
[1]]) ? 1 : 0;
870 trace_output (OP_FLAG
);
877 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT16
, OP_VOID
);
879 State
.F0
= (State
.regs
[OP
[0]] == SEXT4(OP
[1])) ? 1 : 0;
880 trace_output (OP_FLAG
);
887 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
889 State
.F0
= (State
.regs
[OP
[0]] == OP
[1]) ? 1 : 0;
890 trace_output (OP_FLAG
);
897 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
899 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < SEXT4(OP
[1])) ? 1 : 0;
900 trace_output (OP_FLAG
);
907 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
909 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(OP
[1])) ? 1 : 0;
910 trace_output (OP_FLAG
);
917 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
919 State
.F0
= (State
.regs
[OP
[0]] < State
.regs
[OP
[1]]) ? 1 : 0;
920 trace_output (OP_FLAG
);
927 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
929 State
.F0
= (State
.regs
[OP
[0]] < OP
[1]) ? 1 : 0;
930 trace_output (OP_FLAG
);
939 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
953 trace_output (OP_FLAG
);
960 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
961 State
.exception
= SIGTRAP
;
968 uint16 foo
, tmp
, tmpf
;
970 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
971 foo
= (State
.regs
[OP
[0]] << 1) | (State
.regs
[OP
[0]+1] >> 15);
972 tmp
= (int16
)foo
- (int16
)(State
.regs
[OP
[1]]);
973 tmpf
= (foo
>= State
.regs
[OP
[1]]) ? 1 : 0;
974 State
.regs
[OP
[0]] = (tmpf
== 1) ? tmp
: foo
;
975 State
.regs
[OP
[0]+1] = (State
.regs
[OP
[0]+1] << 1) | tmpf
;
976 trace_output (OP_DREG
);
983 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
984 State
.exe
= (State
.F0
== 0);
985 trace_output (OP_FLAG
);
992 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
993 State
.exe
= (State
.F0
!= 0);
994 trace_output (OP_FLAG
);
1001 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
1002 State
.exe
= (State
.F1
== 0);
1003 trace_output (OP_FLAG
);
1010 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
1011 State
.exe
= (State
.F1
!= 0);
1012 trace_output (OP_FLAG
);
1019 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
1020 State
.exe
= (State
.F0
== 0) & (State
.F1
== 0);
1021 trace_output (OP_FLAG
);
1028 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
1029 State
.exe
= (State
.F0
== 0) & (State
.F1
!= 0);
1030 trace_output (OP_FLAG
);
1037 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
1038 State
.exe
= (State
.F0
!= 0) & (State
.F1
== 0);
1039 trace_output (OP_FLAG
);
1046 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
1047 State
.exe
= (State
.F0
!= 0) & (State
.F1
!= 0);
1048 trace_output (OP_FLAG
);
1058 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1059 if (((int16
)State
.regs
[OP
[1]]) >= 0)
1060 tmp
= (State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1];
1062 tmp
= ~((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
1069 State
.regs
[OP
[0]] = i
-1;
1070 trace_output (OP_REG
);
1075 State
.regs
[OP
[0]] = 16;
1076 trace_output (OP_REG
);
1086 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1087 if (SEXT40(State
.a
[OP
[1]]) >= 0)
1088 tmp
= State
.a
[OP
[1]];
1090 tmp
= ~(State
.a
[OP
[1]]);
1092 foo
= 0x4000000000LL
;
1097 State
.regs
[OP
[0]] = i
-9;
1098 trace_output (OP_REG
);
1103 State
.regs
[OP
[0]] = 16;
1104 trace_output (OP_REG
);
1111 trace_input ("jl", OP_REG
, OP_VOID
, OP_VOID
);
1112 State
.regs
[13] = PC
+1;
1113 PC
= State
.regs
[OP
[0]];
1114 trace_output (OP_VOID
);
1121 trace_input ("jmp", OP_REG
, OP_VOID
, OP_VOID
);
1122 PC
= State
.regs
[OP
[0]];
1123 trace_output (OP_VOID
);
1130 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1131 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1132 trace_output (OP_REG
);
1139 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1140 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1141 INC_ADDR(State
.regs
[OP
[1]],-2);
1142 trace_output (OP_REG
);
1149 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1150 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1151 INC_ADDR(State
.regs
[OP
[1]],2);
1152 trace_output (OP_REG
);
1159 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1160 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1161 trace_output (OP_REG
);
1168 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1169 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1170 State
.regs
[OP
[0]+1] = RW (OP
[1] + State
.regs
[OP
[2]] + 2);
1171 trace_output (OP_DREG
);
1178 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1179 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1180 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
1181 INC_ADDR(State
.regs
[OP
[1]],-4);
1182 trace_output (OP_DREG
);
1189 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1190 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1191 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
1192 INC_ADDR(State
.regs
[OP
[1]],4);
1193 trace_output (OP_REG
);
1200 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1201 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1202 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
1203 trace_output (OP_REG
);
1210 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1211 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1212 SEXT8 (State
.regs
[OP
[0]]);
1213 trace_output (OP_REG
);
1220 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1221 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1222 SEXT8 (State
.regs
[OP
[0]]);
1223 trace_output (OP_REG
);
1230 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1231 State
.regs
[OP
[0]] = SEXT4(OP
[1]);
1232 trace_output (OP_REG
);
1239 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1240 State
.regs
[OP
[0]] = OP
[1];
1241 trace_output (OP_REG
);
1248 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1249 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1250 trace_output (OP_REG
);
1257 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1258 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1259 trace_output (OP_REG
);
1268 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1269 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1272 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1274 if (State
.ST
&& tmp
> MAX32
)
1277 tmp
+= SEXT40(State
.a
[OP
[0]]);
1281 State
.a
[OP
[0]] = MAX32
;
1282 else if (tmp
< MIN32
)
1283 State
.a
[OP
[0]] = MIN32
;
1285 State
.a
[OP
[0]] = tmp
& MASK40
;
1288 State
.a
[OP
[0]] = tmp
& MASK40
;
1289 trace_output (OP_ACCUM
);
1298 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1299 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1301 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1303 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1304 trace_output (OP_ACCUM
);
1313 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1314 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1316 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1317 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1318 trace_output (OP_ACCUM
);
1325 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1326 State
.F1
= State
.F0
;
1327 if ((int16
)State
.regs
[OP
[1]] > (int16
)State
.regs
[OP
[0]])
1329 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1334 trace_output (OP_REG
);
1343 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1344 State
.F1
= State
.F0
;
1345 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1346 if (tmp
> SEXT40(State
.a
[OP
[0]]))
1348 State
.a
[OP
[0]] = tmp
& MASK40
;
1353 trace_output (OP_ACCUM
);
1360 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1361 State
.F1
= State
.F0
;
1362 if (SEXT40(State
.a
[OP
[1]]) > SEXT40(State
.a
[OP
[0]]))
1364 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1369 trace_output (OP_ACCUM
);
1377 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1378 State
.F1
= State
.F0
;
1379 if ((int16
)State
.regs
[OP
[1]] < (int16
)State
.regs
[OP
[0]])
1381 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1386 trace_output (OP_REG
);
1395 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1396 State
.F1
= State
.F0
;
1397 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1398 if (tmp
< SEXT40(State
.a
[OP
[0]]))
1400 State
.a
[OP
[0]] = tmp
& MASK40
;
1405 trace_output (OP_ACCUM
);
1412 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1413 State
.F1
= State
.F0
;
1414 if (SEXT40(State
.a
[OP
[1]]) < SEXT40(State
.a
[OP
[0]]))
1416 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1421 trace_output (OP_ACCUM
);
1430 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1431 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1434 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1436 if (State
.ST
&& tmp
> MAX32
)
1439 tmp
= SEXT40(State
.a
[OP
[0]]) - tmp
;
1443 State
.a
[OP
[0]] = MAX32
;
1444 else if (tmp
< MIN32
)
1445 State
.a
[OP
[0]] = MIN32
;
1447 State
.a
[OP
[0]] = tmp
& MASK40
;
1450 State
.a
[OP
[0]] = tmp
& MASK40
;
1451 trace_output (OP_ACCUM
);
1460 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1461 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1463 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1465 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1466 trace_output (OP_ACCUM
);
1475 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1476 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1478 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1480 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1481 trace_output (OP_ACCUM
);
1488 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1489 State
.regs
[OP
[0]] *= State
.regs
[OP
[1]];
1490 trace_output (OP_REG
);
1499 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1500 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1503 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1505 if (State
.ST
&& tmp
> MAX32
)
1506 State
.a
[OP
[0]] = MAX32
;
1508 State
.a
[OP
[0]] = tmp
& MASK40
;
1509 trace_output (OP_ACCUM
);
1518 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1519 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * State
.regs
[OP
[2]]);
1524 State
.a
[OP
[0]] = tmp
& MASK40
;
1525 trace_output (OP_ACCUM
);
1534 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1535 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1540 State
.a
[OP
[0]] = tmp
& MASK40
;
1541 trace_output (OP_ACCUM
);
1548 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1549 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1550 trace_output (OP_REG
);
1557 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1558 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1559 State
.regs
[OP
[0]+1] = State
.regs
[OP
[1]+1];
1560 trace_output (OP_DREG
);
1567 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1568 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1569 State
.regs
[OP
[0]+1] = State
.a
[OP
[1]] & 0xffff;
1570 trace_output (OP_DREG
);
1577 trace_input ("mv2wtac", OP_ACCUM_OUTPUT
, OP_DREG
, OP_VOID
);
1578 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1]) & MASK40
;
1579 trace_output (OP_ACCUM
);
1586 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1587 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1588 trace_output (OP_ACCUM
);
1595 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1596 State
.regs
[OP
[0]] = SEXT8 (State
.regs
[OP
[1]] & 0xff);
1597 trace_output (OP_REG
);
1604 trace_input ("mf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1606 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1607 trace_output (OP_REG
);
1614 trace_input ("mf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1616 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1617 trace_output (OP_REG
);
1624 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1625 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 32) & 0xff;
1626 trace_output (OP_ACCUM
);
1633 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1634 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1635 trace_output (OP_REG
);
1642 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1643 State
.regs
[OP
[0]] = State
.a
[OP
[1]] & 0xffff;
1644 trace_output (OP_REG
);
1651 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
1654 /* PSW is treated specially */
1656 if (State
.SM
) PSW
|= 0x8000;
1657 if (State
.EA
) PSW
|= 0x2000;
1658 if (State
.DB
) PSW
|= 0x1000;
1659 if (State
.IE
) PSW
|= 0x400;
1660 if (State
.RP
) PSW
|= 0x200;
1661 if (State
.MD
) PSW
|= 0x100;
1662 if (State
.FX
) PSW
|= 0x80;
1663 if (State
.ST
) PSW
|= 0x40;
1664 if (State
.F0
) PSW
|= 8;
1665 if (State
.F1
) PSW
|= 4;
1666 if (State
.C
) PSW
|= 1;
1668 State
.regs
[OP
[0]] = State
.cregs
[OP
[1]];
1669 trace_output (OP_REG
);
1676 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
1677 State
.a
[OP
[1]] &= MASK32
;
1678 State
.a
[OP
[1]] |= (int64
)(State
.regs
[OP
[0]] & 0xff) << 32;
1679 trace_output (OP_ACCUM_REVERSE
);
1688 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
1689 tmp
= State
.a
[OP
[1]] & 0xffff;
1690 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | tmp
) & MASK40
;
1691 trace_output (OP_ACCUM_REVERSE
);
1698 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
1699 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]])) & MASK40
;
1700 trace_output (OP_ACCUM_REVERSE
);
1707 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
1708 State
.cregs
[OP
[1]] = State
.regs
[OP
[0]];
1711 /* PSW is treated specially */
1712 State
.SM
= (PSW
& 0x8000) ? 1 : 0;
1713 State
.EA
= (PSW
& 0x2000) ? 1 : 0;
1714 State
.DB
= (PSW
& 0x1000) ? 1 : 0;
1715 State
.IE
= (PSW
& 0x400) ? 1 : 0;
1716 State
.RP
= (PSW
& 0x200) ? 1 : 0;
1717 State
.MD
= (PSW
& 0x100) ? 1 : 0;
1718 State
.FX
= (PSW
& 0x80) ? 1 : 0;
1719 State
.ST
= (PSW
& 0x40) ? 1 : 0;
1720 State
.F0
= (PSW
& 8) ? 1 : 0;
1721 State
.F1
= (PSW
& 4) ? 1 : 0;
1723 if (State
.ST
&& !State
.FX
)
1725 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1726 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1728 State
.exception
= SIGILL
;
1731 trace_output (OP_CR_REVERSE
);
1738 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1739 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & 0xff;
1740 trace_output (OP_REG
);
1747 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
1748 State
.regs
[OP
[0]] = 0 - State
.regs
[OP
[0]];
1749 trace_output (OP_REG
);
1758 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
1759 tmp
= -SEXT40(State
.a
[OP
[0]]);
1763 State
.a
[OP
[0]] = MAX32
;
1764 else if (tmp
< MIN32
)
1765 State
.a
[OP
[0]] = MIN32
;
1767 State
.a
[OP
[0]] = tmp
& MASK40
;
1770 State
.a
[OP
[0]] = tmp
& MASK40
;
1771 trace_output (OP_ACCUM
);
1779 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
1780 trace_output (OP_VOID
);
1782 if (State
.ins_type
== INS_LEFT
|| State
.ins_type
== INS_LEFT_PARALLEL
)
1792 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
1793 State
.regs
[OP
[0]] = ~(State
.regs
[OP
[0]]);
1794 trace_output (OP_REG
);
1801 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
1802 State
.regs
[OP
[0]] |= State
.regs
[OP
[1]];
1803 trace_output (OP_REG
);
1810 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
1811 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] | OP
[2];
1812 trace_output (OP_REG
);
1820 int shift
= SEXT3 (OP
[2]);
1822 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1825 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1826 "ERROR at PC 0x%x: instruction only valid for A0\n",
1828 State
.exception
= SIGILL
;
1831 State
.F1
= State
.F0
;
1833 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) << shift
;
1835 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) >> -shift
;
1836 tmp
= ( SEXT60(tmp
) + 0x8000 ) >> 16;
1839 State
.regs
[OP
[0]] = 0x7fff;
1840 State
.regs
[OP
[0]+1] = 0xffff;
1843 else if (tmp
< MIN32
)
1845 State
.regs
[OP
[0]] = 0x8000;
1846 State
.regs
[OP
[0]+1] = 0;
1851 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1852 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
1855 trace_output (OP_DREG
);
1863 int shift
= SEXT3 (OP
[2]);
1865 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1866 State
.F1
= State
.F0
;
1868 tmp
= SEXT44 (State
.a
[1]) << shift
;
1870 tmp
= SEXT44 (State
.a
[1]) >> -shift
;
1875 State
.regs
[OP
[0]] = 0x7fff;
1878 else if (tmp
< 0xfff80000000LL
)
1880 State
.regs
[OP
[0]] = 0x8000;
1885 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1888 trace_output (OP_REG
);
1895 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1898 RPT_C
= State
.regs
[OP
[0]];
1902 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep with count=0 is illegal.\n");
1903 State
.exception
= SIGILL
;
1907 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep must include at least 4 instructions.\n");
1908 State
.exception
= SIGILL
;
1910 trace_output (OP_VOID
);
1917 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
1924 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi with count=0 is illegal.\n");
1925 State
.exception
= SIGILL
;
1929 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi must include at least 4 instructions.\n");
1930 State
.exception
= SIGILL
;
1932 trace_output (OP_VOID
);
1939 d10v_callback
->printf_filtered(d10v_callback
, "ERROR: rtd - NOT IMPLEMENTED\n");
1940 State
.exception
= SIGILL
;
1947 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
1950 trace_output (OP_VOID
);
1959 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1960 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT40(State
.a
[OP
[1]]) >> 16);
1964 State
.a
[OP
[0]] = MAX32
;
1965 else if (tmp
< MIN32
)
1966 State
.a
[OP
[0]] = MIN32
;
1968 State
.a
[OP
[0]] = tmp
& MASK40
;
1971 State
.a
[OP
[0]] = tmp
& MASK40
;
1972 trace_output (OP_ACCUM
);
1979 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
1980 State
.regs
[OP
[0]] = (State
.F0
== 0) ? 1 : 0;
1981 trace_output (OP_REG
);
1988 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
1989 State
.regs
[OP
[0]] = (State
.F0
== 1) ? 1 : 0;
1990 trace_output (OP_REG
);
1997 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
1999 trace_output (OP_VOID
);
2006 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
2007 State
.regs
[OP
[0]] <<= (State
.regs
[OP
[1]] & 0xf);
2008 trace_output (OP_REG
);
2016 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
2017 if ((State
.regs
[OP
[1]] & 31) <= 16)
2018 tmp
= SEXT40 (State
.a
[OP
[0]]) << (State
.regs
[OP
[1]] & 31);
2021 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2022 State
.exception
= SIGILL
;
2029 State
.a
[OP
[0]] = MAX32
;
2030 else if (tmp
< 0xffffff80000000LL
)
2031 State
.a
[OP
[0]] = MIN32
;
2033 State
.a
[OP
[0]] = tmp
& MASK40
;
2036 State
.a
[OP
[0]] = tmp
& MASK40
;
2037 trace_output (OP_ACCUM
);
2044 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2045 State
.regs
[OP
[0]] <<= OP
[1];
2046 trace_output (OP_REG
);
2058 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2059 tmp
= SEXT40(State
.a
[OP
[0]]) << OP
[1];
2064 State
.a
[OP
[0]] = MAX32
;
2065 else if (tmp
< 0xffffff80000000LL
)
2066 State
.a
[OP
[0]] = MIN32
;
2068 State
.a
[OP
[0]] = tmp
& MASK40
;
2071 State
.a
[OP
[0]] = tmp
& MASK40
;
2072 trace_output (OP_ACCUM
);
2081 trace_input ("slx", OP_REG
, OP_FLAG
, OP_VOID
);
2082 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] << 1) | State
.F0
;
2083 trace_output (OP_REG
);
2090 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
2091 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> (State
.regs
[OP
[1]] & 0xf);
2092 trace_output (OP_REG
);
2099 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2100 if ((State
.regs
[OP
[1]] & 31) <= 16)
2101 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
2104 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2105 State
.exception
= SIGILL
;
2109 trace_output (OP_ACCUM
);
2116 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2117 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> OP
[1];
2118 trace_output (OP_REG
);
2128 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2129 State
.a
[OP
[0]] >>= OP
[1];
2130 trace_output (OP_ACCUM
);
2137 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2138 State
.regs
[OP
[0]] >>= (State
.regs
[OP
[1]] & 0xf);
2139 trace_output (OP_REG
);
2146 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2147 if ((State
.regs
[OP
[1]] & 31) <= 16)
2148 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
2151 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2152 State
.exception
= SIGILL
;
2156 trace_output (OP_ACCUM
);
2163 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2164 State
.regs
[OP
[0]] >>= OP
[1];
2165 trace_output (OP_REG
);
2175 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2176 State
.a
[OP
[0]] >>= OP
[1];
2177 trace_output (OP_ACCUM
);
2186 trace_input ("srx", OP_REG
, OP_FLAG
, OP_VOID
);
2187 tmp
= State
.F0
<< 15;
2188 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] >> 1) | tmp
;
2189 trace_output (OP_REG
);
2196 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2197 SW (OP
[1] + State
.regs
[OP
[2]], State
.regs
[OP
[0]]);
2198 trace_output (OP_VOID
);
2205 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2206 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2207 trace_output (OP_VOID
);
2214 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2217 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2218 State
.exception
= SIGILL
;
2221 State
.regs
[OP
[1]] -= 2;
2222 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2223 trace_output (OP_VOID
);
2230 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2231 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2232 INC_ADDR (State
.regs
[OP
[1]],2);
2233 trace_output (OP_VOID
);
2240 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2241 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2242 INC_ADDR (State
.regs
[OP
[1]],-2);
2243 trace_output (OP_VOID
);
2250 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2251 SW (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2252 SW (State
.regs
[OP
[2]]+OP
[1]+2, State
.regs
[OP
[0]+1]);
2253 trace_output (OP_VOID
);
2260 trace_input ("st2w", OP_REG
, OP_MEMREF
, OP_VOID
);
2261 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2262 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2263 trace_output (OP_VOID
);
2270 trace_input ("st2w", OP_REG
, OP_PREDEC
, OP_VOID
);
2273 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2274 State
.exception
= SIGILL
;
2277 State
.regs
[OP
[1]] -= 4;
2278 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2279 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2280 trace_output (OP_VOID
);
2287 trace_input ("st2w", OP_REG
, OP_POSTDEC
, OP_VOID
);
2288 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2289 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2290 INC_ADDR (State
.regs
[OP
[1]],4);
2291 trace_output (OP_VOID
);
2298 trace_input ("st2w", OP_REG
, OP_POSTINC
, OP_VOID
);
2299 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2300 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2301 INC_ADDR (State
.regs
[OP
[1]],-4);
2302 trace_output (OP_VOID
);
2309 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2310 SB (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2311 trace_output (OP_VOID
);
2318 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2319 SB (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2320 trace_output (OP_VOID
);
2327 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2328 State
.exception
= SIG_D10V_STOP
;
2329 trace_output (OP_VOID
);
2338 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
2339 tmp
= (int16
)State
.regs
[OP
[0]]- (int16
)State
.regs
[OP
[1]];
2340 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2341 State
.regs
[OP
[0]] = tmp
& 0xffff;
2342 trace_output (OP_REG
);
2351 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
2352 tmp
= SEXT40(State
.a
[OP
[0]]) - (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
2356 State
.a
[OP
[0]] = MAX32
;
2357 else if ( tmp
< MIN32
)
2358 State
.a
[OP
[0]] = MIN32
;
2360 State
.a
[OP
[0]] = tmp
& MASK40
;
2363 State
.a
[OP
[0]] = tmp
& MASK40
;
2365 trace_output (OP_ACCUM
);
2375 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2376 tmp
= SEXT40(State
.a
[OP
[0]]) - SEXT40(State
.a
[OP
[1]]);
2380 State
.a
[OP
[0]] = MAX32
;
2381 else if ( tmp
< MIN32
)
2382 State
.a
[OP
[0]] = MIN32
;
2384 State
.a
[OP
[0]] = tmp
& MASK40
;
2387 State
.a
[OP
[0]] = tmp
& MASK40
;
2389 trace_output (OP_ACCUM
);
2399 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
2400 a
= (int32
)((State
.regs
[OP
[0]] << 16) | State
.regs
[OP
[0]+1]);
2401 b
= (int32
)((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
2403 State
.C
= (tmp
& 0xffffffff00000000LL
) ? 1 : 0;
2404 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2405 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2406 trace_output (OP_DREG
);
2415 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2416 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40 (State
.a
[OP
[2]]);
2417 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2418 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2419 trace_output (OP_DREG
);
2428 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2429 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2430 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2431 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2432 trace_output (OP_DREG
);
2441 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2442 State
.F1
= State
.F0
;
2443 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40(State
.a
[OP
[2]]);
2446 State
.regs
[OP
[0]] = 0x7fff;
2447 State
.regs
[OP
[0]+1] = 0xffff;
2450 else if (tmp
< MIN32
)
2452 State
.regs
[OP
[0]] = 0x8000;
2453 State
.regs
[OP
[0]+1] = 0;
2458 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2459 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2462 trace_output (OP_DREG
);
2471 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2472 State
.F1
= State
.F0
;
2473 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2476 State
.regs
[OP
[0]] = 0x7fff;
2477 State
.regs
[OP
[0]+1] = 0xffff;
2480 else if (tmp
< MIN32
)
2482 State
.regs
[OP
[0]] = 0x8000;
2483 State
.regs
[OP
[0]+1] = 0;
2488 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2489 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2492 trace_output (OP_DREG
);
2503 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2504 tmp
= (int16
)State
.regs
[OP
[0]] - OP
[1];
2505 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2506 State
.regs
[OP
[0]] = tmp
& 0xffff;
2507 trace_output (OP_REG
);
2514 trace_input ("trap", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
2515 trace_output (OP_VOID
);
2521 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown trap code %d\n", OP
[0]);
2522 State
.exception
= SIGILL
;
2524 /* Use any other traps for batch debugging. */
2527 static int first_time
= 1;
2532 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap # PC ");
2533 for (i
= 0; i
< 16; i
++)
2534 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %sr%d", (i
> 9) ? "" : " ", i
);
2535 (*d10v_callback
->printf_filtered
) (d10v_callback
, " a0 a1 f0 f1 c\n");
2538 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
2540 for (i
= 0; i
< 16; i
++)
2541 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.4x", (int) State
.regs
[i
]);
2543 for (i
= 0; i
< 2; i
++)
2544 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.2x%.8lx",
2545 ((int)(State
.a
[OP
[i
]] >> 32) & 0xff),
2546 ((unsigned long)State
.a
[OP
[i
]]) & 0xffffffff);
2548 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %d %d %d\n",
2549 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
2554 /* Trap 0 is used for simulating low-level I/O */
2556 int save_errno
= errno
;
2559 /* Registers passed to trap 0 */
2561 #define FUNC State.regs[6] /* function number */
2562 #define PARM1 State.regs[2] /* optional parm 1 */
2563 #define PARM2 State.regs[3] /* optional parm 2 */
2564 #define PARM3 State.regs[4] /* optional parm 3 */
2565 #define PARM4 State.regs[5] /* optional parm 3 */
2567 /* Registers set by trap 0 */
2569 #define RETVAL State.regs[2] /* return value */
2570 #define RETVAL_HIGH State.regs[2] /* return value */
2571 #define RETVAL_LOW State.regs[3] /* return value */
2572 #define RETERR State.regs[4] /* return error code */
2574 /* Turn a pointer in a register into a pointer into real memory. */
2576 #define MEMPTR(x) ((char *)((x) + State.imem))
2580 #if !defined(__GO32__) && !defined(_WIN32)
2585 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2586 (char **)MEMPTR (PARM3
));
2589 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2597 RETVAL
= pipe (host_fd
);
2598 SW (buf
, host_fd
[0]);
2599 buf
+= sizeof(uint16
);
2600 SW (buf
, host_fd
[1]);
2607 RETVAL
= wait (&status
);
2613 RETVAL
= d10v_callback
->read (d10v_callback
, PARM1
, MEMPTR (PARM2
),
2618 RETVAL
= (int)d10v_callback
->write_stdout (d10v_callback
,
2619 MEMPTR (PARM2
), PARM3
);
2621 RETVAL
= (int)d10v_callback
->write (d10v_callback
, PARM1
,
2622 MEMPTR (PARM2
), PARM3
);
2626 unsigned long ret
= d10v_callback
->lseek (d10v_callback
, PARM1
,
2627 (((unsigned long)PARM2
) << 16) || (unsigned long)PARM3
,
2629 RETVAL_HIGH
= ret
>> 16;
2630 RETVAL_LOW
= ret
& 0xffff;
2634 RETVAL
= d10v_callback
->close (d10v_callback
, PARM1
);
2637 RETVAL
= d10v_callback
->open (d10v_callback
, MEMPTR (PARM1
), PARM2
);
2640 State
.exception
= SIG_D10V_EXIT
;
2644 /* stat system call */
2646 struct stat host_stat
;
2649 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2653 /* The hard-coded offsets and sizes were determined by using
2654 * the D10V compiler on a test program that used struct stat.
2656 SW (buf
, host_stat
.st_dev
);
2657 SW (buf
+2, host_stat
.st_ino
);
2658 SW (buf
+4, host_stat
.st_mode
);
2659 SW (buf
+6, host_stat
.st_nlink
);
2660 SW (buf
+8, host_stat
.st_uid
);
2661 SW (buf
+10, host_stat
.st_gid
);
2662 SW (buf
+12, host_stat
.st_rdev
);
2663 SLW (buf
+16, host_stat
.st_size
);
2664 SLW (buf
+20, host_stat
.st_atime
);
2665 SLW (buf
+28, host_stat
.st_mtime
);
2666 SLW (buf
+36, host_stat
.st_ctime
);
2671 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2674 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2677 /* Cast the second argument to void *, to avoid type mismatch
2678 if a prototype is present. */
2679 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2684 RETERR
= d10v_callback
->get_errno(d10v_callback
);
2689 /* Trap 1 prints a string */
2691 char *fstr
= State
.regs
[2] + State
.imem
;
2692 fputs (fstr
, stdout
);
2697 /* Trap 2 calls printf */
2699 char *fstr
= State
.regs
[2] + State
.imem
;
2700 (*d10v_callback
->printf_filtered
) (d10v_callback
, fstr
,
2701 (int16
)State
.regs
[3],
2702 (int16
)State
.regs
[4],
2703 (int16
)State
.regs
[5]);
2708 /* Trap 3 writes a character */
2709 putchar (State
.regs
[2]);
2719 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2720 State
.F1
= State
.F0
;
2721 State
.F0
= (State
.regs
[OP
[0]] & OP
[1]) ? 1 : 0;
2722 trace_output (OP_FLAG
);
2729 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2730 State
.F1
= State
.F0
;
2731 State
.F0
= (~(State
.regs
[OP
[0]]) & OP
[1]) ? 1 : 0;
2732 trace_output (OP_FLAG
);
2739 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
2741 trace_output (OP_VOID
);
2748 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
2749 State
.regs
[OP
[0]] ^= State
.regs
[OP
[1]];
2750 trace_output (OP_REG
);
2757 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
2758 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] ^ OP
[2];
2759 trace_output (OP_REG
);
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