ad77e05bb77cde3a018660f0be7c773bf1d0f70b
13 #include "sys/syscall.h"
15 extern char *strrchr ();
47 static void trace_input_func
PARAMS ((char *name
,
52 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
54 static void trace_output_func
PARAMS ((enum op_types result
));
56 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
58 #ifndef SIZE_INSTRUCTION
59 #define SIZE_INSTRUCTION 8
63 #define SIZE_OPERANDS 18
67 #define SIZE_VALUES 13
71 #define SIZE_LOCATION 20
78 #ifndef SIZE_LINE_NUMBER
79 #define SIZE_LINE_NUMBER 4
83 trace_input_func (name
, in1
, in2
, in3
)
97 const char *functionname
;
98 unsigned int linenumber
;
101 if ((d10v_debug
& DEBUG_TRACE
) == 0)
104 switch (State
.ins_type
)
107 case INS_UNKNOWN
: type
= " ?"; break;
108 case INS_LEFT
: type
= " L"; break;
109 case INS_RIGHT
: type
= " R"; break;
110 case INS_LEFT_PARALLEL
: type
= "*L"; break;
111 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
112 case INS_LEFT_COND_TEST
: type
= "?L"; break;
113 case INS_RIGHT_COND_TEST
: type
= "?R"; break;
114 case INS_LEFT_COND_EXE
: type
= "&L"; break;
115 case INS_RIGHT_COND_EXE
: type
= "&R"; break;
116 case INS_LONG
: type
= " B"; break;
119 if ((d10v_debug
& DEBUG_LINE_NUMBER
) == 0)
120 (*d10v_callback
->printf_filtered
) (d10v_callback
,
122 SIZE_PC
, (unsigned)PC
,
124 SIZE_INSTRUCTION
, name
);
129 byte_pc
= decode_pc ();
130 if (text
&& byte_pc
>= text_start
&& byte_pc
< text_end
)
132 filename
= (const char *)0;
133 functionname
= (const char *)0;
135 if (bfd_find_nearest_line (prog_bfd
, text
, (struct symbol_cache_entry
**)0, byte_pc
- text_start
,
136 &filename
, &functionname
, &linenumber
))
141 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
146 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
147 p
+= SIZE_LINE_NUMBER
+2;
152 sprintf (p
, "%s ", functionname
);
157 char *q
= strrchr (filename
, '/');
158 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
167 (*d10v_callback
->printf_filtered
) (d10v_callback
,
168 "0x%.*x %s: %-*.*s %-*s ",
169 SIZE_PC
, (unsigned)PC
,
171 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
172 SIZE_INSTRUCTION
, name
);
180 for (i
= 0; i
< 3; i
++)
195 sprintf (p
, "%sr%d", comma
, OP
[i
]);
203 sprintf (p
, "%scr%d", comma
, OP
[i
]);
209 case OP_ACCUM_OUTPUT
:
210 case OP_ACCUM_REVERSE
:
211 sprintf (p
, "%sa%d", comma
, OP
[i
]);
217 sprintf (p
, "%s%d", comma
, OP
[i
]);
223 sprintf (p
, "%s%d", comma
, SEXT8(OP
[i
]));
229 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
235 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
241 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
247 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
253 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
259 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
265 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
273 sprintf (p
, "%sf0", comma
);
276 sprintf (p
, "%sf1", comma
);
279 sprintf (p
, "%sc", comma
);
287 if ((d10v_debug
& DEBUG_VALUES
) == 0)
291 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%s", buf
);
296 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%-*s", SIZE_OPERANDS
, buf
);
299 for (i
= 0; i
< 3; i
++)
305 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "");
311 case OP_ACCUM_OUTPUT
:
313 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "---");
321 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
322 (uint16
)State
.regs
[OP
[i
]]);
326 tmp
= (long)((((uint32
) State
.regs
[OP
[i
]]) << 16) | ((uint32
) State
.regs
[OP
[i
]+1]));
327 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
332 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
333 (uint16
)State
.cregs
[OP
[i
]]);
337 case OP_ACCUM_REVERSE
:
338 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
339 ((int)(State
.a
[OP
[i
]] >> 32) & 0xff),
340 ((unsigned long)State
.a
[OP
[i
]]) & 0xffffffff);
344 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
349 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
350 (uint16
)SEXT4(OP
[i
]));
354 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
355 (uint16
)SEXT8(OP
[i
]));
359 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
360 (uint16
)SEXT3(OP
[i
]));
365 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF0 = %d", SIZE_VALUES
-6, "",
369 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF1 = %d", SIZE_VALUES
-6, "",
373 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sC = %d", SIZE_VALUES
-5, "",
379 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
381 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
382 (uint16
)State
.regs
[OP
[++i
]]);
386 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
387 (uint16
)State
.regs
[2]);
391 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
392 (uint16
)State
.regs
[3]);
396 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
397 (uint16
)State
.regs
[4]);
401 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
402 (uint16
)State
.regs
[2]);
403 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
404 (uint16
)State
.regs
[3]);
411 (*d10v_callback
->flush_stdout
) (d10v_callback
);
415 trace_output_func (result
)
416 enum op_types result
;
418 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
430 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
431 (uint16
)State
.regs
[OP
[0]],
432 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
437 tmp
= (long)((((uint32
) State
.regs
[OP
[0]]) << 16) | ((uint32
) State
.regs
[OP
[0]+1]));
438 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "", tmp
,
439 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
444 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
445 (uint16
)State
.cregs
[OP
[0]],
446 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
450 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
451 (uint16
)State
.cregs
[OP
[1]],
452 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
456 case OP_ACCUM_OUTPUT
:
457 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
458 ((int)(State
.a
[OP
[0]] >> 32) & 0xff),
459 ((unsigned long)State
.a
[OP
[0]]) & 0xffffffff,
460 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
463 case OP_ACCUM_REVERSE
:
464 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
465 ((int)(State
.a
[OP
[1]] >> 32) & 0xff),
466 ((unsigned long)State
.a
[OP
[1]]) & 0xffffffff,
467 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
472 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES
, "",
473 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
477 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
478 (uint16
)State
.regs
[2],
479 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
483 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "",
484 (uint16
)State
.regs
[2], (uint16
)State
.regs
[3],
485 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
490 (*d10v_callback
->flush_stdout
) (d10v_callback
);
494 #define trace_input(NAME, IN1, IN2, IN3)
495 #define trace_output(RESULT)
502 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
504 if ((int16
)(State
.regs
[OP
[0]]) < 0)
506 State
.regs
[OP
[0]] = -(int16
)(State
.regs
[OP
[0]]);
511 trace_output (OP_REG
);
520 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
522 State
.a
[OP
[0]] = SEXT40(State
.a
[OP
[0]]);
524 if (State
.a
[OP
[0]] < 0 )
526 tmp
= -State
.a
[OP
[0]];
530 State
.a
[OP
[0]] = MAX32
;
531 else if (tmp
< MIN32
)
532 State
.a
[OP
[0]] = MIN32
;
534 State
.a
[OP
[0]] = tmp
& MASK40
;
537 State
.a
[OP
[0]] = tmp
& MASK40
;
542 trace_output (OP_ACCUM
);
549 uint16 tmp
= State
.regs
[OP
[0]];
550 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
551 State
.regs
[OP
[0]] += State
.regs
[OP
[1]];
552 if ( tmp
> State
.regs
[OP
[0]])
556 trace_output (OP_REG
);
564 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
566 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
570 State
.a
[OP
[0]] = MAX32
;
571 else if ( tmp
< MIN32
)
572 State
.a
[OP
[0]] = MIN32
;
574 State
.a
[OP
[0]] = tmp
& MASK40
;
577 State
.a
[OP
[0]] = tmp
& MASK40
;
578 trace_output (OP_ACCUM
);
586 tmp
= SEXT40(State
.a
[OP
[0]]) + SEXT40(State
.a
[OP
[1]]);
588 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
592 State
.a
[OP
[0]] = MAX32
;
593 else if ( tmp
< MIN32
)
594 State
.a
[OP
[0]] = MIN32
;
596 State
.a
[OP
[0]] = tmp
& MASK40
;
599 State
.a
[OP
[0]] = tmp
& MASK40
;
600 trace_output (OP_ACCUM
);
608 uint32 a
= (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1];
609 uint32 b
= (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
611 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
614 State
.regs
[OP
[0]] = tmp
>> 16;
615 State
.regs
[OP
[0]+1] = tmp
& 0xFFFF;
616 trace_output (OP_DREG
);
623 uint16 tmp
= State
.regs
[OP
[1]];
624 State
.regs
[OP
[0]] = tmp
+ OP
[2];
626 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
627 State
.C
= (State
.regs
[OP
[0]] < tmp
);
628 trace_output (OP_REG
);
636 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
638 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
639 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
640 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
641 trace_output (OP_DREG
);
649 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
651 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
652 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
653 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
654 trace_output (OP_DREG
);
664 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
665 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
668 State
.regs
[OP
[0]] = 0x7fff;
669 State
.regs
[OP
[0]+1] = 0xffff;
672 else if (tmp
< MIN32
)
674 State
.regs
[OP
[0]] = 0x8000;
675 State
.regs
[OP
[0]+1] = 0;
680 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
681 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
684 trace_output (OP_DREG
);
694 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
695 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
698 State
.regs
[OP
[0]] = 0x7fff;
699 State
.regs
[OP
[0]+1] = 0xffff;
702 else if (tmp
< MIN32
)
704 State
.regs
[OP
[0]] = 0x8000;
705 State
.regs
[OP
[0]+1] = 0;
710 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
711 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
714 trace_output (OP_DREG
);
721 uint tmp
= State
.regs
[OP
[0]];
725 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
726 State
.regs
[OP
[0]] += OP
[1];
727 State
.C
= (State
.regs
[OP
[0]] < tmp
);
728 trace_output (OP_REG
);
735 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
736 State
.regs
[OP
[0]] &= State
.regs
[OP
[1]];
737 trace_output (OP_REG
);
744 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
745 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & OP
[2];
746 trace_output (OP_REG
);
753 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
754 State
.regs
[OP
[0]] &= ~(0x8000 >> OP
[1]);
755 trace_output (OP_REG
);
762 trace_input ("bl.s", OP_CONSTANT8
, OP_R2
, OP_R3
);
763 State
.regs
[13] = PC
+1;
764 JMP( PC
+ SEXT8 (OP
[0]));
765 trace_output (OP_VOID
);
772 trace_input ("bl.l", OP_CONSTANT16
, OP_R2
, OP_R3
);
773 State
.regs
[13] = PC
+1;
775 trace_output (OP_VOID
);
782 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
783 State
.regs
[OP
[0]] ^= 0x8000 >> OP
[1];
784 trace_output (OP_REG
);
791 trace_input ("bra.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
792 JMP (PC
+ SEXT8 (OP
[0]));
793 trace_output (OP_VOID
);
800 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
802 trace_output (OP_VOID
);
809 trace_input ("brf0f.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
811 JMP (PC
+ SEXT8 (OP
[0]));
812 trace_output (OP_FLAG
);
819 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
822 trace_output (OP_FLAG
);
829 trace_input ("brf0t.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
831 JMP (PC
+ SEXT8 (OP
[0]));
832 trace_output (OP_FLAG
);
839 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
842 trace_output (OP_FLAG
);
849 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
850 State
.regs
[OP
[0]] |= 0x8000 >> OP
[1];
851 trace_output (OP_REG
);
858 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
860 State
.F0
= (State
.regs
[OP
[0]] & (0x8000 >> OP
[1])) ? 1 : 0;
861 trace_output (OP_FLAG
);
868 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
870 trace_output (OP_ACCUM
);
877 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
879 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(State
.regs
[OP
[1]])) ? 1 : 0;
880 trace_output (OP_FLAG
);
887 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
889 State
.F0
= (SEXT40(State
.a
[OP
[0]]) < SEXT40(State
.a
[OP
[1]])) ? 1 : 0;
890 trace_output (OP_FLAG
);
897 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
899 State
.F0
= (State
.regs
[OP
[0]] == State
.regs
[OP
[1]]) ? 1 : 0;
900 trace_output (OP_FLAG
);
907 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
909 State
.F0
= ((State
.a
[OP
[0]] & MASK40
) == (State
.a
[OP
[1]] & MASK40
)) ? 1 : 0;
910 trace_output (OP_FLAG
);
917 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
919 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)SEXT4(OP
[1])) ? 1 : 0;
920 trace_output (OP_FLAG
);
927 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
929 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)OP
[1]) ? 1 : 0;
930 trace_output (OP_FLAG
);
937 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
939 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)SEXT4(OP
[1])) ? 1 : 0;
940 trace_output (OP_FLAG
);
947 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
949 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(OP
[1])) ? 1 : 0;
950 trace_output (OP_FLAG
);
957 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
959 State
.F0
= (State
.regs
[OP
[0]] < State
.regs
[OP
[1]]) ? 1 : 0;
960 trace_output (OP_FLAG
);
967 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
969 State
.F0
= (State
.regs
[OP
[0]] < (reg_t
)OP
[1]) ? 1 : 0;
970 trace_output (OP_FLAG
);
979 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
993 trace_output (OP_FLAG
);
1000 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1001 State
.exception
= SIGTRAP
;
1008 uint16 foo
, tmp
, tmpf
;
1010 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
1011 foo
= (State
.regs
[OP
[0]] << 1) | (State
.regs
[OP
[0]+1] >> 15);
1012 tmp
= (int16
)foo
- (int16
)(State
.regs
[OP
[1]]);
1013 tmpf
= (foo
>= State
.regs
[OP
[1]]) ? 1 : 0;
1014 State
.regs
[OP
[0]] = (tmpf
== 1) ? tmp
: foo
;
1015 State
.regs
[OP
[0]+1] = (State
.regs
[OP
[0]+1] << 1) | tmpf
;
1016 trace_output (OP_DREG
);
1023 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
1024 State
.exe
= (State
.F0
== 0);
1025 trace_output (OP_FLAG
);
1032 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
1033 State
.exe
= (State
.F0
!= 0);
1034 trace_output (OP_FLAG
);
1041 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
1042 State
.exe
= (State
.F1
== 0);
1043 trace_output (OP_FLAG
);
1050 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
1051 State
.exe
= (State
.F1
!= 0);
1052 trace_output (OP_FLAG
);
1059 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
1060 State
.exe
= (State
.F0
== 0) & (State
.F1
== 0);
1061 trace_output (OP_FLAG
);
1068 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
1069 State
.exe
= (State
.F0
== 0) & (State
.F1
!= 0);
1070 trace_output (OP_FLAG
);
1077 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
1078 State
.exe
= (State
.F0
!= 0) & (State
.F1
== 0);
1079 trace_output (OP_FLAG
);
1086 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
1087 State
.exe
= (State
.F0
!= 0) & (State
.F1
!= 0);
1088 trace_output (OP_FLAG
);
1098 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1099 if (((int16
)State
.regs
[OP
[1]]) >= 0)
1100 tmp
= (State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1];
1102 tmp
= ~((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
1109 State
.regs
[OP
[0]] = i
-1;
1110 trace_output (OP_REG
);
1115 State
.regs
[OP
[0]] = 16;
1116 trace_output (OP_REG
);
1126 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1127 tmp
= SEXT40(State
.a
[OP
[1]]);
1129 tmp
= ~tmp
& MASK40
;
1131 foo
= 0x4000000000LL
;
1136 State
.regs
[OP
[0]] = i
-9;
1137 trace_output (OP_REG
);
1142 State
.regs
[OP
[0]] = 16;
1143 trace_output (OP_REG
);
1150 trace_input ("jl", OP_REG
, OP_R2
, OP_R3
);
1151 State
.regs
[13] = PC
+1;
1152 JMP (State
.regs
[OP
[0]]);
1153 trace_output (OP_VOID
);
1160 trace_input ("jmp", OP_REG
,
1161 (OP
[0] == 13) ? OP_R2
: OP_VOID
,
1162 (OP
[0] == 13) ? OP_R3
: OP_VOID
);
1164 JMP (State
.regs
[OP
[0]]);
1165 trace_output (OP_VOID
);
1172 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1173 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1174 trace_output (OP_REG
);
1181 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1182 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1183 INC_ADDR(State
.regs
[OP
[1]],-2);
1184 trace_output (OP_REG
);
1191 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1192 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1193 INC_ADDR(State
.regs
[OP
[1]],2);
1194 trace_output (OP_REG
);
1201 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1202 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1203 trace_output (OP_REG
);
1210 uint16 addr
= State
.regs
[OP
[2]];
1211 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1212 State
.regs
[OP
[0]] = RW (OP
[1] + addr
);
1213 State
.regs
[OP
[0]+1] = RW (OP
[1] + addr
+ 2);
1214 trace_output (OP_DREG
);
1221 uint16 addr
= State
.regs
[OP
[1]];
1222 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1223 State
.regs
[OP
[0]] = RW (addr
);
1224 State
.regs
[OP
[0]+1] = RW (addr
+2);
1225 INC_ADDR(State
.regs
[OP
[1]],-4);
1226 trace_output (OP_DREG
);
1233 uint16 addr
= State
.regs
[OP
[1]];
1234 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1235 State
.regs
[OP
[0]] = RW (addr
);
1236 State
.regs
[OP
[0]+1] = RW (addr
+2);
1237 INC_ADDR(State
.regs
[OP
[1]],4);
1238 trace_output (OP_DREG
);
1245 uint16 addr
= State
.regs
[OP
[1]];
1246 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1247 State
.regs
[OP
[0]] = RW (addr
);
1248 State
.regs
[OP
[0]+1] = RW (addr
+2);
1249 trace_output (OP_DREG
);
1256 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1257 State
.regs
[OP
[0]] = SEXT8 (RB (OP
[1] + State
.regs
[OP
[2]]));
1258 trace_output (OP_REG
);
1265 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1266 State
.regs
[OP
[0]] = SEXT8 (RB (State
.regs
[OP
[1]]));
1267 trace_output (OP_REG
);
1274 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1275 State
.regs
[OP
[0]] = SEXT4(OP
[1]);
1276 trace_output (OP_REG
);
1283 trace_input ("ldi.l", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1284 State
.regs
[OP
[0]] = OP
[1];
1285 trace_output (OP_REG
);
1292 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1293 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1294 trace_output (OP_REG
);
1301 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1302 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1303 trace_output (OP_REG
);
1312 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1313 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1316 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1318 if (State
.ST
&& tmp
> MAX32
)
1321 tmp
+= SEXT40(State
.a
[OP
[0]]);
1325 State
.a
[OP
[0]] = MAX32
;
1326 else if (tmp
< MIN32
)
1327 State
.a
[OP
[0]] = MIN32
;
1329 State
.a
[OP
[0]] = tmp
& MASK40
;
1332 State
.a
[OP
[0]] = tmp
& MASK40
;
1333 trace_output (OP_ACCUM
);
1342 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1343 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1345 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1347 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1348 trace_output (OP_ACCUM
);
1357 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1358 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1360 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1361 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1362 trace_output (OP_ACCUM
);
1369 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1370 State
.F1
= State
.F0
;
1371 if ((int16
)State
.regs
[OP
[1]] > (int16
)State
.regs
[OP
[0]])
1373 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1378 trace_output (OP_REG
);
1387 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1388 State
.F1
= State
.F0
;
1389 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1390 if (tmp
> SEXT40(State
.a
[OP
[0]]))
1392 State
.a
[OP
[0]] = tmp
& MASK40
;
1397 trace_output (OP_ACCUM
);
1404 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1405 State
.F1
= State
.F0
;
1406 if (SEXT40(State
.a
[OP
[1]]) > SEXT40(State
.a
[OP
[0]]))
1408 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1413 trace_output (OP_ACCUM
);
1421 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1422 State
.F1
= State
.F0
;
1423 if ((int16
)State
.regs
[OP
[1]] < (int16
)State
.regs
[OP
[0]])
1425 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1430 trace_output (OP_REG
);
1439 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1440 State
.F1
= State
.F0
;
1441 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1442 if (tmp
< SEXT40(State
.a
[OP
[0]]))
1444 State
.a
[OP
[0]] = tmp
& MASK40
;
1449 trace_output (OP_ACCUM
);
1456 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1457 State
.F1
= State
.F0
;
1458 if (SEXT40(State
.a
[OP
[1]]) < SEXT40(State
.a
[OP
[0]]))
1460 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1465 trace_output (OP_ACCUM
);
1474 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1475 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1478 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1480 if (State
.ST
&& tmp
> MAX32
)
1483 tmp
= SEXT40(State
.a
[OP
[0]]) - tmp
;
1487 State
.a
[OP
[0]] = MAX32
;
1488 else if (tmp
< MIN32
)
1489 State
.a
[OP
[0]] = MIN32
;
1491 State
.a
[OP
[0]] = tmp
& MASK40
;
1494 State
.a
[OP
[0]] = tmp
& MASK40
;
1495 trace_output (OP_ACCUM
);
1504 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1505 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1507 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1509 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1510 trace_output (OP_ACCUM
);
1519 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1520 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1522 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1524 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1525 trace_output (OP_ACCUM
);
1532 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1533 State
.regs
[OP
[0]] *= State
.regs
[OP
[1]];
1534 trace_output (OP_REG
);
1543 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1544 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1547 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1549 if (State
.ST
&& tmp
> MAX32
)
1550 State
.a
[OP
[0]] = MAX32
;
1552 State
.a
[OP
[0]] = tmp
& MASK40
;
1553 trace_output (OP_ACCUM
);
1562 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1563 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * State
.regs
[OP
[2]]);
1568 State
.a
[OP
[0]] = tmp
& MASK40
;
1569 trace_output (OP_ACCUM
);
1578 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1579 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1584 State
.a
[OP
[0]] = tmp
& MASK40
;
1585 trace_output (OP_ACCUM
);
1592 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1593 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1594 trace_output (OP_REG
);
1601 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1602 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1603 State
.regs
[OP
[0]+1] = State
.regs
[OP
[1]+1];
1604 trace_output (OP_DREG
);
1611 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1612 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1613 State
.regs
[OP
[0]+1] = State
.a
[OP
[1]] & 0xffff;
1614 trace_output (OP_DREG
);
1621 trace_input ("mv2wtac", OP_DREG
, OP_ACCUM_OUTPUT
, OP_VOID
);
1622 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1]) & MASK40
;
1623 trace_output (OP_ACCUM_REVERSE
);
1630 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1631 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1632 trace_output (OP_ACCUM
);
1639 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1640 State
.regs
[OP
[0]] = SEXT8 (State
.regs
[OP
[1]] & 0xff);
1641 trace_output (OP_REG
);
1648 trace_input ("mf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1650 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1651 trace_output (OP_REG
);
1658 trace_input ("mf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1660 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1661 trace_output (OP_REG
);
1668 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1669 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 32) & 0xff;
1670 trace_output (OP_ACCUM
);
1677 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1678 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1679 trace_output (OP_REG
);
1686 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1687 State
.regs
[OP
[0]] = State
.a
[OP
[1]] & 0xffff;
1688 trace_output (OP_REG
);
1695 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
1698 /* PSW is treated specially */
1700 if (State
.SM
) PSW
|= 0x8000;
1701 if (State
.EA
) PSW
|= 0x2000;
1702 if (State
.DB
) PSW
|= 0x1000;
1703 if (State
.IE
) PSW
|= 0x400;
1704 if (State
.RP
) PSW
|= 0x200;
1705 if (State
.MD
) PSW
|= 0x100;
1706 if (State
.FX
) PSW
|= 0x80;
1707 if (State
.ST
) PSW
|= 0x40;
1708 if (State
.F0
) PSW
|= 8;
1709 if (State
.F1
) PSW
|= 4;
1710 if (State
.C
) PSW
|= 1;
1712 State
.regs
[OP
[0]] = State
.cregs
[OP
[1]];
1713 trace_output (OP_REG
);
1720 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
1721 State
.a
[OP
[1]] &= MASK32
;
1722 State
.a
[OP
[1]] |= (int64
)(State
.regs
[OP
[0]] & 0xff) << 32;
1723 trace_output (OP_ACCUM_REVERSE
);
1732 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
1733 tmp
= State
.a
[OP
[1]] & 0xffff;
1734 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | tmp
) & MASK40
;
1735 trace_output (OP_ACCUM_REVERSE
);
1742 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
1743 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]])) & MASK40
;
1744 trace_output (OP_ACCUM_REVERSE
);
1751 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
1752 State
.cregs
[OP
[1]] = State
.regs
[OP
[0]];
1755 /* PSW is treated specially */
1756 State
.SM
= (PSW
& 0x8000) ? 1 : 0;
1757 State
.EA
= (PSW
& 0x2000) ? 1 : 0;
1758 State
.DB
= (PSW
& 0x1000) ? 1 : 0;
1759 State
.IE
= (PSW
& 0x400) ? 1 : 0;
1760 State
.RP
= (PSW
& 0x200) ? 1 : 0;
1761 State
.MD
= (PSW
& 0x100) ? 1 : 0;
1762 State
.FX
= (PSW
& 0x80) ? 1 : 0;
1763 State
.ST
= (PSW
& 0x40) ? 1 : 0;
1764 State
.F0
= (PSW
& 8) ? 1 : 0;
1765 State
.F1
= (PSW
& 4) ? 1 : 0;
1767 if (State
.ST
&& !State
.FX
)
1769 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1770 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1772 State
.exception
= SIGILL
;
1775 trace_output (OP_CR_REVERSE
);
1782 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1783 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & 0xff;
1784 trace_output (OP_REG
);
1791 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
1792 State
.regs
[OP
[0]] = 0 - State
.regs
[OP
[0]];
1793 trace_output (OP_REG
);
1802 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
1803 tmp
= -SEXT40(State
.a
[OP
[0]]);
1807 State
.a
[OP
[0]] = MAX32
;
1808 else if (tmp
< MIN32
)
1809 State
.a
[OP
[0]] = MIN32
;
1811 State
.a
[OP
[0]] = tmp
& MASK40
;
1814 State
.a
[OP
[0]] = tmp
& MASK40
;
1815 trace_output (OP_ACCUM
);
1823 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
1825 ins_type_counters
[ (int)State
.ins_type
]--; /* don't count nops as normal instructions */
1826 switch (State
.ins_type
)
1829 ins_type_counters
[ (int)INS_UNKNOWN
]++;
1832 case INS_LEFT_PARALLEL
:
1833 /* Don't count a parallel op that includes a NOP as a true parallel op */
1834 ins_type_counters
[ (int)INS_RIGHT_PARALLEL
]--;
1835 ins_type_counters
[ (int)INS_RIGHT
]++;
1836 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
1840 case INS_LEFT_COND_EXE
:
1841 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
1844 case INS_RIGHT_PARALLEL
:
1845 /* Don't count a parallel op that includes a NOP as a true parallel op */
1846 ins_type_counters
[ (int)INS_LEFT_PARALLEL
]--;
1847 ins_type_counters
[ (int)INS_LEFT
]++;
1848 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
1852 case INS_RIGHT_COND_EXE
:
1853 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
1857 trace_output (OP_VOID
);
1864 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
1865 State
.regs
[OP
[0]] = ~(State
.regs
[OP
[0]]);
1866 trace_output (OP_REG
);
1873 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
1874 State
.regs
[OP
[0]] |= State
.regs
[OP
[1]];
1875 trace_output (OP_REG
);
1882 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
1883 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] | OP
[2];
1884 trace_output (OP_REG
);
1892 int shift
= SEXT3 (OP
[2]);
1894 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1897 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1898 "ERROR at PC 0x%x: instruction only valid for A0\n",
1900 State
.exception
= SIGILL
;
1903 State
.F1
= State
.F0
;
1905 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) << shift
;
1907 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) >> -shift
;
1908 tmp
= ( SEXT60(tmp
) + 0x8000 ) >> 16;
1911 State
.regs
[OP
[0]] = 0x7fff;
1912 State
.regs
[OP
[0]+1] = 0xffff;
1915 else if (tmp
< MIN32
)
1917 State
.regs
[OP
[0]] = 0x8000;
1918 State
.regs
[OP
[0]+1] = 0;
1923 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1924 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
1927 trace_output (OP_DREG
);
1935 int shift
= SEXT3 (OP
[2]);
1937 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1938 State
.F1
= State
.F0
;
1940 tmp
= SEXT44 (State
.a
[OP
[1]]) << shift
;
1942 tmp
= SEXT44 (State
.a
[OP
[1]]) >> -shift
;
1947 State
.regs
[OP
[0]] = 0x7fff;
1950 else if (tmp
< 0xfff80000000LL
)
1952 State
.regs
[OP
[0]] = 0x8000;
1957 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1960 trace_output (OP_REG
);
1967 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1970 RPT_C
= State
.regs
[OP
[0]];
1974 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep with count=0 is illegal.\n");
1975 State
.exception
= SIGILL
;
1979 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep must include at least 4 instructions.\n");
1980 State
.exception
= SIGILL
;
1982 trace_output (OP_VOID
);
1989 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
1996 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi with count=0 is illegal.\n");
1997 State
.exception
= SIGILL
;
2001 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi must include at least 4 instructions.\n");
2002 State
.exception
= SIGILL
;
2004 trace_output (OP_VOID
);
2011 d10v_callback
->printf_filtered(d10v_callback
, "ERROR: rtd - NOT IMPLEMENTED\n");
2012 State
.exception
= SIGILL
;
2019 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
2022 trace_output (OP_VOID
);
2031 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2032 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT40(State
.a
[OP
[1]]) >> 16);
2036 State
.a
[OP
[0]] = MAX32
;
2037 else if (tmp
< MIN32
)
2038 State
.a
[OP
[0]] = MIN32
;
2040 State
.a
[OP
[0]] = tmp
& MASK40
;
2043 State
.a
[OP
[0]] = tmp
& MASK40
;
2044 trace_output (OP_ACCUM
);
2051 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2052 State
.regs
[OP
[0]] = (State
.F0
== 0) ? 1 : 0;
2053 trace_output (OP_REG
);
2060 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2061 State
.regs
[OP
[0]] = (State
.F0
== 1) ? 1 : 0;
2062 trace_output (OP_REG
);
2069 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
2071 trace_output (OP_VOID
);
2078 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
2079 State
.regs
[OP
[0]] <<= (State
.regs
[OP
[1]] & 0xf);
2080 trace_output (OP_REG
);
2088 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
2089 if ((State
.regs
[OP
[1]] & 31) <= 16)
2090 tmp
= SEXT40 (State
.a
[OP
[0]]) << (State
.regs
[OP
[1]] & 31);
2093 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2094 State
.exception
= SIGILL
;
2101 State
.a
[OP
[0]] = MAX32
;
2102 else if (tmp
< 0xffffff80000000LL
)
2103 State
.a
[OP
[0]] = MIN32
;
2105 State
.a
[OP
[0]] = tmp
& MASK40
;
2108 State
.a
[OP
[0]] = tmp
& MASK40
;
2109 trace_output (OP_ACCUM
);
2116 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2117 State
.regs
[OP
[0]] <<= OP
[1];
2118 trace_output (OP_REG
);
2130 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2131 tmp
= SEXT40(State
.a
[OP
[0]]) << OP
[1];
2136 State
.a
[OP
[0]] = MAX32
;
2137 else if (tmp
< 0xffffff80000000LL
)
2138 State
.a
[OP
[0]] = MIN32
;
2140 State
.a
[OP
[0]] = tmp
& MASK40
;
2143 State
.a
[OP
[0]] = tmp
& MASK40
;
2144 trace_output (OP_ACCUM
);
2151 trace_input ("slx", OP_REG
, OP_FLAG
, OP_VOID
);
2152 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] << 1) | State
.F0
;
2153 trace_output (OP_REG
);
2160 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
2161 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> (State
.regs
[OP
[1]] & 0xf);
2162 trace_output (OP_REG
);
2169 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2170 if ((State
.regs
[OP
[1]] & 31) <= 16)
2171 State
.a
[OP
[0]] = (SEXT40(State
.a
[OP
[0]]) >> (State
.regs
[OP
[1]] & 31)) & MASK40
;
2174 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2175 State
.exception
= SIGILL
;
2179 trace_output (OP_ACCUM
);
2186 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2187 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> OP
[1];
2188 trace_output (OP_REG
);
2198 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2199 State
.a
[OP
[0]] = (SEXT40(State
.a
[OP
[0]]) >> OP
[1]) & MASK40
;
2200 trace_output (OP_ACCUM
);
2207 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2208 State
.regs
[OP
[0]] >>= (State
.regs
[OP
[1]] & 0xf);
2209 trace_output (OP_REG
);
2216 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2217 if ((State
.regs
[OP
[1]] & 31) <= 16)
2218 State
.a
[OP
[0]] = (uint64
)((State
.a
[OP
[0]] & MASK40
) >> (State
.regs
[OP
[1]] & 31));
2221 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2222 State
.exception
= SIGILL
;
2226 trace_output (OP_ACCUM
);
2233 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2234 State
.regs
[OP
[0]] >>= OP
[1];
2235 trace_output (OP_REG
);
2245 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2246 State
.a
[OP
[0]] = (uint64
)(State
.a
[OP
[0]] & MASK40
) >> OP
[1];
2247 trace_output (OP_ACCUM
);
2256 trace_input ("srx", OP_REG
, OP_FLAG
, OP_VOID
);
2257 tmp
= State
.F0
<< 15;
2258 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] >> 1) | tmp
;
2259 trace_output (OP_REG
);
2266 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2267 SW (OP
[1] + State
.regs
[OP
[2]], State
.regs
[OP
[0]]);
2268 trace_output (OP_VOID
);
2275 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2276 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2277 trace_output (OP_VOID
);
2284 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2287 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2288 State
.exception
= SIGILL
;
2291 State
.regs
[OP
[1]] -= 2;
2292 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2293 trace_output (OP_VOID
);
2300 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2301 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2302 INC_ADDR (State
.regs
[OP
[1]],2);
2303 trace_output (OP_VOID
);
2310 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2313 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2314 State
.exception
= SIGILL
;
2317 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2318 INC_ADDR (State
.regs
[OP
[1]],-2);
2319 trace_output (OP_VOID
);
2326 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2327 SW (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2328 SW (State
.regs
[OP
[2]]+OP
[1]+2, State
.regs
[OP
[0]+1]);
2329 trace_output (OP_VOID
);
2336 trace_input ("st2w", OP_DREG
, OP_MEMREF
, OP_VOID
);
2337 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2338 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2339 trace_output (OP_VOID
);
2346 trace_input ("st2w", OP_DREG
, OP_PREDEC
, OP_VOID
);
2349 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2350 State
.exception
= SIGILL
;
2353 State
.regs
[OP
[1]] -= 4;
2354 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2355 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2356 trace_output (OP_VOID
);
2363 trace_input ("st2w", OP_DREG
, OP_POSTDEC
, OP_VOID
);
2366 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2367 State
.exception
= SIGILL
;
2370 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2371 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2372 INC_ADDR (State
.regs
[OP
[1]],4);
2373 trace_output (OP_VOID
);
2380 trace_input ("st2w", OP_DREG
, OP_POSTINC
, OP_VOID
);
2381 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2382 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2383 INC_ADDR (State
.regs
[OP
[1]],-4);
2384 trace_output (OP_VOID
);
2391 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2392 SB (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2393 trace_output (OP_VOID
);
2400 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2401 SB (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2402 trace_output (OP_VOID
);
2409 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2410 State
.exception
= SIG_D10V_STOP
;
2411 trace_output (OP_VOID
);
2420 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
2421 tmp
= State
.regs
[OP
[0]] - State
.regs
[OP
[1]];
2422 State
.C
= (tmp
> State
.regs
[OP
[0]]);
2423 State
.regs
[OP
[0]] = tmp
;
2424 trace_output (OP_REG
);
2433 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
2434 tmp
= SEXT40(State
.a
[OP
[0]]) - (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
2438 State
.a
[OP
[0]] = MAX32
;
2439 else if ( tmp
< MIN32
)
2440 State
.a
[OP
[0]] = MIN32
;
2442 State
.a
[OP
[0]] = tmp
& MASK40
;
2445 State
.a
[OP
[0]] = tmp
& MASK40
;
2447 trace_output (OP_ACCUM
);
2457 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2458 tmp
= SEXT40(State
.a
[OP
[0]]) - SEXT40(State
.a
[OP
[1]]);
2462 State
.a
[OP
[0]] = MAX32
;
2463 else if ( tmp
< MIN32
)
2464 State
.a
[OP
[0]] = MIN32
;
2466 State
.a
[OP
[0]] = tmp
& MASK40
;
2469 State
.a
[OP
[0]] = tmp
& MASK40
;
2471 trace_output (OP_ACCUM
);
2480 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
2481 a
= (uint32
)((State
.regs
[OP
[0]] << 16) | State
.regs
[OP
[0]+1]);
2482 b
= (uint32
)((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
2484 State
.C
= (tmp
> a
);
2485 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2486 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2487 trace_output (OP_DREG
);
2496 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2497 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40 (State
.a
[OP
[2]]);
2498 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2499 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2500 trace_output (OP_DREG
);
2509 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2510 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2511 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2512 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2513 trace_output (OP_DREG
);
2522 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2523 State
.F1
= State
.F0
;
2524 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40(State
.a
[OP
[2]]);
2527 State
.regs
[OP
[0]] = 0x7fff;
2528 State
.regs
[OP
[0]+1] = 0xffff;
2531 else if (tmp
< MIN32
)
2533 State
.regs
[OP
[0]] = 0x8000;
2534 State
.regs
[OP
[0]+1] = 0;
2539 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2540 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2543 trace_output (OP_DREG
);
2552 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2553 State
.F1
= State
.F0
;
2554 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2557 State
.regs
[OP
[0]] = 0x7fff;
2558 State
.regs
[OP
[0]+1] = 0xffff;
2561 else if (tmp
< MIN32
)
2563 State
.regs
[OP
[0]] = 0x8000;
2564 State
.regs
[OP
[0]+1] = 0;
2569 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2570 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2573 trace_output (OP_DREG
);
2584 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2585 tmp
= State
.regs
[OP
[0]] - OP
[1];
2586 State
.C
= (tmp
> State
.regs
[OP
[0]]);
2587 State
.regs
[OP
[0]] = tmp
;
2588 trace_output (OP_REG
);
2595 trace_input ("trap", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
2596 trace_output (OP_VOID
);
2602 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown trap code %d\n", OP
[0]);
2603 State
.exception
= SIGILL
;
2605 /* Use any other traps for batch debugging. */
2608 static int first_time
= 1;
2613 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap # PC ");
2614 for (i
= 0; i
< 16; i
++)
2615 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %sr%d", (i
> 9) ? "" : " ", i
);
2616 (*d10v_callback
->printf_filtered
) (d10v_callback
, " a0 a1 f0 f1 c\n");
2619 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
2621 for (i
= 0; i
< 16; i
++)
2622 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.4x", (int) State
.regs
[i
]);
2624 for (i
= 0; i
< 2; i
++)
2625 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.2x%.8lx",
2626 ((int)(State
.a
[i
] >> 32) & 0xff),
2627 ((unsigned long)State
.a
[i
]) & 0xffffffff);
2629 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %d %d %d\n",
2630 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
2631 (*d10v_callback
->flush_stdout
) (d10v_callback
);
2636 case 0: /* old system call trap, to be deleted */
2637 case 15: /* new system call trap */
2638 /* Trap 15 is used for simulating low-level I/O */
2642 /* Registers passed to trap 0 */
2644 #define FUNC State.regs[6] /* function number */
2645 #define PARM1 State.regs[2] /* optional parm 1 */
2646 #define PARM2 State.regs[3] /* optional parm 2 */
2647 #define PARM3 State.regs[4] /* optional parm 3 */
2648 #define PARM4 State.regs[5] /* optional parm 3 */
2650 /* Registers set by trap 0 */
2652 #define RETVAL State.regs[2] /* return value */
2653 #define RETVAL_HIGH State.regs[2] /* return value */
2654 #define RETVAL_LOW State.regs[3] /* return value */
2655 #define RETERR State.regs[4] /* return error code */
2657 /* Turn a pointer in a register into a pointer into real memory. */
2659 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2663 #if !defined(__GO32__) && !defined(_WIN32)
2666 trace_input ("<fork>", OP_VOID
, OP_VOID
, OP_VOID
);
2667 trace_output (OP_R2
);
2671 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
2673 trace_output (OP_R2
);
2677 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
2678 if (PARM1
== getpid ())
2680 trace_output (OP_VOID
);
2681 State
.exception
= PARM2
;
2689 case 1: os_sig
= SIGHUP
; break;
2692 case 2: os_sig
= SIGINT
; break;
2695 case 3: os_sig
= SIGQUIT
; break;
2698 case 4: os_sig
= SIGILL
; break;
2701 case 5: os_sig
= SIGTRAP
; break;
2704 case 6: os_sig
= SIGABRT
; break;
2705 #elif defined(SIGIOT)
2706 case 6: os_sig
= SIGIOT
; break;
2709 case 7: os_sig
= SIGEMT
; break;
2712 case 8: os_sig
= SIGFPE
; break;
2715 case 9: os_sig
= SIGKILL
; break;
2718 case 10: os_sig
= SIGBUS
; break;
2721 case 11: os_sig
= SIGSEGV
; break;
2724 case 12: os_sig
= SIGSYS
; break;
2727 case 13: os_sig
= SIGPIPE
; break;
2730 case 14: os_sig
= SIGALRM
; break;
2733 case 15: os_sig
= SIGTERM
; break;
2736 case 16: os_sig
= SIGURG
; break;
2739 case 17: os_sig
= SIGSTOP
; break;
2742 case 18: os_sig
= SIGTSTP
; break;
2745 case 19: os_sig
= SIGCONT
; break;
2748 case 20: os_sig
= SIGCHLD
; break;
2749 #elif defined(SIGCLD)
2750 case 20: os_sig
= SIGCLD
; break;
2753 case 21: os_sig
= SIGTTIN
; break;
2756 case 22: os_sig
= SIGTTOU
; break;
2759 case 23: os_sig
= SIGIO
; break;
2760 #elif defined (SIGPOLL)
2761 case 23: os_sig
= SIGPOLL
; break;
2764 case 24: os_sig
= SIGXCPU
; break;
2767 case 25: os_sig
= SIGXFSZ
; break;
2770 case 26: os_sig
= SIGVTALRM
; break;
2773 case 27: os_sig
= SIGPROF
; break;
2776 case 28: os_sig
= SIGWINCH
; break;
2779 case 29: os_sig
= SIGLOST
; break;
2782 case 30: os_sig
= SIGUSR1
; break;
2785 case 31: os_sig
= SIGUSR2
; break;
2791 trace_output (OP_VOID
);
2792 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown signal %d\n", PARM2
);
2793 (*d10v_callback
->flush_stdout
) (d10v_callback
);
2794 State
.exception
= SIGILL
;
2798 RETVAL
= kill (PARM1
, PARM2
);
2799 trace_output (OP_R2
);
2805 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2806 (char **)MEMPTR (PARM3
));
2807 trace_input ("<execve>", OP_R2
, OP_R3
, OP_R4
);
2808 trace_output (OP_R2
);
2813 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2814 trace_input ("<execv>", OP_R2
, OP_R3
, OP_VOID
);
2815 trace_output (OP_R2
);
2825 RETVAL
= pipe (host_fd
);
2826 SW (buf
, host_fd
[0]);
2827 buf
+= sizeof(uint16
);
2828 SW (buf
, host_fd
[1]);
2829 trace_input ("<pipe>", OP_R2
, OP_VOID
, OP_VOID
);
2830 trace_output (OP_R2
);
2839 RETVAL
= wait (&status
);
2842 trace_input ("<wait>", OP_R2
, OP_VOID
, OP_VOID
);
2843 trace_output (OP_R2
);
2849 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
2851 trace_output (OP_R2
);
2855 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
2856 trace_output (OP_VOID
);
2857 State
.exception
= PARM2
;
2862 RETVAL
= d10v_callback
->read (d10v_callback
, PARM1
, MEMPTR (PARM2
),
2864 trace_input ("<read>", OP_R2
, OP_R3
, OP_R4
);
2865 trace_output (OP_R2
);
2870 RETVAL
= (int)d10v_callback
->write_stdout (d10v_callback
,
2871 MEMPTR (PARM2
), PARM3
);
2873 RETVAL
= (int)d10v_callback
->write (d10v_callback
, PARM1
,
2874 MEMPTR (PARM2
), PARM3
);
2875 trace_input ("<write>", OP_R2
, OP_R3
, OP_R4
);
2876 trace_output (OP_R2
);
2881 unsigned long ret
= d10v_callback
->lseek (d10v_callback
, PARM1
,
2882 (((unsigned long)PARM2
) << 16) || (unsigned long)PARM3
,
2884 RETVAL_HIGH
= ret
>> 16;
2885 RETVAL_LOW
= ret
& 0xffff;
2887 trace_input ("<lseek>", OP_R2
, OP_R3
, OP_R4
);
2888 trace_output (OP_R2R3
);
2892 RETVAL
= d10v_callback
->close (d10v_callback
, PARM1
);
2893 trace_input ("<close>", OP_R2
, OP_VOID
, OP_VOID
);
2894 trace_output (OP_R2
);
2898 RETVAL
= d10v_callback
->open (d10v_callback
, MEMPTR (PARM1
), PARM2
);
2899 trace_input ("<open>", OP_R2
, OP_R3
, OP_R4
);
2900 trace_output (OP_R2
);
2901 trace_input ("<open>", OP_R2
, OP_R3
, OP_R4
);
2902 trace_output (OP_R2
);
2906 State
.exception
= SIG_D10V_EXIT
;
2907 trace_input ("<exit>", OP_R2
, OP_VOID
, OP_VOID
);
2908 trace_output (OP_VOID
);
2912 /* stat system call */
2914 struct stat host_stat
;
2917 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2921 /* The hard-coded offsets and sizes were determined by using
2922 * the D10V compiler on a test program that used struct stat.
2924 SW (buf
, host_stat
.st_dev
);
2925 SW (buf
+2, host_stat
.st_ino
);
2926 SW (buf
+4, host_stat
.st_mode
);
2927 SW (buf
+6, host_stat
.st_nlink
);
2928 SW (buf
+8, host_stat
.st_uid
);
2929 SW (buf
+10, host_stat
.st_gid
);
2930 SW (buf
+12, host_stat
.st_rdev
);
2931 SLW (buf
+16, host_stat
.st_size
);
2932 SLW (buf
+20, host_stat
.st_atime
);
2933 SLW (buf
+28, host_stat
.st_mtime
);
2934 SLW (buf
+36, host_stat
.st_ctime
);
2936 trace_input ("<stat>", OP_R2
, OP_R3
, OP_VOID
);
2937 trace_output (OP_R2
);
2941 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2942 trace_input ("<chown>", OP_R2
, OP_R3
, OP_R4
);
2943 trace_output (OP_R2
);
2947 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2948 trace_input ("<chmod>", OP_R2
, OP_R3
, OP_R4
);
2949 trace_output (OP_R2
);
2954 /* Cast the second argument to void *, to avoid type mismatch
2955 if a prototype is present. */
2956 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2957 trace_input ("<utime>", OP_R2
, OP_R3
, OP_R4
);
2958 trace_output (OP_R2
);
2965 unsigned long ret
= time (PARM1
? MEMPTR (PARM1
) : NULL
);
2966 RETVAL_HIGH
= ret
>> 16;
2967 RETVAL_LOW
= ret
& 0xffff;
2969 trace_input ("<time>", OP_R2
, OP_R3
, OP_R4
);
2970 trace_output (OP_R2R3
);
2977 RETERR
= (RETVAL
== (uint16
) -1) ? d10v_callback
->get_errno(d10v_callback
) : 0;
2987 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2988 State
.F1
= State
.F0
;
2989 State
.F0
= (State
.regs
[OP
[0]] & OP
[1]) ? 1 : 0;
2990 trace_output (OP_FLAG
);
2997 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2998 State
.F1
= State
.F0
;
2999 State
.F0
= (~(State
.regs
[OP
[0]]) & OP
[1]) ? 1 : 0;
3000 trace_output (OP_FLAG
);
3007 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
3009 trace_output (OP_VOID
);
3016 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
3017 State
.regs
[OP
[0]] ^= State
.regs
[OP
[1]];
3018 trace_output (OP_REG
);
3025 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
3026 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] ^ OP
[2];
3027 trace_output (OP_REG
);
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